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KVM: VMX: Move some cr[04] related constants to vmx.c
[net-next-2.6.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
72#define KVM_GUEST_CR4_MASK \
73 (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
74#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
75#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
76
4b8d54f9
ZE		 77/*
78 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
79 * ple_gap: upper bound on the amount of time between two successive
80 * executions of PAUSE in a loop. Also indicate if ple enabled.
81 * According to test, this time is usually small than 41 cycles.
82 * ple_window: upper bound on the amount of time a guest is allowed to execute
83 * in a PAUSE loop. Tests indicate that most spinlocks are held for
84 * less than 2^12 cycles
85 * Time is measured based on a counter that runs at the same rate as the TSC,
86 * refer SDM volume 3b section 21.6.13 & 22.1.3.
87 */
88#define KVM_VMX_DEFAULT_PLE_GAP 41
89#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
90static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
91module_param(ple_gap, int, S_IRUGO);
92
93static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
94module_param(ple_window, int, S_IRUGO);
95
a2fa3e9f
GH		 96struct vmcs {
97 u32 revision_id;
98 u32 abort;
99 char data[0];
100};
101
26bb0981
AK		 102struct shared_msr_entry {
103 unsigned index;
104 u64 data;
d5696725 105 u64 mask;
26bb0981
AK		 106};
107
a2fa3e9f 108struct vcpu_vmx {
fb3f0f51 109 struct kvm_vcpu vcpu;
543e4243 110 struct list_head local_vcpus_link;
313dbd49 111 unsigned long host_rsp;
a2fa3e9f 112 int launched;
29bd8a78 113 u8 fail;
1155f76a 114 u32 idt_vectoring_info;
26bb0981 115 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 116 int nmsrs;
117 int save_nmsrs;
a2fa3e9f 118#ifdef CONFIG_X86_64
44ea2b17
AK		 119 u64 msr_host_kernel_gs_base;
120 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 121#endif
122 struct vmcs *vmcs;
123 struct {
124 int loaded;
125 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 126 int gs_ldt_reload_needed;
127 int fs_reload_needed;
d77c26fc 128 } host_state;
9c8cba37 129 struct {
7ffd92c5
AK		 130 int vm86_active;
131 u8 save_iopl;
132 struct kvm_save_segment {
133 u16 selector;
134 unsigned long base;
135 u32 limit;
136 u32 ar;
137 } tr, es, ds, fs, gs;
9c8cba37
AK		 138 struct {
139 bool pending;
140 u8 vector;
141 unsigned rip;
142 } irq;
143 } rmode;
2384d2b3 144 int vpid;
04fa4d32 145 bool emulation_required;
3b86cd99
JK		 146
147 /* Support for vnmi-less CPUs */
148 int soft_vnmi_blocked;
149 ktime_t entry_time;
150 s64 vnmi_blocked_time;
a0861c02 151 u32 exit_reason;
a2fa3e9f
GH		 152};
153
154static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
155{
fb3f0f51 156 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 157}
158
b7ebfb05 159static int init_rmode(struct kvm *kvm);
4e1096d2 160static u64 construct_eptp(unsigned long root_hpa);
75880a01 161
6aa8b732
AK		 162static DEFINE_PER_CPU(struct vmcs *, vmxarea);
163static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 164static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 165
3e7c73e9
AK		 166static unsigned long *vmx_io_bitmap_a;
167static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 168static unsigned long *vmx_msr_bitmap_legacy;
169static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 170
2384d2b3
SY		 171static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
172static DEFINE_SPINLOCK(vmx_vpid_lock);
173
1c3d14fe 174static struct vmcs_config {
6aa8b732
AK		 175 int size;
176 int order;
177 u32 revision_id;
1c3d14fe
YS		 178 u32 pin_based_exec_ctrl;
179 u32 cpu_based_exec_ctrl;
f78e0e2e 180 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 181 u32 vmexit_ctrl;
182 u32 vmentry_ctrl;
183} vmcs_config;
6aa8b732 184
efff9e53 185static struct vmx_capability {
d56f546d
SY		 186 u32 ept;
187 u32 vpid;
188} vmx_capability;
189
6aa8b732
AK		 190#define VMX_SEGMENT_FIELD(seg) \
191 [VCPU_SREG_##seg] = { \
192 .selector = GUEST_##seg##_SELECTOR, \
193 .base = GUEST_##seg##_BASE, \
194 .limit = GUEST_##seg##_LIMIT, \
195 .ar_bytes = GUEST_##seg##_AR_BYTES, \
196 }
197
198static struct kvm_vmx_segment_field {
199 unsigned selector;
200 unsigned base;
201 unsigned limit;
202 unsigned ar_bytes;
203} kvm_vmx_segment_fields[] = {
204 VMX_SEGMENT_FIELD(CS),
205 VMX_SEGMENT_FIELD(DS),
206 VMX_SEGMENT_FIELD(ES),
207 VMX_SEGMENT_FIELD(FS),
208 VMX_SEGMENT_FIELD(GS),
209 VMX_SEGMENT_FIELD(SS),
210 VMX_SEGMENT_FIELD(TR),
211 VMX_SEGMENT_FIELD(LDTR),
212};
213
26bb0981
AK		 214static u64 host_efer;
215
6de4f3ad
AK		 216static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
217
4d56c8a7
AK		 218/*
219 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
220 * away by decrementing the array size.
221 */
6aa8b732 222static const u32 vmx_msr_index[] = {
05b3e0c2 223#ifdef CONFIG_X86_64
44ea2b17 224 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 225#endif
226 MSR_EFER, MSR_K6_STAR,
227};
9d8f549d 228#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 229
6aa8b732
AK		 230static inline int is_page_fault(u32 intr_info)
231{
232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
233 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 234 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 235}
236
2ab455cc
AL		 237static inline int is_no_device(u32 intr_info)
238{
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
240 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 241 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 242}
243
7aa81cc0
AL		 244static inline int is_invalid_opcode(u32 intr_info)
245{
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 248 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 249}
250
6aa8b732
AK		 251static inline int is_external_interrupt(u32 intr_info)
252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
254 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
255}
256
a0861c02
AK		 257static inline int is_machine_check(u32 intr_info)
258{
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
261 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
262}
263
25c5f225
SY		 264static inline int cpu_has_vmx_msr_bitmap(void)
265{
04547156 266 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 267}
268
6e5d865c
YS		 269static inline int cpu_has_vmx_tpr_shadow(void)
270{
04547156 271 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 272}
273
274static inline int vm_need_tpr_shadow(struct kvm *kvm)
275{
04547156 276 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 277}
278
f78e0e2e
SY		 279static inline int cpu_has_secondary_exec_ctrls(void)
280{
04547156
SY		 281 return vmcs_config.cpu_based_exec_ctrl &
282 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 283}
284
774ead3a 285static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 286{
04547156
SY		 287 return vmcs_config.cpu_based_2nd_exec_ctrl &
288 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
289}
290
291static inline bool cpu_has_vmx_flexpriority(void)
292{
293 return cpu_has_vmx_tpr_shadow() &&
294 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 295}
296
e799794e
MT		 297static inline bool cpu_has_vmx_ept_execute_only(void)
298{
299 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
300}
301
302static inline bool cpu_has_vmx_eptp_uncacheable(void)
303{
304 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
305}
306
307static inline bool cpu_has_vmx_eptp_writeback(void)
308{
309 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
310}
311
312static inline bool cpu_has_vmx_ept_2m_page(void)
313{
314 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
315}
316
d56f546d
SY		 317static inline int cpu_has_vmx_invept_individual_addr(void)
318{
04547156 319 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 320}
321
322static inline int cpu_has_vmx_invept_context(void)
323{
04547156 324 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 325}
326
327static inline int cpu_has_vmx_invept_global(void)
328{
04547156 329 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 330}
331
332static inline int cpu_has_vmx_ept(void)
333{
04547156
SY		 334 return vmcs_config.cpu_based_2nd_exec_ctrl &
335 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 336}
337
3a624e29
NK		 338static inline int cpu_has_vmx_unrestricted_guest(void)
339{
340 return vmcs_config.cpu_based_2nd_exec_ctrl &
341 SECONDARY_EXEC_UNRESTRICTED_GUEST;
342}
343
4b8d54f9
ZE		 344static inline int cpu_has_vmx_ple(void)
345{
346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
348}
349
f78e0e2e
SY		 350static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
351{
04547156
SY		 352 return flexpriority_enabled &&
353 (cpu_has_vmx_virtualize_apic_accesses()) &&
354 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 355}
356
2384d2b3
SY		 357static inline int cpu_has_vmx_vpid(void)
358{
04547156
SY		 359 return vmcs_config.cpu_based_2nd_exec_ctrl &
360 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 361}
362
f08864b4
SY		 363static inline int cpu_has_virtual_nmis(void)
364{
365 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
366}
367
04547156
SY		 368static inline bool report_flexpriority(void)
369{
370 return flexpriority_enabled;
371}
372
8b9cf98c 373static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 374{
375 int i;
376
a2fa3e9f 377 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 378 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 379 return i;
380 return -1;
381}
382
2384d2b3
SY		 383static inline void __invvpid(int ext, u16 vpid, gva_t gva)
384{
385 struct {
386 u64 vpid : 16;
387 u64 rsvd : 48;
388 u64 gva;
389 } operand = { vpid, 0, gva };
390
4ecac3fd 391 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 392 /* CF==1 or ZF==1 --> rc = -1 */
393 "; ja 1f ; ud2 ; 1:"
394 : : "a"(&operand), "c"(ext) : "cc", "memory");
395}
396
1439442c
SY		 397static inline void __invept(int ext, u64 eptp, gpa_t gpa)
398{
399 struct {
400 u64 eptp, gpa;
401 } operand = {eptp, gpa};
402
4ecac3fd 403 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 404 /* CF==1 or ZF==1 --> rc = -1 */
405 "; ja 1f ; ud2 ; 1:\n"
406 : : "a" (&operand), "c" (ext) : "cc", "memory");
407}
408
26bb0981 409static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 410{
411 int i;
412
8b9cf98c 413 i = __find_msr_index(vmx, msr);
a75beee6 414 if (i >= 0)
a2fa3e9f 415 return &vmx->guest_msrs[i];
8b6d44c7 416 return NULL;
7725f0ba
AK		 417}
418
6aa8b732
AK		 419static void vmcs_clear(struct vmcs *vmcs)
420{
421 u64 phys_addr = __pa(vmcs);
422 u8 error;
423
4ecac3fd 424 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 425 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
426 : "cc", "memory");
427 if (error)
428 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
429 vmcs, phys_addr);
430}
431
432static void __vcpu_clear(void *arg)
433{
8b9cf98c 434 struct vcpu_vmx *vmx = arg;
d3b2c338 435 int cpu = raw_smp_processor_id();
6aa8b732 436
8b9cf98c 437 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 438 vmcs_clear(vmx->vmcs);
439 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 440 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 441 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 442 list_del(&vmx->local_vcpus_link);
443 vmx->vcpu.cpu = -1;
444 vmx->launched = 0;
6aa8b732
AK		 445}
446
8b9cf98c 447static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 448{
eae5ecb5
AK		 449 if (vmx->vcpu.cpu == -1)
450 return;
8691e5a8 451 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 452}
453
2384d2b3
SY		 454static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
455{
456 if (vmx->vpid == 0)
457 return;
458
459 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
460}
461
1439442c
SY		 462static inline void ept_sync_global(void)
463{
464 if (cpu_has_vmx_invept_global())
465 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
466}
467
468static inline void ept_sync_context(u64 eptp)
469{
089d034e 470 if (enable_ept) {
1439442c
SY		 471 if (cpu_has_vmx_invept_context())
472 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
473 else
474 ept_sync_global();
475 }
476}
477
478static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
479{
089d034e 480 if (enable_ept) {
1439442c
SY		 481 if (cpu_has_vmx_invept_individual_addr())
482 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
483 eptp, gpa);
484 else
485 ept_sync_context(eptp);
486 }
487}
488
6aa8b732
AK		 489static unsigned long vmcs_readl(unsigned long field)
490{
491 unsigned long value;
492
4ecac3fd 493 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 494 : "=a"(value) : "d"(field) : "cc");
495 return value;
496}
497
498static u16 vmcs_read16(unsigned long field)
499{
500 return vmcs_readl(field);
501}
502
503static u32 vmcs_read32(unsigned long field)
504{
505 return vmcs_readl(field);
506}
507
508static u64 vmcs_read64(unsigned long field)
509{
05b3e0c2 510#ifdef CONFIG_X86_64
6aa8b732
AK		 511 return vmcs_readl(field);
512#else
513 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
514#endif
515}
516
e52de1b8
AK		 517static noinline void vmwrite_error(unsigned long field, unsigned long value)
518{
519 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
520 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
521 dump_stack();
522}
523
6aa8b732
AK		 524static void vmcs_writel(unsigned long field, unsigned long value)
525{
526 u8 error;
527
4ecac3fd 528 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 529 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 530 if (unlikely(error))
531 vmwrite_error(field, value);
6aa8b732
AK		 532}
533
534static void vmcs_write16(unsigned long field, u16 value)
535{
536 vmcs_writel(field, value);
537}
538
539static void vmcs_write32(unsigned long field, u32 value)
540{
541 vmcs_writel(field, value);
542}
543
544static void vmcs_write64(unsigned long field, u64 value)
545{
6aa8b732 546 vmcs_writel(field, value);
7682f2d0 547#ifndef CONFIG_X86_64
6aa8b732
AK		 548 asm volatile ("");
549 vmcs_writel(field+1, value >> 32);
550#endif
551}
552
2ab455cc
AL		 553static void vmcs_clear_bits(unsigned long field, u32 mask)
554{
555 vmcs_writel(field, vmcs_readl(field) & ~mask);
556}
557
558static void vmcs_set_bits(unsigned long field, u32 mask)
559{
560 vmcs_writel(field, vmcs_readl(field) | mask);
561}
562
abd3f2d6
AK		 563static void update_exception_bitmap(struct kvm_vcpu *vcpu)
564{
565 u32 eb;
566
a0861c02 567 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 568 if (!vcpu->fpu_active)
569 eb |= 1u << NM_VECTOR;
e8a48342
AK		 570 /*
571 * Unconditionally intercept #DB so we can maintain dr6 without
572 * reading it every exit.
573 */
574 eb |= 1u << DB_VECTOR;
d0bfb940 575 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 576 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
577 eb |= 1u << BP_VECTOR;
578 }
7ffd92c5 579 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 580 eb = ~0;
089d034e 581 if (enable_ept)
1439442c 582 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 583 vmcs_write32(EXCEPTION_BITMAP, eb);
584}
585
33ed6329
AK		 586static void reload_tss(void)
587{
33ed6329
AK		 588 /*
589 * VT restores TR but not its size. Useless.
590 */
591 struct descriptor_table gdt;
a5f61300 592 struct desc_struct *descs;
33ed6329 593
d6e88aec 594 kvm_get_gdt(&gdt);
33ed6329
AK		 595 descs = (void *)gdt.base;
596 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
597 load_TR_desc();
33ed6329
AK		 598}
599
92c0d900 600static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 601{
3a34a881 602 u64 guest_efer;
51c6cf66
AK		 603 u64 ignore_bits;
604
26bb0981 605 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 606
51c6cf66
AK		 607 /*
608 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
609 * outside long mode
610 */
611 ignore_bits = EFER_NX | EFER_SCE;
612#ifdef CONFIG_X86_64
613 ignore_bits |= EFER_LMA | EFER_LME;
614 /* SCE is meaningful only in long mode on Intel */
615 if (guest_efer & EFER_LMA)
616 ignore_bits &= ~(u64)EFER_SCE;
617#endif
51c6cf66
AK		 618 guest_efer &= ~ignore_bits;
619 guest_efer |= host_efer & ignore_bits;
26bb0981 620 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 621 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 622 return true;
51c6cf66
AK		 623}
624
04d2cc77 625static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 626{
04d2cc77 627 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 628 int i;
04d2cc77 629
a2fa3e9f 630 if (vmx->host_state.loaded)
33ed6329
AK		 631 return;
632
a2fa3e9f 633 vmx->host_state.loaded = 1;
33ed6329
AK		 634 /*
635 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
636 * allow segment selectors with cpl > 0 or ti == 1.
637 */
d6e88aec 638 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 639 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 640 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 641 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 642 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 643 vmx->host_state.fs_reload_needed = 0;
644 } else {
33ed6329 645 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 646 vmx->host_state.fs_reload_needed = 1;
33ed6329 647 }
d6e88aec 648 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 649 if (!(vmx->host_state.gs_sel & 7))
650 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 651 else {
652 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 653 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 654 }
655
656#ifdef CONFIG_X86_64
657 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
658 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
659#else
a2fa3e9f
GH		 660 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
661 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 662#endif
707c0874
AK		 663
664#ifdef CONFIG_X86_64
44ea2b17
AK		 665 if (is_long_mode(&vmx->vcpu)) {
666 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
667 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
668 }
707c0874 669#endif
26bb0981
AK		 670 for (i = 0; i < vmx->save_nmsrs; ++i)
671 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 672 vmx->guest_msrs[i].data,
673 vmx->guest_msrs[i].mask);
33ed6329
AK		 674}
675
a9b21b62 676static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 677{
15ad7146 678 unsigned long flags;
33ed6329 679
a2fa3e9f 680 if (!vmx->host_state.loaded)
33ed6329
AK		 681 return;
682
e1beb1d3 683 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 684 vmx->host_state.loaded = 0;
152d3f2f 685 if (vmx->host_state.fs_reload_needed)
d6e88aec 686 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 687 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 688 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 689 /*
690 * If we have to reload gs, we must take care to
691 * preserve our gs base.
692 */
15ad7146 693 local_irq_save(flags);
d6e88aec 694 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 695#ifdef CONFIG_X86_64
696 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
697#endif
15ad7146 698 local_irq_restore(flags);
33ed6329 699 }
152d3f2f 700 reload_tss();
44ea2b17
AK		 701#ifdef CONFIG_X86_64
702 if (is_long_mode(&vmx->vcpu)) {
703 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
704 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
705 }
706#endif
33ed6329
AK		 707}
708
a9b21b62
AK		 709static void vmx_load_host_state(struct vcpu_vmx *vmx)
710{
711 preempt_disable();
712 __vmx_load_host_state(vmx);
713 preempt_enable();
714}
715
6aa8b732
AK		 716/*
717 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
718 * vcpu mutex is already taken.
719 */
15ad7146 720static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 721{
a2fa3e9f
GH		 722 struct vcpu_vmx *vmx = to_vmx(vcpu);
723 u64 phys_addr = __pa(vmx->vmcs);
019960ae 724 u64 tsc_this, delta, new_offset;
6aa8b732 725
a3d7f85f 726 if (vcpu->cpu != cpu) {
8b9cf98c 727 vcpu_clear(vmx);
2f599714 728 kvm_migrate_timers(vcpu);
eb5109e3 729 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 730 local_irq_disable();
731 list_add(&vmx->local_vcpus_link,
732 &per_cpu(vcpus_on_cpu, cpu));
733 local_irq_enable();
a3d7f85f 734 }
6aa8b732 735
a2fa3e9f 736 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 737 u8 error;
738
a2fa3e9f 739 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 740 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 741 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
742 : "cc");
743 if (error)
744 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 745 vmx->vmcs, phys_addr);
6aa8b732
AK		 746 }
747
748 if (vcpu->cpu != cpu) {
749 struct descriptor_table dt;
750 unsigned long sysenter_esp;
751
752 vcpu->cpu = cpu;
753 /*
754 * Linux uses per-cpu TSS and GDT, so set these when switching
755 * processors.
756 */
d6e88aec
AK		 757 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
758 kvm_get_gdt(&dt);
6aa8b732
AK		 759 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
760
761 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
762 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 763
764 /*
765 * Make sure the time stamp counter is monotonous.
766 */
767 rdtscll(tsc_this);
019960ae
AK		 768 if (tsc_this < vcpu->arch.host_tsc) {
769 delta = vcpu->arch.host_tsc - tsc_this;
770 new_offset = vmcs_read64(TSC_OFFSET) + delta;
771 vmcs_write64(TSC_OFFSET, new_offset);
772 }
6aa8b732 773 }
6aa8b732
AK		 774}
775
776static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
777{
a9b21b62 778 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 779}
780
5fd86fcf
AK		 781static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
782{
783 if (vcpu->fpu_active)
784 return;
785 vcpu->fpu_active = 1;
707d92fa 786 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 787 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 788 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 789 update_exception_bitmap(vcpu);
790}
791
792static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
793{
794 if (!vcpu->fpu_active)
795 return;
796 vcpu->fpu_active = 0;
707d92fa 797 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 798 update_exception_bitmap(vcpu);
799}
800
6aa8b732
AK		 801static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
802{
345dcaa8
AK		 803 unsigned long rflags;
804
805 rflags = vmcs_readl(GUEST_RFLAGS);
806 if (to_vmx(vcpu)->rmode.vm86_active)
807 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
808 return rflags;
6aa8b732
AK		 809}
810
811static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
812{
7ffd92c5 813 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 814 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 815 vmcs_writel(GUEST_RFLAGS, rflags);
816}
817
2809f5d2
GC		 818static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819{
820 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 int ret = 0;
822
823 if (interruptibility & GUEST_INTR_STATE_STI)
824 ret |= X86_SHADOW_INT_STI;
825 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
826 ret |= X86_SHADOW_INT_MOV_SS;
827
828 return ret & mask;
829}
830
831static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
832{
833 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
834 u32 interruptibility = interruptibility_old;
835
836 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
837
838 if (mask & X86_SHADOW_INT_MOV_SS)
839 interruptibility |= GUEST_INTR_STATE_MOV_SS;
840 if (mask & X86_SHADOW_INT_STI)
841 interruptibility |= GUEST_INTR_STATE_STI;
842
843 if ((interruptibility != interruptibility_old))
844 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
845}
846
6aa8b732
AK		 847static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
848{
849 unsigned long rip;
6aa8b732 850
5fdbf976 851 rip = kvm_rip_read(vcpu);
6aa8b732 852 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 853 kvm_rip_write(vcpu, rip);
6aa8b732 854
2809f5d2
GC		 855 /* skipping an emulated instruction also counts */
856 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 857}
858
298101da
AK		 859static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
860 bool has_error_code, u32 error_code)
861{
77ab6db0 862 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 863 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 864
8ab2d2e2 865 if (has_error_code) {
77ab6db0 866 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 867 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
868 }
77ab6db0 869
7ffd92c5 870 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 871 vmx->rmode.irq.pending = true;
872 vmx->rmode.irq.vector = nr;
873 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 874 if (kvm_exception_is_soft(nr))
875 vmx->rmode.irq.rip +=
876 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 877 intr_info |= INTR_TYPE_SOFT_INTR;
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 879 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
880 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
881 return;
882 }
883
66fd3f7f
GN		 884 if (kvm_exception_is_soft(nr)) {
885 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
886 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 887 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
888 } else
889 intr_info |= INTR_TYPE_HARD_EXCEPTION;
890
891 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 892}
893
a75beee6
ED		 894/*
895 * Swap MSR entry in host/guest MSR entry array.
896 */
8b9cf98c 897static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 898{
26bb0981 899 struct shared_msr_entry tmp;
a2fa3e9f
GH		 900
901 tmp = vmx->guest_msrs[to];
902 vmx->guest_msrs[to] = vmx->guest_msrs[from];
903 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 904}
905
e38aea3e
AK		 906/*
907 * Set up the vmcs to automatically save and restore system
908 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
909 * mode, as fiddling with msrs is very expensive.
910 */
8b9cf98c 911static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 912{
26bb0981 913 int save_nmsrs, index;
5897297b 914 unsigned long *msr_bitmap;
e38aea3e 915
33f9c505 916 vmx_load_host_state(vmx);
a75beee6
ED		 917 save_nmsrs = 0;
918#ifdef CONFIG_X86_64
8b9cf98c 919 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 920 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 921 if (index >= 0)
8b9cf98c
RR		 922 move_msr_up(vmx, index, save_nmsrs++);
923 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 924 if (index >= 0)
8b9cf98c
RR		 925 move_msr_up(vmx, index, save_nmsrs++);
926 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 927 if (index >= 0)
8b9cf98c 928 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 929 /*
930 * MSR_K6_STAR is only needed on long mode guests, and only
931 * if efer.sce is enabled.
932 */
8b9cf98c 933 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 934 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 935 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 936 }
937#endif
92c0d900
AK		 938 index = __find_msr_index(vmx, MSR_EFER);
939 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 940 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 941
26bb0981 942 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 943
944 if (cpu_has_vmx_msr_bitmap()) {
945 if (is_long_mode(&vmx->vcpu))
946 msr_bitmap = vmx_msr_bitmap_longmode;
947 else
948 msr_bitmap = vmx_msr_bitmap_legacy;
949
950 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
951 }
e38aea3e
AK		 952}
953
6aa8b732
AK		 954/*
955 * reads and returns guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset -- 21.3
957 */
958static u64 guest_read_tsc(void)
959{
960 u64 host_tsc, tsc_offset;
961
962 rdtscll(host_tsc);
963 tsc_offset = vmcs_read64(TSC_OFFSET);
964 return host_tsc + tsc_offset;
965}
966
967/*
968 * writes 'guest_tsc' into guest's timestamp counter "register"
969 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
970 */
53f658b3 971static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 972{
6aa8b732
AK		 973 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
974}
975
6aa8b732
AK		 976/*
977 * Reads an msr value (of 'msr_index') into 'pdata'.
978 * Returns 0 on success, non-0 otherwise.
979 * Assumes vcpu_load() was already called.
980 */
981static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
982{
983 u64 data;
26bb0981 984 struct shared_msr_entry *msr;
6aa8b732
AK		 985
986 if (!pdata) {
987 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
988 return -EINVAL;
989 }
990
991 switch (msr_index) {
05b3e0c2 992#ifdef CONFIG_X86_64
6aa8b732
AK		 993 case MSR_FS_BASE:
994 data = vmcs_readl(GUEST_FS_BASE);
995 break;
996 case MSR_GS_BASE:
997 data = vmcs_readl(GUEST_GS_BASE);
998 break;
44ea2b17
AK		 999 case MSR_KERNEL_GS_BASE:
1000 vmx_load_host_state(to_vmx(vcpu));
1001 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1002 break;
26bb0981 1003#endif
6aa8b732 1004 case MSR_EFER:
3bab1f5d 1005 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1006 case MSR_IA32_TSC:
6aa8b732
AK		 1007 data = guest_read_tsc();
1008 break;
1009 case MSR_IA32_SYSENTER_CS:
1010 data = vmcs_read32(GUEST_SYSENTER_CS);
1011 break;
1012 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1013 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1014 break;
1015 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1016 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1017 break;
6aa8b732 1018 default:
26bb0981 1019 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1020 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1021 if (msr) {
542423b0 1022 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1023 data = msr->data;
1024 break;
6aa8b732 1025 }
3bab1f5d 1026 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1027 }
1028
1029 *pdata = data;
1030 return 0;
1031}
1032
1033/*
1034 * Writes msr value into into the appropriate "register".
1035 * Returns 0 on success, non-0 otherwise.
1036 * Assumes vcpu_load() was already called.
1037 */
1038static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1039{
a2fa3e9f 1040 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1041 struct shared_msr_entry *msr;
53f658b3 1042 u64 host_tsc;
2cc51560
ED		 1043 int ret = 0;
1044
6aa8b732 1045 switch (msr_index) {
3bab1f5d 1046 case MSR_EFER:
a9b21b62 1047 vmx_load_host_state(vmx);
2cc51560 1048 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1049 break;
16175a79 1050#ifdef CONFIG_X86_64
6aa8b732
AK		 1051 case MSR_FS_BASE:
1052 vmcs_writel(GUEST_FS_BASE, data);
1053 break;
1054 case MSR_GS_BASE:
1055 vmcs_writel(GUEST_GS_BASE, data);
1056 break;
44ea2b17
AK		 1057 case MSR_KERNEL_GS_BASE:
1058 vmx_load_host_state(vmx);
1059 vmx->msr_guest_kernel_gs_base = data;
1060 break;
6aa8b732
AK		 1061#endif
1062 case MSR_IA32_SYSENTER_CS:
1063 vmcs_write32(GUEST_SYSENTER_CS, data);
1064 break;
1065 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1066 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1067 break;
1068 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1069 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1070 break;
af24a4e4 1071 case MSR_IA32_TSC:
53f658b3
MT		 1072 rdtscll(host_tsc);
1073 guest_write_tsc(data, host_tsc);
6aa8b732 1074 break;
468d472f
SY		 1075 case MSR_IA32_CR_PAT:
1076 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1077 vmcs_write64(GUEST_IA32_PAT, data);
1078 vcpu->arch.pat = data;
1079 break;
1080 }
1081 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1082 default:
8b9cf98c 1083 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1084 if (msr) {
542423b0 1085 vmx_load_host_state(vmx);
3bab1f5d
AK		 1086 msr->data = data;
1087 break;
6aa8b732 1088 }
2cc51560 1089 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1090 }
1091
2cc51560 1092 return ret;
6aa8b732
AK		 1093}
1094
5fdbf976 1095static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1096{
5fdbf976
MT		 1097 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1098 switch (reg) {
1099 case VCPU_REGS_RSP:
1100 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1101 break;
1102 case VCPU_REGS_RIP:
1103 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1104 break;
6de4f3ad
AK		 1105 case VCPU_EXREG_PDPTR:
1106 if (enable_ept)
1107 ept_save_pdptrs(vcpu);
1108 break;
5fdbf976
MT		 1109 default:
1110 break;
1111 }
6aa8b732
AK		 1112}
1113
355be0b9 1114static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1115{
ae675ef0
JK		 1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1118 else
1119 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1120
abd3f2d6 1121 update_exception_bitmap(vcpu);
6aa8b732
AK		 1122}
1123
1124static __init int cpu_has_kvm_support(void)
1125{
6210e37b 1126 return cpu_has_vmx();
6aa8b732
AK		 1127}
1128
1129static __init int vmx_disabled_by_bios(void)
1130{
1131 u64 msr;
1132
1133 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1134 return (msr & (FEATURE_CONTROL_LOCKED |
1135 FEATURE_CONTROL_VMXON_ENABLED))
1136 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1137 /* locked but not enabled */
6aa8b732
AK		 1138}
1139
10474ae8 1140static int hardware_enable(void *garbage)
6aa8b732
AK		 1141{
1142 int cpu = raw_smp_processor_id();
1143 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1144 u64 old;
1145
10474ae8
AG		 1146 if (read_cr4() & X86_CR4_VMXE)
1147 return -EBUSY;
1148
543e4243 1149 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1150 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1151 if ((old & (FEATURE_CONTROL_LOCKED |
1152 FEATURE_CONTROL_VMXON_ENABLED))
1153 != (FEATURE_CONTROL_LOCKED |
1154 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1155 /* enable and lock */
62b3ffb8 1156 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1157 FEATURE_CONTROL_LOCKED |
1158 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1159 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1160 asm volatile (ASM_VMX_VMXON_RAX
1161 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1162 : "memory", "cc");
10474ae8
AG		 1163
1164 ept_sync_global();
1165
1166 return 0;
6aa8b732
AK		 1167}
1168
543e4243
AK		 1169static void vmclear_local_vcpus(void)
1170{
1171 int cpu = raw_smp_processor_id();
1172 struct vcpu_vmx *vmx, *n;
1173
1174 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1175 local_vcpus_link)
1176 __vcpu_clear(vmx);
1177}
1178
710ff4a8
EH		 1179
1180/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1181 * tricks.
1182 */
1183static void kvm_cpu_vmxoff(void)
6aa8b732 1184{
4ecac3fd 1185 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1186 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1187}
1188
710ff4a8
EH		 1189static void hardware_disable(void *garbage)
1190{
1191 vmclear_local_vcpus();
1192 kvm_cpu_vmxoff();
1193}
1194
1c3d14fe 1195static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1196 u32 msr, u32 *result)
1c3d14fe
YS		 1197{
1198 u32 vmx_msr_low, vmx_msr_high;
1199 u32 ctl = ctl_min | ctl_opt;
1200
1201 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1202
1203 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1204 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1205
1206 /* Ensure minimum (required) set of control bits are supported. */
1207 if (ctl_min & ~ctl)
002c7f7c 1208 return -EIO;
1c3d14fe
YS		 1209
1210 *result = ctl;
1211 return 0;
1212}
1213
002c7f7c 1214static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1215{
1216 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1217 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1218 u32 _pin_based_exec_control = 0;
1219 u32 _cpu_based_exec_control = 0;
f78e0e2e 1220 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1221 u32 _vmexit_control = 0;
1222 u32 _vmentry_control = 0;
1223
1224 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1225 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1226 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1227 &_pin_based_exec_control) < 0)
002c7f7c 1228 return -EIO;
1c3d14fe
YS		 1229
1230 min = CPU_BASED_HLT_EXITING |
1231#ifdef CONFIG_X86_64
1232 CPU_BASED_CR8_LOAD_EXITING |
1233 CPU_BASED_CR8_STORE_EXITING |
1234#endif
d56f546d
SY		 1235 CPU_BASED_CR3_LOAD_EXITING |
1236 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1237 CPU_BASED_USE_IO_BITMAPS |
1238 CPU_BASED_MOV_DR_EXITING |
a7052897 1239 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1240 CPU_BASED_MWAIT_EXITING |
1241 CPU_BASED_MONITOR_EXITING |
a7052897 1242 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1243 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1244 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1245 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1246 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1247 &_cpu_based_exec_control) < 0)
002c7f7c 1248 return -EIO;
6e5d865c
YS		 1249#ifdef CONFIG_X86_64
1250 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1251 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1252 ~CPU_BASED_CR8_STORE_EXITING;
1253#endif
f78e0e2e 1254 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1255 min2 = 0;
1256 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1257 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1258 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1259 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1260 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1262 if (adjust_vmx_controls(min2, opt2,
1263 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1264 &_cpu_based_2nd_exec_control) < 0)
1265 return -EIO;
1266 }
1267#ifndef CONFIG_X86_64
1268 if (!(_cpu_based_2nd_exec_control &
1269 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1270 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1271#endif
d56f546d 1272 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1273 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1274 enabled */
5fff7d27
GN		 1275 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1276 CPU_BASED_CR3_STORE_EXITING |
1277 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1278 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1279 vmx_capability.ept, vmx_capability.vpid);
1280 }
1c3d14fe
YS		 1281
1282 min = 0;
1283#ifdef CONFIG_X86_64
1284 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1285#endif
468d472f 1286 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1287 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1288 &_vmexit_control) < 0)
002c7f7c 1289 return -EIO;
1c3d14fe 1290
468d472f
SY		 1291 min = 0;
1292 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1293 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1294 &_vmentry_control) < 0)
002c7f7c 1295 return -EIO;
6aa8b732 1296
c68876fd 1297 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1298
1299 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1300 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1301 return -EIO;
1c3d14fe
YS		 1302
1303#ifdef CONFIG_X86_64
1304 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1305 if (vmx_msr_high & (1u<<16))
002c7f7c 1306 return -EIO;
1c3d14fe
YS		 1307#endif
1308
1309 /* Require Write-Back (WB) memory type for VMCS accesses. */
1310 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1311 return -EIO;
1c3d14fe 1312
002c7f7c
YS		 1313 vmcs_conf->size = vmx_msr_high & 0x1fff;
1314 vmcs_conf->order = get_order(vmcs_config.size);
1315 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1316
002c7f7c
YS		 1317 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1318 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1319 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1320 vmcs_conf->vmexit_ctrl = _vmexit_control;
1321 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1322
1323 return 0;
c68876fd 1324}
6aa8b732
AK		 1325
1326static struct vmcs *alloc_vmcs_cpu(int cpu)
1327{
1328 int node = cpu_to_node(cpu);
1329 struct page *pages;
1330 struct vmcs *vmcs;
1331
6484eb3e 1332 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1333 if (!pages)
1334 return NULL;
1335 vmcs = page_address(pages);
1c3d14fe
YS		 1336 memset(vmcs, 0, vmcs_config.size);
1337 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1338 return vmcs;
1339}
1340
1341static struct vmcs *alloc_vmcs(void)
1342{
d3b2c338 1343 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1344}
1345
1346static void free_vmcs(struct vmcs *vmcs)
1347{
1c3d14fe 1348 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1349}
1350
39959588 1351static void free_kvm_area(void)
6aa8b732
AK		 1352{
1353 int cpu;
1354
3230bb47 1355 for_each_possible_cpu(cpu) {
6aa8b732 1356 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1357 per_cpu(vmxarea, cpu) = NULL;
1358 }
6aa8b732
AK		 1359}
1360
6aa8b732
AK		 1361static __init int alloc_kvm_area(void)
1362{
1363 int cpu;
1364
3230bb47 1365 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1366 struct vmcs *vmcs;
1367
1368 vmcs = alloc_vmcs_cpu(cpu);
1369 if (!vmcs) {
1370 free_kvm_area();
1371 return -ENOMEM;
1372 }
1373
1374 per_cpu(vmxarea, cpu) = vmcs;
1375 }
1376 return 0;
1377}
1378
1379static __init int hardware_setup(void)
1380{
002c7f7c
YS		 1381 if (setup_vmcs_config(&vmcs_config) < 0)
1382 return -EIO;
50a37eb4
JR		 1383
1384 if (boot_cpu_has(X86_FEATURE_NX))
1385 kvm_enable_efer_bits(EFER_NX);
1386
93ba03c2
SY		 1387 if (!cpu_has_vmx_vpid())
1388 enable_vpid = 0;
1389
3a624e29 1390 if (!cpu_has_vmx_ept()) {
93ba03c2 1391 enable_ept = 0;
3a624e29
NK		 1392 enable_unrestricted_guest = 0;
1393 }
1394
1395 if (!cpu_has_vmx_unrestricted_guest())
1396 enable_unrestricted_guest = 0;
93ba03c2
SY		 1397
1398 if (!cpu_has_vmx_flexpriority())
1399 flexpriority_enabled = 0;
1400
95ba8273
GN		 1401 if (!cpu_has_vmx_tpr_shadow())
1402 kvm_x86_ops->update_cr8_intercept = NULL;
1403
54dee993
MT		 1404 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1405 kvm_disable_largepages();
1406
4b8d54f9
ZE		 1407 if (!cpu_has_vmx_ple())
1408 ple_gap = 0;
1409
6aa8b732
AK		 1410 return alloc_kvm_area();
1411}
1412
1413static __exit void hardware_unsetup(void)
1414{
1415 free_kvm_area();
1416}
1417
6aa8b732
AK		 1418static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1419{
1420 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1421
6af11b9e 1422 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1423 vmcs_write16(sf->selector, save->selector);
1424 vmcs_writel(sf->base, save->base);
1425 vmcs_write32(sf->limit, save->limit);
1426 vmcs_write32(sf->ar_bytes, save->ar);
1427 } else {
1428 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1429 << AR_DPL_SHIFT;
1430 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1431 }
1432}
1433
1434static void enter_pmode(struct kvm_vcpu *vcpu)
1435{
1436 unsigned long flags;
a89a8fb9 1437 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1438
a89a8fb9 1439 vmx->emulation_required = 1;
7ffd92c5 1440 vmx->rmode.vm86_active = 0;
6aa8b732 1441
7ffd92c5
AK		 1442 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1443 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1444 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1445
1446 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1447 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1448 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1449 vmcs_writel(GUEST_RFLAGS, flags);
1450
66aee91a
RR		 1451 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1452 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1453
1454 update_exception_bitmap(vcpu);
1455
a89a8fb9
MG		 1456 if (emulate_invalid_guest_state)
1457 return;
1458
7ffd92c5
AK		 1459 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1460 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1461 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1462 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1463
1464 vmcs_write16(GUEST_SS_SELECTOR, 0);
1465 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1466
1467 vmcs_write16(GUEST_CS_SELECTOR,
1468 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1469 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1470}
1471
d77c26fc 1472static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1473{
bfc6d222 1474 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1475 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1476 kvm->memslots[0].npages - 3;
1477 return base_gfn << PAGE_SHIFT;
1478 }
bfc6d222 1479 return kvm->arch.tss_addr;
6aa8b732
AK		 1480}
1481
1482static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1483{
1484 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1485
1486 save->selector = vmcs_read16(sf->selector);
1487 save->base = vmcs_readl(sf->base);
1488 save->limit = vmcs_read32(sf->limit);
1489 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1490 vmcs_write16(sf->selector, save->base >> 4);
1491 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1492 vmcs_write32(sf->limit, 0xffff);
1493 vmcs_write32(sf->ar_bytes, 0xf3);
1494}
1495
1496static void enter_rmode(struct kvm_vcpu *vcpu)
1497{
1498 unsigned long flags;
a89a8fb9 1499 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1500
3a624e29
NK		 1501 if (enable_unrestricted_guest)
1502 return;
1503
a89a8fb9 1504 vmx->emulation_required = 1;
7ffd92c5 1505 vmx->rmode.vm86_active = 1;
6aa8b732 1506
7ffd92c5 1507 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1508 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1509
7ffd92c5 1510 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1511 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1512
7ffd92c5 1513 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1514 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1515
1516 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1517 vmx->rmode.save_iopl
ad312c7c 1518 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1519
053de044 1520 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1521
1522 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1523 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1524 update_exception_bitmap(vcpu);
1525
a89a8fb9
MG		 1526 if (emulate_invalid_guest_state)
1527 goto continue_rmode;
1528
6aa8b732
AK		 1529 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1530 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1531 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1532
1533 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1534 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1535 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1536 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1537 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1538
7ffd92c5
AK		 1539 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1540 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1541 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1542 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1543
a89a8fb9 1544continue_rmode:
8668a3c4 1545 kvm_mmu_reset_context(vcpu);
b7ebfb05 1546 init_rmode(vcpu->kvm);
6aa8b732
AK		 1547}
1548
401d10de
AS		 1549static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1550{
1551 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1552 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1553
1554 if (!msr)
1555 return;
401d10de 1556
44ea2b17
AK		 1557 /*
1558 * Force kernel_gs_base reloading before EFER changes, as control
1559 * of this msr depends on is_long_mode().
1560 */
1561 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1562 vcpu->arch.shadow_efer = efer;
1563 if (!msr)
1564 return;
1565 if (efer & EFER_LMA) {
1566 vmcs_write32(VM_ENTRY_CONTROLS,
1567 vmcs_read32(VM_ENTRY_CONTROLS) |
1568 VM_ENTRY_IA32E_MODE);
1569 msr->data = efer;
1570 } else {
1571 vmcs_write32(VM_ENTRY_CONTROLS,
1572 vmcs_read32(VM_ENTRY_CONTROLS) &
1573 ~VM_ENTRY_IA32E_MODE);
1574
1575 msr->data = efer & ~EFER_LME;
1576 }
1577 setup_msrs(vmx);
1578}
1579
05b3e0c2 1580#ifdef CONFIG_X86_64
6aa8b732
AK		 1581
1582static void enter_lmode(struct kvm_vcpu *vcpu)
1583{
1584 u32 guest_tr_ar;
1585
1586 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1587 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1588 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1589 __func__);
6aa8b732
AK		 1590 vmcs_write32(GUEST_TR_AR_BYTES,
1591 (guest_tr_ar & ~AR_TYPE_MASK)
1592 | AR_TYPE_BUSY_64_TSS);
1593 }
ad312c7c 1594 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1595 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1596}
1597
1598static void exit_lmode(struct kvm_vcpu *vcpu)
1599{
ad312c7c 1600 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1601
1602 vmcs_write32(VM_ENTRY_CONTROLS,
1603 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1604 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1605}
1606
1607#endif
1608
2384d2b3
SY		 1609static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1610{
1611 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1612 if (enable_ept)
4e1096d2 1613 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1614}
1615
25c4c276 1616static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1617{
ad312c7c
ZX		 1618 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1619 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1620}
1621
1439442c
SY		 1622static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1623{
6de4f3ad
AK		 1624 if (!test_bit(VCPU_EXREG_PDPTR,
1625 (unsigned long *)&vcpu->arch.regs_dirty))
1626 return;
1627
1439442c 1628 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1629 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1630 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1631 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1632 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1633 }
1634}
1635
8f5d549f
AK		 1636static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1637{
1638 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1639 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1640 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1641 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1642 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1643 }
6de4f3ad
AK		 1644
1645 __set_bit(VCPU_EXREG_PDPTR,
1646 (unsigned long *)&vcpu->arch.regs_avail);
1647 __set_bit(VCPU_EXREG_PDPTR,
1648 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1649}
1650
1439442c
SY		 1651static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1652
1653static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1654 unsigned long cr0,
1655 struct kvm_vcpu *vcpu)
1656{
1657 if (!(cr0 & X86_CR0_PG)) {
1658 /* From paging/starting to nonpaging */
1659 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1660 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1661 (CPU_BASED_CR3_LOAD_EXITING |
1662 CPU_BASED_CR3_STORE_EXITING));
1663 vcpu->arch.cr0 = cr0;
1664 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1665 } else if (!is_paging(vcpu)) {
1666 /* From nonpaging to paging */
1667 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1668 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1669 ~(CPU_BASED_CR3_LOAD_EXITING |
1670 CPU_BASED_CR3_STORE_EXITING));
1671 vcpu->arch.cr0 = cr0;
1672 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1673 }
95eb84a7
SY		 1674
1675 if (!(cr0 & X86_CR0_WP))
1676 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1677}
1678
1679static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1680 struct kvm_vcpu *vcpu)
1681{
1682 if (!is_paging(vcpu)) {
1683 *hw_cr4 &= ~X86_CR4_PAE;
1684 *hw_cr4 |= X86_CR4_PSE;
1685 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1686 *hw_cr4 &= ~X86_CR4_PAE;
1687}
1688
6aa8b732
AK		 1689static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1690{
7ffd92c5 1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1692 unsigned long hw_cr0;
1693
1694 if (enable_unrestricted_guest)
1695 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1696 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1697 else
1698 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1699
5fd86fcf
AK		 1700 vmx_fpu_deactivate(vcpu);
1701
7ffd92c5 1702 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1703 enter_pmode(vcpu);
1704
7ffd92c5 1705 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1706 enter_rmode(vcpu);
1707
05b3e0c2 1708#ifdef CONFIG_X86_64
ad312c7c 1709 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1710 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1711 enter_lmode(vcpu);
707d92fa 1712 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1713 exit_lmode(vcpu);
1714 }
1715#endif
1716
089d034e 1717 if (enable_ept)
1439442c
SY		 1718 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1719
6aa8b732 1720 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1721 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1722 vcpu->arch.cr0 = cr0;
5fd86fcf 1723
707d92fa 1724 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1725 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1726}
1727
1439442c
SY		 1728static u64 construct_eptp(unsigned long root_hpa)
1729{
1730 u64 eptp;
1731
1732 /* TODO write the value reading from MSR */
1733 eptp = VMX_EPT_DEFAULT_MT |
1734 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1735 eptp |= (root_hpa & PAGE_MASK);
1736
1737 return eptp;
1738}
1739
6aa8b732
AK		 1740static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1741{
1439442c
SY		 1742 unsigned long guest_cr3;
1743 u64 eptp;
1744
1745 guest_cr3 = cr3;
089d034e 1746 if (enable_ept) {
1439442c
SY		 1747 eptp = construct_eptp(cr3);
1748 vmcs_write64(EPT_POINTER, eptp);
1439442c 1749 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1750 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1751 ept_load_pdptrs(vcpu);
1439442c
SY		 1752 }
1753
2384d2b3 1754 vmx_flush_tlb(vcpu);
1439442c 1755 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1756 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1757 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1758}
1759
1760static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1761{
7ffd92c5 1762 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1763 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1764
ad312c7c 1765 vcpu->arch.cr4 = cr4;
089d034e 1766 if (enable_ept)
1439442c
SY		 1767 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1768
1769 vmcs_writel(CR4_READ_SHADOW, cr4);
1770 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1771}
1772
6aa8b732
AK		 1773static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1774{
1775 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1776
1777 return vmcs_readl(sf->base);
1778}
1779
1780static void vmx_get_segment(struct kvm_vcpu *vcpu,
1781 struct kvm_segment *var, int seg)
1782{
1783 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1784 u32 ar;
1785
1786 var->base = vmcs_readl(sf->base);
1787 var->limit = vmcs_read32(sf->limit);
1788 var->selector = vmcs_read16(sf->selector);
1789 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1790 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1791 ar = 0;
1792 var->type = ar & 15;
1793 var->s = (ar >> 4) & 1;
1794 var->dpl = (ar >> 5) & 3;
1795 var->present = (ar >> 7) & 1;
1796 var->avl = (ar >> 12) & 1;
1797 var->l = (ar >> 13) & 1;
1798 var->db = (ar >> 14) & 1;
1799 var->g = (ar >> 15) & 1;
1800 var->unusable = (ar >> 16) & 1;
1801}
1802
2e4d2653
IE		 1803static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1804{
2e4d2653
IE		 1805 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1806 return 0;
1807
1808 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1809 return 3;
1810
eab4b8aa 1811 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1812}
1813
653e3108 1814static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1815{
6aa8b732
AK		 1816 u32 ar;
1817
653e3108 1818 if (var->unusable)
6aa8b732
AK		 1819 ar = 1 << 16;
1820 else {
1821 ar = var->type & 15;
1822 ar |= (var->s & 1) << 4;
1823 ar |= (var->dpl & 3) << 5;
1824 ar |= (var->present & 1) << 7;
1825 ar |= (var->avl & 1) << 12;
1826 ar |= (var->l & 1) << 13;
1827 ar |= (var->db & 1) << 14;
1828 ar |= (var->g & 1) << 15;
1829 }
f7fbf1fd
UL		 1830 if (ar == 0) /* a 0 value means unusable */
1831 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1832
1833 return ar;
1834}
1835
1836static void vmx_set_segment(struct kvm_vcpu *vcpu,
1837 struct kvm_segment *var, int seg)
1838{
7ffd92c5 1839 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1840 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1841 u32 ar;
1842
7ffd92c5
AK		 1843 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1844 vmx->rmode.tr.selector = var->selector;
1845 vmx->rmode.tr.base = var->base;
1846 vmx->rmode.tr.limit = var->limit;
1847 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1848 return;
1849 }
1850 vmcs_writel(sf->base, var->base);
1851 vmcs_write32(sf->limit, var->limit);
1852 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1853 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1854 /*
1855 * Hack real-mode segments into vm86 compatibility.
1856 */
1857 if (var->base == 0xffff0000 && var->selector == 0xf000)
1858 vmcs_writel(sf->base, 0xf0000);
1859 ar = 0xf3;
1860 } else
1861 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1862
1863 /*
1864 * Fix the "Accessed" bit in AR field of segment registers for older
1865 * qemu binaries.
1866 * IA32 arch specifies that at the time of processor reset the
1867 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1868 * is setting it to 0 in the usedland code. This causes invalid guest
1869 * state vmexit when "unrestricted guest" mode is turned on.
1870 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1871 * tree. Newer qemu binaries with that qemu fix would not need this
1872 * kvm hack.
1873 */
1874 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1875 ar |= 0x1; /* Accessed */
1876
6aa8b732
AK		 1877 vmcs_write32(sf->ar_bytes, ar);
1878}
1879
6aa8b732
AK		 1880static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1881{
1882 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1883
1884 *db = (ar >> 14) & 1;
1885 *l = (ar >> 13) & 1;
1886}
1887
1888static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1889{
1890 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1891 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1892}
1893
1894static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1895{
1896 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1897 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1898}
1899
1900static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1901{
1902 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1903 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1904}
1905
1906static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1907{
1908 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1909 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1910}
1911
648dfaa7
MG		 1912static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1913{
1914 struct kvm_segment var;
1915 u32 ar;
1916
1917 vmx_get_segment(vcpu, &var, seg);
1918 ar = vmx_segment_access_rights(&var);
1919
1920 if (var.base != (var.selector << 4))
1921 return false;
1922 if (var.limit != 0xffff)
1923 return false;
1924 if (ar != 0xf3)
1925 return false;
1926
1927 return true;
1928}
1929
1930static bool code_segment_valid(struct kvm_vcpu *vcpu)
1931{
1932 struct kvm_segment cs;
1933 unsigned int cs_rpl;
1934
1935 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1936 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1937
1872a3f4
AK		 1938 if (cs.unusable)
1939 return false;
648dfaa7
MG		 1940 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1941 return false;
1942 if (!cs.s)
1943 return false;
1872a3f4 1944 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1945 if (cs.dpl > cs_rpl)
1946 return false;
1872a3f4 1947 } else {
648dfaa7
MG		 1948 if (cs.dpl != cs_rpl)
1949 return false;
1950 }
1951 if (!cs.present)
1952 return false;
1953
1954 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1955 return true;
1956}
1957
1958static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1959{
1960 struct kvm_segment ss;
1961 unsigned int ss_rpl;
1962
1963 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1964 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1965
1872a3f4
AK		 1966 if (ss.unusable)
1967 return true;
1968 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1969 return false;
1970 if (!ss.s)
1971 return false;
1972 if (ss.dpl != ss_rpl) /* DPL != RPL */
1973 return false;
1974 if (!ss.present)
1975 return false;
1976
1977 return true;
1978}
1979
1980static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1981{
1982 struct kvm_segment var;
1983 unsigned int rpl;
1984
1985 vmx_get_segment(vcpu, &var, seg);
1986 rpl = var.selector & SELECTOR_RPL_MASK;
1987
1872a3f4
AK		 1988 if (var.unusable)
1989 return true;
648dfaa7
MG		 1990 if (!var.s)
1991 return false;
1992 if (!var.present)
1993 return false;
1994 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1995 if (var.dpl < rpl) /* DPL < RPL */
1996 return false;
1997 }
1998
1999 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2000 * rights flags
2001 */
2002 return true;
2003}
2004
2005static bool tr_valid(struct kvm_vcpu *vcpu)
2006{
2007 struct kvm_segment tr;
2008
2009 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2010
1872a3f4
AK		 2011 if (tr.unusable)
2012 return false;
648dfaa7
MG		 2013 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2014 return false;
1872a3f4 2015 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2016 return false;
2017 if (!tr.present)
2018 return false;
2019
2020 return true;
2021}
2022
2023static bool ldtr_valid(struct kvm_vcpu *vcpu)
2024{
2025 struct kvm_segment ldtr;
2026
2027 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2028
1872a3f4
AK		 2029 if (ldtr.unusable)
2030 return true;
648dfaa7
MG		 2031 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2032 return false;
2033 if (ldtr.type != 2)
2034 return false;
2035 if (!ldtr.present)
2036 return false;
2037
2038 return true;
2039}
2040
2041static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2042{
2043 struct kvm_segment cs, ss;
2044
2045 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2046 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2047
2048 return ((cs.selector & SELECTOR_RPL_MASK) ==
2049 (ss.selector & SELECTOR_RPL_MASK));
2050}
2051
2052/*
2053 * Check if guest state is valid. Returns true if valid, false if
2054 * not.
2055 * We assume that registers are always usable
2056 */
2057static bool guest_state_valid(struct kvm_vcpu *vcpu)
2058{
2059 /* real mode guest state checks */
2060 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2061 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2062 return false;
2063 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2064 return false;
2065 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2066 return false;
2067 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2068 return false;
2069 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2070 return false;
2071 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2072 return false;
2073 } else {
2074 /* protected mode guest state checks */
2075 if (!cs_ss_rpl_check(vcpu))
2076 return false;
2077 if (!code_segment_valid(vcpu))
2078 return false;
2079 if (!stack_segment_valid(vcpu))
2080 return false;
2081 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2082 return false;
2083 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2084 return false;
2085 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2086 return false;
2087 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2088 return false;
2089 if (!tr_valid(vcpu))
2090 return false;
2091 if (!ldtr_valid(vcpu))
2092 return false;
2093 }
2094 /* TODO:
2095 * - Add checks on RIP
2096 * - Add checks on RFLAGS
2097 */
2098
2099 return true;
2100}
2101
d77c26fc 2102static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2103{
6aa8b732 2104 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2105 u16 data = 0;
10589a46 2106 int ret = 0;
195aefde 2107 int r;
6aa8b732 2108
195aefde
IE		 2109 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2110 if (r < 0)
10589a46 2111 goto out;
195aefde 2112 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2113 r = kvm_write_guest_page(kvm, fn++, &data,
2114 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2115 if (r < 0)
10589a46 2116 goto out;
195aefde
IE		 2117 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2118 if (r < 0)
10589a46 2119 goto out;
195aefde
IE		 2120 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2121 if (r < 0)
10589a46 2122 goto out;
195aefde 2123 data = ~0;
10589a46
MT		 2124 r = kvm_write_guest_page(kvm, fn, &data,
2125 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2126 sizeof(u8));
195aefde 2127 if (r < 0)
10589a46
MT		 2128 goto out;
2129
2130 ret = 1;
2131out:
10589a46 2132 return ret;
6aa8b732
AK		 2133}
2134
b7ebfb05
SY		 2135static int init_rmode_identity_map(struct kvm *kvm)
2136{
2137 int i, r, ret;
2138 pfn_t identity_map_pfn;
2139 u32 tmp;
2140
089d034e 2141 if (!enable_ept)
b7ebfb05
SY		 2142 return 1;
2143 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2144 printk(KERN_ERR "EPT: identity-mapping pagetable "
2145 "haven't been allocated!\n");
2146 return 0;
2147 }
2148 if (likely(kvm->arch.ept_identity_pagetable_done))
2149 return 1;
2150 ret = 0;
b927a3ce 2151 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2152 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2153 if (r < 0)
2154 goto out;
2155 /* Set up identity-mapping pagetable for EPT in real mode */
2156 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2157 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2158 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2159 r = kvm_write_guest_page(kvm, identity_map_pfn,
2160 &tmp, i * sizeof(tmp), sizeof(tmp));
2161 if (r < 0)
2162 goto out;
2163 }
2164 kvm->arch.ept_identity_pagetable_done = true;
2165 ret = 1;
2166out:
2167 return ret;
2168}
2169
6aa8b732
AK		 2170static void seg_setup(int seg)
2171{
2172 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2173 unsigned int ar;
6aa8b732
AK		 2174
2175 vmcs_write16(sf->selector, 0);
2176 vmcs_writel(sf->base, 0);
2177 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2178 if (enable_unrestricted_guest) {
2179 ar = 0x93;
2180 if (seg == VCPU_SREG_CS)
2181 ar |= 0x08; /* code segment */
2182 } else
2183 ar = 0xf3;
2184
2185 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2186}
2187
f78e0e2e
SY		 2188static int alloc_apic_access_page(struct kvm *kvm)
2189{
2190 struct kvm_userspace_memory_region kvm_userspace_mem;
2191 int r = 0;
2192
72dc67a6 2193 down_write(&kvm->slots_lock);
bfc6d222 2194 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2195 goto out;
2196 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2197 kvm_userspace_mem.flags = 0;
2198 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2199 kvm_userspace_mem.memory_size = PAGE_SIZE;
2200 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2201 if (r)
2202 goto out;
72dc67a6 2203
bfc6d222 2204 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2205out:
72dc67a6 2206 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2207 return r;
2208}
2209
b7ebfb05
SY		 2210static int alloc_identity_pagetable(struct kvm *kvm)
2211{
2212 struct kvm_userspace_memory_region kvm_userspace_mem;
2213 int r = 0;
2214
2215 down_write(&kvm->slots_lock);
2216 if (kvm->arch.ept_identity_pagetable)
2217 goto out;
2218 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2219 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2220 kvm_userspace_mem.guest_phys_addr =
2221 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2222 kvm_userspace_mem.memory_size = PAGE_SIZE;
2223 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2224 if (r)
2225 goto out;
2226
b7ebfb05 2227 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2228 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2229out:
2230 up_write(&kvm->slots_lock);
2231 return r;
2232}
2233
2384d2b3
SY		 2234static void allocate_vpid(struct vcpu_vmx *vmx)
2235{
2236 int vpid;
2237
2238 vmx->vpid = 0;
919818ab 2239 if (!enable_vpid)
2384d2b3
SY		 2240 return;
2241 spin_lock(&vmx_vpid_lock);
2242 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2243 if (vpid < VMX_NR_VPIDS) {
2244 vmx->vpid = vpid;
2245 __set_bit(vpid, vmx_vpid_bitmap);
2246 }
2247 spin_unlock(&vmx_vpid_lock);
2248}
2249
5897297b 2250static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2251{
3e7c73e9 2252 int f = sizeof(unsigned long);
25c5f225
SY		 2253
2254 if (!cpu_has_vmx_msr_bitmap())
2255 return;
2256
2257 /*
2258 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2259 * have the write-low and read-high bitmap offsets the wrong way round.
2260 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2261 */
25c5f225 2262 if (msr <= 0x1fff) {
3e7c73e9
AK		 2263 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2264 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2265 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2266 msr &= 0x1fff;
3e7c73e9
AK		 2267 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2268 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2269 }
25c5f225
SY		 2270}
2271
5897297b
AK		 2272static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2273{
2274 if (!longmode_only)
2275 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2276 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2277}
2278
6aa8b732
AK		 2279/*
2280 * Sets up the vmcs for emulated real mode.
2281 */
8b9cf98c 2282static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2283{
468d472f 2284 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2285 u32 junk;
53f658b3 2286 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2287 unsigned long a;
2288 struct descriptor_table dt;
2289 int i;
cd2276a7 2290 unsigned long kvm_vmx_return;
6e5d865c 2291 u32 exec_control;
6aa8b732 2292
6aa8b732 2293 /* I/O */
3e7c73e9
AK		 2294 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2295 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2296
25c5f225 2297 if (cpu_has_vmx_msr_bitmap())
5897297b 2298 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2299
6aa8b732
AK		 2300 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2301
6aa8b732 2302 /* Control */
1c3d14fe
YS		 2303 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2304 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2305
2306 exec_control = vmcs_config.cpu_based_exec_ctrl;
2307 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2308 exec_control &= ~CPU_BASED_TPR_SHADOW;
2309#ifdef CONFIG_X86_64
2310 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2311 CPU_BASED_CR8_LOAD_EXITING;
2312#endif
2313 }
089d034e 2314 if (!enable_ept)
d56f546d 2315 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2316 CPU_BASED_CR3_LOAD_EXITING |
2317 CPU_BASED_INVLPG_EXITING;
6e5d865c 2318 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2319
83ff3b9d
SY		 2320 if (cpu_has_secondary_exec_ctrls()) {
2321 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2322 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2323 exec_control &=
2324 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2325 if (vmx->vpid == 0)
2326 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2327 if (!enable_ept) {
d56f546d 2328 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2329 enable_unrestricted_guest = 0;
2330 }
3a624e29
NK		 2331 if (!enable_unrestricted_guest)
2332 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2333 if (!ple_gap)
2334 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2335 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2336 }
f78e0e2e 2337
4b8d54f9
ZE		 2338 if (ple_gap) {
2339 vmcs_write32(PLE_GAP, ple_gap);
2340 vmcs_write32(PLE_WINDOW, ple_window);
2341 }
2342
c7addb90
AK		 2343 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2344 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2345 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2346
2347 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2348 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2349 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2350
2351 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2352 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2353 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2354 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2355 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2356 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2357#ifdef CONFIG_X86_64
6aa8b732
AK		 2358 rdmsrl(MSR_FS_BASE, a);
2359 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2360 rdmsrl(MSR_GS_BASE, a);
2361 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2362#else
2363 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2364 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2365#endif
2366
2367 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2368
d6e88aec 2369 kvm_get_idt(&dt);
6aa8b732
AK		 2370 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2371
d77c26fc 2372 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2373 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2374 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2376 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2377
2378 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2379 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2380 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2381 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2382 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2383 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2384
468d472f
SY		 2385 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2386 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2387 host_pat = msr_low | ((u64) msr_high << 32);
2388 vmcs_write64(HOST_IA32_PAT, host_pat);
2389 }
2390 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2391 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2392 host_pat = msr_low | ((u64) msr_high << 32);
2393 /* Write the default value follow host pat */
2394 vmcs_write64(GUEST_IA32_PAT, host_pat);
2395 /* Keep arch.pat sync with GUEST_IA32_PAT */
2396 vmx->vcpu.arch.pat = host_pat;
2397 }
2398
6aa8b732
AK		 2399 for (i = 0; i < NR_VMX_MSR; ++i) {
2400 u32 index = vmx_msr_index[i];
2401 u32 data_low, data_high;
2402 u64 data;
a2fa3e9f 2403 int j = vmx->nmsrs;
6aa8b732
AK		 2404
2405 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2406 continue;
432bd6cb
AK		 2407 if (wrmsr_safe(index, data_low, data_high) < 0)
2408 continue;
6aa8b732 2409 data = data_low | ((u64)data_high << 32);
26bb0981
AK		 2410 vmx->guest_msrs[j].index = i;
2411 vmx->guest_msrs[j].data = 0;
d5696725 2412 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2413 ++vmx->nmsrs;
6aa8b732 2414 }
6aa8b732 2415
1c3d14fe 2416 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2417
2418 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2419 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2420
e00c8cf2
AK		 2421 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2422 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2423
53f658b3
MT		 2424 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2425 rdtscll(tsc_this);
2426 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2427 tsc_base = tsc_this;
2428
2429 guest_write_tsc(0, tsc_base);
f78e0e2e 2430
e00c8cf2
AK		 2431 return 0;
2432}
2433
b7ebfb05
SY		 2434static int init_rmode(struct kvm *kvm)
2435{
2436 if (!init_rmode_tss(kvm))
2437 return 0;
2438 if (!init_rmode_identity_map(kvm))
2439 return 0;
2440 return 1;
2441}
2442
e00c8cf2
AK		 2443static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2444{
2445 struct vcpu_vmx *vmx = to_vmx(vcpu);
2446 u64 msr;
2447 int ret;
2448
5fdbf976 2449 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2450 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2451 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2452 ret = -ENOMEM;
2453 goto out;
2454 }
2455
7ffd92c5 2456 vmx->rmode.vm86_active = 0;
e00c8cf2 2457
3b86cd99
JK		 2458 vmx->soft_vnmi_blocked = 0;
2459
ad312c7c 2460 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2461 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2462 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2463 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2464 msr |= MSR_IA32_APICBASE_BSP;
2465 kvm_set_apic_base(&vmx->vcpu, msr);
2466
2467 fx_init(&vmx->vcpu);
2468
5706be0d 2469 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2470 /*
2471 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2472 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2473 */
c5af89b6 2474 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2475 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2476 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2477 } else {
ad312c7c
ZX		 2478 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2479 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2480 }
e00c8cf2
AK		 2481
2482 seg_setup(VCPU_SREG_DS);
2483 seg_setup(VCPU_SREG_ES);
2484 seg_setup(VCPU_SREG_FS);
2485 seg_setup(VCPU_SREG_GS);
2486 seg_setup(VCPU_SREG_SS);
2487
2488 vmcs_write16(GUEST_TR_SELECTOR, 0);
2489 vmcs_writel(GUEST_TR_BASE, 0);
2490 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2491 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2492
2493 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2494 vmcs_writel(GUEST_LDTR_BASE, 0);
2495 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2496 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2497
2498 vmcs_write32(GUEST_SYSENTER_CS, 0);
2499 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2500 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2501
2502 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2503 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2504 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2505 else
5fdbf976
MT		 2506 kvm_rip_write(vcpu, 0);
2507 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2508
e00c8cf2
AK		 2509 vmcs_writel(GUEST_DR7, 0x400);
2510
2511 vmcs_writel(GUEST_GDTR_BASE, 0);
2512 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2513
2514 vmcs_writel(GUEST_IDTR_BASE, 0);
2515 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2516
2517 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2518 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2519 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2520
e00c8cf2
AK		 2521 /* Special registers */
2522 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2523
2524 setup_msrs(vmx);
2525
6aa8b732
AK		 2526 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2527
f78e0e2e
SY		 2528 if (cpu_has_vmx_tpr_shadow()) {
2529 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2530 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2531 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2532 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2533 vmcs_write32(TPR_THRESHOLD, 0);
2534 }
2535
2536 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2537 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2538 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2539
2384d2b3
SY		 2540 if (vmx->vpid != 0)
2541 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2542
fa40052c 2543 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2544 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2545 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2546 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2547 vmx_fpu_activate(&vmx->vcpu);
2548 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2549
2384d2b3
SY		 2550 vpid_sync_vcpu_all(vmx);
2551
3200f405 2552 ret = 0;
6aa8b732 2553
a89a8fb9
MG		 2554 /* HACK: Don't enable emulation on guest boot/reset */
2555 vmx->emulation_required = 0;
2556
6aa8b732 2557out:
3200f405 2558 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2559 return ret;
2560}
2561
3b86cd99
JK		 2562static void enable_irq_window(struct kvm_vcpu *vcpu)
2563{
2564 u32 cpu_based_vm_exec_control;
2565
2566 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2567 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2568 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2569}
2570
2571static void enable_nmi_window(struct kvm_vcpu *vcpu)
2572{
2573 u32 cpu_based_vm_exec_control;
2574
2575 if (!cpu_has_virtual_nmis()) {
2576 enable_irq_window(vcpu);
2577 return;
2578 }
2579
2580 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2581 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2582 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2583}
2584
66fd3f7f 2585static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2586{
9c8cba37 2587 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2588 uint32_t intr;
2589 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2590
229456fc 2591 trace_kvm_inj_virq(irq);
2714d1d3 2592
fa89a817 2593 ++vcpu->stat.irq_injections;
7ffd92c5 2594 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2595 vmx->rmode.irq.pending = true;
2596 vmx->rmode.irq.vector = irq;
5fdbf976 2597 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2598 if (vcpu->arch.interrupt.soft)
2599 vmx->rmode.irq.rip +=
2600 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2602 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2603 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2604 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2605 return;
2606 }
66fd3f7f
GN		 2607 intr = irq | INTR_INFO_VALID_MASK;
2608 if (vcpu->arch.interrupt.soft) {
2609 intr |= INTR_TYPE_SOFT_INTR;
2610 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2611 vmx->vcpu.arch.event_exit_inst_len);
2612 } else
2613 intr |= INTR_TYPE_EXT_INTR;
2614 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2615}
2616
f08864b4
SY		 2617static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2618{
66a5a347
JK		 2619 struct vcpu_vmx *vmx = to_vmx(vcpu);
2620
3b86cd99
JK		 2621 if (!cpu_has_virtual_nmis()) {
2622 /*
2623 * Tracking the NMI-blocked state in software is built upon
2624 * finding the next open IRQ window. This, in turn, depends on
2625 * well-behaving guests: They have to keep IRQs disabled at
2626 * least as long as the NMI handler runs. Otherwise we may
2627 * cause NMI nesting, maybe breaking the guest. But as this is
2628 * highly unlikely, we can live with the residual risk.
2629 */
2630 vmx->soft_vnmi_blocked = 1;
2631 vmx->vnmi_blocked_time = 0;
2632 }
2633
487b391d 2634 ++vcpu->stat.nmi_injections;
7ffd92c5 2635 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2636 vmx->rmode.irq.pending = true;
2637 vmx->rmode.irq.vector = NMI_VECTOR;
2638 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2640 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2641 INTR_INFO_VALID_MASK);
2642 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2643 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2644 return;
2645 }
f08864b4
SY		 2646 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2647 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2648}
2649
c4282df9 2650static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2651{
3b86cd99 2652 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2653 return 0;
33f089ca 2654
c4282df9
GN		 2655 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2656 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2657 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2658}
2659
3cfc3092
JK		 2660static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2661{
2662 if (!cpu_has_virtual_nmis())
2663 return to_vmx(vcpu)->soft_vnmi_blocked;
2664 else
2665 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2666 GUEST_INTR_STATE_NMI);
2667}
2668
2669static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2670{
2671 struct vcpu_vmx *vmx = to_vmx(vcpu);
2672
2673 if (!cpu_has_virtual_nmis()) {
2674 if (vmx->soft_vnmi_blocked != masked) {
2675 vmx->soft_vnmi_blocked = masked;
2676 vmx->vnmi_blocked_time = 0;
2677 }
2678 } else {
2679 if (masked)
2680 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2681 GUEST_INTR_STATE_NMI);
2682 else
2683 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2684 GUEST_INTR_STATE_NMI);
2685 }
2686}
2687
78646121
GN		 2688static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2689{
c4282df9
GN		 2690 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2691 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2692 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2693}
2694
cbc94022
IE		 2695static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2696{
2697 int ret;
2698 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2699 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2700 .guest_phys_addr = addr,
2701 .memory_size = PAGE_SIZE * 3,
2702 .flags = 0,
2703 };
2704
2705 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2706 if (ret)
2707 return ret;
bfc6d222 2708 kvm->arch.tss_addr = addr;
cbc94022
IE		 2709 return 0;
2710}
2711
6aa8b732
AK		 2712static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2713 int vec, u32 err_code)
2714{
b3f37707
NK		 2715 /*
2716 * Instruction with address size override prefix opcode 0x67
2717 * Cause the #SS fault with 0 error code in VM86 mode.
2718 */
2719 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2720 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2721 return 1;
77ab6db0
JK		 2722 /*
2723 * Forward all other exceptions that are valid in real mode.
2724 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2725 * the required debugging infrastructure rework.
2726 */
2727 switch (vec) {
77ab6db0 2728 case DB_VECTOR:
d0bfb940
JK		 2729 if (vcpu->guest_debug &
2730 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2731 return 0;
2732 kvm_queue_exception(vcpu, vec);
2733 return 1;
77ab6db0 2734 case BP_VECTOR:
d0bfb940
JK		 2735 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2736 return 0;
2737 /* fall through */
2738 case DE_VECTOR:
77ab6db0
JK		 2739 case OF_VECTOR:
2740 case BR_VECTOR:
2741 case UD_VECTOR:
2742 case DF_VECTOR:
2743 case SS_VECTOR:
2744 case GP_VECTOR:
2745 case MF_VECTOR:
2746 kvm_queue_exception(vcpu, vec);
2747 return 1;
2748 }
6aa8b732
AK		 2749 return 0;
2750}
2751
a0861c02
AK		 2752/*
2753 * Trigger machine check on the host. We assume all the MSRs are already set up
2754 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2755 * We pass a fake environment to the machine check handler because we want
2756 * the guest to be always treated like user space, no matter what context
2757 * it used internally.
2758 */
2759static void kvm_machine_check(void)
2760{
2761#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2762 struct pt_regs regs = {
2763 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2764 .flags = X86_EFLAGS_IF,
2765 };
2766
2767 do_machine_check(&regs, 0);
2768#endif
2769}
2770
851ba692 2771static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2772{
2773 /* already handled by vcpu_run */
2774 return 1;
2775}
2776
851ba692 2777static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2778{
1155f76a 2779 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2780 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2781 u32 intr_info, ex_no, error_code;
42dbaa5a 2782 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2783 u32 vect_info;
2784 enum emulation_result er;
2785
1155f76a 2786 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2787 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2788
a0861c02 2789 if (is_machine_check(intr_info))
851ba692 2790 return handle_machine_check(vcpu);
a0861c02 2791
6aa8b732 2792 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2793 !is_page_fault(intr_info)) {
2794 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2795 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2796 vcpu->run->internal.ndata = 2;
2797 vcpu->run->internal.data[0] = vect_info;
2798 vcpu->run->internal.data[1] = intr_info;
2799 return 0;
2800 }
6aa8b732 2801
e4a41889 2802 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2803 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2804
2805 if (is_no_device(intr_info)) {
5fd86fcf 2806 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2807 return 1;
2808 }
2809
7aa81cc0 2810 if (is_invalid_opcode(intr_info)) {
851ba692 2811 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2812 if (er != EMULATE_DONE)
7ee5d940 2813 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2814 return 1;
2815 }
2816
6aa8b732 2817 error_code = 0;
5fdbf976 2818 rip = kvm_rip_read(vcpu);
2e11384c 2819 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2820 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2821 if (is_page_fault(intr_info)) {
1439442c 2822 /* EPT won't cause page fault directly */
089d034e 2823 if (enable_ept)
1439442c 2824 BUG();
6aa8b732 2825 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2826 trace_kvm_page_fault(cr2, error_code);
2827
3298b75c 2828 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2829 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2830 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2831 }
2832
7ffd92c5 2833 if (vmx->rmode.vm86_active &&
6aa8b732 2834 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2835 error_code)) {
ad312c7c
ZX		 2836 if (vcpu->arch.halt_request) {
2837 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2838 return kvm_emulate_halt(vcpu);
2839 }
6aa8b732 2840 return 1;
72d6e5a0 2841 }
6aa8b732 2842
d0bfb940 2843 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2844 switch (ex_no) {
2845 case DB_VECTOR:
2846 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2847 if (!(vcpu->guest_debug &
2848 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2849 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2850 kvm_queue_exception(vcpu, DB_VECTOR);
2851 return 1;
2852 }
2853 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2854 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2855 /* fall through */
2856 case BP_VECTOR:
6aa8b732 2857 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2858 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2859 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2860 break;
2861 default:
d0bfb940
JK		 2862 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2863 kvm_run->ex.exception = ex_no;
2864 kvm_run->ex.error_code = error_code;
42dbaa5a 2865 break;
6aa8b732 2866 }
6aa8b732
AK		 2867 return 0;
2868}
2869
851ba692 2870static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2871{
1165f5fe 2872 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2873 return 1;
2874}
2875
851ba692 2876static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2877{
851ba692 2878 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2879 return 0;
2880}
6aa8b732 2881
851ba692 2882static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2883{
bfdaab09 2884 unsigned long exit_qualification;
34c33d16 2885 int size, in, string;
039576c0 2886 unsigned port;
6aa8b732 2887
1165f5fe 2888 ++vcpu->stat.io_exits;
bfdaab09 2889 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2890 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2891
2892 if (string) {
851ba692 2893 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2894 return 0;
2895 return 1;
2896 }
2897
2898 size = (exit_qualification & 7) + 1;
2899 in = (exit_qualification & 8) != 0;
039576c0 2900 port = exit_qualification >> 16;
e70669ab 2901
e93f36bc 2902 skip_emulated_instruction(vcpu);
851ba692 2903 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2904}
2905
102d8325
IM		 2906static void
2907vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2908{
2909 /*
2910 * Patch in the VMCALL instruction:
2911 */
2912 hypercall[0] = 0x0f;
2913 hypercall[1] = 0x01;
2914 hypercall[2] = 0xc1;
102d8325
IM		 2915}
2916
851ba692 2917static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2918{
229456fc 2919 unsigned long exit_qualification, val;
6aa8b732
AK		 2920 int cr;
2921 int reg;
2922
bfdaab09 2923 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2924 cr = exit_qualification & 15;
2925 reg = (exit_qualification >> 8) & 15;
2926 switch ((exit_qualification >> 4) & 3) {
2927 case 0: /* mov to cr */
229456fc
MT		 2928 val = kvm_register_read(vcpu, reg);
2929 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2930 switch (cr) {
2931 case 0:
229456fc 2932 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2933 skip_emulated_instruction(vcpu);
2934 return 1;
2935 case 3:
229456fc 2936 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2937 skip_emulated_instruction(vcpu);
2938 return 1;
2939 case 4:
229456fc 2940 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2941 skip_emulated_instruction(vcpu);
2942 return 1;
0a5fff19
GN		 2943 case 8: {
2944 u8 cr8_prev = kvm_get_cr8(vcpu);
2945 u8 cr8 = kvm_register_read(vcpu, reg);
2946 kvm_set_cr8(vcpu, cr8);
2947 skip_emulated_instruction(vcpu);
2948 if (irqchip_in_kernel(vcpu->kvm))
2949 return 1;
2950 if (cr8_prev <= cr8)
2951 return 1;
851ba692 2952 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2953 return 0;
2954 }
6aa8b732
AK		 2955 };
2956 break;
25c4c276 2957 case 2: /* clts */
5fd86fcf 2958 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2959 vcpu->arch.cr0 &= ~X86_CR0_TS;
2960 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2961 vmx_fpu_activate(vcpu);
25c4c276
AL		 2962 skip_emulated_instruction(vcpu);
2963 return 1;
6aa8b732
AK		 2964 case 1: /*mov from cr*/
2965 switch (cr) {
2966 case 3:
5fdbf976 2967 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2968 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2969 skip_emulated_instruction(vcpu);
2970 return 1;
2971 case 8:
229456fc
MT		 2972 val = kvm_get_cr8(vcpu);
2973 kvm_register_write(vcpu, reg, val);
2974 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2975 skip_emulated_instruction(vcpu);
2976 return 1;
2977 }
2978 break;
2979 case 3: /* lmsw */
2d3ad1f4 2980 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2981
2982 skip_emulated_instruction(vcpu);
2983 return 1;
2984 default:
2985 break;
2986 }
851ba692 2987 vcpu->run->exit_reason = 0;
f0242478 2988 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2989 (int)(exit_qualification >> 4) & 3, cr);
2990 return 0;
2991}
2992
851ba692 2993static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2994{
bfdaab09 2995 unsigned long exit_qualification;
6aa8b732
AK		 2996 unsigned long val;
2997 int dr, reg;
2998
0a79b009
AK		 2999 if (!kvm_require_cpl(vcpu, 0))
3000 return 1;
42dbaa5a
JK		 3001 dr = vmcs_readl(GUEST_DR7);
3002 if (dr & DR7_GD) {
3003 /*
3004 * As the vm-exit takes precedence over the debug trap, we
3005 * need to emulate the latter, either for the host or the
3006 * guest debugging itself.
3007 */
3008 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3009 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3010 vcpu->run->debug.arch.dr7 = dr;
3011 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3012 vmcs_readl(GUEST_CS_BASE) +
3013 vmcs_readl(GUEST_RIP);
851ba692
AK		 3014 vcpu->run->debug.arch.exception = DB_VECTOR;
3015 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3016 return 0;
3017 } else {
3018 vcpu->arch.dr7 &= ~DR7_GD;
3019 vcpu->arch.dr6 |= DR6_BD;
3020 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3021 kvm_queue_exception(vcpu, DB_VECTOR);
3022 return 1;
3023 }
3024 }
3025
bfdaab09 3026 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3027 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3028 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3029 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3030 switch (dr) {
42dbaa5a
JK		 3031 case 0 ... 3:
3032 val = vcpu->arch.db[dr];
3033 break;
6aa8b732 3034 case 6:
42dbaa5a 3035 val = vcpu->arch.dr6;
6aa8b732
AK		 3036 break;
3037 case 7:
42dbaa5a 3038 val = vcpu->arch.dr7;
6aa8b732
AK		 3039 break;
3040 default:
3041 val = 0;
3042 }
5fdbf976 3043 kvm_register_write(vcpu, reg, val);
6aa8b732 3044 } else {
42dbaa5a
JK		 3045 val = vcpu->arch.regs[reg];
3046 switch (dr) {
3047 case 0 ... 3:
3048 vcpu->arch.db[dr] = val;
3049 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3050 vcpu->arch.eff_db[dr] = val;
3051 break;
3052 case 4 ... 5:
3053 if (vcpu->arch.cr4 & X86_CR4_DE)
3054 kvm_queue_exception(vcpu, UD_VECTOR);
3055 break;
3056 case 6:
3057 if (val & 0xffffffff00000000ULL) {
3058 kvm_queue_exception(vcpu, GP_VECTOR);
3059 break;
3060 }
3061 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3062 break;
3063 case 7:
3064 if (val & 0xffffffff00000000ULL) {
3065 kvm_queue_exception(vcpu, GP_VECTOR);
3066 break;
3067 }
3068 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3069 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3070 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3071 vcpu->arch.switch_db_regs =
3072 (val & DR7_BP_EN_MASK);
3073 }
3074 break;
3075 }
6aa8b732 3076 }
6aa8b732
AK		 3077 skip_emulated_instruction(vcpu);
3078 return 1;
3079}
3080
851ba692 3081static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3082{
06465c5a
AK		 3083 kvm_emulate_cpuid(vcpu);
3084 return 1;
6aa8b732
AK		 3085}
3086
851ba692 3087static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3088{
ad312c7c 3089 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3090 u64 data;
3091
3092 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3093 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3094 return 1;
3095 }
3096
229456fc 3097 trace_kvm_msr_read(ecx, data);
2714d1d3 3098
6aa8b732 3099 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3100 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3101 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3102 skip_emulated_instruction(vcpu);
3103 return 1;
3104}
3105
851ba692 3106static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3107{
ad312c7c
ZX		 3108 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3109 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3110 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3111
229456fc 3112 trace_kvm_msr_write(ecx, data);
2714d1d3 3113
6aa8b732 3114 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3115 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3116 return 1;
3117 }
3118
3119 skip_emulated_instruction(vcpu);
3120 return 1;
3121}
3122
851ba692 3123static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3124{
3125 return 1;
3126}
3127
851ba692 3128static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3129{
85f455f7
ED		 3130 u32 cpu_based_vm_exec_control;
3131
3132 /* clear pending irq */
3133 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3134 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3135 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3136
a26bf12a 3137 ++vcpu->stat.irq_window_exits;
2714d1d3 3138
c1150d8c
DL		 3139 /*
3140 * If the user space waits to inject interrupts, exit as soon as
3141 * possible
3142 */
8061823a 3143 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3144 vcpu->run->request_interrupt_window &&
8061823a 3145 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3146 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3147 return 0;
3148 }
6aa8b732
AK		 3149 return 1;
3150}
3151
851ba692 3152static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3153{
3154 skip_emulated_instruction(vcpu);
d3bef15f 3155 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3156}
3157
851ba692 3158static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3159{
510043da 3160 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3161 kvm_emulate_hypercall(vcpu);
3162 return 1;
c21415e8
IM		 3163}
3164
851ba692 3165static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3166{
3167 kvm_queue_exception(vcpu, UD_VECTOR);
3168 return 1;
3169}
3170
851ba692 3171static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3172{
f9c617f6 3173 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3174
3175 kvm_mmu_invlpg(vcpu, exit_qualification);
3176 skip_emulated_instruction(vcpu);
3177 return 1;
3178}
3179
851ba692 3180static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3181{
3182 skip_emulated_instruction(vcpu);
3183 /* TODO: Add support for VT-d/pass-through device */
3184 return 1;
3185}
3186
851ba692 3187static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3188{
f9c617f6 3189 unsigned long exit_qualification;
f78e0e2e
SY		 3190 enum emulation_result er;
3191 unsigned long offset;
3192
f9c617f6 3193 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3194 offset = exit_qualification & 0xffful;
3195
851ba692 3196 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3197
3198 if (er != EMULATE_DONE) {
3199 printk(KERN_ERR
3200 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3201 offset);
7f582ab6 3202 return -ENOEXEC;
f78e0e2e
SY		 3203 }
3204 return 1;
3205}
3206
851ba692 3207static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3208{
60637aac 3209 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3210 unsigned long exit_qualification;
3211 u16 tss_selector;
64a7ec06
GN		 3212 int reason, type, idt_v;
3213
3214 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3215 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3216
3217 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3218
3219 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3220 if (reason == TASK_SWITCH_GATE && idt_v) {
3221 switch (type) {
3222 case INTR_TYPE_NMI_INTR:
3223 vcpu->arch.nmi_injected = false;
3224 if (cpu_has_virtual_nmis())
3225 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3226 GUEST_INTR_STATE_NMI);
3227 break;
3228 case INTR_TYPE_EXT_INTR:
66fd3f7f 3229 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3230 kvm_clear_interrupt_queue(vcpu);
3231 break;
3232 case INTR_TYPE_HARD_EXCEPTION:
3233 case INTR_TYPE_SOFT_EXCEPTION:
3234 kvm_clear_exception_queue(vcpu);
3235 break;
3236 default:
3237 break;
3238 }
60637aac 3239 }
37817f29
IE		 3240 tss_selector = exit_qualification;
3241
64a7ec06
GN		 3242 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3243 type != INTR_TYPE_EXT_INTR &&
3244 type != INTR_TYPE_NMI_INTR))
3245 skip_emulated_instruction(vcpu);
3246
42dbaa5a
JK		 3247 if (!kvm_task_switch(vcpu, tss_selector, reason))
3248 return 0;
3249
3250 /* clear all local breakpoint enable flags */
3251 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3252
3253 /*
3254 * TODO: What about debug traps on tss switch?
3255 * Are we supposed to inject them and update dr6?
3256 */
3257
3258 return 1;
37817f29
IE		 3259}
3260
851ba692 3261static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3262{
f9c617f6 3263 unsigned long exit_qualification;
1439442c 3264 gpa_t gpa;
1439442c 3265 int gla_validity;
1439442c 3266
f9c617f6 3267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3268
3269 if (exit_qualification & (1 << 6)) {
3270 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3271 return -EINVAL;
1439442c
SY		 3272 }
3273
3274 gla_validity = (exit_qualification >> 7) & 0x3;
3275 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3276 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3277 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3278 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3279 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3280 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3281 (long unsigned int)exit_qualification);
851ba692
AK		 3282 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3283 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3284 return 0;
1439442c
SY		 3285 }
3286
3287 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3288 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3289 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3290}
3291
68f89400
MT		 3292static u64 ept_rsvd_mask(u64 spte, int level)
3293{
3294 int i;
3295 u64 mask = 0;
3296
3297 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3298 mask |= (1ULL << i);
3299
3300 if (level > 2)
3301 /* bits 7:3 reserved */
3302 mask |= 0xf8;
3303 else if (level == 2) {
3304 if (spte & (1ULL << 7))
3305 /* 2MB ref, bits 20:12 reserved */
3306 mask |= 0x1ff000;
3307 else
3308 /* bits 6:3 reserved */
3309 mask |= 0x78;
3310 }
3311
3312 return mask;
3313}
3314
3315static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3316 int level)
3317{
3318 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3319
3320 /* 010b (write-only) */
3321 WARN_ON((spte & 0x7) == 0x2);
3322
3323 /* 110b (write/execute) */
3324 WARN_ON((spte & 0x7) == 0x6);
3325
3326 /* 100b (execute-only) and value not supported by logical processor */
3327 if (!cpu_has_vmx_ept_execute_only())
3328 WARN_ON((spte & 0x7) == 0x4);
3329
3330 /* not 000b */
3331 if ((spte & 0x7)) {
3332 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3333
3334 if (rsvd_bits != 0) {
3335 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3336 __func__, rsvd_bits);
3337 WARN_ON(1);
3338 }
3339
3340 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3341 u64 ept_mem_type = (spte & 0x38) >> 3;
3342
3343 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3344 ept_mem_type == 7) {
3345 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3346 __func__, ept_mem_type);
3347 WARN_ON(1);
3348 }
3349 }
3350 }
3351}
3352
851ba692 3353static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3354{
3355 u64 sptes[4];
3356 int nr_sptes, i;
3357 gpa_t gpa;
3358
3359 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3360
3361 printk(KERN_ERR "EPT: Misconfiguration.\n");
3362 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3363
3364 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3365
3366 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3367 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3368
851ba692
AK		 3369 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3370 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3371
3372 return 0;
3373}
3374
851ba692 3375static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3376{
3377 u32 cpu_based_vm_exec_control;
3378
3379 /* clear pending NMI */
3380 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3381 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3382 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3383 ++vcpu->stat.nmi_window_exits;
3384
3385 return 1;
3386}
3387
80ced186 3388static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3389{
8b3079a5
AK		 3390 struct vcpu_vmx *vmx = to_vmx(vcpu);
3391 enum emulation_result err = EMULATE_DONE;
80ced186 3392 int ret = 1;
ea953ef0
MG		 3393
3394 while (!guest_state_valid(vcpu)) {
851ba692 3395 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3396
80ced186
MG		 3397 if (err == EMULATE_DO_MMIO) {
3398 ret = 0;
3399 goto out;
3400 }
1d5a4d9b
GT		 3401
3402 if (err != EMULATE_DONE) {
3403 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3404 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3405 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3406 vcpu->run->internal.ndata = 0;
80ced186
MG		 3407 ret = 0;
3408 goto out;
ea953ef0
MG		 3409 }
3410
3411 if (signal_pending(current))
80ced186 3412 goto out;
ea953ef0
MG		 3413 if (need_resched())
3414 schedule();
3415 }
3416
80ced186
MG		 3417 vmx->emulation_required = 0;
3418out:
3419 return ret;
ea953ef0
MG		 3420}
3421
4b8d54f9
ZE		 3422/*
3423 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3424 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3425 */
9fb41ba8 3426static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3427{
3428 skip_emulated_instruction(vcpu);
3429 kvm_vcpu_on_spin(vcpu);
3430
3431 return 1;
3432}
3433
59708670
SY		 3434static int handle_invalid_op(struct kvm_vcpu *vcpu)
3435{
3436 kvm_queue_exception(vcpu, UD_VECTOR);
3437 return 1;
3438}
3439
6aa8b732
AK		 3440/*
3441 * The exit handlers return 1 if the exit was handled fully and guest execution
3442 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3443 * to be done to userspace and return 0.
3444 */
851ba692 3445static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3446 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3447 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3448 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3449 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3450 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3451 [EXIT_REASON_CR_ACCESS] = handle_cr,
3452 [EXIT_REASON_DR_ACCESS] = handle_dr,
3453 [EXIT_REASON_CPUID] = handle_cpuid,
3454 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3455 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3456 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3457 [EXIT_REASON_HLT] = handle_halt,
a7052897 3458 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3459 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3460 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3461 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3462 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3463 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3464 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3465 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3466 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3467 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3468 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3469 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3470 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3471 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3472 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3473 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3474 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3475 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3476 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3477 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3478 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3479};
3480
3481static const int kvm_vmx_max_exit_handlers =
50a3485c 3482 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3483
3484/*
3485 * The guest has exited. See if we can fix it or if we need userspace
3486 * assistance.
3487 */
851ba692 3488static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3489{
29bd8a78 3490 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3491 u32 exit_reason = vmx->exit_reason;
1155f76a 3492 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3493
229456fc 3494 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3495
80ced186
MG		 3496 /* If guest state is invalid, start emulating */
3497 if (vmx->emulation_required && emulate_invalid_guest_state)
3498 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3499
1439442c
SY		 3500 /* Access CR3 don't cause VMExit in paging mode, so we need
3501 * to sync with guest real CR3. */
6de4f3ad 3502 if (enable_ept && is_paging(vcpu))
1439442c 3503 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3504
29bd8a78 3505 if (unlikely(vmx->fail)) {
851ba692
AK		 3506 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3507 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3508 = vmcs_read32(VM_INSTRUCTION_ERROR);
3509 return 0;
3510 }
6aa8b732 3511
d77c26fc 3512 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3513 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3514 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3515 exit_reason != EXIT_REASON_TASK_SWITCH))
3516 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3517 "(0x%x) and exit reason is 0x%x\n",
3518 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3519
3520 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3521 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3522 vmx->soft_vnmi_blocked = 0;
3b86cd99 3523 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3524 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3525 /*
3526 * This CPU don't support us in finding the end of an
3527 * NMI-blocked window if the guest runs with IRQs
3528 * disabled. So we pull the trigger after 1 s of
3529 * futile waiting, but inform the user about this.
3530 */
3531 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3532 "state on VCPU %d after 1 s timeout\n",
3533 __func__, vcpu->vcpu_id);
3534 vmx->soft_vnmi_blocked = 0;
3b86cd99 3535 }
3b86cd99
JK		 3536 }
3537
6aa8b732
AK		 3538 if (exit_reason < kvm_vmx_max_exit_handlers
3539 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3540 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3541 else {
851ba692
AK		 3542 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3543 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3544 }
3545 return 0;
3546}
3547
95ba8273 3548static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3549{
95ba8273 3550 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3551 vmcs_write32(TPR_THRESHOLD, 0);
3552 return;
3553 }
3554
95ba8273 3555 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3556}
3557
cf393f75
AK		 3558static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3559{
3560 u32 exit_intr_info;
7b4a25cb 3561 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3562 bool unblock_nmi;
3563 u8 vector;
668f612f
AK		 3564 int type;
3565 bool idtv_info_valid;
cf393f75
AK		 3566
3567 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3568
a0861c02
AK		 3569 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3570
3571 /* Handle machine checks before interrupts are enabled */
3572 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3573 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3574 && is_machine_check(exit_intr_info)))
3575 kvm_machine_check();
3576
20f65983
GN		 3577 /* We need to handle NMIs before interrupts are enabled */
3578 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3579 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3580 asm("int $2");
20f65983
GN		 3581
3582 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3583
cf393f75
AK		 3584 if (cpu_has_virtual_nmis()) {
3585 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3586 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3587 /*
7b4a25cb 3588 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3589 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3590 * a guest IRET fault.
7b4a25cb
GN		 3591 * SDM 3: 23.2.2 (September 2008)
3592 * Bit 12 is undefined in any of the following cases:
3593 * If the VM exit sets the valid bit in the IDT-vectoring
3594 * information field.
3595 * If the VM exit is due to a double fault.
cf393f75 3596 */
7b4a25cb
GN		 3597 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3598 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3599 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3600 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3601 } else if (unlikely(vmx->soft_vnmi_blocked))
3602 vmx->vnmi_blocked_time +=
3603 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3604
37b96e98
GN		 3605 vmx->vcpu.arch.nmi_injected = false;
3606 kvm_clear_exception_queue(&vmx->vcpu);
3607 kvm_clear_interrupt_queue(&vmx->vcpu);
3608
3609 if (!idtv_info_valid)
3610 return;
3611
668f612f
AK		 3612 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3613 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3614
64a7ec06 3615 switch (type) {
37b96e98
GN		 3616 case INTR_TYPE_NMI_INTR:
3617 vmx->vcpu.arch.nmi_injected = true;
668f612f 3618 /*
7b4a25cb 3619 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3620 * Clear bit "block by NMI" before VM entry if a NMI
3621 * delivery faulted.
668f612f 3622 */
37b96e98
GN		 3623 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3624 GUEST_INTR_STATE_NMI);
3625 break;
37b96e98 3626 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3627 vmx->vcpu.arch.event_exit_inst_len =
3628 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3629 /* fall through */
3630 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3631 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3632 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3633 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3634 } else
3635 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3636 break;
66fd3f7f
GN		 3637 case INTR_TYPE_SOFT_INTR:
3638 vmx->vcpu.arch.event_exit_inst_len =
3639 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3640 /* fall through */
37b96e98 3641 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3642 kvm_queue_interrupt(&vmx->vcpu, vector,
3643 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3644 break;
3645 default:
3646 break;
f7d9238f 3647 }
cf393f75
AK		 3648}
3649
9c8cba37
AK		 3650/*
3651 * Failure to inject an interrupt should give us the information
3652 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3653 * when fetching the interrupt redirection bitmap in the real-mode
3654 * tss, this doesn't happen. So we do it ourselves.
3655 */
3656static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3657{
3658 vmx->rmode.irq.pending = 0;
5fdbf976 3659 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3660 return;
5fdbf976 3661 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3662 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3663 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3664 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3665 return;
3666 }
3667 vmx->idt_vectoring_info =
3668 VECTORING_INFO_VALID_MASK
3669 | INTR_TYPE_EXT_INTR
3670 | vmx->rmode.irq.vector;
3671}
3672
c801949d
AK		 3673#ifdef CONFIG_X86_64
3674#define R "r"
3675#define Q "q"
3676#else
3677#define R "e"
3678#define Q "l"
3679#endif
3680
851ba692 3681static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3682{
a2fa3e9f 3683 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3684
3b86cd99
JK		 3685 /* Record the guest's net vcpu time for enforced NMI injections. */
3686 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3687 vmx->entry_time = ktime_get();
3688
80ced186
MG		 3689 /* Don't enter VMX if guest state is invalid, let the exit handler
3690 start emulation until we arrive back to a valid state */
3691 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3692 return;
a89a8fb9 3693
5fdbf976
MT		 3694 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3695 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3696 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3697 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3698
787ff736
GN		 3699 /* When single-stepping over STI and MOV SS, we must clear the
3700 * corresponding interruptibility bits in the guest state. Otherwise
3701 * vmentry fails as it then expects bit 14 (BS) in pending debug
3702 * exceptions being set, but that's not correct for the guest debugging
3703 * case. */
3704 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3705 vmx_set_interrupt_shadow(vcpu, 0);
3706
e6adf283
AK		 3707 /*
3708 * Loading guest fpu may have cleared host cr0.ts
3709 */
3710 vmcs_writel(HOST_CR0, read_cr0());
3711
e8a48342
AK		 3712 if (vcpu->arch.switch_db_regs)
3713 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3714
d77c26fc 3715 asm(
6aa8b732 3716 /* Store host registers */
c801949d
AK		 3717 "push %%"R"dx; push %%"R"bp;"
3718 "push %%"R"cx \n\t"
313dbd49
AK		 3719 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3720 "je 1f \n\t"
3721 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3722 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3723 "1: \n\t"
d3edefc0
AK		 3724 /* Reload cr2 if changed */
3725 "mov %c[cr2](%0), %%"R"ax \n\t"
3726 "mov %%cr2, %%"R"dx \n\t"
3727 "cmp %%"R"ax, %%"R"dx \n\t"
3728 "je 2f \n\t"
3729 "mov %%"R"ax, %%cr2 \n\t"
3730 "2: \n\t"
6aa8b732 3731 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3732 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3733 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3734 "mov %c[rax](%0), %%"R"ax \n\t"
3735 "mov %c[rbx](%0), %%"R"bx \n\t"
3736 "mov %c[rdx](%0), %%"R"dx \n\t"
3737 "mov %c[rsi](%0), %%"R"si \n\t"
3738 "mov %c[rdi](%0), %%"R"di \n\t"
3739 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3740#ifdef CONFIG_X86_64
e08aa78a
AK		 3741 "mov %c[r8](%0), %%r8 \n\t"
3742 "mov %c[r9](%0), %%r9 \n\t"
3743 "mov %c[r10](%0), %%r10 \n\t"
3744 "mov %c[r11](%0), %%r11 \n\t"
3745 "mov %c[r12](%0), %%r12 \n\t"
3746 "mov %c[r13](%0), %%r13 \n\t"
3747 "mov %c[r14](%0), %%r14 \n\t"
3748 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3749#endif
c801949d
AK		 3750 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3751
6aa8b732 3752 /* Enter guest mode */
cd2276a7 3753 "jne .Llaunched \n\t"
4ecac3fd 3754 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3755 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3756 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3757 ".Lkvm_vmx_return: "
6aa8b732 3758 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3759 "xchg %0, (%%"R"sp) \n\t"
3760 "mov %%"R"ax, %c[rax](%0) \n\t"
3761 "mov %%"R"bx, %c[rbx](%0) \n\t"
3762 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3763 "mov %%"R"dx, %c[rdx](%0) \n\t"
3764 "mov %%"R"si, %c[rsi](%0) \n\t"
3765 "mov %%"R"di, %c[rdi](%0) \n\t"
3766 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3767#ifdef CONFIG_X86_64
e08aa78a
AK		 3768 "mov %%r8, %c[r8](%0) \n\t"
3769 "mov %%r9, %c[r9](%0) \n\t"
3770 "mov %%r10, %c[r10](%0) \n\t"
3771 "mov %%r11, %c[r11](%0) \n\t"
3772 "mov %%r12, %c[r12](%0) \n\t"
3773 "mov %%r13, %c[r13](%0) \n\t"
3774 "mov %%r14, %c[r14](%0) \n\t"
3775 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3776#endif
c801949d
AK		 3777 "mov %%cr2, %%"R"ax \n\t"
3778 "mov %%"R"ax, %c[cr2](%0) \n\t"
3779
3780 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3781 "setbe %c[fail](%0) \n\t"
3782 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3783 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3784 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3785 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3786 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3787 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3788 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3789 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3790 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3791 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3792 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3793#ifdef CONFIG_X86_64
ad312c7c
ZX		 3794 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3795 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3796 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3797 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3798 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3799 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3800 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3801 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3802#endif
ad312c7c 3803 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3804 : "cc", "memory"
c801949d 3805 , R"bx", R"di", R"si"
c2036300 3806#ifdef CONFIG_X86_64
c2036300
LV		 3807 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3808#endif
3809 );
6aa8b732 3810
6de4f3ad
AK		 3811 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3812 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3813 vcpu->arch.regs_dirty = 0;
3814
e8a48342
AK		 3815 if (vcpu->arch.switch_db_regs)
3816 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3817
1155f76a 3818 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3819 if (vmx->rmode.irq.pending)
3820 fixup_rmode_irq(vmx);
1155f76a 3821
d77c26fc 3822 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3823 vmx->launched = 1;
1b6269db 3824
cf393f75 3825 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3826}
3827
c801949d
AK		 3828#undef R
3829#undef Q
3830
6aa8b732
AK		 3831static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3832{
a2fa3e9f
GH		 3833 struct vcpu_vmx *vmx = to_vmx(vcpu);
3834
3835 if (vmx->vmcs) {
543e4243 3836 vcpu_clear(vmx);
a2fa3e9f
GH		 3837 free_vmcs(vmx->vmcs);
3838 vmx->vmcs = NULL;
6aa8b732
AK		 3839 }
3840}
3841
3842static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3843{
fb3f0f51
RR		 3844 struct vcpu_vmx *vmx = to_vmx(vcpu);
3845
2384d2b3
SY		 3846 spin_lock(&vmx_vpid_lock);
3847 if (vmx->vpid != 0)
3848 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3849 spin_unlock(&vmx_vpid_lock);
6aa8b732 3850 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3851 kfree(vmx->guest_msrs);
3852 kvm_vcpu_uninit(vcpu);
a4770347 3853 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3854}
3855
fb3f0f51 3856static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3857{
fb3f0f51 3858 int err;
c16f862d 3859 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3860 int cpu;
6aa8b732 3861
a2fa3e9f 3862 if (!vmx)
fb3f0f51
RR		 3863 return ERR_PTR(-ENOMEM);
3864
2384d2b3
SY		 3865 allocate_vpid(vmx);
3866
fb3f0f51
RR		 3867 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3868 if (err)
3869 goto free_vcpu;
965b58a5 3870
a2fa3e9f 3871 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3872 if (!vmx->guest_msrs) {
3873 err = -ENOMEM;
3874 goto uninit_vcpu;
3875 }
965b58a5 3876
a2fa3e9f
GH		 3877 vmx->vmcs = alloc_vmcs();
3878 if (!vmx->vmcs)
fb3f0f51 3879 goto free_msrs;
a2fa3e9f
GH		 3880
3881 vmcs_clear(vmx->vmcs);
3882
15ad7146
AK		 3883 cpu = get_cpu();
3884 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3885 err = vmx_vcpu_setup(vmx);
fb3f0f51 3886 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3887 put_cpu();
fb3f0f51
RR		 3888 if (err)
3889 goto free_vmcs;
5e4a0b3c
MT		 3890 if (vm_need_virtualize_apic_accesses(kvm))
3891 if (alloc_apic_access_page(kvm) != 0)
3892 goto free_vmcs;
fb3f0f51 3893
b927a3ce
SY		 3894 if (enable_ept) {
3895 if (!kvm->arch.ept_identity_map_addr)
3896 kvm->arch.ept_identity_map_addr =
3897 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3898 if (alloc_identity_pagetable(kvm) != 0)
3899 goto free_vmcs;
b927a3ce 3900 }
b7ebfb05 3901
fb3f0f51
RR		 3902 return &vmx->vcpu;
3903
3904free_vmcs:
3905 free_vmcs(vmx->vmcs);
3906free_msrs:
fb3f0f51
RR		 3907 kfree(vmx->guest_msrs);
3908uninit_vcpu:
3909 kvm_vcpu_uninit(&vmx->vcpu);
3910free_vcpu:
a4770347 3911 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3912 return ERR_PTR(err);
6aa8b732
AK		 3913}
3914
002c7f7c
YS		 3915static void __init vmx_check_processor_compat(void *rtn)
3916{
3917 struct vmcs_config vmcs_conf;
3918
3919 *(int *)rtn = 0;
3920 if (setup_vmcs_config(&vmcs_conf) < 0)
3921 *(int *)rtn = -EIO;
3922 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3923 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3924 smp_processor_id());
3925 *(int *)rtn = -EIO;
3926 }
3927}
3928
67253af5
SY		 3929static int get_ept_level(void)
3930{
3931 return VMX_EPT_DEFAULT_GAW + 1;
3932}
3933
4b12f0de 3934static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3935{
4b12f0de
SY		 3936 u64 ret;
3937
522c68c4
SY		 3938 /* For VT-d and EPT combination
3939 * 1. MMIO: always map as UC
3940 * 2. EPT with VT-d:
3941 * a. VT-d without snooping control feature: can't guarantee the
3942 * result, try to trust guest.
3943 * b. VT-d with snooping control feature: snooping control feature of
3944 * VT-d engine can guarantee the cache correctness. Just set it
3945 * to WB to keep consistent with host. So the same as item 3.
3946 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3947 * consistent with host MTRR
3948 */
4b12f0de
SY		 3949 if (is_mmio)
3950 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3951 else if (vcpu->kvm->arch.iommu_domain &&
3952 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3953 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3954 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3955 else
522c68c4
SY		 3956 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3957 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3958
3959 return ret;
64d4d521
SY		 3960}
3961
229456fc
MT		 3962static const struct trace_print_flags vmx_exit_reasons_str[] = {
3963 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3964 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3965 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3966 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3967 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3968 { EXIT_REASON_CR_ACCESS, "cr_access" },
3969 { EXIT_REASON_DR_ACCESS, "dr_access" },
3970 { EXIT_REASON_CPUID, "cpuid" },
3971 { EXIT_REASON_MSR_READ, "rdmsr" },
3972 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3973 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3974 { EXIT_REASON_HLT, "halt" },
3975 { EXIT_REASON_INVLPG, "invlpg" },
3976 { EXIT_REASON_VMCALL, "hypercall" },
3977 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3978 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3979 { EXIT_REASON_WBINVD, "wbinvd" },
3980 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3981 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3982 { -1, NULL }
3983};
3984
344f414f
JR		 3985static bool vmx_gb_page_enable(void)
3986{
3987 return false;
3988}
3989
cbdd1bea 3990static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3991 .cpu_has_kvm_support = cpu_has_kvm_support,
3992 .disabled_by_bios = vmx_disabled_by_bios,
3993 .hardware_setup = hardware_setup,
3994 .hardware_unsetup = hardware_unsetup,
002c7f7c 3995 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3996 .hardware_enable = hardware_enable,
3997 .hardware_disable = hardware_disable,
04547156 3998 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3999
4000 .vcpu_create = vmx_create_vcpu,
4001 .vcpu_free = vmx_free_vcpu,
04d2cc77 4002 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4003
04d2cc77 4004 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4005 .vcpu_load = vmx_vcpu_load,
4006 .vcpu_put = vmx_vcpu_put,
4007
4008 .set_guest_debug = set_guest_debug,
4009 .get_msr = vmx_get_msr,
4010 .set_msr = vmx_set_msr,
4011 .get_segment_base = vmx_get_segment_base,
4012 .get_segment = vmx_get_segment,
4013 .set_segment = vmx_set_segment,
2e4d2653 4014 .get_cpl = vmx_get_cpl,
6aa8b732 4015 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 4016 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4017 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4018 .set_cr3 = vmx_set_cr3,
4019 .set_cr4 = vmx_set_cr4,
6aa8b732 4020 .set_efer = vmx_set_efer,
6aa8b732
AK		 4021 .get_idt = vmx_get_idt,
4022 .set_idt = vmx_set_idt,
4023 .get_gdt = vmx_get_gdt,
4024 .set_gdt = vmx_set_gdt,
5fdbf976 4025 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4026 .get_rflags = vmx_get_rflags,
4027 .set_rflags = vmx_set_rflags,
4028
4029 .tlb_flush = vmx_flush_tlb,
6aa8b732 4030
6aa8b732 4031 .run = vmx_vcpu_run,
6062d012 4032 .handle_exit = vmx_handle_exit,
6aa8b732 4033 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4034 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4035 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4036 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4037 .set_irq = vmx_inject_irq,
95ba8273 4038 .set_nmi = vmx_inject_nmi,
298101da 4039 .queue_exception = vmx_queue_exception,
78646121 4040 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4041 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4042 .get_nmi_mask = vmx_get_nmi_mask,
4043 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4044 .enable_nmi_window = enable_nmi_window,
4045 .enable_irq_window = enable_irq_window,
4046 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4047
cbc94022 4048 .set_tss_addr = vmx_set_tss_addr,
67253af5 4049 .get_tdp_level = get_ept_level,
4b12f0de 4050 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4051
4052 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 4053 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 4054};
4055
4056static int __init vmx_init(void)
4057{
26bb0981
AK		 4058 int r, i;
4059
4060 rdmsrl_safe(MSR_EFER, &host_efer);
4061
4062 for (i = 0; i < NR_VMX_MSR; ++i)
4063 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4064
3e7c73e9 4065 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4066 if (!vmx_io_bitmap_a)
4067 return -ENOMEM;
4068
3e7c73e9 4069 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4070 if (!vmx_io_bitmap_b) {
4071 r = -ENOMEM;
4072 goto out;
4073 }
4074
5897297b
AK		 4075 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4076 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4077 r = -ENOMEM;
4078 goto out1;
4079 }
4080
5897297b
AK		 4081 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4082 if (!vmx_msr_bitmap_longmode) {
4083 r = -ENOMEM;
4084 goto out2;
4085 }
4086
fdef3ad1
HQ		 4087 /*
4088 * Allow direct access to the PC debug port (it is often used for I/O
4089 * delays, but the vmexits simply slow things down).
4090 */
3e7c73e9
AK		 4091 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4092 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4093
3e7c73e9 4094 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4095
5897297b
AK		 4096 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4097 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4098
2384d2b3
SY		 4099 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4100
cb498ea2 4101 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4102 if (r)
5897297b 4103 goto out3;
25c5f225 4104
5897297b
AK		 4105 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4106 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4107 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4108 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4109 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4110 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4111
089d034e 4112 if (enable_ept) {
1439442c 4113 bypass_guest_pf = 0;
5fdbcb9d 4114 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4115 VMX_EPT_WRITABLE_MASK);
534e38b4 4116 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4117 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4118 kvm_enable_tdp();
4119 } else
4120 kvm_disable_tdp();
1439442c 4121
c7addb90
AK		 4122 if (bypass_guest_pf)
4123 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4124
fdef3ad1
HQ		 4125 return 0;
4126
5897297b
AK		 4127out3:
4128 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4129out2:
5897297b 4130 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4131out1:
3e7c73e9 4132 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4133out:
3e7c73e9 4134 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4135 return r;
6aa8b732
AK		 4136}
4137
4138static void __exit vmx_exit(void)
4139{
5897297b
AK		 4140 free_page((unsigned long)vmx_msr_bitmap_legacy);
4141 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4142 free_page((unsigned long)vmx_io_bitmap_b);
4143 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4144
cb498ea2 4145 kvm_exit();
6aa8b732
AK		 4146}
4147
4148module_init(vmx_init)
4149module_exit(vmx_exit)
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