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KVM: IOAPIC/LAPIC: Enable NMI support
[net-next-2.6.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
c7addb90
AK		 38static int bypass_guest_pf = 1;
39module_param(bypass_guest_pf, bool, 0);
40
2384d2b3
SY		 41static int enable_vpid = 1;
42module_param(enable_vpid, bool, 0);
43
4c9fc8ef
AK		 44static int flexpriority_enabled = 1;
45module_param(flexpriority_enabled, bool, 0);
46
1439442c 47static int enable_ept = 1;
d56f546d
SY		 48module_param(enable_ept, bool, 0);
49
a2fa3e9f
GH		 50struct vmcs {
51 u32 revision_id;
52 u32 abort;
53 char data[0];
54};
55
56struct vcpu_vmx {
fb3f0f51 57 struct kvm_vcpu vcpu;
543e4243 58 struct list_head local_vcpus_link;
a2fa3e9f 59 int launched;
29bd8a78 60 u8 fail;
1155f76a 61 u32 idt_vectoring_info;
a2fa3e9f
GH		 62 struct kvm_msr_entry *guest_msrs;
63 struct kvm_msr_entry *host_msrs;
64 int nmsrs;
65 int save_nmsrs;
66 int msr_offset_efer;
67#ifdef CONFIG_X86_64
68 int msr_offset_kernel_gs_base;
69#endif
70 struct vmcs *vmcs;
71 struct {
72 int loaded;
73 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 74 int gs_ldt_reload_needed;
75 int fs_reload_needed;
51c6cf66 76 int guest_efer_loaded;
d77c26fc 77 } host_state;
9c8cba37
AK		 78 struct {
79 struct {
80 bool pending;
81 u8 vector;
82 unsigned rip;
83 } irq;
84 } rmode;
2384d2b3 85 int vpid;
a2fa3e9f
GH		 86};
87
88static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
89{
fb3f0f51 90 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 91}
92
b7ebfb05 93static int init_rmode(struct kvm *kvm);
75880a01 94
6aa8b732
AK		 95static DEFINE_PER_CPU(struct vmcs *, vmxarea);
96static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 97static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 98
fdef3ad1
HQ		 99static struct page *vmx_io_bitmap_a;
100static struct page *vmx_io_bitmap_b;
25c5f225 101static struct page *vmx_msr_bitmap;
fdef3ad1 102
2384d2b3
SY		 103static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
104static DEFINE_SPINLOCK(vmx_vpid_lock);
105
1c3d14fe 106static struct vmcs_config {
6aa8b732
AK		 107 int size;
108 int order;
109 u32 revision_id;
1c3d14fe
YS		 110 u32 pin_based_exec_ctrl;
111 u32 cpu_based_exec_ctrl;
f78e0e2e 112 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 113 u32 vmexit_ctrl;
114 u32 vmentry_ctrl;
115} vmcs_config;
6aa8b732 116
d56f546d
SY		 117struct vmx_capability {
118 u32 ept;
119 u32 vpid;
120} vmx_capability;
121
6aa8b732
AK		 122#define VMX_SEGMENT_FIELD(seg) \
123 [VCPU_SREG_##seg] = { \
124 .selector = GUEST_##seg##_SELECTOR, \
125 .base = GUEST_##seg##_BASE, \
126 .limit = GUEST_##seg##_LIMIT, \
127 .ar_bytes = GUEST_##seg##_AR_BYTES, \
128 }
129
130static struct kvm_vmx_segment_field {
131 unsigned selector;
132 unsigned base;
133 unsigned limit;
134 unsigned ar_bytes;
135} kvm_vmx_segment_fields[] = {
136 VMX_SEGMENT_FIELD(CS),
137 VMX_SEGMENT_FIELD(DS),
138 VMX_SEGMENT_FIELD(ES),
139 VMX_SEGMENT_FIELD(FS),
140 VMX_SEGMENT_FIELD(GS),
141 VMX_SEGMENT_FIELD(SS),
142 VMX_SEGMENT_FIELD(TR),
143 VMX_SEGMENT_FIELD(LDTR),
144};
145
4d56c8a7
AK		 146/*
147 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
148 * away by decrementing the array size.
149 */
6aa8b732 150static const u32 vmx_msr_index[] = {
05b3e0c2 151#ifdef CONFIG_X86_64
6aa8b732
AK		 152 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
153#endif
154 MSR_EFER, MSR_K6_STAR,
155};
9d8f549d 156#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 157
a2fa3e9f
GH		 158static void load_msrs(struct kvm_msr_entry *e, int n)
159{
160 int i;
161
162 for (i = 0; i < n; ++i)
163 wrmsrl(e[i].index, e[i].data);
164}
165
166static void save_msrs(struct kvm_msr_entry *e, int n)
167{
168 int i;
169
170 for (i = 0; i < n; ++i)
171 rdmsrl(e[i].index, e[i].data);
172}
173
6aa8b732
AK		 174static inline int is_page_fault(u32 intr_info)
175{
176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
177 INTR_INFO_VALID_MASK)) ==
178 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
179}
180
2ab455cc
AL		 181static inline int is_no_device(u32 intr_info)
182{
183 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
184 INTR_INFO_VALID_MASK)) ==
185 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
186}
187
7aa81cc0
AL		 188static inline int is_invalid_opcode(u32 intr_info)
189{
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
193}
194
6aa8b732
AK		 195static inline int is_external_interrupt(u32 intr_info)
196{
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
198 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
199}
200
25c5f225
SY		 201static inline int cpu_has_vmx_msr_bitmap(void)
202{
203 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
204}
205
6e5d865c
YS		 206static inline int cpu_has_vmx_tpr_shadow(void)
207{
208 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
209}
210
211static inline int vm_need_tpr_shadow(struct kvm *kvm)
212{
213 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
214}
215
f78e0e2e
SY		 216static inline int cpu_has_secondary_exec_ctrls(void)
217{
218 return (vmcs_config.cpu_based_exec_ctrl &
219 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
220}
221
774ead3a 222static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 223{
4c9fc8ef
AK		 224 return flexpriority_enabled
225 && (vmcs_config.cpu_based_2nd_exec_ctrl &
226 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 227}
228
d56f546d
SY		 229static inline int cpu_has_vmx_invept_individual_addr(void)
230{
231 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
232}
233
234static inline int cpu_has_vmx_invept_context(void)
235{
236 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
237}
238
239static inline int cpu_has_vmx_invept_global(void)
240{
241 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
242}
243
244static inline int cpu_has_vmx_ept(void)
245{
246 return (vmcs_config.cpu_based_2nd_exec_ctrl &
247 SECONDARY_EXEC_ENABLE_EPT);
248}
249
250static inline int vm_need_ept(void)
251{
252 return (cpu_has_vmx_ept() && enable_ept);
253}
254
f78e0e2e
SY		 255static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
256{
257 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
258 (irqchip_in_kernel(kvm)));
259}
260
2384d2b3
SY		 261static inline int cpu_has_vmx_vpid(void)
262{
263 return (vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_ENABLE_VPID);
265}
266
8b9cf98c 267static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 268{
269 int i;
270
a2fa3e9f
GH		 271 for (i = 0; i < vmx->nmsrs; ++i)
272 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 273 return i;
274 return -1;
275}
276
2384d2b3
SY		 277static inline void __invvpid(int ext, u16 vpid, gva_t gva)
278{
279 struct {
280 u64 vpid : 16;
281 u64 rsvd : 48;
282 u64 gva;
283 } operand = { vpid, 0, gva };
284
4ecac3fd 285 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 286 /* CF==1 or ZF==1 --> rc = -1 */
287 "; ja 1f ; ud2 ; 1:"
288 : : "a"(&operand), "c"(ext) : "cc", "memory");
289}
290
1439442c
SY		 291static inline void __invept(int ext, u64 eptp, gpa_t gpa)
292{
293 struct {
294 u64 eptp, gpa;
295 } operand = {eptp, gpa};
296
4ecac3fd 297 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 298 /* CF==1 or ZF==1 --> rc = -1 */
299 "; ja 1f ; ud2 ; 1:\n"
300 : : "a" (&operand), "c" (ext) : "cc", "memory");
301}
302
8b9cf98c 303static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 304{
305 int i;
306
8b9cf98c 307 i = __find_msr_index(vmx, msr);
a75beee6 308 if (i >= 0)
a2fa3e9f 309 return &vmx->guest_msrs[i];
8b6d44c7 310 return NULL;
7725f0ba
AK		 311}
312
6aa8b732
AK		 313static void vmcs_clear(struct vmcs *vmcs)
314{
315 u64 phys_addr = __pa(vmcs);
316 u8 error;
317
4ecac3fd 318 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 319 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
320 : "cc", "memory");
321 if (error)
322 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
323 vmcs, phys_addr);
324}
325
326static void __vcpu_clear(void *arg)
327{
8b9cf98c 328 struct vcpu_vmx *vmx = arg;
d3b2c338 329 int cpu = raw_smp_processor_id();
6aa8b732 330
8b9cf98c 331 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 332 vmcs_clear(vmx->vmcs);
333 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 334 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 335 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 336 list_del(&vmx->local_vcpus_link);
337 vmx->vcpu.cpu = -1;
338 vmx->launched = 0;
6aa8b732
AK		 339}
340
8b9cf98c 341static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 342{
eae5ecb5
AK		 343 if (vmx->vcpu.cpu == -1)
344 return;
8691e5a8 345 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 346}
347
2384d2b3
SY		 348static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
349{
350 if (vmx->vpid == 0)
351 return;
352
353 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
354}
355
1439442c
SY		 356static inline void ept_sync_global(void)
357{
358 if (cpu_has_vmx_invept_global())
359 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
360}
361
362static inline void ept_sync_context(u64 eptp)
363{
364 if (vm_need_ept()) {
365 if (cpu_has_vmx_invept_context())
366 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
367 else
368 ept_sync_global();
369 }
370}
371
372static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
373{
374 if (vm_need_ept()) {
375 if (cpu_has_vmx_invept_individual_addr())
376 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
377 eptp, gpa);
378 else
379 ept_sync_context(eptp);
380 }
381}
382
6aa8b732
AK		 383static unsigned long vmcs_readl(unsigned long field)
384{
385 unsigned long value;
386
4ecac3fd 387 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 388 : "=a"(value) : "d"(field) : "cc");
389 return value;
390}
391
392static u16 vmcs_read16(unsigned long field)
393{
394 return vmcs_readl(field);
395}
396
397static u32 vmcs_read32(unsigned long field)
398{
399 return vmcs_readl(field);
400}
401
402static u64 vmcs_read64(unsigned long field)
403{
05b3e0c2 404#ifdef CONFIG_X86_64
6aa8b732
AK		 405 return vmcs_readl(field);
406#else
407 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
408#endif
409}
410
e52de1b8
AK		 411static noinline void vmwrite_error(unsigned long field, unsigned long value)
412{
413 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
414 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
415 dump_stack();
416}
417
6aa8b732
AK		 418static void vmcs_writel(unsigned long field, unsigned long value)
419{
420 u8 error;
421
4ecac3fd 422 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 423 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 424 if (unlikely(error))
425 vmwrite_error(field, value);
6aa8b732
AK		 426}
427
428static void vmcs_write16(unsigned long field, u16 value)
429{
430 vmcs_writel(field, value);
431}
432
433static void vmcs_write32(unsigned long field, u32 value)
434{
435 vmcs_writel(field, value);
436}
437
438static void vmcs_write64(unsigned long field, u64 value)
439{
6aa8b732 440 vmcs_writel(field, value);
7682f2d0 441#ifndef CONFIG_X86_64
6aa8b732
AK		 442 asm volatile ("");
443 vmcs_writel(field+1, value >> 32);
444#endif
445}
446
2ab455cc
AL		 447static void vmcs_clear_bits(unsigned long field, u32 mask)
448{
449 vmcs_writel(field, vmcs_readl(field) & ~mask);
450}
451
452static void vmcs_set_bits(unsigned long field, u32 mask)
453{
454 vmcs_writel(field, vmcs_readl(field) | mask);
455}
456
abd3f2d6
AK		 457static void update_exception_bitmap(struct kvm_vcpu *vcpu)
458{
459 u32 eb;
460
7aa81cc0 461 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 462 if (!vcpu->fpu_active)
463 eb |= 1u << NM_VECTOR;
464 if (vcpu->guest_debug.enabled)
465 eb |= 1u << 1;
ad312c7c 466 if (vcpu->arch.rmode.active)
abd3f2d6 467 eb = ~0;
1439442c
SY		 468 if (vm_need_ept())
469 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 470 vmcs_write32(EXCEPTION_BITMAP, eb);
471}
472
33ed6329
AK		 473static void reload_tss(void)
474{
33ed6329
AK		 475 /*
476 * VT restores TR but not its size. Useless.
477 */
478 struct descriptor_table gdt;
a5f61300 479 struct desc_struct *descs;
33ed6329
AK		 480
481 get_gdt(&gdt);
482 descs = (void *)gdt.base;
483 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
484 load_TR_desc();
33ed6329
AK		 485}
486
8b9cf98c 487static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 488{
a2fa3e9f 489 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 490 u64 host_efer = vmx->host_msrs[efer_offset].data;
491 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
492 u64 ignore_bits;
493
494 if (efer_offset < 0)
495 return;
496 /*
497 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
498 * outside long mode
499 */
500 ignore_bits = EFER_NX | EFER_SCE;
501#ifdef CONFIG_X86_64
502 ignore_bits |= EFER_LMA | EFER_LME;
503 /* SCE is meaningful only in long mode on Intel */
504 if (guest_efer & EFER_LMA)
505 ignore_bits &= ~(u64)EFER_SCE;
506#endif
507 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
508 return;
2cc51560 509
51c6cf66
AK		 510 vmx->host_state.guest_efer_loaded = 1;
511 guest_efer &= ~ignore_bits;
512 guest_efer |= host_efer & ignore_bits;
513 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 514 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 515}
516
51c6cf66
AK		 517static void reload_host_efer(struct vcpu_vmx *vmx)
518{
519 if (vmx->host_state.guest_efer_loaded) {
520 vmx->host_state.guest_efer_loaded = 0;
521 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
522 }
523}
524
04d2cc77 525static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 526{
04d2cc77
AK		 527 struct vcpu_vmx *vmx = to_vmx(vcpu);
528
a2fa3e9f 529 if (vmx->host_state.loaded)
33ed6329
AK		 530 return;
531
a2fa3e9f 532 vmx->host_state.loaded = 1;
33ed6329
AK		 533 /*
534 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
535 * allow segment selectors with cpl > 0 or ti == 1.
536 */
a2fa3e9f 537 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 538 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 539 vmx->host_state.fs_sel = read_fs();
152d3f2f 540 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 541 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 542 vmx->host_state.fs_reload_needed = 0;
543 } else {
33ed6329 544 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 545 vmx->host_state.fs_reload_needed = 1;
33ed6329 546 }
a2fa3e9f
GH		 547 vmx->host_state.gs_sel = read_gs();
548 if (!(vmx->host_state.gs_sel & 7))
549 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 550 else {
551 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 552 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 553 }
554
555#ifdef CONFIG_X86_64
556 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
557 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
558#else
a2fa3e9f
GH		 559 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
560 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 561#endif
707c0874
AK		 562
563#ifdef CONFIG_X86_64
d77c26fc 564 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 565 save_msrs(vmx->host_msrs +
566 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 567
707c0874 568#endif
a2fa3e9f 569 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 570 load_transition_efer(vmx);
33ed6329
AK		 571}
572
a9b21b62 573static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 574{
15ad7146 575 unsigned long flags;
33ed6329 576
a2fa3e9f 577 if (!vmx->host_state.loaded)
33ed6329
AK		 578 return;
579
e1beb1d3 580 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 581 vmx->host_state.loaded = 0;
152d3f2f 582 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 583 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 584 if (vmx->host_state.gs_ldt_reload_needed) {
585 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 586 /*
587 * If we have to reload gs, we must take care to
588 * preserve our gs base.
589 */
15ad7146 590 local_irq_save(flags);
a2fa3e9f 591 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 592#ifdef CONFIG_X86_64
593 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
594#endif
15ad7146 595 local_irq_restore(flags);
33ed6329 596 }
152d3f2f 597 reload_tss();
a2fa3e9f
GH		 598 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
599 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 600 reload_host_efer(vmx);
33ed6329
AK		 601}
602
a9b21b62
AK		 603static void vmx_load_host_state(struct vcpu_vmx *vmx)
604{
605 preempt_disable();
606 __vmx_load_host_state(vmx);
607 preempt_enable();
608}
609
6aa8b732
AK		 610/*
611 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
612 * vcpu mutex is already taken.
613 */
15ad7146 614static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 615{
a2fa3e9f
GH		 616 struct vcpu_vmx *vmx = to_vmx(vcpu);
617 u64 phys_addr = __pa(vmx->vmcs);
019960ae 618 u64 tsc_this, delta, new_offset;
6aa8b732 619
a3d7f85f 620 if (vcpu->cpu != cpu) {
8b9cf98c 621 vcpu_clear(vmx);
2f599714 622 kvm_migrate_timers(vcpu);
2384d2b3 623 vpid_sync_vcpu_all(vmx);
543e4243
AK		 624 local_irq_disable();
625 list_add(&vmx->local_vcpus_link,
626 &per_cpu(vcpus_on_cpu, cpu));
627 local_irq_enable();
a3d7f85f 628 }
6aa8b732 629
a2fa3e9f 630 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 631 u8 error;
632
a2fa3e9f 633 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 634 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 635 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
636 : "cc");
637 if (error)
638 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 639 vmx->vmcs, phys_addr);
6aa8b732
AK		 640 }
641
642 if (vcpu->cpu != cpu) {
643 struct descriptor_table dt;
644 unsigned long sysenter_esp;
645
646 vcpu->cpu = cpu;
647 /*
648 * Linux uses per-cpu TSS and GDT, so set these when switching
649 * processors.
650 */
651 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
652 get_gdt(&dt);
653 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
654
655 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
656 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 657
658 /*
659 * Make sure the time stamp counter is monotonous.
660 */
661 rdtscll(tsc_this);
019960ae
AK		 662 if (tsc_this < vcpu->arch.host_tsc) {
663 delta = vcpu->arch.host_tsc - tsc_this;
664 new_offset = vmcs_read64(TSC_OFFSET) + delta;
665 vmcs_write64(TSC_OFFSET, new_offset);
666 }
6aa8b732 667 }
6aa8b732
AK		 668}
669
670static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
671{
a9b21b62 672 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 673}
674
5fd86fcf
AK		 675static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
676{
677 if (vcpu->fpu_active)
678 return;
679 vcpu->fpu_active = 1;
707d92fa 680 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 681 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 682 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 683 update_exception_bitmap(vcpu);
684}
685
686static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
687{
688 if (!vcpu->fpu_active)
689 return;
690 vcpu->fpu_active = 0;
707d92fa 691 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 692 update_exception_bitmap(vcpu);
693}
694
6aa8b732
AK		 695static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
696{
697 return vmcs_readl(GUEST_RFLAGS);
698}
699
700static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
701{
ad312c7c 702 if (vcpu->arch.rmode.active)
053de044 703 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 704 vmcs_writel(GUEST_RFLAGS, rflags);
705}
706
707static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
708{
709 unsigned long rip;
710 u32 interruptibility;
711
712 rip = vmcs_readl(GUEST_RIP);
713 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
714 vmcs_writel(GUEST_RIP, rip);
715
716 /*
717 * We emulated an instruction, so temporary interrupt blocking
718 * should be removed, if set.
719 */
720 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
721 if (interruptibility & 3)
722 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
723 interruptibility & ~3);
ad312c7c 724 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 725}
726
298101da
AK		 727static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
728 bool has_error_code, u32 error_code)
729{
730 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
731 nr | INTR_TYPE_EXCEPTION
2e11384c 732 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da
AK		 733 | INTR_INFO_VALID_MASK);
734 if (has_error_code)
735 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
736}
737
738static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
739{
740 struct vcpu_vmx *vmx = to_vmx(vcpu);
741
742 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
743}
744
a75beee6
ED		 745/*
746 * Swap MSR entry in host/guest MSR entry array.
747 */
54e11fa1 748#ifdef CONFIG_X86_64
8b9cf98c 749static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 750{
a2fa3e9f
GH		 751 struct kvm_msr_entry tmp;
752
753 tmp = vmx->guest_msrs[to];
754 vmx->guest_msrs[to] = vmx->guest_msrs[from];
755 vmx->guest_msrs[from] = tmp;
756 tmp = vmx->host_msrs[to];
757 vmx->host_msrs[to] = vmx->host_msrs[from];
758 vmx->host_msrs[from] = tmp;
a75beee6 759}
54e11fa1 760#endif
a75beee6 761
e38aea3e
AK		 762/*
763 * Set up the vmcs to automatically save and restore system
764 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
765 * mode, as fiddling with msrs is very expensive.
766 */
8b9cf98c 767static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 768{
2cc51560 769 int save_nmsrs;
e38aea3e 770
33f9c505 771 vmx_load_host_state(vmx);
a75beee6
ED		 772 save_nmsrs = 0;
773#ifdef CONFIG_X86_64
8b9cf98c 774 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 775 int index;
776
8b9cf98c 777 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 778 if (index >= 0)
8b9cf98c
RR		 779 move_msr_up(vmx, index, save_nmsrs++);
780 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 781 if (index >= 0)
8b9cf98c
RR		 782 move_msr_up(vmx, index, save_nmsrs++);
783 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 784 if (index >= 0)
8b9cf98c
RR		 785 move_msr_up(vmx, index, save_nmsrs++);
786 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 787 if (index >= 0)
8b9cf98c 788 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 789 /*
790 * MSR_K6_STAR is only needed on long mode guests, and only
791 * if efer.sce is enabled.
792 */
8b9cf98c 793 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 794 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 795 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 796 }
797#endif
a2fa3e9f 798 vmx->save_nmsrs = save_nmsrs;
e38aea3e 799
4d56c8a7 800#ifdef CONFIG_X86_64
a2fa3e9f 801 vmx->msr_offset_kernel_gs_base =
8b9cf98c 802 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 803#endif
8b9cf98c 804 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 805}
806
6aa8b732
AK		 807/*
808 * reads and returns guest's timestamp counter "register"
809 * guest_tsc = host_tsc + tsc_offset -- 21.3
810 */
811static u64 guest_read_tsc(void)
812{
813 u64 host_tsc, tsc_offset;
814
815 rdtscll(host_tsc);
816 tsc_offset = vmcs_read64(TSC_OFFSET);
817 return host_tsc + tsc_offset;
818}
819
820/*
821 * writes 'guest_tsc' into guest's timestamp counter "register"
822 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
823 */
824static void guest_write_tsc(u64 guest_tsc)
825{
826 u64 host_tsc;
827
828 rdtscll(host_tsc);
829 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
830}
831
6aa8b732
AK		 832/*
833 * Reads an msr value (of 'msr_index') into 'pdata'.
834 * Returns 0 on success, non-0 otherwise.
835 * Assumes vcpu_load() was already called.
836 */
837static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
838{
839 u64 data;
a2fa3e9f 840 struct kvm_msr_entry *msr;
6aa8b732
AK		 841
842 if (!pdata) {
843 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
844 return -EINVAL;
845 }
846
847 switch (msr_index) {
05b3e0c2 848#ifdef CONFIG_X86_64
6aa8b732
AK		 849 case MSR_FS_BASE:
850 data = vmcs_readl(GUEST_FS_BASE);
851 break;
852 case MSR_GS_BASE:
853 data = vmcs_readl(GUEST_GS_BASE);
854 break;
855 case MSR_EFER:
3bab1f5d 856 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 857#endif
858 case MSR_IA32_TIME_STAMP_COUNTER:
859 data = guest_read_tsc();
860 break;
861 case MSR_IA32_SYSENTER_CS:
862 data = vmcs_read32(GUEST_SYSENTER_CS);
863 break;
864 case MSR_IA32_SYSENTER_EIP:
f5b42c33 865 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 866 break;
867 case MSR_IA32_SYSENTER_ESP:
f5b42c33 868 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 869 break;
6aa8b732 870 default:
8b9cf98c 871 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 872 if (msr) {
873 data = msr->data;
874 break;
6aa8b732 875 }
3bab1f5d 876 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 877 }
878
879 *pdata = data;
880 return 0;
881}
882
883/*
884 * Writes msr value into into the appropriate "register".
885 * Returns 0 on success, non-0 otherwise.
886 * Assumes vcpu_load() was already called.
887 */
888static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
889{
a2fa3e9f
GH		 890 struct vcpu_vmx *vmx = to_vmx(vcpu);
891 struct kvm_msr_entry *msr;
2cc51560
ED		 892 int ret = 0;
893
6aa8b732 894 switch (msr_index) {
05b3e0c2 895#ifdef CONFIG_X86_64
3bab1f5d 896 case MSR_EFER:
a9b21b62 897 vmx_load_host_state(vmx);
2cc51560 898 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 899 break;
6aa8b732
AK		 900 case MSR_FS_BASE:
901 vmcs_writel(GUEST_FS_BASE, data);
902 break;
903 case MSR_GS_BASE:
904 vmcs_writel(GUEST_GS_BASE, data);
905 break;
906#endif
907 case MSR_IA32_SYSENTER_CS:
908 vmcs_write32(GUEST_SYSENTER_CS, data);
909 break;
910 case MSR_IA32_SYSENTER_EIP:
f5b42c33 911 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 912 break;
913 case MSR_IA32_SYSENTER_ESP:
f5b42c33 914 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 915 break;
d27d4aca 916 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 917 guest_write_tsc(data);
918 break;
6aa8b732 919 default:
a9b21b62 920 vmx_load_host_state(vmx);
8b9cf98c 921 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 922 if (msr) {
923 msr->data = data;
924 break;
6aa8b732 925 }
2cc51560 926 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 927 }
928
2cc51560 929 return ret;
6aa8b732
AK		 930}
931
932/*
933 * Sync the rsp and rip registers into the vcpu structure. This allows
ad312c7c 934 * registers to be accessed by indexing vcpu->arch.regs.
6aa8b732
AK		 935 */
936static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
937{
ad312c7c
ZX		 938 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
939 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
6aa8b732
AK		 940}
941
942/*
943 * Syncs rsp and rip back into the vmcs. Should be called after possible
944 * modification.
945 */
946static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
947{
ad312c7c
ZX		 948 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
949 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
6aa8b732
AK		 950}
951
952static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
953{
954 unsigned long dr7 = 0x400;
6aa8b732
AK		 955 int old_singlestep;
956
6aa8b732
AK		 957 old_singlestep = vcpu->guest_debug.singlestep;
958
959 vcpu->guest_debug.enabled = dbg->enabled;
960 if (vcpu->guest_debug.enabled) {
961 int i;
962
963 dr7 |= 0x200; /* exact */
964 for (i = 0; i < 4; ++i) {
965 if (!dbg->breakpoints[i].enabled)
966 continue;
967 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
968 dr7 |= 2 << (i*2); /* global enable */
969 dr7 |= 0 << (i*4+16); /* execution breakpoint */
970 }
971
6aa8b732 972 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 973 } else
6aa8b732 974 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 975
976 if (old_singlestep && !vcpu->guest_debug.singlestep) {
977 unsigned long flags;
978
979 flags = vmcs_readl(GUEST_RFLAGS);
980 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
981 vmcs_writel(GUEST_RFLAGS, flags);
982 }
983
abd3f2d6 984 update_exception_bitmap(vcpu);
6aa8b732
AK		 985 vmcs_writel(GUEST_DR7, dr7);
986
987 return 0;
988}
989
2a8067f1
ED		 990static int vmx_get_irq(struct kvm_vcpu *vcpu)
991{
1155f76a 992 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 993 u32 idtv_info_field;
994
1155f76a 995 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 996 if (idtv_info_field & INTR_INFO_VALID_MASK) {
997 if (is_external_interrupt(idtv_info_field))
998 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
999 else
d77c26fc 1000 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 1001 }
1002 return -1;
1003}
1004
6aa8b732
AK		 1005static __init int cpu_has_kvm_support(void)
1006{
1007 unsigned long ecx = cpuid_ecx(1);
1008 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1009}
1010
1011static __init int vmx_disabled_by_bios(void)
1012{
1013 u64 msr;
1014
1015 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 1016 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1017 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1018 == MSR_IA32_FEATURE_CONTROL_LOCKED;
1019 /* locked but not enabled */
6aa8b732
AK		 1020}
1021
774c47f1 1022static void hardware_enable(void *garbage)
6aa8b732
AK		 1023{
1024 int cpu = raw_smp_processor_id();
1025 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1026 u64 old;
1027
543e4243 1028 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1029 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 1030 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1031 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1032 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1033 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1034 /* enable and lock */
62b3ffb8
YS		 1035 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1036 MSR_IA32_FEATURE_CONTROL_LOCKED |
1037 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1038 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1039 asm volatile (ASM_VMX_VMXON_RAX
1040 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1041 : "memory", "cc");
1042}
1043
543e4243
AK		 1044static void vmclear_local_vcpus(void)
1045{
1046 int cpu = raw_smp_processor_id();
1047 struct vcpu_vmx *vmx, *n;
1048
1049 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1050 local_vcpus_link)
1051 __vcpu_clear(vmx);
1052}
1053
6aa8b732
AK		 1054static void hardware_disable(void *garbage)
1055{
543e4243 1056 vmclear_local_vcpus();
4ecac3fd 1057 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1058 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1059}
1060
1c3d14fe 1061static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1062 u32 msr, u32 *result)
1c3d14fe
YS		 1063{
1064 u32 vmx_msr_low, vmx_msr_high;
1065 u32 ctl = ctl_min | ctl_opt;
1066
1067 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1068
1069 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1070 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1071
1072 /* Ensure minimum (required) set of control bits are supported. */
1073 if (ctl_min & ~ctl)
002c7f7c 1074 return -EIO;
1c3d14fe
YS		 1075
1076 *result = ctl;
1077 return 0;
1078}
1079
002c7f7c 1080static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1081{
1082 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1083 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1084 u32 _pin_based_exec_control = 0;
1085 u32 _cpu_based_exec_control = 0;
f78e0e2e 1086 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1087 u32 _vmexit_control = 0;
1088 u32 _vmentry_control = 0;
1089
1090 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1091 opt = 0;
1092 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1093 &_pin_based_exec_control) < 0)
002c7f7c 1094 return -EIO;
1c3d14fe
YS		 1095
1096 min = CPU_BASED_HLT_EXITING |
1097#ifdef CONFIG_X86_64
1098 CPU_BASED_CR8_LOAD_EXITING |
1099 CPU_BASED_CR8_STORE_EXITING |
1100#endif
d56f546d
SY		 1101 CPU_BASED_CR3_LOAD_EXITING |
1102 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1103 CPU_BASED_USE_IO_BITMAPS |
1104 CPU_BASED_MOV_DR_EXITING |
1105 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e 1106 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1107 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1108 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1109 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1110 &_cpu_based_exec_control) < 0)
002c7f7c 1111 return -EIO;
6e5d865c
YS		 1112#ifdef CONFIG_X86_64
1113 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1114 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1115 ~CPU_BASED_CR8_STORE_EXITING;
1116#endif
f78e0e2e 1117 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1118 min2 = 0;
1119 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1120 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1121 SECONDARY_EXEC_ENABLE_VPID |
1122 SECONDARY_EXEC_ENABLE_EPT;
1123 if (adjust_vmx_controls(min2, opt2,
1124 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1125 &_cpu_based_2nd_exec_control) < 0)
1126 return -EIO;
1127 }
1128#ifndef CONFIG_X86_64
1129 if (!(_cpu_based_2nd_exec_control &
1130 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1131 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1132#endif
d56f546d
SY		 1133 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1134 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1135 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1136 CPU_BASED_CR3_STORE_EXITING);
1137 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1138 &_cpu_based_exec_control) < 0)
1139 return -EIO;
1140 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1141 vmx_capability.ept, vmx_capability.vpid);
1142 }
1c3d14fe
YS		 1143
1144 min = 0;
1145#ifdef CONFIG_X86_64
1146 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1147#endif
1148 opt = 0;
1149 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1150 &_vmexit_control) < 0)
002c7f7c 1151 return -EIO;
1c3d14fe
YS		 1152
1153 min = opt = 0;
1154 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1155 &_vmentry_control) < 0)
002c7f7c 1156 return -EIO;
6aa8b732 1157
c68876fd 1158 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1159
1160 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1161 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1162 return -EIO;
1c3d14fe
YS		 1163
1164#ifdef CONFIG_X86_64
1165 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1166 if (vmx_msr_high & (1u<<16))
002c7f7c 1167 return -EIO;
1c3d14fe
YS		 1168#endif
1169
1170 /* Require Write-Back (WB) memory type for VMCS accesses. */
1171 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1172 return -EIO;
1c3d14fe 1173
002c7f7c
YS		 1174 vmcs_conf->size = vmx_msr_high & 0x1fff;
1175 vmcs_conf->order = get_order(vmcs_config.size);
1176 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1177
002c7f7c
YS		 1178 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1179 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1180 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1181 vmcs_conf->vmexit_ctrl = _vmexit_control;
1182 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1183
1184 return 0;
c68876fd 1185}
6aa8b732
AK		 1186
1187static struct vmcs *alloc_vmcs_cpu(int cpu)
1188{
1189 int node = cpu_to_node(cpu);
1190 struct page *pages;
1191 struct vmcs *vmcs;
1192
1c3d14fe 1193 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1194 if (!pages)
1195 return NULL;
1196 vmcs = page_address(pages);
1c3d14fe
YS		 1197 memset(vmcs, 0, vmcs_config.size);
1198 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1199 return vmcs;
1200}
1201
1202static struct vmcs *alloc_vmcs(void)
1203{
d3b2c338 1204 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1205}
1206
1207static void free_vmcs(struct vmcs *vmcs)
1208{
1c3d14fe 1209 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1210}
1211
39959588 1212static void free_kvm_area(void)
6aa8b732
AK		 1213{
1214 int cpu;
1215
1216 for_each_online_cpu(cpu)
1217 free_vmcs(per_cpu(vmxarea, cpu));
1218}
1219
6aa8b732
AK		 1220static __init int alloc_kvm_area(void)
1221{
1222 int cpu;
1223
1224 for_each_online_cpu(cpu) {
1225 struct vmcs *vmcs;
1226
1227 vmcs = alloc_vmcs_cpu(cpu);
1228 if (!vmcs) {
1229 free_kvm_area();
1230 return -ENOMEM;
1231 }
1232
1233 per_cpu(vmxarea, cpu) = vmcs;
1234 }
1235 return 0;
1236}
1237
1238static __init int hardware_setup(void)
1239{
002c7f7c
YS		 1240 if (setup_vmcs_config(&vmcs_config) < 0)
1241 return -EIO;
50a37eb4
JR		 1242
1243 if (boot_cpu_has(X86_FEATURE_NX))
1244 kvm_enable_efer_bits(EFER_NX);
1245
6aa8b732
AK		 1246 return alloc_kvm_area();
1247}
1248
1249static __exit void hardware_unsetup(void)
1250{
1251 free_kvm_area();
1252}
1253
6aa8b732
AK		 1254static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1255{
1256 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1257
6af11b9e 1258 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1259 vmcs_write16(sf->selector, save->selector);
1260 vmcs_writel(sf->base, save->base);
1261 vmcs_write32(sf->limit, save->limit);
1262 vmcs_write32(sf->ar_bytes, save->ar);
1263 } else {
1264 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1265 << AR_DPL_SHIFT;
1266 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1267 }
1268}
1269
1270static void enter_pmode(struct kvm_vcpu *vcpu)
1271{
1272 unsigned long flags;
1273
ad312c7c 1274 vcpu->arch.rmode.active = 0;
6aa8b732 1275
ad312c7c
ZX		 1276 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1277 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1278 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1279
1280 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1281 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1282 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1283 vmcs_writel(GUEST_RFLAGS, flags);
1284
66aee91a
RR		 1285 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1286 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1287
1288 update_exception_bitmap(vcpu);
1289
ad312c7c
ZX		 1290 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1291 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1292 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1293 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1294
1295 vmcs_write16(GUEST_SS_SELECTOR, 0);
1296 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1297
1298 vmcs_write16(GUEST_CS_SELECTOR,
1299 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1300 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1301}
1302
d77c26fc 1303static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1304{
bfc6d222 1305 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1306 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1307 kvm->memslots[0].npages - 3;
1308 return base_gfn << PAGE_SHIFT;
1309 }
bfc6d222 1310 return kvm->arch.tss_addr;
6aa8b732
AK		 1311}
1312
1313static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1314{
1315 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1316
1317 save->selector = vmcs_read16(sf->selector);
1318 save->base = vmcs_readl(sf->base);
1319 save->limit = vmcs_read32(sf->limit);
1320 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1321 vmcs_write16(sf->selector, save->base >> 4);
1322 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1323 vmcs_write32(sf->limit, 0xffff);
1324 vmcs_write32(sf->ar_bytes, 0xf3);
1325}
1326
1327static void enter_rmode(struct kvm_vcpu *vcpu)
1328{
1329 unsigned long flags;
1330
ad312c7c 1331 vcpu->arch.rmode.active = 1;
6aa8b732 1332
ad312c7c 1333 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1334 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1335
ad312c7c 1336 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1337 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1338
ad312c7c 1339 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1340 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1341
1342 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1343 vcpu->arch.rmode.save_iopl
1344 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1345
053de044 1346 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1347
1348 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1349 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1350 update_exception_bitmap(vcpu);
1351
1352 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1353 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1354 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1355
1356 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1357 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1358 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1359 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1360 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1361
ad312c7c
ZX		 1362 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1363 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1364 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1365 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1366
8668a3c4 1367 kvm_mmu_reset_context(vcpu);
b7ebfb05 1368 init_rmode(vcpu->kvm);
6aa8b732
AK		 1369}
1370
05b3e0c2 1371#ifdef CONFIG_X86_64
6aa8b732
AK		 1372
1373static void enter_lmode(struct kvm_vcpu *vcpu)
1374{
1375 u32 guest_tr_ar;
1376
1377 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1378 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1379 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1380 __func__);
6aa8b732
AK		 1381 vmcs_write32(GUEST_TR_AR_BYTES,
1382 (guest_tr_ar & ~AR_TYPE_MASK)
1383 | AR_TYPE_BUSY_64_TSS);
1384 }
1385
ad312c7c 1386 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1387
8b9cf98c 1388 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1389 vmcs_write32(VM_ENTRY_CONTROLS,
1390 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1391 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1392}
1393
1394static void exit_lmode(struct kvm_vcpu *vcpu)
1395{
ad312c7c 1396 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1397
1398 vmcs_write32(VM_ENTRY_CONTROLS,
1399 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1400 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1401}
1402
1403#endif
1404
2384d2b3
SY		 1405static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1406{
1407 vpid_sync_vcpu_all(to_vmx(vcpu));
1408}
1409
25c4c276 1410static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1411{
ad312c7c
ZX		 1412 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1413 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1414}
1415
1439442c
SY		 1416static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1417{
1418 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1419 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1420 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1421 return;
1422 }
1423 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1424 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1425 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1426 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1427 }
1428}
1429
1430static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1431
1432static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1433 unsigned long cr0,
1434 struct kvm_vcpu *vcpu)
1435{
1436 if (!(cr0 & X86_CR0_PG)) {
1437 /* From paging/starting to nonpaging */
1438 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1439 vmcs_config.cpu_based_exec_ctrl |
1440 (CPU_BASED_CR3_LOAD_EXITING |
1441 CPU_BASED_CR3_STORE_EXITING));
1442 vcpu->arch.cr0 = cr0;
1443 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1444 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1445 *hw_cr0 &= ~X86_CR0_WP;
1446 } else if (!is_paging(vcpu)) {
1447 /* From nonpaging to paging */
1448 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1449 vmcs_config.cpu_based_exec_ctrl &
1450 ~(CPU_BASED_CR3_LOAD_EXITING |
1451 CPU_BASED_CR3_STORE_EXITING));
1452 vcpu->arch.cr0 = cr0;
1453 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1454 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1455 *hw_cr0 &= ~X86_CR0_WP;
1456 }
1457}
1458
1459static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1460 struct kvm_vcpu *vcpu)
1461{
1462 if (!is_paging(vcpu)) {
1463 *hw_cr4 &= ~X86_CR4_PAE;
1464 *hw_cr4 |= X86_CR4_PSE;
1465 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1466 *hw_cr4 &= ~X86_CR4_PAE;
1467}
1468
6aa8b732
AK		 1469static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1470{
1439442c
SY		 1471 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1472 KVM_VM_CR0_ALWAYS_ON;
1473
5fd86fcf
AK		 1474 vmx_fpu_deactivate(vcpu);
1475
ad312c7c 1476 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1477 enter_pmode(vcpu);
1478
ad312c7c 1479 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1480 enter_rmode(vcpu);
1481
05b3e0c2 1482#ifdef CONFIG_X86_64
ad312c7c 1483 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1484 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1485 enter_lmode(vcpu);
707d92fa 1486 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1487 exit_lmode(vcpu);
1488 }
1489#endif
1490
1439442c
SY		 1491 if (vm_need_ept())
1492 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1493
6aa8b732 1494 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1495 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1496 vcpu->arch.cr0 = cr0;
5fd86fcf 1497
707d92fa 1498 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1499 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1500}
1501
1439442c
SY		 1502static u64 construct_eptp(unsigned long root_hpa)
1503{
1504 u64 eptp;
1505
1506 /* TODO write the value reading from MSR */
1507 eptp = VMX_EPT_DEFAULT_MT |
1508 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1509 eptp |= (root_hpa & PAGE_MASK);
1510
1511 return eptp;
1512}
1513
6aa8b732
AK		 1514static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1515{
1439442c
SY		 1516 unsigned long guest_cr3;
1517 u64 eptp;
1518
1519 guest_cr3 = cr3;
1520 if (vm_need_ept()) {
1521 eptp = construct_eptp(cr3);
1522 vmcs_write64(EPT_POINTER, eptp);
1523 ept_sync_context(eptp);
1524 ept_load_pdptrs(vcpu);
1525 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1526 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1527 }
1528
2384d2b3 1529 vmx_flush_tlb(vcpu);
1439442c 1530 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1531 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1532 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1533}
1534
1535static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1536{
1439442c
SY		 1537 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1538 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1539
ad312c7c 1540 vcpu->arch.cr4 = cr4;
1439442c
SY		 1541 if (vm_need_ept())
1542 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1543
1544 vmcs_writel(CR4_READ_SHADOW, cr4);
1545 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1546}
1547
6aa8b732
AK		 1548static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1549{
8b9cf98c
RR		 1550 struct vcpu_vmx *vmx = to_vmx(vcpu);
1551 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1552
ad312c7c 1553 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1554 if (!msr)
1555 return;
6aa8b732
AK		 1556 if (efer & EFER_LMA) {
1557 vmcs_write32(VM_ENTRY_CONTROLS,
1558 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1559 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1560 msr->data = efer;
1561
1562 } else {
1563 vmcs_write32(VM_ENTRY_CONTROLS,
1564 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1565 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1566
1567 msr->data = efer & ~EFER_LME;
1568 }
8b9cf98c 1569 setup_msrs(vmx);
6aa8b732
AK		 1570}
1571
6aa8b732
AK		 1572static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1573{
1574 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1575
1576 return vmcs_readl(sf->base);
1577}
1578
1579static void vmx_get_segment(struct kvm_vcpu *vcpu,
1580 struct kvm_segment *var, int seg)
1581{
1582 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1583 u32 ar;
1584
1585 var->base = vmcs_readl(sf->base);
1586 var->limit = vmcs_read32(sf->limit);
1587 var->selector = vmcs_read16(sf->selector);
1588 ar = vmcs_read32(sf->ar_bytes);
1589 if (ar & AR_UNUSABLE_MASK)
1590 ar = 0;
1591 var->type = ar & 15;
1592 var->s = (ar >> 4) & 1;
1593 var->dpl = (ar >> 5) & 3;
1594 var->present = (ar >> 7) & 1;
1595 var->avl = (ar >> 12) & 1;
1596 var->l = (ar >> 13) & 1;
1597 var->db = (ar >> 14) & 1;
1598 var->g = (ar >> 15) & 1;
1599 var->unusable = (ar >> 16) & 1;
1600}
1601
2e4d2653
IE		 1602static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1603{
1604 struct kvm_segment kvm_seg;
1605
1606 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1607 return 0;
1608
1609 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1610 return 3;
1611
1612 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1613 return kvm_seg.selector & 3;
1614}
1615
653e3108 1616static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1617{
6aa8b732
AK		 1618 u32 ar;
1619
653e3108 1620 if (var->unusable)
6aa8b732
AK		 1621 ar = 1 << 16;
1622 else {
1623 ar = var->type & 15;
1624 ar |= (var->s & 1) << 4;
1625 ar |= (var->dpl & 3) << 5;
1626 ar |= (var->present & 1) << 7;
1627 ar |= (var->avl & 1) << 12;
1628 ar |= (var->l & 1) << 13;
1629 ar |= (var->db & 1) << 14;
1630 ar |= (var->g & 1) << 15;
1631 }
f7fbf1fd
UL		 1632 if (ar == 0) /* a 0 value means unusable */
1633 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1634
1635 return ar;
1636}
1637
1638static void vmx_set_segment(struct kvm_vcpu *vcpu,
1639 struct kvm_segment *var, int seg)
1640{
1641 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1642 u32 ar;
1643
ad312c7c
ZX		 1644 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1645 vcpu->arch.rmode.tr.selector = var->selector;
1646 vcpu->arch.rmode.tr.base = var->base;
1647 vcpu->arch.rmode.tr.limit = var->limit;
1648 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1649 return;
1650 }
1651 vmcs_writel(sf->base, var->base);
1652 vmcs_write32(sf->limit, var->limit);
1653 vmcs_write16(sf->selector, var->selector);
ad312c7c 1654 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1655 /*
1656 * Hack real-mode segments into vm86 compatibility.
1657 */
1658 if (var->base == 0xffff0000 && var->selector == 0xf000)
1659 vmcs_writel(sf->base, 0xf0000);
1660 ar = 0xf3;
1661 } else
1662 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1663 vmcs_write32(sf->ar_bytes, ar);
1664}
1665
6aa8b732
AK		 1666static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1667{
1668 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1669
1670 *db = (ar >> 14) & 1;
1671 *l = (ar >> 13) & 1;
1672}
1673
1674static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1675{
1676 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1677 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1678}
1679
1680static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1681{
1682 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1683 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1684}
1685
1686static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1687{
1688 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1689 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1690}
1691
1692static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1693{
1694 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1695 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1696}
1697
d77c26fc 1698static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1699{
6aa8b732 1700 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1701 u16 data = 0;
10589a46 1702 int ret = 0;
195aefde 1703 int r;
6aa8b732 1704
195aefde
IE		 1705 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1706 if (r < 0)
10589a46 1707 goto out;
195aefde
IE		 1708 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1709 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1710 if (r < 0)
10589a46 1711 goto out;
195aefde
IE		 1712 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1713 if (r < 0)
10589a46 1714 goto out;
195aefde
IE		 1715 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1716 if (r < 0)
10589a46 1717 goto out;
195aefde 1718 data = ~0;
10589a46
MT		 1719 r = kvm_write_guest_page(kvm, fn, &data,
1720 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1721 sizeof(u8));
195aefde 1722 if (r < 0)
10589a46
MT		 1723 goto out;
1724
1725 ret = 1;
1726out:
10589a46 1727 return ret;
6aa8b732
AK		 1728}
1729
b7ebfb05
SY		 1730static int init_rmode_identity_map(struct kvm *kvm)
1731{
1732 int i, r, ret;
1733 pfn_t identity_map_pfn;
1734 u32 tmp;
1735
1736 if (!vm_need_ept())
1737 return 1;
1738 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1739 printk(KERN_ERR "EPT: identity-mapping pagetable "
1740 "haven't been allocated!\n");
1741 return 0;
1742 }
1743 if (likely(kvm->arch.ept_identity_pagetable_done))
1744 return 1;
1745 ret = 0;
1746 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1747 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1748 if (r < 0)
1749 goto out;
1750 /* Set up identity-mapping pagetable for EPT in real mode */
1751 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1752 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1753 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1754 r = kvm_write_guest_page(kvm, identity_map_pfn,
1755 &tmp, i * sizeof(tmp), sizeof(tmp));
1756 if (r < 0)
1757 goto out;
1758 }
1759 kvm->arch.ept_identity_pagetable_done = true;
1760 ret = 1;
1761out:
1762 return ret;
1763}
1764
6aa8b732
AK		 1765static void seg_setup(int seg)
1766{
1767 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1768
1769 vmcs_write16(sf->selector, 0);
1770 vmcs_writel(sf->base, 0);
1771 vmcs_write32(sf->limit, 0xffff);
1772 vmcs_write32(sf->ar_bytes, 0x93);
1773}
1774
f78e0e2e
SY		 1775static int alloc_apic_access_page(struct kvm *kvm)
1776{
1777 struct kvm_userspace_memory_region kvm_userspace_mem;
1778 int r = 0;
1779
72dc67a6 1780 down_write(&kvm->slots_lock);
bfc6d222 1781 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1782 goto out;
1783 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1784 kvm_userspace_mem.flags = 0;
1785 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1786 kvm_userspace_mem.memory_size = PAGE_SIZE;
1787 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1788 if (r)
1789 goto out;
72dc67a6
IE		 1790
1791 down_read(&current->mm->mmap_sem);
bfc6d222 1792 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1793 up_read(&current->mm->mmap_sem);
f78e0e2e 1794out:
72dc67a6 1795 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1796 return r;
1797}
1798
b7ebfb05
SY		 1799static int alloc_identity_pagetable(struct kvm *kvm)
1800{
1801 struct kvm_userspace_memory_region kvm_userspace_mem;
1802 int r = 0;
1803
1804 down_write(&kvm->slots_lock);
1805 if (kvm->arch.ept_identity_pagetable)
1806 goto out;
1807 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1808 kvm_userspace_mem.flags = 0;
1809 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1810 kvm_userspace_mem.memory_size = PAGE_SIZE;
1811 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1812 if (r)
1813 goto out;
1814
1815 down_read(&current->mm->mmap_sem);
1816 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1817 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1818 up_read(&current->mm->mmap_sem);
1819out:
1820 up_write(&kvm->slots_lock);
1821 return r;
1822}
1823
2384d2b3
SY		 1824static void allocate_vpid(struct vcpu_vmx *vmx)
1825{
1826 int vpid;
1827
1828 vmx->vpid = 0;
1829 if (!enable_vpid || !cpu_has_vmx_vpid())
1830 return;
1831 spin_lock(&vmx_vpid_lock);
1832 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1833 if (vpid < VMX_NR_VPIDS) {
1834 vmx->vpid = vpid;
1835 __set_bit(vpid, vmx_vpid_bitmap);
1836 }
1837 spin_unlock(&vmx_vpid_lock);
1838}
1839
8b2cf73c 1840static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 1841{
1842 void *va;
1843
1844 if (!cpu_has_vmx_msr_bitmap())
1845 return;
1846
1847 /*
1848 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1849 * have the write-low and read-high bitmap offsets the wrong way round.
1850 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1851 */
1852 va = kmap(msr_bitmap);
1853 if (msr <= 0x1fff) {
1854 __clear_bit(msr, va + 0x000); /* read-low */
1855 __clear_bit(msr, va + 0x800); /* write-low */
1856 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1857 msr &= 0x1fff;
1858 __clear_bit(msr, va + 0x400); /* read-high */
1859 __clear_bit(msr, va + 0xc00); /* write-high */
1860 }
1861 kunmap(msr_bitmap);
1862}
1863
6aa8b732
AK		 1864/*
1865 * Sets up the vmcs for emulated real mode.
1866 */
8b9cf98c 1867static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1868{
1869 u32 host_sysenter_cs;
1870 u32 junk;
1871 unsigned long a;
1872 struct descriptor_table dt;
1873 int i;
cd2276a7 1874 unsigned long kvm_vmx_return;
6e5d865c 1875 u32 exec_control;
6aa8b732 1876
6aa8b732 1877 /* I/O */
fdef3ad1
HQ		 1878 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1879 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1880
25c5f225
SY		 1881 if (cpu_has_vmx_msr_bitmap())
1882 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1883
6aa8b732
AK		 1884 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1885
6aa8b732 1886 /* Control */
1c3d14fe
YS		 1887 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1888 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1889
1890 exec_control = vmcs_config.cpu_based_exec_ctrl;
1891 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1892 exec_control &= ~CPU_BASED_TPR_SHADOW;
1893#ifdef CONFIG_X86_64
1894 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1895 CPU_BASED_CR8_LOAD_EXITING;
1896#endif
1897 }
d56f546d
SY		 1898 if (!vm_need_ept())
1899 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1900 CPU_BASED_CR3_LOAD_EXITING;
6e5d865c 1901 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1902
83ff3b9d
SY		 1903 if (cpu_has_secondary_exec_ctrls()) {
1904 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1905 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1906 exec_control &=
1907 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 1908 if (vmx->vpid == 0)
1909 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 1910 if (!vm_need_ept())
1911 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 1912 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1913 }
f78e0e2e 1914
c7addb90
AK		 1915 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1916 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1917 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1918
1919 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1920 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1921 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1922
1923 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1924 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1925 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1926 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1927 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1928 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1929#ifdef CONFIG_X86_64
6aa8b732
AK		 1930 rdmsrl(MSR_FS_BASE, a);
1931 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1932 rdmsrl(MSR_GS_BASE, a);
1933 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1934#else
1935 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1936 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1937#endif
1938
1939 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1940
1941 get_idt(&dt);
1942 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1943
d77c26fc 1944 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1945 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1946 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1947 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1948 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1949
1950 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1951 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1952 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1953 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1954 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1955 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1956
6aa8b732
AK		 1957 for (i = 0; i < NR_VMX_MSR; ++i) {
1958 u32 index = vmx_msr_index[i];
1959 u32 data_low, data_high;
1960 u64 data;
a2fa3e9f 1961 int j = vmx->nmsrs;
6aa8b732
AK		 1962
1963 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1964 continue;
432bd6cb
AK		 1965 if (wrmsr_safe(index, data_low, data_high) < 0)
1966 continue;
6aa8b732 1967 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1968 vmx->host_msrs[j].index = index;
1969 vmx->host_msrs[j].reserved = 0;
1970 vmx->host_msrs[j].data = data;
1971 vmx->guest_msrs[j] = vmx->host_msrs[j];
1972 ++vmx->nmsrs;
6aa8b732 1973 }
6aa8b732 1974
1c3d14fe 1975 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1976
1977 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1978 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1979
e00c8cf2
AK		 1980 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1981 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1982
f78e0e2e 1983
e00c8cf2
AK		 1984 return 0;
1985}
1986
b7ebfb05
SY		 1987static int init_rmode(struct kvm *kvm)
1988{
1989 if (!init_rmode_tss(kvm))
1990 return 0;
1991 if (!init_rmode_identity_map(kvm))
1992 return 0;
1993 return 1;
1994}
1995
e00c8cf2
AK		 1996static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1997{
1998 struct vcpu_vmx *vmx = to_vmx(vcpu);
1999 u64 msr;
2000 int ret;
2001
3200f405 2002 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2003 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2004 ret = -ENOMEM;
2005 goto out;
2006 }
2007
ad312c7c 2008 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2009
ad312c7c 2010 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2011 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2012 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2013 if (vmx->vcpu.vcpu_id == 0)
2014 msr |= MSR_IA32_APICBASE_BSP;
2015 kvm_set_apic_base(&vmx->vcpu, msr);
2016
2017 fx_init(&vmx->vcpu);
2018
2019 /*
2020 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2021 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2022 */
2023 if (vmx->vcpu.vcpu_id == 0) {
2024 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2025 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2026 } else {
ad312c7c
ZX		 2027 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2028 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 2029 }
2030 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2031 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2032
2033 seg_setup(VCPU_SREG_DS);
2034 seg_setup(VCPU_SREG_ES);
2035 seg_setup(VCPU_SREG_FS);
2036 seg_setup(VCPU_SREG_GS);
2037 seg_setup(VCPU_SREG_SS);
2038
2039 vmcs_write16(GUEST_TR_SELECTOR, 0);
2040 vmcs_writel(GUEST_TR_BASE, 0);
2041 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2042 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2043
2044 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2045 vmcs_writel(GUEST_LDTR_BASE, 0);
2046 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2047 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2048
2049 vmcs_write32(GUEST_SYSENTER_CS, 0);
2050 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2051 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2052
2053 vmcs_writel(GUEST_RFLAGS, 0x02);
2054 if (vmx->vcpu.vcpu_id == 0)
2055 vmcs_writel(GUEST_RIP, 0xfff0);
2056 else
2057 vmcs_writel(GUEST_RIP, 0);
2058 vmcs_writel(GUEST_RSP, 0);
2059
2060 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2061 vmcs_writel(GUEST_DR7, 0x400);
2062
2063 vmcs_writel(GUEST_GDTR_BASE, 0);
2064 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2065
2066 vmcs_writel(GUEST_IDTR_BASE, 0);
2067 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2068
2069 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2070 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2071 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2072
2073 guest_write_tsc(0);
2074
2075 /* Special registers */
2076 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2077
2078 setup_msrs(vmx);
2079
6aa8b732
AK		 2080 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2081
f78e0e2e
SY		 2082 if (cpu_has_vmx_tpr_shadow()) {
2083 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2084 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2085 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2086 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2087 vmcs_write32(TPR_THRESHOLD, 0);
2088 }
2089
2090 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2091 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2092 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2093
2384d2b3
SY		 2094 if (vmx->vpid != 0)
2095 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2096
ad312c7c
ZX		 2097 vmx->vcpu.arch.cr0 = 0x60000010;
2098 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2099 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2100 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2101 vmx_fpu_activate(&vmx->vcpu);
2102 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2103
2384d2b3
SY		 2104 vpid_sync_vcpu_all(vmx);
2105
3200f405 2106 ret = 0;
6aa8b732 2107
6aa8b732 2108out:
3200f405 2109 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2110 return ret;
2111}
2112
85f455f7
ED		 2113static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2114{
9c8cba37
AK		 2115 struct vcpu_vmx *vmx = to_vmx(vcpu);
2116
2714d1d3
FEL		 2117 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2118
ad312c7c 2119 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2120 vmx->rmode.irq.pending = true;
2121 vmx->rmode.irq.vector = irq;
2122 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 2123 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2124 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2125 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 2126 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2127 return;
2128 }
2129 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2130 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2131}
2132
6aa8b732
AK		 2133static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2134{
ad312c7c
ZX		 2135 int word_index = __ffs(vcpu->arch.irq_summary);
2136 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2137 int irq = word_index * BITS_PER_LONG + bit_index;
2138
ad312c7c
ZX		 2139 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2140 if (!vcpu->arch.irq_pending[word_index])
2141 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 2142 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 2143}
2144
c1150d8c
DL		 2145
2146static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2147 struct kvm_run *kvm_run)
6aa8b732 2148{
c1150d8c
DL		 2149 u32 cpu_based_vm_exec_control;
2150
ad312c7c 2151 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 2152 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2153 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2154
ad312c7c
ZX		 2155 if (vcpu->arch.interrupt_window_open &&
2156 vcpu->arch.irq_summary &&
c1150d8c 2157 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 2158 /*
c1150d8c 2159 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 2160 */
2161 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 2162
2163 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 2164 if (!vcpu->arch.interrupt_window_open &&
2165 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 2166 /*
2167 * Interrupts blocked. Wait for unblock.
2168 */
c1150d8c
DL		 2169 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2170 else
2171 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2172 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 2173}
2174
cbc94022
IE		 2175static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2176{
2177 int ret;
2178 struct kvm_userspace_memory_region tss_mem = {
2179 .slot = 8,
2180 .guest_phys_addr = addr,
2181 .memory_size = PAGE_SIZE * 3,
2182 .flags = 0,
2183 };
2184
2185 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2186 if (ret)
2187 return ret;
bfc6d222 2188 kvm->arch.tss_addr = addr;
cbc94022
IE		 2189 return 0;
2190}
2191
6aa8b732
AK		 2192static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2193{
2194 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2195
2196 set_debugreg(dbg->bp[0], 0);
2197 set_debugreg(dbg->bp[1], 1);
2198 set_debugreg(dbg->bp[2], 2);
2199 set_debugreg(dbg->bp[3], 3);
2200
2201 if (dbg->singlestep) {
2202 unsigned long flags;
2203
2204 flags = vmcs_readl(GUEST_RFLAGS);
2205 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2206 vmcs_writel(GUEST_RFLAGS, flags);
2207 }
2208}
2209
2210static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2211 int vec, u32 err_code)
2212{
ad312c7c 2213 if (!vcpu->arch.rmode.active)
6aa8b732
AK		 2214 return 0;
2215
b3f37707
NK		 2216 /*
2217 * Instruction with address size override prefix opcode 0x67
2218 * Cause the #SS fault with 0 error code in VM86 mode.
2219 */
2220 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2221 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 2222 return 1;
2223 return 0;
2224}
2225
2226static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2227{
1155f76a 2228 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2229 u32 intr_info, error_code;
2230 unsigned long cr2, rip;
2231 u32 vect_info;
2232 enum emulation_result er;
2233
1155f76a 2234 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2235 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2236
2237 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2238 !is_page_fault(intr_info))
6aa8b732 2239 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2240 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2241
85f455f7 2242 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2243 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2244 set_bit(irq, vcpu->arch.irq_pending);
2245 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2246 }
2247
1b6269db
AK		 2248 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2249 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2250
2251 if (is_no_device(intr_info)) {
5fd86fcf 2252 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2253 return 1;
2254 }
2255
7aa81cc0 2256 if (is_invalid_opcode(intr_info)) {
571008da 2257 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2258 if (er != EMULATE_DONE)
7ee5d940 2259 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2260 return 1;
2261 }
2262
6aa8b732
AK		 2263 error_code = 0;
2264 rip = vmcs_readl(GUEST_RIP);
2e11384c 2265 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2266 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2267 if (is_page_fault(intr_info)) {
1439442c
SY		 2268 /* EPT won't cause page fault directly */
2269 if (vm_need_ept())
2270 BUG();
6aa8b732 2271 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2272 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2273 (u32)((u64)cr2 >> 32), handler);
3067714c 2274 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2275 }
2276
ad312c7c 2277 if (vcpu->arch.rmode.active &&
6aa8b732 2278 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2279 error_code)) {
ad312c7c
ZX		 2280 if (vcpu->arch.halt_request) {
2281 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2282 return kvm_emulate_halt(vcpu);
2283 }
6aa8b732 2284 return 1;
72d6e5a0 2285 }
6aa8b732 2286
d77c26fc
MD		 2287 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2288 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2289 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2290 return 0;
2291 }
2292 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2293 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2294 kvm_run->ex.error_code = error_code;
2295 return 0;
2296}
2297
2298static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2299 struct kvm_run *kvm_run)
2300{
1165f5fe 2301 ++vcpu->stat.irq_exits;
2714d1d3 2302 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2303 return 1;
2304}
2305
988ad74f
AK		 2306static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2307{
2308 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2309 return 0;
2310}
6aa8b732 2311
6aa8b732
AK		 2312static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2313{
bfdaab09 2314 unsigned long exit_qualification;
039576c0
AK		 2315 int size, down, in, string, rep;
2316 unsigned port;
6aa8b732 2317
1165f5fe 2318 ++vcpu->stat.io_exits;
bfdaab09 2319 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2320 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2321
2322 if (string) {
3427318f
LV		 2323 if (emulate_instruction(vcpu,
2324 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2325 return 0;
2326 return 1;
2327 }
2328
2329 size = (exit_qualification & 7) + 1;
2330 in = (exit_qualification & 8) != 0;
039576c0 2331 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2332 rep = (exit_qualification & 32) != 0;
2333 port = exit_qualification >> 16;
e70669ab 2334
3090dd73 2335 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2336}
2337
102d8325
IM		 2338static void
2339vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2340{
2341 /*
2342 * Patch in the VMCALL instruction:
2343 */
2344 hypercall[0] = 0x0f;
2345 hypercall[1] = 0x01;
2346 hypercall[2] = 0xc1;
102d8325
IM		 2347}
2348
6aa8b732
AK		 2349static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2350{
bfdaab09 2351 unsigned long exit_qualification;
6aa8b732
AK		 2352 int cr;
2353 int reg;
2354
bfdaab09 2355 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2356 cr = exit_qualification & 15;
2357 reg = (exit_qualification >> 8) & 15;
2358 switch ((exit_qualification >> 4) & 3) {
2359 case 0: /* mov to cr */
2714d1d3
FEL		 2360 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2361 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
6aa8b732
AK		 2362 switch (cr) {
2363 case 0:
2364 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2365 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2366 skip_emulated_instruction(vcpu);
2367 return 1;
2368 case 3:
2369 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2370 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2371 skip_emulated_instruction(vcpu);
2372 return 1;
2373 case 4:
2374 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2375 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2376 skip_emulated_instruction(vcpu);
2377 return 1;
2378 case 8:
2379 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2380 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
6aa8b732 2381 skip_emulated_instruction(vcpu);
e5314067
AK		 2382 if (irqchip_in_kernel(vcpu->kvm))
2383 return 1;
253abdee
YS		 2384 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2385 return 0;
6aa8b732
AK		 2386 };
2387 break;
25c4c276
AL		 2388 case 2: /* clts */
2389 vcpu_load_rsp_rip(vcpu);
5fd86fcf 2390 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2391 vcpu->arch.cr0 &= ~X86_CR0_TS;
2392 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2393 vmx_fpu_activate(vcpu);
2714d1d3 2394 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2395 skip_emulated_instruction(vcpu);
2396 return 1;
6aa8b732
AK		 2397 case 1: /*mov from cr*/
2398 switch (cr) {
2399 case 3:
2400 vcpu_load_rsp_rip(vcpu);
ad312c7c 2401 vcpu->arch.regs[reg] = vcpu->arch.cr3;
6aa8b732 2402 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2403 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2404 (u32)vcpu->arch.regs[reg],
2405 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2406 handler);
6aa8b732
AK		 2407 skip_emulated_instruction(vcpu);
2408 return 1;
2409 case 8:
6aa8b732 2410 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2411 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
6aa8b732 2412 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2413 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2414 (u32)vcpu->arch.regs[reg], handler);
6aa8b732
AK		 2415 skip_emulated_instruction(vcpu);
2416 return 1;
2417 }
2418 break;
2419 case 3: /* lmsw */
2d3ad1f4 2420 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2421
2422 skip_emulated_instruction(vcpu);
2423 return 1;
2424 default:
2425 break;
2426 }
2427 kvm_run->exit_reason = 0;
f0242478 2428 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2429 (int)(exit_qualification >> 4) & 3, cr);
2430 return 0;
2431}
2432
2433static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2434{
bfdaab09 2435 unsigned long exit_qualification;
6aa8b732
AK		 2436 unsigned long val;
2437 int dr, reg;
2438
2439 /*
2440 * FIXME: this code assumes the host is debugging the guest.
2441 * need to deal with guest debugging itself too.
2442 */
bfdaab09 2443 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2444 dr = exit_qualification & 7;
2445 reg = (exit_qualification >> 8) & 15;
2446 vcpu_load_rsp_rip(vcpu);
2447 if (exit_qualification & 16) {
2448 /* mov from dr */
2449 switch (dr) {
2450 case 6:
2451 val = 0xffff0ff0;
2452 break;
2453 case 7:
2454 val = 0x400;
2455 break;
2456 default:
2457 val = 0;
2458 }
ad312c7c 2459 vcpu->arch.regs[reg] = val;
2714d1d3 2460 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2461 } else {
2462 /* mov to dr */
2463 }
2464 vcpu_put_rsp_rip(vcpu);
2465 skip_emulated_instruction(vcpu);
2466 return 1;
2467}
2468
2469static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2470{
06465c5a
AK		 2471 kvm_emulate_cpuid(vcpu);
2472 return 1;
6aa8b732
AK		 2473}
2474
2475static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2476{
ad312c7c 2477 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2478 u64 data;
2479
2480 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2481 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2482 return 1;
2483 }
2484
2714d1d3
FEL		 2485 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2486 handler);
2487
6aa8b732 2488 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2489 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2490 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2491 skip_emulated_instruction(vcpu);
2492 return 1;
2493}
2494
2495static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2496{
ad312c7c
ZX		 2497 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2498 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2499 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2500
2714d1d3
FEL		 2501 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2502 handler);
2503
6aa8b732 2504 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2505 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2506 return 1;
2507 }
2508
2509 skip_emulated_instruction(vcpu);
2510 return 1;
2511}
2512
6e5d865c
YS		 2513static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2514 struct kvm_run *kvm_run)
2515{
2516 return 1;
2517}
2518
6aa8b732
AK		 2519static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2520 struct kvm_run *kvm_run)
2521{
85f455f7
ED		 2522 u32 cpu_based_vm_exec_control;
2523
2524 /* clear pending irq */
2525 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2526 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2527 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2528
2529 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2530
c1150d8c
DL		 2531 /*
2532 * If the user space waits to inject interrupts, exit as soon as
2533 * possible
2534 */
2535 if (kvm_run->request_interrupt_window &&
ad312c7c 2536 !vcpu->arch.irq_summary) {
c1150d8c 2537 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2538 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2539 return 0;
2540 }
6aa8b732
AK		 2541 return 1;
2542}
2543
2544static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2545{
2546 skip_emulated_instruction(vcpu);
d3bef15f 2547 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2548}
2549
c21415e8
IM		 2550static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2551{
510043da 2552 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2553 kvm_emulate_hypercall(vcpu);
2554 return 1;
c21415e8
IM		 2555}
2556
e5edaa01
ED		 2557static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2558{
2559 skip_emulated_instruction(vcpu);
2560 /* TODO: Add support for VT-d/pass-through device */
2561 return 1;
2562}
2563
f78e0e2e
SY		 2564static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2565{
2566 u64 exit_qualification;
2567 enum emulation_result er;
2568 unsigned long offset;
2569
2570 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2571 offset = exit_qualification & 0xffful;
2572
2573 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2574
2575 if (er != EMULATE_DONE) {
2576 printk(KERN_ERR
2577 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2578 offset);
2579 return -ENOTSUPP;
2580 }
2581 return 1;
2582}
2583
37817f29
IE		 2584static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2585{
2586 unsigned long exit_qualification;
2587 u16 tss_selector;
2588 int reason;
2589
2590 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2591
2592 reason = (u32)exit_qualification >> 30;
2593 tss_selector = exit_qualification;
2594
2595 return kvm_task_switch(vcpu, tss_selector, reason);
2596}
2597
1439442c
SY		 2598static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2599{
2600 u64 exit_qualification;
2601 enum emulation_result er;
2602 gpa_t gpa;
2603 unsigned long hva;
2604 int gla_validity;
2605 int r;
2606
2607 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2608
2609 if (exit_qualification & (1 << 6)) {
2610 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2611 return -ENOTSUPP;
2612 }
2613
2614 gla_validity = (exit_qualification >> 7) & 0x3;
2615 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2616 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2617 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2618 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2619 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2620 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2621 (long unsigned int)exit_qualification);
2622 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2623 kvm_run->hw.hardware_exit_reason = 0;
2624 return -ENOTSUPP;
2625 }
2626
2627 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2628 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2629 if (!kvm_is_error_hva(hva)) {
2630 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2631 if (r < 0) {
2632 printk(KERN_ERR "EPT: Not enough memory!\n");
2633 return -ENOMEM;
2634 }
2635 return 1;
2636 } else {
2637 /* must be MMIO */
2638 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2639
2640 if (er == EMULATE_FAIL) {
2641 printk(KERN_ERR
2642 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2643 er);
2644 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2645 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2646 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2647 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2648 (long unsigned int)exit_qualification);
2649 return -ENOTSUPP;
2650 } else if (er == EMULATE_DO_MMIO)
2651 return 0;
2652 }
2653 return 1;
2654}
2655
6aa8b732
AK		 2656/*
2657 * The exit handlers return 1 if the exit was handled fully and guest execution
2658 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2659 * to be done to userspace and return 0.
2660 */
2661static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2662 struct kvm_run *kvm_run) = {
2663 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2664 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2665 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2666 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2667 [EXIT_REASON_CR_ACCESS] = handle_cr,
2668 [EXIT_REASON_DR_ACCESS] = handle_dr,
2669 [EXIT_REASON_CPUID] = handle_cpuid,
2670 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2671 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2672 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2673 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2674 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2675 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2676 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2677 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 2678 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 2679 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 2680};
2681
2682static const int kvm_vmx_max_exit_handlers =
50a3485c 2683 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2684
2685/*
2686 * The guest has exited. See if we can fix it or if we need userspace
2687 * assistance.
2688 */
2689static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2690{
6aa8b732 2691 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2692 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2693 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 2694
2714d1d3
FEL		 2695 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2696 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2697
1439442c
SY		 2698 /* Access CR3 don't cause VMExit in paging mode, so we need
2699 * to sync with guest real CR3. */
2700 if (vm_need_ept() && is_paging(vcpu)) {
2701 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2702 ept_load_pdptrs(vcpu);
2703 }
2704
29bd8a78
AK		 2705 if (unlikely(vmx->fail)) {
2706 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2707 kvm_run->fail_entry.hardware_entry_failure_reason
2708 = vmcs_read32(VM_INSTRUCTION_ERROR);
2709 return 0;
2710 }
6aa8b732 2711
d77c26fc 2712 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c
SY		 2713 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2714 exit_reason != EXIT_REASON_EPT_VIOLATION))
6aa8b732 2715 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2716 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2717 if (exit_reason < kvm_vmx_max_exit_handlers
2718 && kvm_vmx_exit_handlers[exit_reason])
2719 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2720 else {
2721 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2722 kvm_run->hw.hardware_exit_reason = exit_reason;
2723 }
2724 return 0;
2725}
2726
6e5d865c
YS		 2727static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2728{
2729 int max_irr, tpr;
2730
2731 if (!vm_need_tpr_shadow(vcpu->kvm))
2732 return;
2733
2734 if (!kvm_lapic_enabled(vcpu) ||
2735 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2736 vmcs_write32(TPR_THRESHOLD, 0);
2737 return;
2738 }
2739
2740 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2741 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2742}
2743
85f455f7
ED		 2744static void enable_irq_window(struct kvm_vcpu *vcpu)
2745{
2746 u32 cpu_based_vm_exec_control;
2747
2748 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2749 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2750 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2751}
2752
2753static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2754{
1155f76a 2755 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2756 u32 idtv_info_field, intr_info_field;
2757 int has_ext_irq, interrupt_window_open;
1b9778da 2758 int vector;
85f455f7 2759
6e5d865c
YS		 2760 update_tpr_threshold(vcpu);
2761
85f455f7
ED		 2762 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2763 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2764 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2765 if (intr_info_field & INTR_INFO_VALID_MASK) {
2766 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2767 /* TODO: fault when IDT_Vectoring */
9584bf2c
RH		 2768 if (printk_ratelimit())
2769 printk(KERN_ERR "Fault when IDT_Vectoring\n");
85f455f7
ED		 2770 }
2771 if (has_ext_irq)
2772 enable_irq_window(vcpu);
2773 return;
2774 }
2775 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2776 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2777 == INTR_TYPE_EXT_INTR
ad312c7c 2778 && vcpu->arch.rmode.active) {
9c8cba37
AK		 2779 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2780
2781 vmx_inject_irq(vcpu, vect);
2782 if (unlikely(has_ext_irq))
2783 enable_irq_window(vcpu);
2784 return;
2785 }
2786
2714d1d3
FEL		 2787 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2788
85f455f7
ED		 2789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2790 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2791 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2792
2e11384c 2793 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
85f455f7
ED		 2794 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2795 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2796 if (unlikely(has_ext_irq))
2797 enable_irq_window(vcpu);
2798 return;
2799 }
2800 if (!has_ext_irq)
2801 return;
2802 interrupt_window_open =
2803 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2804 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2805 if (interrupt_window_open) {
2806 vector = kvm_cpu_get_interrupt(vcpu);
2807 vmx_inject_irq(vcpu, vector);
2808 kvm_timer_intr_post(vcpu, vector);
2809 } else
85f455f7
ED		 2810 enable_irq_window(vcpu);
2811}
2812
9c8cba37
AK		 2813/*
2814 * Failure to inject an interrupt should give us the information
2815 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2816 * when fetching the interrupt redirection bitmap in the real-mode
2817 * tss, this doesn't happen. So we do it ourselves.
2818 */
2819static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2820{
2821 vmx->rmode.irq.pending = 0;
2822 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2823 return;
2824 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2825 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2826 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2827 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2828 return;
2829 }
2830 vmx->idt_vectoring_info =
2831 VECTORING_INFO_VALID_MASK
2832 | INTR_TYPE_EXT_INTR
2833 | vmx->rmode.irq.vector;
2834}
2835
04d2cc77 2836static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2837{
a2fa3e9f 2838 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2839 u32 intr_info;
e6adf283
AK		 2840
2841 /*
2842 * Loading guest fpu may have cleared host cr0.ts
2843 */
2844 vmcs_writel(HOST_CR0, read_cr0());
2845
d77c26fc 2846 asm(
6aa8b732 2847 /* Store host registers */
05b3e0c2 2848#ifdef CONFIG_X86_64
c2036300 2849 "push %%rdx; push %%rbp;"
6aa8b732 2850 "push %%rcx \n\t"
6aa8b732 2851#else
ff593e5a
LV		 2852 "push %%edx; push %%ebp;"
2853 "push %%ecx \n\t"
6aa8b732 2854#endif
4ecac3fd 2855 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6aa8b732 2856 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2857 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2858 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2859#ifdef CONFIG_X86_64
e08aa78a 2860 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2861 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2862 "mov %c[rax](%0), %%rax \n\t"
2863 "mov %c[rbx](%0), %%rbx \n\t"
2864 "mov %c[rdx](%0), %%rdx \n\t"
2865 "mov %c[rsi](%0), %%rsi \n\t"
2866 "mov %c[rdi](%0), %%rdi \n\t"
2867 "mov %c[rbp](%0), %%rbp \n\t"
2868 "mov %c[r8](%0), %%r8 \n\t"
2869 "mov %c[r9](%0), %%r9 \n\t"
2870 "mov %c[r10](%0), %%r10 \n\t"
2871 "mov %c[r11](%0), %%r11 \n\t"
2872 "mov %c[r12](%0), %%r12 \n\t"
2873 "mov %c[r13](%0), %%r13 \n\t"
2874 "mov %c[r14](%0), %%r14 \n\t"
2875 "mov %c[r15](%0), %%r15 \n\t"
2876 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2877#else
e08aa78a 2878 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2879 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2880 "mov %c[rax](%0), %%eax \n\t"
2881 "mov %c[rbx](%0), %%ebx \n\t"
2882 "mov %c[rdx](%0), %%edx \n\t"
2883 "mov %c[rsi](%0), %%esi \n\t"
2884 "mov %c[rdi](%0), %%edi \n\t"
2885 "mov %c[rbp](%0), %%ebp \n\t"
2886 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2887#endif
2888 /* Enter guest mode */
cd2276a7 2889 "jne .Llaunched \n\t"
4ecac3fd 2890 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 2891 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 2892 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 2893 ".Lkvm_vmx_return: "
6aa8b732 2894 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2895#ifdef CONFIG_X86_64
e08aa78a
AK		 2896 "xchg %0, (%%rsp) \n\t"
2897 "mov %%rax, %c[rax](%0) \n\t"
2898 "mov %%rbx, %c[rbx](%0) \n\t"
2899 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2900 "mov %%rdx, %c[rdx](%0) \n\t"
2901 "mov %%rsi, %c[rsi](%0) \n\t"
2902 "mov %%rdi, %c[rdi](%0) \n\t"
2903 "mov %%rbp, %c[rbp](%0) \n\t"
2904 "mov %%r8, %c[r8](%0) \n\t"
2905 "mov %%r9, %c[r9](%0) \n\t"
2906 "mov %%r10, %c[r10](%0) \n\t"
2907 "mov %%r11, %c[r11](%0) \n\t"
2908 "mov %%r12, %c[r12](%0) \n\t"
2909 "mov %%r13, %c[r13](%0) \n\t"
2910 "mov %%r14, %c[r14](%0) \n\t"
2911 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2912 "mov %%cr2, %%rax \n\t"
e08aa78a 2913 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2914
e08aa78a 2915 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2916#else
e08aa78a
AK		 2917 "xchg %0, (%%esp) \n\t"
2918 "mov %%eax, %c[rax](%0) \n\t"
2919 "mov %%ebx, %c[rbx](%0) \n\t"
2920 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2921 "mov %%edx, %c[rdx](%0) \n\t"
2922 "mov %%esi, %c[rsi](%0) \n\t"
2923 "mov %%edi, %c[rdi](%0) \n\t"
2924 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2925 "mov %%cr2, %%eax \n\t"
e08aa78a 2926 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2927
e08aa78a 2928 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2929#endif
e08aa78a
AK		 2930 "setbe %c[fail](%0) \n\t"
2931 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2932 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2933 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 2934 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2935 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2936 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2937 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2938 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2939 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2940 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 2941#ifdef CONFIG_X86_64
ad312c7c
ZX		 2942 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2943 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2944 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2945 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2946 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2947 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2948 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2949 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 2950#endif
ad312c7c 2951 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 2952 : "cc", "memory"
2953#ifdef CONFIG_X86_64
2954 , "rbx", "rdi", "rsi"
2955 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2956#else
2957 , "ebx", "edi", "rsi"
c2036300
LV		 2958#endif
2959 );
6aa8b732 2960
1155f76a 2961 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2962 if (vmx->rmode.irq.pending)
2963 fixup_rmode_irq(vmx);
1155f76a 2964
ad312c7c 2965 vcpu->arch.interrupt_window_open =
d77c26fc 2966 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2967
d77c26fc 2968 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2969 vmx->launched = 1;
1b6269db
AK		 2970
2971 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2972
2973 /* We need to handle NMIs before interrupts are enabled */
2714d1d3
FEL		 2974 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2975 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 2976 asm("int $2");
2714d1d3 2977 }
6aa8b732
AK		 2978}
2979
6aa8b732
AK		 2980static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2981{
a2fa3e9f
GH		 2982 struct vcpu_vmx *vmx = to_vmx(vcpu);
2983
2984 if (vmx->vmcs) {
543e4243 2985 vcpu_clear(vmx);
a2fa3e9f
GH		 2986 free_vmcs(vmx->vmcs);
2987 vmx->vmcs = NULL;
6aa8b732
AK		 2988 }
2989}
2990
2991static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2992{
fb3f0f51
RR		 2993 struct vcpu_vmx *vmx = to_vmx(vcpu);
2994
2384d2b3
SY		 2995 spin_lock(&vmx_vpid_lock);
2996 if (vmx->vpid != 0)
2997 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2998 spin_unlock(&vmx_vpid_lock);
6aa8b732 2999 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3000 kfree(vmx->host_msrs);
3001 kfree(vmx->guest_msrs);
3002 kvm_vcpu_uninit(vcpu);
a4770347 3003 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3004}
3005
fb3f0f51 3006static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3007{
fb3f0f51 3008 int err;
c16f862d 3009 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3010 int cpu;
6aa8b732 3011
a2fa3e9f 3012 if (!vmx)
fb3f0f51
RR		 3013 return ERR_PTR(-ENOMEM);
3014
2384d2b3 3015 allocate_vpid(vmx);
1439442c
SY		 3016 if (id == 0 && vm_need_ept()) {
3017 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3018 VMX_EPT_WRITABLE_MASK |
3019 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3020 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3021 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3022 VMX_EPT_EXECUTABLE_MASK);
3023 kvm_enable_tdp();
3024 }
2384d2b3 3025
fb3f0f51
RR		 3026 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3027 if (err)
3028 goto free_vcpu;
965b58a5 3029
a2fa3e9f 3030 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3031 if (!vmx->guest_msrs) {
3032 err = -ENOMEM;
3033 goto uninit_vcpu;
3034 }
965b58a5 3035
a2fa3e9f
GH		 3036 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3037 if (!vmx->host_msrs)
fb3f0f51 3038 goto free_guest_msrs;
965b58a5 3039
a2fa3e9f
GH		 3040 vmx->vmcs = alloc_vmcs();
3041 if (!vmx->vmcs)
fb3f0f51 3042 goto free_msrs;
a2fa3e9f
GH		 3043
3044 vmcs_clear(vmx->vmcs);
3045
15ad7146
AK		 3046 cpu = get_cpu();
3047 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3048 err = vmx_vcpu_setup(vmx);
fb3f0f51 3049 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3050 put_cpu();
fb3f0f51
RR		 3051 if (err)
3052 goto free_vmcs;
5e4a0b3c
MT		 3053 if (vm_need_virtualize_apic_accesses(kvm))
3054 if (alloc_apic_access_page(kvm) != 0)
3055 goto free_vmcs;
fb3f0f51 3056
b7ebfb05
SY		 3057 if (vm_need_ept())
3058 if (alloc_identity_pagetable(kvm) != 0)
3059 goto free_vmcs;
3060
fb3f0f51
RR		 3061 return &vmx->vcpu;
3062
3063free_vmcs:
3064 free_vmcs(vmx->vmcs);
3065free_msrs:
3066 kfree(vmx->host_msrs);
3067free_guest_msrs:
3068 kfree(vmx->guest_msrs);
3069uninit_vcpu:
3070 kvm_vcpu_uninit(&vmx->vcpu);
3071free_vcpu:
a4770347 3072 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3073 return ERR_PTR(err);
6aa8b732
AK		 3074}
3075
002c7f7c
YS		 3076static void __init vmx_check_processor_compat(void *rtn)
3077{
3078 struct vmcs_config vmcs_conf;
3079
3080 *(int *)rtn = 0;
3081 if (setup_vmcs_config(&vmcs_conf) < 0)
3082 *(int *)rtn = -EIO;
3083 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3084 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3085 smp_processor_id());
3086 *(int *)rtn = -EIO;
3087 }
3088}
3089
67253af5
SY		 3090static int get_ept_level(void)
3091{
3092 return VMX_EPT_DEFAULT_GAW + 1;
3093}
3094
cbdd1bea 3095static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3096 .cpu_has_kvm_support = cpu_has_kvm_support,
3097 .disabled_by_bios = vmx_disabled_by_bios,
3098 .hardware_setup = hardware_setup,
3099 .hardware_unsetup = hardware_unsetup,
002c7f7c 3100 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3101 .hardware_enable = hardware_enable,
3102 .hardware_disable = hardware_disable,
774ead3a 3103 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3104
3105 .vcpu_create = vmx_create_vcpu,
3106 .vcpu_free = vmx_free_vcpu,
04d2cc77 3107 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3108
04d2cc77 3109 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3110 .vcpu_load = vmx_vcpu_load,
3111 .vcpu_put = vmx_vcpu_put,
3112
3113 .set_guest_debug = set_guest_debug,
04d2cc77 3114 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3115 .get_msr = vmx_get_msr,
3116 .set_msr = vmx_set_msr,
3117 .get_segment_base = vmx_get_segment_base,
3118 .get_segment = vmx_get_segment,
3119 .set_segment = vmx_set_segment,
2e4d2653 3120 .get_cpl = vmx_get_cpl,
6aa8b732 3121 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3122 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3123 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3124 .set_cr3 = vmx_set_cr3,
3125 .set_cr4 = vmx_set_cr4,
6aa8b732 3126 .set_efer = vmx_set_efer,
6aa8b732
AK		 3127 .get_idt = vmx_get_idt,
3128 .set_idt = vmx_set_idt,
3129 .get_gdt = vmx_get_gdt,
3130 .set_gdt = vmx_set_gdt,
3131 .cache_regs = vcpu_load_rsp_rip,
3132 .decache_regs = vcpu_put_rsp_rip,
3133 .get_rflags = vmx_get_rflags,
3134 .set_rflags = vmx_set_rflags,
3135
3136 .tlb_flush = vmx_flush_tlb,
6aa8b732 3137
6aa8b732 3138 .run = vmx_vcpu_run,
04d2cc77 3139 .handle_exit = kvm_handle_exit,
6aa8b732 3140 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3141 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3142 .get_irq = vmx_get_irq,
3143 .set_irq = vmx_inject_irq,
298101da
AK		 3144 .queue_exception = vmx_queue_exception,
3145 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3146 .inject_pending_irq = vmx_intr_assist,
3147 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3148
3149 .set_tss_addr = vmx_set_tss_addr,
67253af5 3150 .get_tdp_level = get_ept_level,
6aa8b732
AK		 3151};
3152
3153static int __init vmx_init(void)
3154{
25c5f225 3155 void *va;
fdef3ad1
HQ		 3156 int r;
3157
3158 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3159 if (!vmx_io_bitmap_a)
3160 return -ENOMEM;
3161
3162 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3163 if (!vmx_io_bitmap_b) {
3164 r = -ENOMEM;
3165 goto out;
3166 }
3167
25c5f225
SY		 3168 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3169 if (!vmx_msr_bitmap) {
3170 r = -ENOMEM;
3171 goto out1;
3172 }
3173
fdef3ad1
HQ		 3174 /*
3175 * Allow direct access to the PC debug port (it is often used for I/O
3176 * delays, but the vmexits simply slow things down).
3177 */
25c5f225
SY		 3178 va = kmap(vmx_io_bitmap_a);
3179 memset(va, 0xff, PAGE_SIZE);
3180 clear_bit(0x80, va);
cd0536d7 3181 kunmap(vmx_io_bitmap_a);
fdef3ad1 3182
25c5f225
SY		 3183 va = kmap(vmx_io_bitmap_b);
3184 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3185 kunmap(vmx_io_bitmap_b);
fdef3ad1 3186
25c5f225
SY		 3187 va = kmap(vmx_msr_bitmap);
3188 memset(va, 0xff, PAGE_SIZE);
3189 kunmap(vmx_msr_bitmap);
3190
2384d2b3
SY		 3191 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3192
cb498ea2 3193 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3194 if (r)
25c5f225
SY		 3195 goto out2;
3196
3197 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3198 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3199 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3200 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3201 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3202
1439442c
SY		 3203 if (cpu_has_vmx_ept())
3204 bypass_guest_pf = 0;
3205
c7addb90
AK		 3206 if (bypass_guest_pf)
3207 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3208
1439442c
SY		 3209 ept_sync_global();
3210
fdef3ad1
HQ		 3211 return 0;
3212
25c5f225
SY		 3213out2:
3214 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3215out1:
3216 __free_page(vmx_io_bitmap_b);
3217out:
3218 __free_page(vmx_io_bitmap_a);
3219 return r;
6aa8b732
AK		 3220}
3221
3222static void __exit vmx_exit(void)
3223{
25c5f225 3224 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3225 __free_page(vmx_io_bitmap_b);
3226 __free_page(vmx_io_bitmap_a);
3227
cb498ea2 3228 kvm_exit();
6aa8b732
AK		 3229}
3230
3231module_init(vmx_init)
3232module_exit(vmx_exit)
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