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KVM: Update cr8 intercept when APIC TPR is changed by userspace
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
410e4d57
JR		 50#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
24e09cbf
JR		 54#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
c0725420
AG		 56/* Turn on to get debugging output*/
57/* #define NESTED_DEBUG */
58
59#ifdef NESTED_DEBUG
60#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61#else
62#define nsvm_printk(fmt, args...) do {} while(0)
63#endif
64
6c8166a7
AK		 65static const u32 host_save_user_msrs[] = {
66#ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69#endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71};
72
73#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75struct kvm_vcpu;
76
e6aa9abd
JR		 77struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
aad42c64
JR		 87
88 /* cache for intercepts of the guest */
89 u16 intercept_cr_read;
90 u16 intercept_cr_write;
91 u16 intercept_dr_read;
92 u16 intercept_dr_write;
93 u32 intercept_exceptions;
94 u64 intercept;
95
e6aa9abd
JR		 96};
97
6c8166a7
AK		 98struct vcpu_svm {
99 struct kvm_vcpu vcpu;
100 struct vmcb *vmcb;
101 unsigned long vmcb_pa;
102 struct svm_cpu_data *svm_data;
103 uint64_t asid_generation;
104 uint64_t sysenter_esp;
105 uint64_t sysenter_eip;
106
107 u64 next_rip;
108
109 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 u64 host_gs_base;
6c8166a7
AK		 111
112 u32 *msrpm;
6c8166a7 113
e6aa9abd 114 struct nested_state nested;
6c8166a7
AK		 115};
116
709ddebf
JR		 117/* enable NPT for AMD64 and X86 with PAE */
118#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119static bool npt_enabled = true;
120#else
e3da3acd 121static bool npt_enabled = false;
709ddebf 122#endif
6c7dac72
JR		 123static int npt = 1;
124
125module_param(npt, int, S_IRUGO);
e3da3acd 126
4b6e4dca 127static int nested = 1;
236de055
AG		 128module_param(nested, int, S_IRUGO);
129
44874f84 130static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 131static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 132
410e4d57 133static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 134static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 135static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
136 bool has_error_code, u32 error_code);
137
a2fa3e9f
GH		 138static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
139{
fb3f0f51 140 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 141}
142
3d6368ef
AG		 143static inline bool is_nested(struct vcpu_svm *svm)
144{
e6aa9abd 145 return svm->nested.vmcb;
3d6368ef
AG		 146}
147
2af9194d
JR		 148static inline void enable_gif(struct vcpu_svm *svm)
149{
150 svm->vcpu.arch.hflags |= HF_GIF_MASK;
151}
152
153static inline void disable_gif(struct vcpu_svm *svm)
154{
155 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
156}
157
158static inline bool gif_set(struct vcpu_svm *svm)
159{
160 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
161}
162
4866d5e3 163static unsigned long iopm_base;
6aa8b732
AK		 164
165struct kvm_ldttss_desc {
166 u16 limit0;
167 u16 base0;
168 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
169 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
170 u32 base3;
171 u32 zero1;
172} __attribute__((packed));
173
174struct svm_cpu_data {
175 int cpu;
176
5008fdf5
AK		 177 u64 asid_generation;
178 u32 max_asid;
179 u32 next_asid;
6aa8b732
AK		 180 struct kvm_ldttss_desc *tss_desc;
181
182 struct page *save_area;
183};
184
185static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 186static uint32_t svm_features;
6aa8b732
AK		 187
188struct svm_init_data {
189 int cpu;
190 int r;
191};
192
193static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
194
9d8f549d 195#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 196#define MSRS_RANGE_SIZE 2048
197#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198
199#define MAX_INST_SIZE 15
200
80b7706e
JR		 201static inline u32 svm_has(u32 feat)
202{
203 return svm_features & feat;
204}
205
6aa8b732
AK		 206static inline void clgi(void)
207{
4ecac3fd 208 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 209}
210
211static inline void stgi(void)
212{
4ecac3fd 213 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 214}
215
216static inline void invlpga(unsigned long addr, u32 asid)
217{
4ecac3fd 218 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 219}
220
6aa8b732
AK		 221static inline void force_new_asid(struct kvm_vcpu *vcpu)
222{
a2fa3e9f 223 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 224}
225
226static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
227{
228 force_new_asid(vcpu);
229}
230
231static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
232{
709ddebf 233 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 234 efer &= ~EFER_LME;
6aa8b732 235
9962d032 236 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 237 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 238}
239
298101da
AK		 240static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
241 bool has_error_code, u32 error_code)
242{
243 struct vcpu_svm *svm = to_svm(vcpu);
244
cf74a78b
AG		 245 /* If we are within a nested VM we'd better #VMEXIT and let the
246 guest handle the exception */
247 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
248 return;
249
298101da
AK		 250 svm->vmcb->control.event_inj = nr
251 | SVM_EVTINJ_VALID
252 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
253 | SVM_EVTINJ_TYPE_EXEPT;
254 svm->vmcb->control.event_inj_err = error_code;
255}
256
6aa8b732
AK		 257static int is_external_interrupt(u32 info)
258{
259 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
260 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
261}
262
2809f5d2
GC		 263static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
264{
265 struct vcpu_svm *svm = to_svm(vcpu);
266 u32 ret = 0;
267
268 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
269 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
270 return ret & mask;
271}
272
273static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274{
275 struct vcpu_svm *svm = to_svm(vcpu);
276
277 if (mask == 0)
278 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
279 else
280 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
281
282}
283
6aa8b732
AK		 284static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
285{
a2fa3e9f
GH		 286 struct vcpu_svm *svm = to_svm(vcpu);
287
288 if (!svm->next_rip) {
f629cf84
GN		 289 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
290 EMULATE_DONE)
291 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 292 return;
293 }
5fdbf976
MT		 294 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
295 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
296 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 297
5fdbf976 298 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 299 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 300}
301
302static int has_svm(void)
303{
63d1142f 304 const char *msg;
6aa8b732 305
63d1142f 306 if (!cpu_has_svm(&msg)) {
ff81ff10 307 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 308 return 0;
309 }
310
6aa8b732
AK		 311 return 1;
312}
313
314static void svm_hardware_disable(void *garbage)
315{
2c8dceeb 316 cpu_svm_disable();
6aa8b732
AK		 317}
318
319static void svm_hardware_enable(void *garbage)
320{
321
322 struct svm_cpu_data *svm_data;
323 uint64_t efer;
b792c344 324 struct descriptor_table gdt_descr;
6aa8b732
AK		 325 struct desc_struct *gdt;
326 int me = raw_smp_processor_id();
327
328 if (!has_svm()) {
329 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
330 return;
331 }
332 svm_data = per_cpu(svm_data, me);
333
334 if (!svm_data) {
335 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
336 me);
337 return;
338 }
339
340 svm_data->asid_generation = 1;
341 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
342 svm_data->next_asid = svm_data->max_asid + 1;
343
b792c344
AM		 344 kvm_get_gdt(&gdt_descr);
345 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 346 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
347
348 rdmsrl(MSR_EFER, efer);
9962d032 349 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 350
351 wrmsrl(MSR_VM_HSAVE_PA,
352 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
353}
354
0da1db75
JR		 355static void svm_cpu_uninit(int cpu)
356{
357 struct svm_cpu_data *svm_data
358 = per_cpu(svm_data, raw_smp_processor_id());
359
360 if (!svm_data)
361 return;
362
363 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
364 __free_page(svm_data->save_area);
365 kfree(svm_data);
366}
367
6aa8b732
AK		 368static int svm_cpu_init(int cpu)
369{
370 struct svm_cpu_data *svm_data;
371 int r;
372
373 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
374 if (!svm_data)
375 return -ENOMEM;
376 svm_data->cpu = cpu;
377 svm_data->save_area = alloc_page(GFP_KERNEL);
378 r = -ENOMEM;
379 if (!svm_data->save_area)
380 goto err_1;
381
382 per_cpu(svm_data, cpu) = svm_data;
383
384 return 0;
385
386err_1:
387 kfree(svm_data);
388 return r;
389
390}
391
bfc733a7
RR		 392static void set_msr_interception(u32 *msrpm, unsigned msr,
393 int read, int write)
6aa8b732
AK		 394{
395 int i;
396
397 for (i = 0; i < NUM_MSR_MAPS; i++) {
398 if (msr >= msrpm_ranges[i] &&
399 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
400 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
401 msrpm_ranges[i]) * 2;
402
403 u32 *base = msrpm + (msr_offset / 32);
404 u32 msr_shift = msr_offset % 32;
405 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
406 *base = (*base & ~(0x3 << msr_shift)) |
407 (mask << msr_shift);
bfc733a7 408 return;
6aa8b732
AK		 409 }
410 }
bfc733a7 411 BUG();
6aa8b732
AK		 412}
413
f65c229c
JR		 414static void svm_vcpu_init_msrpm(u32 *msrpm)
415{
416 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
417
418#ifdef CONFIG_X86_64
419 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
423 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
425#endif
426 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
427 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 428}
429
24e09cbf
JR		 430static void svm_enable_lbrv(struct vcpu_svm *svm)
431{
432 u32 *msrpm = svm->msrpm;
433
434 svm->vmcb->control.lbr_ctl = 1;
435 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
439}
440
441static void svm_disable_lbrv(struct vcpu_svm *svm)
442{
443 u32 *msrpm = svm->msrpm;
444
445 svm->vmcb->control.lbr_ctl = 0;
446 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
450}
451
6aa8b732
AK		 452static __init int svm_hardware_setup(void)
453{
454 int cpu;
455 struct page *iopm_pages;
f65c229c 456 void *iopm_va;
6aa8b732
AK		 457 int r;
458
6aa8b732
AK		 459 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
460
461 if (!iopm_pages)
462 return -ENOMEM;
c8681339
AL		 463
464 iopm_va = page_address(iopm_pages);
465 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 466 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
467
50a37eb4
JR		 468 if (boot_cpu_has(X86_FEATURE_NX))
469 kvm_enable_efer_bits(EFER_NX);
470
1b2fd70c
AG		 471 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
472 kvm_enable_efer_bits(EFER_FFXSR);
473
236de055
AG		 474 if (nested) {
475 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
476 kvm_enable_efer_bits(EFER_SVME);
477 }
478
6aa8b732
AK		 479 for_each_online_cpu(cpu) {
480 r = svm_cpu_init(cpu);
481 if (r)
f65c229c 482 goto err;
6aa8b732 483 }
33bd6a0b
JR		 484
485 svm_features = cpuid_edx(SVM_CPUID_FUNC);
486
e3da3acd
JR		 487 if (!svm_has(SVM_FEATURE_NPT))
488 npt_enabled = false;
489
6c7dac72
JR		 490 if (npt_enabled && !npt) {
491 printk(KERN_INFO "kvm: Nested Paging disabled\n");
492 npt_enabled = false;
493 }
494
18552672 495 if (npt_enabled) {
e3da3acd 496 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 497 kvm_enable_tdp();
5f4cb662
JR		 498 } else
499 kvm_disable_tdp();
e3da3acd 500
6aa8b732
AK		 501 return 0;
502
f65c229c 503err:
6aa8b732
AK		 504 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
505 iopm_base = 0;
506 return r;
507}
508
509static __exit void svm_hardware_unsetup(void)
510{
0da1db75
JR		 511 int cpu;
512
513 for_each_online_cpu(cpu)
514 svm_cpu_uninit(cpu);
515
6aa8b732 516 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 517 iopm_base = 0;
6aa8b732
AK		 518}
519
520static void init_seg(struct vmcb_seg *seg)
521{
522 seg->selector = 0;
523 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
524 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
525 seg->limit = 0xffff;
526 seg->base = 0;
527}
528
529static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
530{
531 seg->selector = 0;
532 seg->attrib = SVM_SELECTOR_P_MASK | type;
533 seg->limit = 0xffff;
534 seg->base = 0;
535}
536
e6101a96 537static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 538{
e6101a96
JR		 539 struct vmcb_control_area *control = &svm->vmcb->control;
540 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 541
542 control->intercept_cr_read = INTERCEPT_CR0_MASK |
543 INTERCEPT_CR3_MASK |
649d6864 544 INTERCEPT_CR4_MASK;
6aa8b732
AK		 545
546 control->intercept_cr_write = INTERCEPT_CR0_MASK |
547 INTERCEPT_CR3_MASK |
80a8119c
AK		 548 INTERCEPT_CR4_MASK |
549 INTERCEPT_CR8_MASK;
6aa8b732
AK		 550
551 control->intercept_dr_read = INTERCEPT_DR0_MASK |
552 INTERCEPT_DR1_MASK |
553 INTERCEPT_DR2_MASK |
554 INTERCEPT_DR3_MASK;
555
556 control->intercept_dr_write = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
559 INTERCEPT_DR3_MASK |
560 INTERCEPT_DR5_MASK |
561 INTERCEPT_DR7_MASK;
562
7aa81cc0 563 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 564 (1 << UD_VECTOR) |
565 (1 << MC_VECTOR);
6aa8b732
AK		 566
567
568 control->intercept = (1ULL << INTERCEPT_INTR) |
569 (1ULL << INTERCEPT_NMI) |
0152527b 570 (1ULL << INTERCEPT_SMI) |
6aa8b732 571 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 572 (1ULL << INTERCEPT_INVD) |
6aa8b732 573 (1ULL << INTERCEPT_HLT) |
a7052897 574 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 575 (1ULL << INTERCEPT_INVLPGA) |
576 (1ULL << INTERCEPT_IOIO_PROT) |
577 (1ULL << INTERCEPT_MSR_PROT) |
578 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 579 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 580 (1ULL << INTERCEPT_VMRUN) |
581 (1ULL << INTERCEPT_VMMCALL) |
582 (1ULL << INTERCEPT_VMLOAD) |
583 (1ULL << INTERCEPT_VMSAVE) |
584 (1ULL << INTERCEPT_STGI) |
585 (1ULL << INTERCEPT_CLGI) |
916ce236 586 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 587 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 588 (1ULL << INTERCEPT_MONITOR) |
589 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 590
591 control->iopm_base_pa = iopm_base;
f65c229c 592 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 593 control->tsc_offset = 0;
6aa8b732
AK		 594 control->int_ctl = V_INTR_MASKING_MASK;
595
596 init_seg(&save->es);
597 init_seg(&save->ss);
598 init_seg(&save->ds);
599 init_seg(&save->fs);
600 init_seg(&save->gs);
601
602 save->cs.selector = 0xf000;
603 /* Executable/Readable Code Segment */
604 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
605 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
606 save->cs.limit = 0xffff;
d92899a0
AK		 607 /*
608 * cs.base should really be 0xffff0000, but vmx can't handle that, so
609 * be consistent with it.
610 *
611 * Replace when we have real mode working for vmx.
612 */
613 save->cs.base = 0xf0000;
6aa8b732
AK		 614
615 save->gdtr.limit = 0xffff;
616 save->idtr.limit = 0xffff;
617
618 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
619 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
620
9962d032 621 save->efer = EFER_SVME;
d77c26fc 622 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 623 save->dr7 = 0x400;
624 save->rflags = 2;
625 save->rip = 0x0000fff0;
5fdbf976 626 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 627
628 /*
629 * cr0 val on cpu init should be 0x60000010, we enable cpu
630 * cache by default. the orderly way is to enable cache in bios.
631 */
707d92fa 632 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 633 save->cr4 = X86_CR4_PAE;
6aa8b732 634 /* rdx = ?? */
709ddebf
JR		 635
636 if (npt_enabled) {
637 /* Setup VMCB for Nested Paging */
638 control->nested_ctl = 1;
a7052897
MT		 639 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
640 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 641 control->intercept_exceptions &= ~(1 << PF_VECTOR);
642 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
643 INTERCEPT_CR3_MASK);
644 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 save->g_pat = 0x0007040600070406ULL;
647 /* enable caching because the QEMU Bios doesn't enable it */
648 save->cr0 = X86_CR0_ET;
649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
a79d2f18 652 force_new_asid(&svm->vcpu);
1371d904 653
e6aa9abd 654 svm->nested.vmcb = 0;
2af9194d
JR		 655 svm->vcpu.arch.hflags = 0;
656
657 enable_gif(svm);
6aa8b732
AK		 658}
659
e00c8cf2 660static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 661{
662 struct vcpu_svm *svm = to_svm(vcpu);
663
e6101a96 664 init_vmcb(svm);
70433389 665
c5af89b6 666 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 667 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 668 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
669 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 670 }
5fdbf976
MT		 671 vcpu->arch.regs_avail = ~0;
672 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 673
674 return 0;
04d2cc77
AK		 675}
676
fb3f0f51 677static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 678{
a2fa3e9f 679 struct vcpu_svm *svm;
6aa8b732 680 struct page *page;
f65c229c 681 struct page *msrpm_pages;
b286d5d8 682 struct page *hsave_page;
3d6368ef 683 struct page *nested_msrpm_pages;
fb3f0f51 684 int err;
6aa8b732 685
c16f862d 686 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 687 if (!svm) {
688 err = -ENOMEM;
689 goto out;
690 }
691
692 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
693 if (err)
694 goto free_svm;
695
6aa8b732 696 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 697 if (!page) {
698 err = -ENOMEM;
699 goto uninit;
700 }
6aa8b732 701
f65c229c
JR		 702 err = -ENOMEM;
703 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
704 if (!msrpm_pages)
705 goto uninit;
3d6368ef
AG		 706
707 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
708 if (!nested_msrpm_pages)
709 goto uninit;
710
f65c229c
JR		 711 svm->msrpm = page_address(msrpm_pages);
712 svm_vcpu_init_msrpm(svm->msrpm);
713
b286d5d8
AG		 714 hsave_page = alloc_page(GFP_KERNEL);
715 if (!hsave_page)
716 goto uninit;
e6aa9abd 717 svm->nested.hsave = page_address(hsave_page);
b286d5d8 718
e6aa9abd 719 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 720
a2fa3e9f
GH		 721 svm->vmcb = page_address(page);
722 clear_page(svm->vmcb);
723 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
724 svm->asid_generation = 0;
e6101a96 725 init_vmcb(svm);
a2fa3e9f 726
fb3f0f51
RR		 727 fx_init(&svm->vcpu);
728 svm->vcpu.fpu_active = 1;
ad312c7c 729 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 730 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 731 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 732
fb3f0f51 733 return &svm->vcpu;
36241b8c 734
fb3f0f51
RR		 735uninit:
736 kvm_vcpu_uninit(&svm->vcpu);
737free_svm:
a4770347 738 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 739out:
740 return ERR_PTR(err);
6aa8b732
AK		 741}
742
743static void svm_free_vcpu(struct kvm_vcpu *vcpu)
744{
a2fa3e9f
GH		 745 struct vcpu_svm *svm = to_svm(vcpu);
746
fb3f0f51 747 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 748 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 749 __free_page(virt_to_page(svm->nested.hsave));
750 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 751 kvm_vcpu_uninit(vcpu);
a4770347 752 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 753}
754
15ad7146 755static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 756{
a2fa3e9f 757 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 758 int i;
0cc5064d 759
0cc5064d
AK		 760 if (unlikely(cpu != vcpu->cpu)) {
761 u64 tsc_this, delta;
762
763 /*
764 * Make sure that the guest sees a monotonically
765 * increasing TSC.
766 */
767 rdtscll(tsc_this);
ad312c7c 768 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 769 svm->vmcb->control.tsc_offset += delta;
0cc5064d 770 vcpu->cpu = cpu;
2f599714 771 kvm_migrate_timers(vcpu);
4b656b12 772 svm->asid_generation = 0;
0cc5064d 773 }
94dfbdb3
AL		 774
775 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 776 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 777}
778
779static void svm_vcpu_put(struct kvm_vcpu *vcpu)
780{
a2fa3e9f 781 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 782 int i;
783
e1beb1d3 784 ++vcpu->stat.host_state_reload;
94dfbdb3 785 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 786 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 787
ad312c7c 788 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 789}
790
6aa8b732
AK		 791static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
792{
a2fa3e9f 793 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 794}
795
796static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
797{
a2fa3e9f 798 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 799}
800
6de4f3ad
AK		 801static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
802{
803 switch (reg) {
804 case VCPU_EXREG_PDPTR:
805 BUG_ON(!npt_enabled);
806 load_pdptrs(vcpu, vcpu->arch.cr3);
807 break;
808 default:
809 BUG();
810 }
811}
812
f0b85051
AG		 813static void svm_set_vintr(struct vcpu_svm *svm)
814{
815 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
816}
817
818static void svm_clear_vintr(struct vcpu_svm *svm)
819{
820 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
821}
822
6aa8b732
AK		 823static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
824{
a2fa3e9f 825 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 826
827 switch (seg) {
828 case VCPU_SREG_CS: return &save->cs;
829 case VCPU_SREG_DS: return &save->ds;
830 case VCPU_SREG_ES: return &save->es;
831 case VCPU_SREG_FS: return &save->fs;
832 case VCPU_SREG_GS: return &save->gs;
833 case VCPU_SREG_SS: return &save->ss;
834 case VCPU_SREG_TR: return &save->tr;
835 case VCPU_SREG_LDTR: return &save->ldtr;
836 }
837 BUG();
8b6d44c7 838 return NULL;
6aa8b732
AK		 839}
840
841static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
842{
843 struct vmcb_seg *s = svm_seg(vcpu, seg);
844
845 return s->base;
846}
847
848static void svm_get_segment(struct kvm_vcpu *vcpu,
849 struct kvm_segment *var, int seg)
850{
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 var->base = s->base;
854 var->limit = s->limit;
855 var->selector = s->selector;
856 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
857 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
858 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
859 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
860 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
861 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
862 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
863 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 864
19bca6ab
AP		 865 /* AMD's VMCB does not have an explicit unusable field, so emulate it
866 * for cross vendor migration purposes by "not present"
867 */
868 var->unusable = !var->present || (var->type == 0);
869
1fbdc7a5
AP		 870 switch (seg) {
871 case VCPU_SREG_CS:
872 /*
873 * SVM always stores 0 for the 'G' bit in the CS selector in
874 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
875 * Intel's VMENTRY has a check on the 'G' bit.
876 */
25022acc 877 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 878 break;
879 case VCPU_SREG_TR:
880 /*
881 * Work around a bug where the busy flag in the tr selector
882 * isn't exposed
883 */
c0d09828 884 var->type |= 0x2;
1fbdc7a5
AP		 885 break;
886 case VCPU_SREG_DS:
887 case VCPU_SREG_ES:
888 case VCPU_SREG_FS:
889 case VCPU_SREG_GS:
890 /*
891 * The accessed bit must always be set in the segment
892 * descriptor cache, although it can be cleared in the
893 * descriptor, the cached bit always remains at 1. Since
894 * Intel has a check on this, set it here to support
895 * cross-vendor migration.
896 */
897 if (!var->unusable)
898 var->type |= 0x1;
899 break;
b586eb02
AP		 900 case VCPU_SREG_SS:
901 /* On AMD CPUs sometimes the DB bit in the segment
902 * descriptor is left as 1, although the whole segment has
903 * been made unusable. Clear it here to pass an Intel VMX
904 * entry check when cross vendor migrating.
905 */
906 if (var->unusable)
907 var->db = 0;
908 break;
1fbdc7a5 909 }
6aa8b732
AK		 910}
911
2e4d2653
IE		 912static int svm_get_cpl(struct kvm_vcpu *vcpu)
913{
914 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
915
916 return save->cpl;
917}
918
6aa8b732
AK		 919static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
920{
a2fa3e9f
GH		 921 struct vcpu_svm *svm = to_svm(vcpu);
922
923 dt->limit = svm->vmcb->save.idtr.limit;
924 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 925}
926
927static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 svm->vmcb->save.idtr.limit = dt->limit;
932 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 933}
934
935static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936{
a2fa3e9f
GH		 937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 dt->limit = svm->vmcb->save.gdtr.limit;
940 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 941}
942
943static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944{
a2fa3e9f
GH		 945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 svm->vmcb->save.gdtr.limit = dt->limit;
948 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 949}
950
25c4c276 951static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 952{
953}
954
6aa8b732
AK		 955static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
956{
a2fa3e9f
GH		 957 struct vcpu_svm *svm = to_svm(vcpu);
958
05b3e0c2 959#ifdef CONFIG_X86_64
ad312c7c 960 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 961 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 962 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 963 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 964 }
965
d77c26fc 966 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 967 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 968 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 969 }
970 }
971#endif
709ddebf
JR		 972 if (npt_enabled)
973 goto set;
974
ad312c7c 975 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 976 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 977 vcpu->fpu_active = 1;
978 }
979
ad312c7c 980 vcpu->arch.cr0 = cr0;
707d92fa 981 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 982 if (!vcpu->fpu_active) {
983 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 984 cr0 |= X86_CR0_TS;
6b390b63 985 }
709ddebf
JR		 986set:
987 /*
988 * re-enable caching here because the QEMU bios
989 * does not do it - this results in some delay at
990 * reboot
991 */
992 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 993 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 994}
995
996static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
997{
6394b649 998 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 999 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1000
1001 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1002 force_new_asid(vcpu);
6394b649 1003
ec077263
JR		 1004 vcpu->arch.cr4 = cr4;
1005 if (!npt_enabled)
1006 cr4 |= X86_CR4_PAE;
6394b649 1007 cr4 |= host_cr4_mce;
ec077263 1008 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1009}
1010
1011static void svm_set_segment(struct kvm_vcpu *vcpu,
1012 struct kvm_segment *var, int seg)
1013{
a2fa3e9f 1014 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1015 struct vmcb_seg *s = svm_seg(vcpu, seg);
1016
1017 s->base = var->base;
1018 s->limit = var->limit;
1019 s->selector = var->selector;
1020 if (var->unusable)
1021 s->attrib = 0;
1022 else {
1023 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1024 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1025 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1026 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1027 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1028 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1029 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1030 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1031 }
1032 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1033 svm->vmcb->save.cpl
1034 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1035 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1036
1037}
1038
44c11430 1039static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1040{
d0bfb940
JK		 1041 struct vcpu_svm *svm = to_svm(vcpu);
1042
d0bfb940
JK		 1043 svm->vmcb->control.intercept_exceptions &=
1044 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1045
1046 if (vcpu->arch.singlestep)
1047 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1048
d0bfb940
JK		 1049 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1050 if (vcpu->guest_debug &
1051 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1052 svm->vmcb->control.intercept_exceptions |=
1053 1 << DB_VECTOR;
1054 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1055 svm->vmcb->control.intercept_exceptions |=
1056 1 << BP_VECTOR;
1057 } else
1058 vcpu->guest_debug = 0;
44c11430
GN		 1059}
1060
1061static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1062{
1063 int old_debug = vcpu->guest_debug;
1064 struct vcpu_svm *svm = to_svm(vcpu);
1065
1066 vcpu->guest_debug = dbg->control;
1067
1068 update_db_intercept(vcpu);
d0bfb940 1069
ae675ef0
JK		 1070 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1071 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1072 else
1073 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1074
d0bfb940
JK		 1075 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1076 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1077 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1078 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1079
1080 return 0;
6aa8b732
AK		 1081}
1082
1083static void load_host_msrs(struct kvm_vcpu *vcpu)
1084{
94dfbdb3 1085#ifdef CONFIG_X86_64
a2fa3e9f 1086 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1087#endif
6aa8b732
AK		 1088}
1089
1090static void save_host_msrs(struct kvm_vcpu *vcpu)
1091{
94dfbdb3 1092#ifdef CONFIG_X86_64
a2fa3e9f 1093 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1094#endif
6aa8b732
AK		 1095}
1096
e756fc62 1097static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1098{
1099 if (svm_data->next_asid > svm_data->max_asid) {
1100 ++svm_data->asid_generation;
1101 svm_data->next_asid = 1;
a2fa3e9f 1102 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1103 }
1104
a2fa3e9f
GH		 1105 svm->asid_generation = svm_data->asid_generation;
1106 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1107}
1108
6aa8b732
AK		 1109static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1110{
42dbaa5a
JK		 1111 struct vcpu_svm *svm = to_svm(vcpu);
1112 unsigned long val;
1113
1114 switch (dr) {
1115 case 0 ... 3:
1116 val = vcpu->arch.db[dr];
1117 break;
1118 case 6:
1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 val = vcpu->arch.dr6;
1121 else
1122 val = svm->vmcb->save.dr6;
1123 break;
1124 case 7:
1125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1126 val = vcpu->arch.dr7;
1127 else
1128 val = svm->vmcb->save.dr7;
1129 break;
1130 default:
1131 val = 0;
1132 }
1133
af9ca2d7 1134 return val;
6aa8b732
AK		 1135}
1136
1137static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1138 int *exception)
1139{
a2fa3e9f
GH		 1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
42dbaa5a 1142 *exception = 0;
6aa8b732
AK		 1143
1144 switch (dr) {
1145 case 0 ... 3:
42dbaa5a
JK		 1146 vcpu->arch.db[dr] = value;
1147 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1148 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1149 return;
1150 case 4 ... 5:
42dbaa5a 1151 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1152 *exception = UD_VECTOR;
42dbaa5a
JK		 1153 return;
1154 case 6:
1155 if (value & 0xffffffff00000000ULL) {
1156 *exception = GP_VECTOR;
6aa8b732
AK		 1157 return;
1158 }
42dbaa5a
JK		 1159 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1160 return;
1161 case 7:
1162 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1163 *exception = GP_VECTOR;
1164 return;
1165 }
42dbaa5a
JK		 1166 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1167 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1168 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1169 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1170 }
6aa8b732 1171 return;
6aa8b732 1172 default:
42dbaa5a 1173 /* FIXME: Possible case? */
6aa8b732 1174 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1175 __func__, dr);
6aa8b732
AK		 1176 *exception = UD_VECTOR;
1177 return;
1178 }
1179}
1180
e756fc62 1181static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1182{
6aa8b732
AK		 1183 u64 fault_address;
1184 u32 error_code;
6aa8b732 1185
a2fa3e9f
GH		 1186 fault_address = svm->vmcb->control.exit_info_2;
1187 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1188
229456fc 1189 trace_kvm_page_fault(fault_address, error_code);
44874f84
JR		 1190 /*
1191 * FIXME: Tis shouldn't be necessary here, but there is a flush
1192 * missing in the MMU code. Until we find this bug, flush the
1193 * complete TLB here on an NPF
1194 */
1195 if (npt_enabled)
1196 svm_flush_tlb(&svm->vcpu);
9222be18 1197 else {
3298b75c 1198 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1199 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1200 }
3067714c 1201 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1202}
1203
d0bfb940
JK		 1204static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1205{
1206 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1207 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1208 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1209 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1210 return 1;
1211 }
44c11430
GN		 1212
1213 if (svm->vcpu.arch.singlestep) {
1214 svm->vcpu.arch.singlestep = false;
1215 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1216 svm->vmcb->save.rflags &=
1217 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1218 update_db_intercept(&svm->vcpu);
1219 }
1220
1221 if (svm->vcpu.guest_debug &
1222 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1223 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1224 kvm_run->debug.arch.pc =
1225 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1226 kvm_run->debug.arch.exception = DB_VECTOR;
1227 return 0;
1228 }
1229
1230 return 1;
d0bfb940
JK		 1231}
1232
1233static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1234{
1235 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1236 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1237 kvm_run->debug.arch.exception = BP_VECTOR;
1238 return 0;
1239}
1240
7aa81cc0
AL		 1241static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1242{
1243 int er;
1244
571008da 1245 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1246 if (er != EMULATE_DONE)
7ee5d940 1247 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1248 return 1;
1249}
1250
e756fc62 1251static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1252{
a2fa3e9f 1253 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1254 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1255 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1256 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1257
1258 return 1;
7807fa6c
AL		 1259}
1260
53371b50
JR		 1261static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1262{
1263 /*
1264 * On an #MC intercept the MCE handler is not called automatically in
1265 * the host. So do it by hand here.
1266 */
1267 asm volatile (
1268 "int $0x12\n");
1269 /* not sure if we ever come back to this point */
1270
1271 return 1;
1272}
1273
e756fc62 1274static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1275{
1276 /*
1277 * VMCB is undefined after a SHUTDOWN intercept
1278 * so reinitialize it.
1279 */
a2fa3e9f 1280 clear_page(svm->vmcb);
e6101a96 1281 init_vmcb(svm);
46fe4ddd
JR		 1282
1283 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1284 return 0;
1285}
1286
e756fc62 1287static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1288{
d77c26fc 1289 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1290 int size, in, string;
039576c0 1291 unsigned port;
6aa8b732 1292
e756fc62 1293 ++svm->vcpu.stat.io_exits;
6aa8b732 1294
a2fa3e9f 1295 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1296
e70669ab
LV		 1297 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1298
1299 if (string) {
3427318f
LV		 1300 if (emulate_instruction(&svm->vcpu,
1301 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1302 return 0;
1303 return 1;
1304 }
1305
039576c0
AK		 1306 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1307 port = io_info >> 16;
1308 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1309
e93f36bc 1310 skip_emulated_instruction(&svm->vcpu);
3090dd73 1311 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1312}
1313
c47f098d
JR		 1314static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1315{
1316 return 1;
1317}
1318
a0698055
JR		 1319static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1320{
1321 ++svm->vcpu.stat.irq_exits;
1322 return 1;
1323}
1324
e756fc62 1325static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1326{
1327 return 1;
1328}
1329
e756fc62 1330static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1331{
5fdbf976 1332 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1333 skip_emulated_instruction(&svm->vcpu);
1334 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1335}
1336
e756fc62 1337static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1338{
5fdbf976 1339 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1340 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1341 kvm_emulate_hypercall(&svm->vcpu);
1342 return 1;
02e235bc
AK		 1343}
1344
c0725420
AG		 1345static int nested_svm_check_permissions(struct vcpu_svm *svm)
1346{
1347 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1348 || !is_paging(&svm->vcpu)) {
1349 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1350 return 1;
1351 }
1352
1353 if (svm->vmcb->save.cpl) {
1354 kvm_inject_gp(&svm->vcpu, 0);
1355 return 1;
1356 }
1357
1358 return 0;
1359}
1360
cf74a78b
AG		 1361static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1362 bool has_error_code, u32 error_code)
1363{
0295ad7d
JR		 1364 if (!is_nested(svm))
1365 return 0;
cf74a78b 1366
0295ad7d
JR		 1367 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1368 svm->vmcb->control.exit_code_hi = 0;
1369 svm->vmcb->control.exit_info_1 = error_code;
1370 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1371
410e4d57 1372 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1373}
1374
1375static inline int nested_svm_intr(struct vcpu_svm *svm)
1376{
26666957
JR		 1377 if (!is_nested(svm))
1378 return 0;
cf74a78b 1379
26666957
JR		 1380 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1381 return 0;
cf74a78b 1382
26666957
JR		 1383 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1384 return 0;
cf74a78b 1385
26666957
JR		 1386 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1387
1388 if (nested_svm_exit_handled(svm)) {
1389 nsvm_printk("VMexit -> INTR\n");
1390 return 1;
cf74a78b
AG		 1391 }
1392
1393 return 0;
1394}
1395
34f80cfa
JR		 1396static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1397{
1398 struct page *page;
1399
1400 down_read(&current->mm->mmap_sem);
1401 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1402 up_read(&current->mm->mmap_sem);
1403
1404 if (is_error_page(page))
1405 goto error;
1406
1407 return kmap_atomic(page, idx);
1408
1409error:
1410 kvm_release_page_clean(page);
1411 kvm_inject_gp(&svm->vcpu, 0);
1412
1413 return NULL;
1414}
1415
1416static void nested_svm_unmap(void *addr, enum km_type idx)
1417{
1418 struct page *page;
1419
1420 if (!addr)
1421 return;
1422
1423 page = kmap_atomic_to_page(addr);
1424
1425 kunmap_atomic(addr, idx);
1426 kvm_release_page_dirty(page);
1427}
1428
3d62d9aa 1429static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1430{
4c2161ae 1431 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1432 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1433 bool ret = false;
1434 u32 t0, t1;
1435 u8 *msrpm;
4c2161ae 1436
3d62d9aa
JR		 1437 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1438 return false;
1439
1440 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1441
1442 if (!msrpm)
1443 goto out;
4c2161ae
JR		 1444
1445 switch (msr) {
1446 case 0 ... 0x1fff:
1447 t0 = (msr * 2) % 8;
1448 t1 = msr / 8;
1449 break;
1450 case 0xc0000000 ... 0xc0001fff:
1451 t0 = (8192 + msr - 0xc0000000) * 2;
1452 t1 = (t0 / 8);
1453 t0 %= 8;
1454 break;
1455 case 0xc0010000 ... 0xc0011fff:
1456 t0 = (16384 + msr - 0xc0010000) * 2;
1457 t1 = (t0 / 8);
1458 t0 %= 8;
1459 break;
1460 default:
3d62d9aa
JR		 1461 ret = true;
1462 goto out;
4c2161ae 1463 }
4c2161ae 1464
3d62d9aa
JR		 1465 ret = msrpm[t1] & ((1 << param) << t0);
1466
1467out:
1468 nested_svm_unmap(msrpm, KM_USER0);
1469
1470 return ret;
4c2161ae
JR		 1471}
1472
410e4d57 1473static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1474{
cf74a78b 1475 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1476
410e4d57
JR		 1477 switch (exit_code) {
1478 case SVM_EXIT_INTR:
1479 case SVM_EXIT_NMI:
1480 return NESTED_EXIT_HOST;
cf74a78b 1481 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1482 case SVM_EXIT_NPF:
1483 if (npt_enabled)
1484 return NESTED_EXIT_HOST;
1485 break;
1486 /* When we're shadowing, trap PFs */
1487 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1488 if (!npt_enabled)
1489 return NESTED_EXIT_HOST;
1490 break;
1491 default:
1492 break;
cf74a78b
AG		 1493 }
1494
410e4d57
JR		 1495 return NESTED_EXIT_CONTINUE;
1496}
1497
1498/*
1499 * If this function returns true, this #vmexit was already handled
1500 */
1501static int nested_svm_exit_handled(struct vcpu_svm *svm)
1502{
1503 u32 exit_code = svm->vmcb->control.exit_code;
1504 int vmexit = NESTED_EXIT_HOST;
1505
cf74a78b 1506 switch (exit_code) {
9c4e40b9 1507 case SVM_EXIT_MSR:
3d62d9aa 1508 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1509 break;
cf74a78b
AG		 1510 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1511 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1512 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1513 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1514 break;
1515 }
1516 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1517 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1518 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1519 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1520 break;
1521 }
1522 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1523 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1524 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1525 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1526 break;
1527 }
1528 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1529 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1530 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1531 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1532 break;
1533 }
1534 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1535 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1536 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1537 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1538 break;
1539 }
1540 default: {
1541 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1542 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1543 if (svm->nested.intercept & exit_bits)
410e4d57 1544 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1545 }
1546 }
1547
410e4d57 1548 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1549 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1550 nested_svm_vmexit(svm);
1551 }
1552
1553 return vmexit;
cf74a78b
AG		 1554}
1555
0460a979
JR		 1556static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1557{
1558 struct vmcb_control_area *dst = &dst_vmcb->control;
1559 struct vmcb_control_area *from = &from_vmcb->control;
1560
1561 dst->intercept_cr_read = from->intercept_cr_read;
1562 dst->intercept_cr_write = from->intercept_cr_write;
1563 dst->intercept_dr_read = from->intercept_dr_read;
1564 dst->intercept_dr_write = from->intercept_dr_write;
1565 dst->intercept_exceptions = from->intercept_exceptions;
1566 dst->intercept = from->intercept;
1567 dst->iopm_base_pa = from->iopm_base_pa;
1568 dst->msrpm_base_pa = from->msrpm_base_pa;
1569 dst->tsc_offset = from->tsc_offset;
1570 dst->asid = from->asid;
1571 dst->tlb_ctl = from->tlb_ctl;
1572 dst->int_ctl = from->int_ctl;
1573 dst->int_vector = from->int_vector;
1574 dst->int_state = from->int_state;
1575 dst->exit_code = from->exit_code;
1576 dst->exit_code_hi = from->exit_code_hi;
1577 dst->exit_info_1 = from->exit_info_1;
1578 dst->exit_info_2 = from->exit_info_2;
1579 dst->exit_int_info = from->exit_int_info;
1580 dst->exit_int_info_err = from->exit_int_info_err;
1581 dst->nested_ctl = from->nested_ctl;
1582 dst->event_inj = from->event_inj;
1583 dst->event_inj_err = from->event_inj_err;
1584 dst->nested_cr3 = from->nested_cr3;
1585 dst->lbr_ctl = from->lbr_ctl;
1586}
1587
34f80cfa 1588static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1589{
34f80cfa 1590 struct vmcb *nested_vmcb;
e6aa9abd 1591 struct vmcb *hsave = svm->nested.hsave;
33740e40 1592 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1593
34f80cfa
JR		 1594 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1595 if (!nested_vmcb)
1596 return 1;
1597
cf74a78b 1598 /* Give the current vmcb to the guest */
33740e40
JR		 1599 disable_gif(svm);
1600
1601 nested_vmcb->save.es = vmcb->save.es;
1602 nested_vmcb->save.cs = vmcb->save.cs;
1603 nested_vmcb->save.ss = vmcb->save.ss;
1604 nested_vmcb->save.ds = vmcb->save.ds;
1605 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1606 nested_vmcb->save.idtr = vmcb->save.idtr;
1607 if (npt_enabled)
1608 nested_vmcb->save.cr3 = vmcb->save.cr3;
1609 nested_vmcb->save.cr2 = vmcb->save.cr2;
1610 nested_vmcb->save.rflags = vmcb->save.rflags;
1611 nested_vmcb->save.rip = vmcb->save.rip;
1612 nested_vmcb->save.rsp = vmcb->save.rsp;
1613 nested_vmcb->save.rax = vmcb->save.rax;
1614 nested_vmcb->save.dr7 = vmcb->save.dr7;
1615 nested_vmcb->save.dr6 = vmcb->save.dr6;
1616 nested_vmcb->save.cpl = vmcb->save.cpl;
1617
1618 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1619 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1620 nested_vmcb->control.int_state = vmcb->control.int_state;
1621 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1622 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1623 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1624 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1625 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1626 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1627 nested_vmcb->control.tlb_ctl = 0;
1628 nested_vmcb->control.event_inj = 0;
1629 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1630
1631 /* We always set V_INTR_MASKING and remember the old value in hflags */
1632 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1633 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1634
cf74a78b 1635 /* Restore the original control entries */
0460a979 1636 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1637
1638 /* Kill any pending exceptions */
1639 if (svm->vcpu.arch.exception.pending == true)
1640 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1641
219b65dc
AG		 1642 kvm_clear_exception_queue(&svm->vcpu);
1643 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1644
1645 /* Restore selected save entries */
1646 svm->vmcb->save.es = hsave->save.es;
1647 svm->vmcb->save.cs = hsave->save.cs;
1648 svm->vmcb->save.ss = hsave->save.ss;
1649 svm->vmcb->save.ds = hsave->save.ds;
1650 svm->vmcb->save.gdtr = hsave->save.gdtr;
1651 svm->vmcb->save.idtr = hsave->save.idtr;
1652 svm->vmcb->save.rflags = hsave->save.rflags;
1653 svm_set_efer(&svm->vcpu, hsave->save.efer);
1654 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1655 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1656 if (npt_enabled) {
1657 svm->vmcb->save.cr3 = hsave->save.cr3;
1658 svm->vcpu.arch.cr3 = hsave->save.cr3;
1659 } else {
1660 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1661 }
1662 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1663 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1664 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1665 svm->vmcb->save.dr7 = 0;
1666 svm->vmcb->save.cpl = 0;
1667 svm->vmcb->control.exit_int_info = 0;
1668
cf74a78b 1669 /* Exit nested SVM mode */
e6aa9abd 1670 svm->nested.vmcb = 0;
cf74a78b 1671
34f80cfa 1672 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1673
1674 kvm_mmu_reset_context(&svm->vcpu);
1675 kvm_mmu_load(&svm->vcpu);
1676
1677 return 0;
1678}
3d6368ef 1679
9738b2c9 1680static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1681{
9738b2c9 1682 u32 *nested_msrpm;
3d6368ef 1683 int i;
9738b2c9
JR		 1684
1685 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1686 if (!nested_msrpm)
1687 return false;
1688
3d6368ef 1689 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1690 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1691
e6aa9abd 1692 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1693
9738b2c9
JR		 1694 nested_svm_unmap(nested_msrpm, KM_USER0);
1695
1696 return true;
3d6368ef
AG		 1697}
1698
9738b2c9 1699static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1700{
9738b2c9 1701 struct vmcb *nested_vmcb;
e6aa9abd 1702 struct vmcb *hsave = svm->nested.hsave;
defbba56 1703 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1704
9738b2c9
JR		 1705 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1706 if (!nested_vmcb)
1707 return false;
1708
3d6368ef 1709 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1710 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1711
1712 /* Clear internal status */
219b65dc
AG		 1713 kvm_clear_exception_queue(&svm->vcpu);
1714 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1715
1716 /* Save the old vmcb, so we don't need to pick what we save, but
1717 can restore everything when a VMEXIT occurs */
defbba56
JR		 1718 hsave->save.es = vmcb->save.es;
1719 hsave->save.cs = vmcb->save.cs;
1720 hsave->save.ss = vmcb->save.ss;
1721 hsave->save.ds = vmcb->save.ds;
1722 hsave->save.gdtr = vmcb->save.gdtr;
1723 hsave->save.idtr = vmcb->save.idtr;
1724 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1725 hsave->save.cr0 = svm->vcpu.arch.cr0;
1726 hsave->save.cr4 = svm->vcpu.arch.cr4;
1727 hsave->save.rflags = vmcb->save.rflags;
1728 hsave->save.rip = svm->next_rip;
1729 hsave->save.rsp = vmcb->save.rsp;
1730 hsave->save.rax = vmcb->save.rax;
1731 if (npt_enabled)
1732 hsave->save.cr3 = vmcb->save.cr3;
1733 else
1734 hsave->save.cr3 = svm->vcpu.arch.cr3;
1735
0460a979 1736 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1737
1738 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1739 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1740 else
1741 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1742
1743 /* Load the nested guest state */
1744 svm->vmcb->save.es = nested_vmcb->save.es;
1745 svm->vmcb->save.cs = nested_vmcb->save.cs;
1746 svm->vmcb->save.ss = nested_vmcb->save.ss;
1747 svm->vmcb->save.ds = nested_vmcb->save.ds;
1748 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1749 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1750 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1751 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1752 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1753 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1754 if (npt_enabled) {
1755 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1756 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1757 } else {
1758 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1759 kvm_mmu_reset_context(&svm->vcpu);
1760 }
defbba56 1761 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1762 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1763 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1764 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1765 /* In case we don't even reach vcpu_run, the fields are not updated */
1766 svm->vmcb->save.rax = nested_vmcb->save.rax;
1767 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1768 svm->vmcb->save.rip = nested_vmcb->save.rip;
1769 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1770 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1771 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1772
1773 /* We don't want a nested guest to be more powerful than the guest,
1774 so all intercepts are ORed */
1775 svm->vmcb->control.intercept_cr_read |=
1776 nested_vmcb->control.intercept_cr_read;
1777 svm->vmcb->control.intercept_cr_write |=
1778 nested_vmcb->control.intercept_cr_write;
1779 svm->vmcb->control.intercept_dr_read |=
1780 nested_vmcb->control.intercept_dr_read;
1781 svm->vmcb->control.intercept_dr_write |=
1782 nested_vmcb->control.intercept_dr_write;
1783 svm->vmcb->control.intercept_exceptions |=
1784 nested_vmcb->control.intercept_exceptions;
1785
1786 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1787
e6aa9abd 1788 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1789
aad42c64
JR		 1790 /* cache intercepts */
1791 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1792 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1793 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1794 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1795 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1796 svm->nested.intercept = nested_vmcb->control.intercept;
1797
3d6368ef
AG		 1798 force_new_asid(&svm->vcpu);
1799 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1800 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1801 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1802 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1803 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1804 nested_vmcb->control.int_ctl);
1805 }
1806 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1807 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1808 else
1809 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1810
1811 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1812 nested_vmcb->control.exit_int_info,
1813 nested_vmcb->control.int_state);
1814
1815 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1816 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1817 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1818 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1819 nsvm_printk("Injecting Event: 0x%x\n",
1820 nested_vmcb->control.event_inj);
1821 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1822 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1823
9738b2c9
JR		 1824 nested_svm_unmap(nested_vmcb, KM_USER0);
1825
2af9194d 1826 enable_gif(svm);
3d6368ef 1827
9738b2c9 1828 return true;
3d6368ef
AG		 1829}
1830
9966bf68 1831static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1832{
1833 to_vmcb->save.fs = from_vmcb->save.fs;
1834 to_vmcb->save.gs = from_vmcb->save.gs;
1835 to_vmcb->save.tr = from_vmcb->save.tr;
1836 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1837 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1838 to_vmcb->save.star = from_vmcb->save.star;
1839 to_vmcb->save.lstar = from_vmcb->save.lstar;
1840 to_vmcb->save.cstar = from_vmcb->save.cstar;
1841 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1842 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1843 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1844 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1845}
1846
1847static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1848{
9966bf68
JR		 1849 struct vmcb *nested_vmcb;
1850
5542675b
AG		 1851 if (nested_svm_check_permissions(svm))
1852 return 1;
1853
1854 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1855 skip_emulated_instruction(&svm->vcpu);
1856
9966bf68
JR		 1857 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1858 if (!nested_vmcb)
1859 return 1;
1860
1861 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1862 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1863
1864 return 1;
1865}
1866
1867static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1868{
9966bf68
JR		 1869 struct vmcb *nested_vmcb;
1870
5542675b
AG		 1871 if (nested_svm_check_permissions(svm))
1872 return 1;
1873
1874 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1875 skip_emulated_instruction(&svm->vcpu);
1876
9966bf68
JR		 1877 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1878 if (!nested_vmcb)
1879 return 1;
1880
1881 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1882 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1883
1884 return 1;
1885}
1886
3d6368ef
AG		 1887static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1888{
1889 nsvm_printk("VMrun\n");
1f8da478 1890
3d6368ef
AG		 1891 if (nested_svm_check_permissions(svm))
1892 return 1;
1893
1894 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1895 skip_emulated_instruction(&svm->vcpu);
1896
9738b2c9 1897 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1898 return 1;
1899
9738b2c9 1900 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1901 goto failed;
1902
1903 return 1;
1904
1905failed:
1906
1907 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1908 svm->vmcb->control.exit_code_hi = 0;
1909 svm->vmcb->control.exit_info_1 = 0;
1910 svm->vmcb->control.exit_info_2 = 0;
1911
1912 nested_svm_vmexit(svm);
3d6368ef
AG		 1913
1914 return 1;
1915}
1916
1371d904
AG		 1917static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1918{
1919 if (nested_svm_check_permissions(svm))
1920 return 1;
1921
1922 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1923 skip_emulated_instruction(&svm->vcpu);
1924
2af9194d 1925 enable_gif(svm);
1371d904
AG		 1926
1927 return 1;
1928}
1929
1930static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1931{
1932 if (nested_svm_check_permissions(svm))
1933 return 1;
1934
1935 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1936 skip_emulated_instruction(&svm->vcpu);
1937
2af9194d 1938 disable_gif(svm);
1371d904
AG		 1939
1940 /* After a CLGI no interrupts should come */
1941 svm_clear_vintr(svm);
1942 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1943
1944 return 1;
1945}
1946
ff092385
AG		 1947static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1948{
1949 struct kvm_vcpu *vcpu = &svm->vcpu;
1950 nsvm_printk("INVLPGA\n");
1951
1952 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1953 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1954
1955 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1956 skip_emulated_instruction(&svm->vcpu);
1957 return 1;
1958}
1959
e756fc62
RR		 1960static int invalid_op_interception(struct vcpu_svm *svm,
1961 struct kvm_run *kvm_run)
6aa8b732 1962{
7ee5d940 1963 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1964 return 1;
1965}
1966
e756fc62
RR		 1967static int task_switch_interception(struct vcpu_svm *svm,
1968 struct kvm_run *kvm_run)
6aa8b732 1969{
37817f29 1970 u16 tss_selector;
64a7ec06
GN		 1971 int reason;
1972 int int_type = svm->vmcb->control.exit_int_info &
1973 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1974 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1975 uint32_t type =
1976 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1977 uint32_t idt_v =
1978 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1979
1980 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1981
37817f29
IE		 1982 if (svm->vmcb->control.exit_info_2 &
1983 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1984 reason = TASK_SWITCH_IRET;
1985 else if (svm->vmcb->control.exit_info_2 &
1986 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1987 reason = TASK_SWITCH_JMP;
fe8e7f83 1988 else if (idt_v)
64a7ec06
GN		 1989 reason = TASK_SWITCH_GATE;
1990 else
1991 reason = TASK_SWITCH_CALL;
1992
fe8e7f83
GN		 1993 if (reason == TASK_SWITCH_GATE) {
1994 switch (type) {
1995 case SVM_EXITINTINFO_TYPE_NMI:
1996 svm->vcpu.arch.nmi_injected = false;
1997 break;
1998 case SVM_EXITINTINFO_TYPE_EXEPT:
1999 kvm_clear_exception_queue(&svm->vcpu);
2000 break;
2001 case SVM_EXITINTINFO_TYPE_INTR:
2002 kvm_clear_interrupt_queue(&svm->vcpu);
2003 break;
2004 default:
2005 break;
2006 }
2007 }
64a7ec06 2008
8317c298
GN		 2009 if (reason != TASK_SWITCH_GATE ||
2010 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2011 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2012 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2013 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2014
2015 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2016}
2017
e756fc62 2018static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2019{
5fdbf976 2020 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2021 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2022 return 1;
6aa8b732
AK		 2023}
2024
95ba8273
GN		 2025static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2026{
2027 ++svm->vcpu.stat.nmi_window_exits;
2028 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2029 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2030 return 1;
2031}
2032
a7052897
MT		 2033static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2034{
2035 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2036 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2037 return 1;
2038}
2039
e756fc62
RR		 2040static int emulate_on_interception(struct vcpu_svm *svm,
2041 struct kvm_run *kvm_run)
6aa8b732 2042{
3427318f 2043 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2044 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2045 return 1;
2046}
2047
1d075434
JR		 2048static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2049{
0a5fff19
GN		 2050 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2051 /* instruction emulation calls kvm_set_cr8() */
1d075434 2052 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2053 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2054 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2055 return 1;
95ba8273 2056 }
0a5fff19
GN		 2057 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2058 return 1;
1d075434
JR		 2059 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2060 return 0;
2061}
2062
6aa8b732
AK		 2063static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2064{
a2fa3e9f
GH		 2065 struct vcpu_svm *svm = to_svm(vcpu);
2066
6aa8b732 2067 switch (ecx) {
af24a4e4 2068 case MSR_IA32_TSC: {
6aa8b732
AK		 2069 u64 tsc;
2070
2071 rdtscll(tsc);
a2fa3e9f 2072 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2073 break;
2074 }
0e859cac 2075 case MSR_K6_STAR:
a2fa3e9f 2076 *data = svm->vmcb->save.star;
6aa8b732 2077 break;
0e859cac 2078#ifdef CONFIG_X86_64
6aa8b732 2079 case MSR_LSTAR:
a2fa3e9f 2080 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2081 break;
2082 case MSR_CSTAR:
a2fa3e9f 2083 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2084 break;
2085 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2086 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2087 break;
2088 case MSR_SYSCALL_MASK:
a2fa3e9f 2089 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2090 break;
2091#endif
2092 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2093 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2094 break;
2095 case MSR_IA32_SYSENTER_EIP:
017cb99e 2096 *data = svm->sysenter_eip;
6aa8b732
AK		 2097 break;
2098 case MSR_IA32_SYSENTER_ESP:
017cb99e 2099 *data = svm->sysenter_esp;
6aa8b732 2100 break;
a2938c80
JR		 2101 /* Nobody will change the following 5 values in the VMCB so
2102 we can safely return them on rdmsr. They will always be 0
2103 until LBRV is implemented. */
2104 case MSR_IA32_DEBUGCTLMSR:
2105 *data = svm->vmcb->save.dbgctl;
2106 break;
2107 case MSR_IA32_LASTBRANCHFROMIP:
2108 *data = svm->vmcb->save.br_from;
2109 break;
2110 case MSR_IA32_LASTBRANCHTOIP:
2111 *data = svm->vmcb->save.br_to;
2112 break;
2113 case MSR_IA32_LASTINTFROMIP:
2114 *data = svm->vmcb->save.last_excp_from;
2115 break;
2116 case MSR_IA32_LASTINTTOIP:
2117 *data = svm->vmcb->save.last_excp_to;
2118 break;
b286d5d8 2119 case MSR_VM_HSAVE_PA:
e6aa9abd 2120 *data = svm->nested.hsave_msr;
b286d5d8 2121 break;
eb6f302e
JR		 2122 case MSR_VM_CR:
2123 *data = 0;
2124 break;
c8a73f18
AG		 2125 case MSR_IA32_UCODE_REV:
2126 *data = 0x01000065;
2127 break;
6aa8b732 2128 default:
3bab1f5d 2129 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2130 }
2131 return 0;
2132}
2133
e756fc62 2134static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2135{
ad312c7c 2136 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2137 u64 data;
2138
e756fc62 2139 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2140 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2141 else {
229456fc 2142 trace_kvm_msr_read(ecx, data);
af9ca2d7 2143
5fdbf976 2144 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2145 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2146 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2147 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2148 }
2149 return 1;
2150}
2151
2152static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2153{
a2fa3e9f
GH		 2154 struct vcpu_svm *svm = to_svm(vcpu);
2155
6aa8b732 2156 switch (ecx) {
af24a4e4 2157 case MSR_IA32_TSC: {
6aa8b732
AK		 2158 u64 tsc;
2159
2160 rdtscll(tsc);
a2fa3e9f 2161 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2162 break;
2163 }
0e859cac 2164 case MSR_K6_STAR:
a2fa3e9f 2165 svm->vmcb->save.star = data;
6aa8b732 2166 break;
49b14f24 2167#ifdef CONFIG_X86_64
6aa8b732 2168 case MSR_LSTAR:
a2fa3e9f 2169 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2170 break;
2171 case MSR_CSTAR:
a2fa3e9f 2172 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2173 break;
2174 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2175 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2176 break;
2177 case MSR_SYSCALL_MASK:
a2fa3e9f 2178 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2179 break;
2180#endif
2181 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2182 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2183 break;
2184 case MSR_IA32_SYSENTER_EIP:
017cb99e 2185 svm->sysenter_eip = data;
a2fa3e9f 2186 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2187 break;
2188 case MSR_IA32_SYSENTER_ESP:
017cb99e 2189 svm->sysenter_esp = data;
a2fa3e9f 2190 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2191 break;
a2938c80 2192 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2193 if (!svm_has(SVM_FEATURE_LBRV)) {
2194 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2195 __func__, data);
24e09cbf
JR		 2196 break;
2197 }
2198 if (data & DEBUGCTL_RESERVED_BITS)
2199 return 1;
2200
2201 svm->vmcb->save.dbgctl = data;
2202 if (data & (1ULL<<0))
2203 svm_enable_lbrv(svm);
2204 else
2205 svm_disable_lbrv(svm);
a2938c80 2206 break;
b286d5d8 2207 case MSR_VM_HSAVE_PA:
e6aa9abd 2208 svm->nested.hsave_msr = data;
62b9abaa 2209 break;
3c5d0a44
AG		 2210 case MSR_VM_CR:
2211 case MSR_VM_IGNNE:
3c5d0a44
AG		 2212 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2213 break;
6aa8b732 2214 default:
3bab1f5d 2215 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2216 }
2217 return 0;
2218}
2219
e756fc62 2220static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2221{
ad312c7c 2222 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2223 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2224 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2225
229456fc 2226 trace_kvm_msr_write(ecx, data);
af9ca2d7 2227
5fdbf976 2228 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2229 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2230 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2231 else
e756fc62 2232 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2233 return 1;
2234}
2235
e756fc62 2236static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2237{
e756fc62
RR		 2238 if (svm->vmcb->control.exit_info_1)
2239 return wrmsr_interception(svm, kvm_run);
6aa8b732 2240 else
e756fc62 2241 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2242}
2243
e756fc62 2244static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2245 struct kvm_run *kvm_run)
2246{
f0b85051 2247 svm_clear_vintr(svm);
85f455f7 2248 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2249 /*
2250 * If the user space waits to inject interrupts, exit as soon as
2251 * possible
2252 */
8061823a
GN		 2253 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2254 kvm_run->request_interrupt_window &&
2255 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2256 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2257 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2258 return 0;
2259 }
2260
2261 return 1;
2262}
2263
e756fc62 2264static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2265 struct kvm_run *kvm_run) = {
2266 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2267 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2268 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2269 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2270 /* for now: */
2271 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2272 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2273 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2274 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2275 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2276 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2277 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2278 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2279 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2280 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2281 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2282 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2283 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2284 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2285 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2286 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2287 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2288 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2289 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2290 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2291 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2292 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2293 [SVM_EXIT_SMI] = nop_on_interception,
2294 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2295 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2296 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2297 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2298 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2299 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2300 [SVM_EXIT_HLT] = halt_interception,
a7052897 2301 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2302 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2303 [SVM_EXIT_IOIO] = io_interception,
2304 [SVM_EXIT_MSR] = msr_interception,
2305 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2306 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2307 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2308 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2309 [SVM_EXIT_VMLOAD] = vmload_interception,
2310 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2311 [SVM_EXIT_STGI] = stgi_interception,
2312 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2313 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2314 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2315 [SVM_EXIT_MONITOR] = invalid_op_interception,
2316 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2317 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2318};
2319
04d2cc77 2320static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2321{
04d2cc77 2322 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2323 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2324
229456fc 2325 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2326
cf74a78b 2327 if (is_nested(svm)) {
410e4d57
JR		 2328 int vmexit;
2329
cf74a78b
AG		 2330 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2331 exit_code, svm->vmcb->control.exit_info_1,
2332 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
410e4d57
JR		 2333
2334 vmexit = nested_svm_exit_special(svm);
2335
2336 if (vmexit == NESTED_EXIT_CONTINUE)
2337 vmexit = nested_svm_exit_handled(svm);
2338
2339 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2340 return 1;
cf74a78b
AG		 2341 }
2342
a5c3832d
JR		 2343 svm_complete_interrupts(svm);
2344
709ddebf
JR		 2345 if (npt_enabled) {
2346 int mmu_reload = 0;
2347 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2348 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2349 mmu_reload = 1;
2350 }
2351 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2352 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2353 if (mmu_reload) {
2354 kvm_mmu_reset_context(vcpu);
2355 kvm_mmu_load(vcpu);
2356 }
2357 }
2358
04d2cc77
AK		 2359
2360 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2361 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2362 kvm_run->fail_entry.hardware_entry_failure_reason
2363 = svm->vmcb->control.exit_code;
2364 return 0;
2365 }
2366
a2fa3e9f 2367 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2368 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2369 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2370 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2371 "exit_code 0x%x\n",
b8688d51 2372 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2373 exit_code);
2374
9d8f549d 2375 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2376 || !svm_exit_handlers[exit_code]) {
6aa8b732 2377 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2378 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2379 return 0;
2380 }
2381
e756fc62 2382 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2383}
2384
2385static void reload_tss(struct kvm_vcpu *vcpu)
2386{
2387 int cpu = raw_smp_processor_id();
2388
2389 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2390 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2391 load_TR_desc();
2392}
2393
e756fc62 2394static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2395{
2396 int cpu = raw_smp_processor_id();
2397
2398 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2399
a2fa3e9f 2400 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2401 /* FIXME: handle wraparound of asid_generation */
2402 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2403 new_asid(svm, svm_data);
6aa8b732
AK		 2404}
2405
95ba8273
GN		 2406static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2407{
2408 struct vcpu_svm *svm = to_svm(vcpu);
2409
2410 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2411 vcpu->arch.hflags |= HF_NMI_MASK;
2412 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2413 ++vcpu->stat.nmi_injections;
2414}
6aa8b732 2415
85f455f7 2416static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2417{
2418 struct vmcb_control_area *control;
2419
229456fc 2420 trace_kvm_inj_virq(irq);
af9ca2d7 2421
fa89a817 2422 ++svm->vcpu.stat.irq_injections;
e756fc62 2423 control = &svm->vmcb->control;
85f455f7 2424 control->int_vector = irq;
6aa8b732
AK		 2425 control->int_ctl &= ~V_INTR_PRIO_MASK;
2426 control->int_ctl |= V_IRQ_MASK |
2427 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2428}
2429
66fd3f7f 2430static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2431{
2432 struct vcpu_svm *svm = to_svm(vcpu);
2433
2af9194d 2434 BUG_ON(!(gif_set(svm)));
cf74a78b 2435
219b65dc
AG		 2436 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2437 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2438}
2439
95ba8273 2440static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2441{
2442 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2443
95ba8273 2444 if (irr == -1)
aaacfc9a
JR		 2445 return;
2446
95ba8273
GN		 2447 if (tpr >= irr)
2448 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2449}
aaacfc9a 2450
95ba8273
GN		 2451static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2452{
2453 struct vcpu_svm *svm = to_svm(vcpu);
2454 struct vmcb *vmcb = svm->vmcb;
2455 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2456 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2457}
2458
78646121
GN		 2459static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2460{
2461 struct vcpu_svm *svm = to_svm(vcpu);
2462 struct vmcb *vmcb = svm->vmcb;
2463 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2464 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2465 gif_set(svm) &&
108768de 2466 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
78646121
GN		 2467}
2468
9222be18 2469static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2470{
219b65dc
AG		 2471 struct vcpu_svm *svm = to_svm(vcpu);
2472 nsvm_printk("Trying to open IRQ window\n");
2473
2474 nested_svm_intr(svm);
2475
2476 /* In case GIF=0 we can't rely on the CPU to tell us when
2477 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2478 * The next time we get that intercept, this function will be
2479 * called again though and we'll get the vintr intercept. */
2af9194d 2480 if (gif_set(svm)) {
219b65dc
AG		 2481 svm_set_vintr(svm);
2482 svm_inject_irq(svm, 0x0);
2483 }
85f455f7
ED		 2484}
2485
95ba8273 2486static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2487{
04d2cc77 2488 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2489
44c11430
GN		 2490 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2491 == HF_NMI_MASK)
2492 return; /* IRET will cause a vm exit */
2493
2494 /* Something prevents NMI from been injected. Single step over
2495 possible problem (IRET or exception injection or interrupt
2496 shadow) */
2497 vcpu->arch.singlestep = true;
2498 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2499 update_db_intercept(vcpu);
c1150d8c
DL		 2500}
2501
cbc94022
IE		 2502static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2503{
2504 return 0;
2505}
2506
d9e368d6
AK		 2507static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2508{
2509 force_new_asid(vcpu);
2510}
2511
04d2cc77
AK		 2512static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2513{
2514}
2515
d7bf8221
JR		 2516static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2517{
2518 struct vcpu_svm *svm = to_svm(vcpu);
2519
2520 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2521 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2522 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2523 }
2524}
2525
649d6864
JR		 2526static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2527{
2528 struct vcpu_svm *svm = to_svm(vcpu);
2529 u64 cr8;
2530
649d6864
JR		 2531 cr8 = kvm_get_cr8(vcpu);
2532 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2533 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2534}
2535
9222be18
GN		 2536static void svm_complete_interrupts(struct vcpu_svm *svm)
2537{
2538 u8 vector;
2539 int type;
2540 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2541
44c11430
GN		 2542 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2543 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2544
9222be18
GN		 2545 svm->vcpu.arch.nmi_injected = false;
2546 kvm_clear_exception_queue(&svm->vcpu);
2547 kvm_clear_interrupt_queue(&svm->vcpu);
2548
2549 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2550 return;
2551
2552 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2553 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2554
2555 switch (type) {
2556 case SVM_EXITINTINFO_TYPE_NMI:
2557 svm->vcpu.arch.nmi_injected = true;
2558 break;
2559 case SVM_EXITINTINFO_TYPE_EXEPT:
2560 /* In case of software exception do not reinject an exception
2561 vector, but re-execute and instruction instead */
219b65dc
AG		 2562 if (is_nested(svm))
2563 break;
66fd3f7f 2564 if (kvm_exception_is_soft(vector))
9222be18
GN		 2565 break;
2566 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2567 u32 err = svm->vmcb->control.exit_int_info_err;
2568 kvm_queue_exception_e(&svm->vcpu, vector, err);
2569
2570 } else
2571 kvm_queue_exception(&svm->vcpu, vector);
2572 break;
2573 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2574 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2575 break;
2576 default:
2577 break;
2578 }
2579}
2580
80e31d4f
AK		 2581#ifdef CONFIG_X86_64
2582#define R "r"
2583#else
2584#define R "e"
2585#endif
2586
04d2cc77 2587static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2588{
a2fa3e9f 2589 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2590 u16 fs_selector;
2591 u16 gs_selector;
2592 u16 ldt_selector;
d9e368d6 2593
5fdbf976
MT		 2594 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2595 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2596 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2597
e756fc62 2598 pre_svm_run(svm);
6aa8b732 2599
649d6864
JR		 2600 sync_lapic_to_cr8(vcpu);
2601
6aa8b732 2602 save_host_msrs(vcpu);
d6e88aec
AK		 2603 fs_selector = kvm_read_fs();
2604 gs_selector = kvm_read_gs();
2605 ldt_selector = kvm_read_ldt();
cda0ffdd 2606 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2607 /* required for live migration with NPT */
2608 if (npt_enabled)
2609 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2610
04d2cc77
AK		 2611 clgi();
2612
2613 local_irq_enable();
36241b8c 2614
6aa8b732 2615 asm volatile (
80e31d4f
AK		 2616 "push %%"R"bp; \n\t"
2617 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2618 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2619 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2620 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2621 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2622 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2623#ifdef CONFIG_X86_64
fb3f0f51
RR		 2624 "mov %c[r8](%[svm]), %%r8 \n\t"
2625 "mov %c[r9](%[svm]), %%r9 \n\t"
2626 "mov %c[r10](%[svm]), %%r10 \n\t"
2627 "mov %c[r11](%[svm]), %%r11 \n\t"
2628 "mov %c[r12](%[svm]), %%r12 \n\t"
2629 "mov %c[r13](%[svm]), %%r13 \n\t"
2630 "mov %c[r14](%[svm]), %%r14 \n\t"
2631 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2632#endif
2633
6aa8b732 2634 /* Enter guest mode */
80e31d4f
AK		 2635 "push %%"R"ax \n\t"
2636 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2637 __ex(SVM_VMLOAD) "\n\t"
2638 __ex(SVM_VMRUN) "\n\t"
2639 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2640 "pop %%"R"ax \n\t"
6aa8b732
AK		 2641
2642 /* Save guest registers, load host registers */
80e31d4f
AK		 2643 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2644 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2645 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2646 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2647 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2648 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2649#ifdef CONFIG_X86_64
fb3f0f51
RR		 2650 "mov %%r8, %c[r8](%[svm]) \n\t"
2651 "mov %%r9, %c[r9](%[svm]) \n\t"
2652 "mov %%r10, %c[r10](%[svm]) \n\t"
2653 "mov %%r11, %c[r11](%[svm]) \n\t"
2654 "mov %%r12, %c[r12](%[svm]) \n\t"
2655 "mov %%r13, %c[r13](%[svm]) \n\t"
2656 "mov %%r14, %c[r14](%[svm]) \n\t"
2657 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2658#endif
80e31d4f 2659 "pop %%"R"bp"
6aa8b732 2660 :
fb3f0f51 2661 : [svm]"a"(svm),
6aa8b732 2662 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2663 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2664 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2665 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2666 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2667 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2668 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2669#ifdef CONFIG_X86_64
ad312c7c
ZX		 2670 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2671 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2672 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2673 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2674 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2675 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2676 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2677 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2678#endif
54a08c04 2679 : "cc", "memory"
80e31d4f 2680 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2681#ifdef CONFIG_X86_64
54a08c04
LV		 2682 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2683#endif
2684 );
6aa8b732 2685
ad312c7c 2686 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2687 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2688 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2689 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2690
d6e88aec
AK		 2691 kvm_load_fs(fs_selector);
2692 kvm_load_gs(gs_selector);
2693 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2694 load_host_msrs(vcpu);
2695
2696 reload_tss(vcpu);
2697
56ba47dd
AK		 2698 local_irq_disable();
2699
2700 stgi();
2701
d7bf8221
JR		 2702 sync_cr8_to_lapic(vcpu);
2703
a2fa3e9f 2704 svm->next_rip = 0;
9222be18 2705
6de4f3ad
AK		 2706 if (npt_enabled) {
2707 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2708 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2709 }
6aa8b732
AK		 2710}
2711
80e31d4f
AK		 2712#undef R
2713
6aa8b732
AK		 2714static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2715{
a2fa3e9f
GH		 2716 struct vcpu_svm *svm = to_svm(vcpu);
2717
709ddebf
JR		 2718 if (npt_enabled) {
2719 svm->vmcb->control.nested_cr3 = root;
2720 force_new_asid(vcpu);
2721 return;
2722 }
2723
a2fa3e9f 2724 svm->vmcb->save.cr3 = root;
6aa8b732 2725 force_new_asid(vcpu);
7807fa6c
AL		 2726
2727 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2728 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2729 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2730 vcpu->fpu_active = 0;
2731 }
6aa8b732
AK		 2732}
2733
6aa8b732
AK		 2734static int is_disabled(void)
2735{
6031a61c
JR		 2736 u64 vm_cr;
2737
2738 rdmsrl(MSR_VM_CR, vm_cr);
2739 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2740 return 1;
2741
6aa8b732
AK		 2742 return 0;
2743}
2744
102d8325
IM		 2745static void
2746svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2747{
2748 /*
2749 * Patch in the VMMCALL instruction:
2750 */
2751 hypercall[0] = 0x0f;
2752 hypercall[1] = 0x01;
2753 hypercall[2] = 0xd9;
102d8325
IM		 2754}
2755
002c7f7c
YS		 2756static void svm_check_processor_compat(void *rtn)
2757{
2758 *(int *)rtn = 0;
2759}
2760
774ead3a
AK		 2761static bool svm_cpu_has_accelerated_tpr(void)
2762{
2763 return false;
2764}
2765
67253af5
SY		 2766static int get_npt_level(void)
2767{
2768#ifdef CONFIG_X86_64
2769 return PT64_ROOT_LEVEL;
2770#else
2771 return PT32E_ROOT_LEVEL;
2772#endif
2773}
2774
4b12f0de 2775static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2776{
2777 return 0;
2778}
2779
229456fc
MT		 2780static const struct trace_print_flags svm_exit_reasons_str[] = {
2781 { SVM_EXIT_READ_CR0, "read_cr0" },
2782 { SVM_EXIT_READ_CR3, "read_cr3" },
2783 { SVM_EXIT_READ_CR4, "read_cr4" },
2784 { SVM_EXIT_READ_CR8, "read_cr8" },
2785 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2786 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2787 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2788 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2789 { SVM_EXIT_READ_DR0, "read_dr0" },
2790 { SVM_EXIT_READ_DR1, "read_dr1" },
2791 { SVM_EXIT_READ_DR2, "read_dr2" },
2792 { SVM_EXIT_READ_DR3, "read_dr3" },
2793 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2794 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2795 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2796 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2797 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2798 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2799 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2800 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2801 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2802 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2803 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2804 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2805 { SVM_EXIT_INTR, "interrupt" },
2806 { SVM_EXIT_NMI, "nmi" },
2807 { SVM_EXIT_SMI, "smi" },
2808 { SVM_EXIT_INIT, "init" },
2809 { SVM_EXIT_VINTR, "vintr" },
2810 { SVM_EXIT_CPUID, "cpuid" },
2811 { SVM_EXIT_INVD, "invd" },
2812 { SVM_EXIT_HLT, "hlt" },
2813 { SVM_EXIT_INVLPG, "invlpg" },
2814 { SVM_EXIT_INVLPGA, "invlpga" },
2815 { SVM_EXIT_IOIO, "io" },
2816 { SVM_EXIT_MSR, "msr" },
2817 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2818 { SVM_EXIT_SHUTDOWN, "shutdown" },
2819 { SVM_EXIT_VMRUN, "vmrun" },
2820 { SVM_EXIT_VMMCALL, "hypercall" },
2821 { SVM_EXIT_VMLOAD, "vmload" },
2822 { SVM_EXIT_VMSAVE, "vmsave" },
2823 { SVM_EXIT_STGI, "stgi" },
2824 { SVM_EXIT_CLGI, "clgi" },
2825 { SVM_EXIT_SKINIT, "skinit" },
2826 { SVM_EXIT_WBINVD, "wbinvd" },
2827 { SVM_EXIT_MONITOR, "monitor" },
2828 { SVM_EXIT_MWAIT, "mwait" },
2829 { SVM_EXIT_NPF, "npf" },
2830 { -1, NULL }
2831};
2832
344f414f
JR		 2833static bool svm_gb_page_enable(void)
2834{
2835 return true;
2836}
2837
cbdd1bea 2838static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2839 .cpu_has_kvm_support = has_svm,
2840 .disabled_by_bios = is_disabled,
2841 .hardware_setup = svm_hardware_setup,
2842 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2843 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2844 .hardware_enable = svm_hardware_enable,
2845 .hardware_disable = svm_hardware_disable,
774ead3a 2846 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2847
2848 .vcpu_create = svm_create_vcpu,
2849 .vcpu_free = svm_free_vcpu,
04d2cc77 2850 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2851
04d2cc77 2852 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2853 .vcpu_load = svm_vcpu_load,
2854 .vcpu_put = svm_vcpu_put,
2855
2856 .set_guest_debug = svm_guest_debug,
2857 .get_msr = svm_get_msr,
2858 .set_msr = svm_set_msr,
2859 .get_segment_base = svm_get_segment_base,
2860 .get_segment = svm_get_segment,
2861 .set_segment = svm_set_segment,
2e4d2653 2862 .get_cpl = svm_get_cpl,
1747fb71 2863 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2864 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2865 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2866 .set_cr3 = svm_set_cr3,
2867 .set_cr4 = svm_set_cr4,
2868 .set_efer = svm_set_efer,
2869 .get_idt = svm_get_idt,
2870 .set_idt = svm_set_idt,
2871 .get_gdt = svm_get_gdt,
2872 .set_gdt = svm_set_gdt,
2873 .get_dr = svm_get_dr,
2874 .set_dr = svm_set_dr,
6de4f3ad 2875 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2876 .get_rflags = svm_get_rflags,
2877 .set_rflags = svm_set_rflags,
2878
6aa8b732 2879 .tlb_flush = svm_flush_tlb,
6aa8b732 2880
6aa8b732 2881 .run = svm_vcpu_run,
04d2cc77 2882 .handle_exit = handle_exit,
6aa8b732 2883 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2884 .set_interrupt_shadow = svm_set_interrupt_shadow,
2885 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2886 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2887 .set_irq = svm_set_irq,
95ba8273 2888 .set_nmi = svm_inject_nmi,
298101da 2889 .queue_exception = svm_queue_exception,
78646121 2890 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2891 .nmi_allowed = svm_nmi_allowed,
2892 .enable_nmi_window = enable_nmi_window,
2893 .enable_irq_window = enable_irq_window,
2894 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2895
2896 .set_tss_addr = svm_set_tss_addr,
67253af5 2897 .get_tdp_level = get_npt_level,
4b12f0de 2898 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2899
2900 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2901 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2902};
2903
2904static int __init svm_init(void)
2905{
cb498ea2 2906 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2907 THIS_MODULE);
6aa8b732
AK		 2908}
2909
2910static void __exit svm_exit(void)
2911{
cb498ea2 2912 kvm_exit();
6aa8b732
AK		 2913}
2914
2915module_init(svm_init)
2916module_exit(svm_exit)
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