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KVM: remove duplicated #include
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
410e4d57
JR		 50#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
24e09cbf
JR		 54#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
c0725420
AG		 56/* Turn on to get debugging output*/
57/* #define NESTED_DEBUG */
58
59#ifdef NESTED_DEBUG
60#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61#else
62#define nsvm_printk(fmt, args...) do {} while(0)
63#endif
64
6c8166a7
AK		 65static const u32 host_save_user_msrs[] = {
66#ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69#endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71};
72
73#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75struct kvm_vcpu;
76
e6aa9abd
JR		 77struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
aad42c64
JR		 87
88 /* cache for intercepts of the guest */
89 u16 intercept_cr_read;
90 u16 intercept_cr_write;
91 u16 intercept_dr_read;
92 u16 intercept_dr_write;
93 u32 intercept_exceptions;
94 u64 intercept;
95
e6aa9abd
JR		 96};
97
6c8166a7
AK		 98struct vcpu_svm {
99 struct kvm_vcpu vcpu;
100 struct vmcb *vmcb;
101 unsigned long vmcb_pa;
102 struct svm_cpu_data *svm_data;
103 uint64_t asid_generation;
104 uint64_t sysenter_esp;
105 uint64_t sysenter_eip;
106
107 u64 next_rip;
108
109 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 u64 host_gs_base;
6c8166a7
AK		 111
112 u32 *msrpm;
6c8166a7 113
e6aa9abd 114 struct nested_state nested;
6c8166a7
AK		 115};
116
709ddebf
JR		 117/* enable NPT for AMD64 and X86 with PAE */
118#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119static bool npt_enabled = true;
120#else
e3da3acd 121static bool npt_enabled = false;
709ddebf 122#endif
6c7dac72
JR		 123static int npt = 1;
124
125module_param(npt, int, S_IRUGO);
e3da3acd 126
4b6e4dca 127static int nested = 1;
236de055
AG		 128module_param(nested, int, S_IRUGO);
129
44874f84 130static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 131static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 132
410e4d57 133static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 134static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 135static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
136 bool has_error_code, u32 error_code);
137
a2fa3e9f
GH		 138static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
139{
fb3f0f51 140 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 141}
142
3d6368ef
AG		 143static inline bool is_nested(struct vcpu_svm *svm)
144{
e6aa9abd 145 return svm->nested.vmcb;
3d6368ef
AG		 146}
147
2af9194d
JR		 148static inline void enable_gif(struct vcpu_svm *svm)
149{
150 svm->vcpu.arch.hflags |= HF_GIF_MASK;
151}
152
153static inline void disable_gif(struct vcpu_svm *svm)
154{
155 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
156}
157
158static inline bool gif_set(struct vcpu_svm *svm)
159{
160 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
161}
162
4866d5e3 163static unsigned long iopm_base;
6aa8b732
AK		 164
165struct kvm_ldttss_desc {
166 u16 limit0;
167 u16 base0;
168 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
169 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
170 u32 base3;
171 u32 zero1;
172} __attribute__((packed));
173
174struct svm_cpu_data {
175 int cpu;
176
5008fdf5
AK		 177 u64 asid_generation;
178 u32 max_asid;
179 u32 next_asid;
6aa8b732
AK		 180 struct kvm_ldttss_desc *tss_desc;
181
182 struct page *save_area;
183};
184
185static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 186static uint32_t svm_features;
6aa8b732
AK		 187
188struct svm_init_data {
189 int cpu;
190 int r;
191};
192
193static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
194
9d8f549d 195#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 196#define MSRS_RANGE_SIZE 2048
197#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198
199#define MAX_INST_SIZE 15
200
80b7706e
JR		 201static inline u32 svm_has(u32 feat)
202{
203 return svm_features & feat;
204}
205
6aa8b732
AK		 206static inline void clgi(void)
207{
4ecac3fd 208 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 209}
210
211static inline void stgi(void)
212{
4ecac3fd 213 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 214}
215
216static inline void invlpga(unsigned long addr, u32 asid)
217{
4ecac3fd 218 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 219}
220
6aa8b732
AK		 221static inline void force_new_asid(struct kvm_vcpu *vcpu)
222{
a2fa3e9f 223 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 224}
225
226static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
227{
228 force_new_asid(vcpu);
229}
230
231static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
232{
709ddebf 233 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 234 efer &= ~EFER_LME;
6aa8b732 235
9962d032 236 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 237 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 238}
239
298101da
AK		 240static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
241 bool has_error_code, u32 error_code)
242{
243 struct vcpu_svm *svm = to_svm(vcpu);
244
cf74a78b
AG		 245 /* If we are within a nested VM we'd better #VMEXIT and let the
246 guest handle the exception */
247 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
248 return;
249
298101da
AK		 250 svm->vmcb->control.event_inj = nr
251 | SVM_EVTINJ_VALID
252 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
253 | SVM_EVTINJ_TYPE_EXEPT;
254 svm->vmcb->control.event_inj_err = error_code;
255}
256
6aa8b732
AK		 257static int is_external_interrupt(u32 info)
258{
259 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
260 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
261}
262
2809f5d2
GC		 263static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
264{
265 struct vcpu_svm *svm = to_svm(vcpu);
266 u32 ret = 0;
267
268 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
269 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
270 return ret & mask;
271}
272
273static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274{
275 struct vcpu_svm *svm = to_svm(vcpu);
276
277 if (mask == 0)
278 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
279 else
280 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
281
282}
283
6aa8b732
AK		 284static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
285{
a2fa3e9f
GH		 286 struct vcpu_svm *svm = to_svm(vcpu);
287
288 if (!svm->next_rip) {
851ba692 289 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 290 EMULATE_DONE)
291 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 292 return;
293 }
5fdbf976
MT		 294 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
295 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
296 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 297
5fdbf976 298 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 299 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 300}
301
302static int has_svm(void)
303{
63d1142f 304 const char *msg;
6aa8b732 305
63d1142f 306 if (!cpu_has_svm(&msg)) {
ff81ff10 307 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 308 return 0;
309 }
310
6aa8b732
AK		 311 return 1;
312}
313
314static void svm_hardware_disable(void *garbage)
315{
2c8dceeb 316 cpu_svm_disable();
6aa8b732
AK		 317}
318
10474ae8 319static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 320{
321
322 struct svm_cpu_data *svm_data;
323 uint64_t efer;
b792c344 324 struct descriptor_table gdt_descr;
6aa8b732
AK		 325 struct desc_struct *gdt;
326 int me = raw_smp_processor_id();
327
10474ae8
AG		 328 rdmsrl(MSR_EFER, efer);
329 if (efer & EFER_SVME)
330 return -EBUSY;
331
6aa8b732
AK		 332 if (!has_svm()) {
333 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
10474ae8 334 return -EINVAL;
6aa8b732
AK		 335 }
336 svm_data = per_cpu(svm_data, me);
337
338 if (!svm_data) {
339 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
340 me);
10474ae8 341 return -EINVAL;
6aa8b732
AK		 342 }
343
344 svm_data->asid_generation = 1;
345 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
346 svm_data->next_asid = svm_data->max_asid + 1;
347
b792c344
AM		 348 kvm_get_gdt(&gdt_descr);
349 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 350 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
351
9962d032 352 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 353
354 wrmsrl(MSR_VM_HSAVE_PA,
355 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
10474ae8
AG		 356
357 return 0;
6aa8b732
AK		 358}
359
0da1db75
JR		 360static void svm_cpu_uninit(int cpu)
361{
362 struct svm_cpu_data *svm_data
363 = per_cpu(svm_data, raw_smp_processor_id());
364
365 if (!svm_data)
366 return;
367
368 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
369 __free_page(svm_data->save_area);
370 kfree(svm_data);
371}
372
6aa8b732
AK		 373static int svm_cpu_init(int cpu)
374{
375 struct svm_cpu_data *svm_data;
376 int r;
377
378 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
379 if (!svm_data)
380 return -ENOMEM;
381 svm_data->cpu = cpu;
382 svm_data->save_area = alloc_page(GFP_KERNEL);
383 r = -ENOMEM;
384 if (!svm_data->save_area)
385 goto err_1;
386
387 per_cpu(svm_data, cpu) = svm_data;
388
389 return 0;
390
391err_1:
392 kfree(svm_data);
393 return r;
394
395}
396
bfc733a7
RR		 397static void set_msr_interception(u32 *msrpm, unsigned msr,
398 int read, int write)
6aa8b732
AK		 399{
400 int i;
401
402 for (i = 0; i < NUM_MSR_MAPS; i++) {
403 if (msr >= msrpm_ranges[i] &&
404 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
405 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
406 msrpm_ranges[i]) * 2;
407
408 u32 *base = msrpm + (msr_offset / 32);
409 u32 msr_shift = msr_offset % 32;
410 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
411 *base = (*base & ~(0x3 << msr_shift)) |
412 (mask << msr_shift);
bfc733a7 413 return;
6aa8b732
AK		 414 }
415 }
bfc733a7 416 BUG();
6aa8b732
AK		 417}
418
f65c229c
JR		 419static void svm_vcpu_init_msrpm(u32 *msrpm)
420{
421 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
422
423#ifdef CONFIG_X86_64
424 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
425 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
426 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
427 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
428 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
429 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
430#endif
431 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
432 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 433}
434
24e09cbf
JR		 435static void svm_enable_lbrv(struct vcpu_svm *svm)
436{
437 u32 *msrpm = svm->msrpm;
438
439 svm->vmcb->control.lbr_ctl = 1;
440 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
441 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
442 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
443 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
444}
445
446static void svm_disable_lbrv(struct vcpu_svm *svm)
447{
448 u32 *msrpm = svm->msrpm;
449
450 svm->vmcb->control.lbr_ctl = 0;
451 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
452 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
453 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
454 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
455}
456
6aa8b732
AK		 457static __init int svm_hardware_setup(void)
458{
459 int cpu;
460 struct page *iopm_pages;
f65c229c 461 void *iopm_va;
6aa8b732
AK		 462 int r;
463
6aa8b732
AK		 464 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
465
466 if (!iopm_pages)
467 return -ENOMEM;
c8681339
AL		 468
469 iopm_va = page_address(iopm_pages);
470 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 471 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
472
50a37eb4
JR		 473 if (boot_cpu_has(X86_FEATURE_NX))
474 kvm_enable_efer_bits(EFER_NX);
475
1b2fd70c
AG		 476 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
477 kvm_enable_efer_bits(EFER_FFXSR);
478
236de055
AG		 479 if (nested) {
480 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
481 kvm_enable_efer_bits(EFER_SVME);
482 }
483
6aa8b732
AK		 484 for_each_online_cpu(cpu) {
485 r = svm_cpu_init(cpu);
486 if (r)
f65c229c 487 goto err;
6aa8b732 488 }
33bd6a0b
JR		 489
490 svm_features = cpuid_edx(SVM_CPUID_FUNC);
491
e3da3acd
JR		 492 if (!svm_has(SVM_FEATURE_NPT))
493 npt_enabled = false;
494
6c7dac72
JR		 495 if (npt_enabled && !npt) {
496 printk(KERN_INFO "kvm: Nested Paging disabled\n");
497 npt_enabled = false;
498 }
499
18552672 500 if (npt_enabled) {
e3da3acd 501 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 502 kvm_enable_tdp();
5f4cb662
JR		 503 } else
504 kvm_disable_tdp();
e3da3acd 505
6aa8b732
AK		 506 return 0;
507
f65c229c 508err:
6aa8b732
AK		 509 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
510 iopm_base = 0;
511 return r;
512}
513
514static __exit void svm_hardware_unsetup(void)
515{
0da1db75
JR		 516 int cpu;
517
518 for_each_online_cpu(cpu)
519 svm_cpu_uninit(cpu);
520
6aa8b732 521 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 522 iopm_base = 0;
6aa8b732
AK		 523}
524
525static void init_seg(struct vmcb_seg *seg)
526{
527 seg->selector = 0;
528 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
529 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
530 seg->limit = 0xffff;
531 seg->base = 0;
532}
533
534static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
535{
536 seg->selector = 0;
537 seg->attrib = SVM_SELECTOR_P_MASK | type;
538 seg->limit = 0xffff;
539 seg->base = 0;
540}
541
e6101a96 542static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 543{
e6101a96
JR		 544 struct vmcb_control_area *control = &svm->vmcb->control;
545 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 546
547 control->intercept_cr_read = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
649d6864 549 INTERCEPT_CR4_MASK;
6aa8b732
AK		 550
551 control->intercept_cr_write = INTERCEPT_CR0_MASK |
552 INTERCEPT_CR3_MASK |
80a8119c
AK		 553 INTERCEPT_CR4_MASK |
554 INTERCEPT_CR8_MASK;
6aa8b732
AK		 555
556 control->intercept_dr_read = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
559 INTERCEPT_DR3_MASK;
560
561 control->intercept_dr_write = INTERCEPT_DR0_MASK |
562 INTERCEPT_DR1_MASK |
563 INTERCEPT_DR2_MASK |
564 INTERCEPT_DR3_MASK |
565 INTERCEPT_DR5_MASK |
566 INTERCEPT_DR7_MASK;
567
7aa81cc0 568 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 569 (1 << UD_VECTOR) |
570 (1 << MC_VECTOR);
6aa8b732
AK		 571
572
573 control->intercept = (1ULL << INTERCEPT_INTR) |
574 (1ULL << INTERCEPT_NMI) |
0152527b 575 (1ULL << INTERCEPT_SMI) |
6aa8b732 576 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 577 (1ULL << INTERCEPT_INVD) |
6aa8b732 578 (1ULL << INTERCEPT_HLT) |
a7052897 579 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 580 (1ULL << INTERCEPT_INVLPGA) |
581 (1ULL << INTERCEPT_IOIO_PROT) |
582 (1ULL << INTERCEPT_MSR_PROT) |
583 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 584 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 585 (1ULL << INTERCEPT_VMRUN) |
586 (1ULL << INTERCEPT_VMMCALL) |
587 (1ULL << INTERCEPT_VMLOAD) |
588 (1ULL << INTERCEPT_VMSAVE) |
589 (1ULL << INTERCEPT_STGI) |
590 (1ULL << INTERCEPT_CLGI) |
916ce236 591 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 592 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 593 (1ULL << INTERCEPT_MONITOR) |
594 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 595
596 control->iopm_base_pa = iopm_base;
f65c229c 597 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 598 control->tsc_offset = 0;
6aa8b732
AK		 599 control->int_ctl = V_INTR_MASKING_MASK;
600
601 init_seg(&save->es);
602 init_seg(&save->ss);
603 init_seg(&save->ds);
604 init_seg(&save->fs);
605 init_seg(&save->gs);
606
607 save->cs.selector = 0xf000;
608 /* Executable/Readable Code Segment */
609 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
610 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
611 save->cs.limit = 0xffff;
d92899a0
AK		 612 /*
613 * cs.base should really be 0xffff0000, but vmx can't handle that, so
614 * be consistent with it.
615 *
616 * Replace when we have real mode working for vmx.
617 */
618 save->cs.base = 0xf0000;
6aa8b732
AK		 619
620 save->gdtr.limit = 0xffff;
621 save->idtr.limit = 0xffff;
622
623 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
624 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
625
9962d032 626 save->efer = EFER_SVME;
d77c26fc 627 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 628 save->dr7 = 0x400;
629 save->rflags = 2;
630 save->rip = 0x0000fff0;
5fdbf976 631 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 632
633 /*
634 * cr0 val on cpu init should be 0x60000010, we enable cpu
635 * cache by default. the orderly way is to enable cache in bios.
636 */
707d92fa 637 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 638 save->cr4 = X86_CR4_PAE;
6aa8b732 639 /* rdx = ?? */
709ddebf
JR		 640
641 if (npt_enabled) {
642 /* Setup VMCB for Nested Paging */
643 control->nested_ctl = 1;
a7052897
MT		 644 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
645 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 646 control->intercept_exceptions &= ~(1 << PF_VECTOR);
647 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
648 INTERCEPT_CR3_MASK);
649 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
650 INTERCEPT_CR3_MASK);
651 save->g_pat = 0x0007040600070406ULL;
652 /* enable caching because the QEMU Bios doesn't enable it */
653 save->cr0 = X86_CR0_ET;
654 save->cr3 = 0;
655 save->cr4 = 0;
656 }
a79d2f18 657 force_new_asid(&svm->vcpu);
1371d904 658
e6aa9abd 659 svm->nested.vmcb = 0;
2af9194d
JR		 660 svm->vcpu.arch.hflags = 0;
661
662 enable_gif(svm);
6aa8b732
AK		 663}
664
e00c8cf2 665static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 666{
667 struct vcpu_svm *svm = to_svm(vcpu);
668
e6101a96 669 init_vmcb(svm);
70433389 670
c5af89b6 671 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 672 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 673 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
674 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 675 }
5fdbf976
MT		 676 vcpu->arch.regs_avail = ~0;
677 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 678
679 return 0;
04d2cc77
AK		 680}
681
fb3f0f51 682static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 683{
a2fa3e9f 684 struct vcpu_svm *svm;
6aa8b732 685 struct page *page;
f65c229c 686 struct page *msrpm_pages;
b286d5d8 687 struct page *hsave_page;
3d6368ef 688 struct page *nested_msrpm_pages;
fb3f0f51 689 int err;
6aa8b732 690
c16f862d 691 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 692 if (!svm) {
693 err = -ENOMEM;
694 goto out;
695 }
696
697 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
698 if (err)
699 goto free_svm;
700
6aa8b732 701 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 702 if (!page) {
703 err = -ENOMEM;
704 goto uninit;
705 }
6aa8b732 706
f65c229c
JR		 707 err = -ENOMEM;
708 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
709 if (!msrpm_pages)
710 goto uninit;
3d6368ef
AG		 711
712 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!nested_msrpm_pages)
714 goto uninit;
715
f65c229c
JR		 716 svm->msrpm = page_address(msrpm_pages);
717 svm_vcpu_init_msrpm(svm->msrpm);
718
b286d5d8
AG		 719 hsave_page = alloc_page(GFP_KERNEL);
720 if (!hsave_page)
721 goto uninit;
e6aa9abd 722 svm->nested.hsave = page_address(hsave_page);
b286d5d8 723
e6aa9abd 724 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 725
a2fa3e9f
GH		 726 svm->vmcb = page_address(page);
727 clear_page(svm->vmcb);
728 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
729 svm->asid_generation = 0;
e6101a96 730 init_vmcb(svm);
a2fa3e9f 731
fb3f0f51
RR		 732 fx_init(&svm->vcpu);
733 svm->vcpu.fpu_active = 1;
ad312c7c 734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 735 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 737
fb3f0f51 738 return &svm->vcpu;
36241b8c 739
fb3f0f51
RR		 740uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742free_svm:
a4770347 743 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 744out:
745 return ERR_PTR(err);
6aa8b732
AK		 746}
747
748static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749{
a2fa3e9f
GH		 750 struct vcpu_svm *svm = to_svm(vcpu);
751
fb3f0f51 752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 756 kvm_vcpu_uninit(vcpu);
a4770347 757 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 758}
759
15ad7146 760static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 761{
a2fa3e9f 762 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 763 int i;
0cc5064d 764
0cc5064d
AK		 765 if (unlikely(cpu != vcpu->cpu)) {
766 u64 tsc_this, delta;
767
768 /*
769 * Make sure that the guest sees a monotonically
770 * increasing TSC.
771 */
772 rdtscll(tsc_this);
ad312c7c 773 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 774 svm->vmcb->control.tsc_offset += delta;
77b1ab17
JR		 775 if (is_nested(svm))
776 svm->nested.hsave->control.tsc_offset += delta;
0cc5064d 777 vcpu->cpu = cpu;
2f599714 778 kvm_migrate_timers(vcpu);
4b656b12 779 svm->asid_generation = 0;
0cc5064d 780 }
94dfbdb3
AL		 781
782 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 783 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 784}
785
786static void svm_vcpu_put(struct kvm_vcpu *vcpu)
787{
a2fa3e9f 788 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 789 int i;
790
e1beb1d3 791 ++vcpu->stat.host_state_reload;
94dfbdb3 792 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 793 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 794
ad312c7c 795 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 796}
797
6aa8b732
AK		 798static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
799{
a2fa3e9f 800 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 801}
802
803static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
804{
a2fa3e9f 805 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 806}
807
6de4f3ad
AK		 808static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
809{
810 switch (reg) {
811 case VCPU_EXREG_PDPTR:
812 BUG_ON(!npt_enabled);
813 load_pdptrs(vcpu, vcpu->arch.cr3);
814 break;
815 default:
816 BUG();
817 }
818}
819
f0b85051
AG		 820static void svm_set_vintr(struct vcpu_svm *svm)
821{
822 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
823}
824
825static void svm_clear_vintr(struct vcpu_svm *svm)
826{
827 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
828}
829
6aa8b732
AK		 830static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
831{
a2fa3e9f 832 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 833
834 switch (seg) {
835 case VCPU_SREG_CS: return &save->cs;
836 case VCPU_SREG_DS: return &save->ds;
837 case VCPU_SREG_ES: return &save->es;
838 case VCPU_SREG_FS: return &save->fs;
839 case VCPU_SREG_GS: return &save->gs;
840 case VCPU_SREG_SS: return &save->ss;
841 case VCPU_SREG_TR: return &save->tr;
842 case VCPU_SREG_LDTR: return &save->ldtr;
843 }
844 BUG();
8b6d44c7 845 return NULL;
6aa8b732
AK		 846}
847
848static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
849{
850 struct vmcb_seg *s = svm_seg(vcpu, seg);
851
852 return s->base;
853}
854
855static void svm_get_segment(struct kvm_vcpu *vcpu,
856 struct kvm_segment *var, int seg)
857{
858 struct vmcb_seg *s = svm_seg(vcpu, seg);
859
860 var->base = s->base;
861 var->limit = s->limit;
862 var->selector = s->selector;
863 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
864 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
865 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
866 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
867 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
868 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
869 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
870 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 871
19bca6ab
AP		 872 /* AMD's VMCB does not have an explicit unusable field, so emulate it
873 * for cross vendor migration purposes by "not present"
874 */
875 var->unusable = !var->present || (var->type == 0);
876
1fbdc7a5
AP		 877 switch (seg) {
878 case VCPU_SREG_CS:
879 /*
880 * SVM always stores 0 for the 'G' bit in the CS selector in
881 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
882 * Intel's VMENTRY has a check on the 'G' bit.
883 */
25022acc 884 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 885 break;
886 case VCPU_SREG_TR:
887 /*
888 * Work around a bug where the busy flag in the tr selector
889 * isn't exposed
890 */
c0d09828 891 var->type |= 0x2;
1fbdc7a5
AP		 892 break;
893 case VCPU_SREG_DS:
894 case VCPU_SREG_ES:
895 case VCPU_SREG_FS:
896 case VCPU_SREG_GS:
897 /*
898 * The accessed bit must always be set in the segment
899 * descriptor cache, although it can be cleared in the
900 * descriptor, the cached bit always remains at 1. Since
901 * Intel has a check on this, set it here to support
902 * cross-vendor migration.
903 */
904 if (!var->unusable)
905 var->type |= 0x1;
906 break;
b586eb02
AP		 907 case VCPU_SREG_SS:
908 /* On AMD CPUs sometimes the DB bit in the segment
909 * descriptor is left as 1, although the whole segment has
910 * been made unusable. Clear it here to pass an Intel VMX
911 * entry check when cross vendor migrating.
912 */
913 if (var->unusable)
914 var->db = 0;
915 break;
1fbdc7a5 916 }
6aa8b732
AK		 917}
918
2e4d2653
IE		 919static int svm_get_cpl(struct kvm_vcpu *vcpu)
920{
921 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
922
923 return save->cpl;
924}
925
6aa8b732
AK		 926static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
927{
a2fa3e9f
GH		 928 struct vcpu_svm *svm = to_svm(vcpu);
929
930 dt->limit = svm->vmcb->save.idtr.limit;
931 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 932}
933
934static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
935{
a2fa3e9f
GH		 936 struct vcpu_svm *svm = to_svm(vcpu);
937
938 svm->vmcb->save.idtr.limit = dt->limit;
939 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 940}
941
942static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
943{
a2fa3e9f
GH		 944 struct vcpu_svm *svm = to_svm(vcpu);
945
946 dt->limit = svm->vmcb->save.gdtr.limit;
947 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 948}
949
950static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
951{
a2fa3e9f
GH		 952 struct vcpu_svm *svm = to_svm(vcpu);
953
954 svm->vmcb->save.gdtr.limit = dt->limit;
955 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 956}
957
25c4c276 958static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 959{
960}
961
6aa8b732
AK		 962static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
963{
a2fa3e9f
GH		 964 struct vcpu_svm *svm = to_svm(vcpu);
965
05b3e0c2 966#ifdef CONFIG_X86_64
ad312c7c 967 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 969 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 970 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 971 }
972
d77c26fc 973 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 974 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 975 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 976 }
977 }
978#endif
709ddebf
JR		 979 if (npt_enabled)
980 goto set;
981
ad312c7c 982 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 983 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 984 vcpu->fpu_active = 1;
985 }
986
ad312c7c 987 vcpu->arch.cr0 = cr0;
707d92fa 988 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 989 if (!vcpu->fpu_active) {
990 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 991 cr0 |= X86_CR0_TS;
6b390b63 992 }
709ddebf
JR		 993set:
994 /*
995 * re-enable caching here because the QEMU bios
996 * does not do it - this results in some delay at
997 * reboot
998 */
999 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1000 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 1001}
1002
1003static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1004{
6394b649 1005 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1006 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1007
1008 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009 force_new_asid(vcpu);
6394b649 1010
ec077263
JR		 1011 vcpu->arch.cr4 = cr4;
1012 if (!npt_enabled)
1013 cr4 |= X86_CR4_PAE;
6394b649 1014 cr4 |= host_cr4_mce;
ec077263 1015 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1016}
1017
1018static void svm_set_segment(struct kvm_vcpu *vcpu,
1019 struct kvm_segment *var, int seg)
1020{
a2fa3e9f 1021 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1022 struct vmcb_seg *s = svm_seg(vcpu, seg);
1023
1024 s->base = var->base;
1025 s->limit = var->limit;
1026 s->selector = var->selector;
1027 if (var->unusable)
1028 s->attrib = 0;
1029 else {
1030 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1038 }
1039 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1040 svm->vmcb->save.cpl
1041 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1042 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1043
1044}
1045
44c11430 1046static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1047{
d0bfb940
JK		 1048 struct vcpu_svm *svm = to_svm(vcpu);
1049
d0bfb940
JK		 1050 svm->vmcb->control.intercept_exceptions &=
1051 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1052
1053 if (vcpu->arch.singlestep)
1054 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1055
d0bfb940
JK		 1056 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057 if (vcpu->guest_debug &
1058 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059 svm->vmcb->control.intercept_exceptions |=
1060 1 << DB_VECTOR;
1061 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062 svm->vmcb->control.intercept_exceptions |=
1063 1 << BP_VECTOR;
1064 } else
1065 vcpu->guest_debug = 0;
44c11430
GN		 1066}
1067
1068static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1069{
1070 int old_debug = vcpu->guest_debug;
1071 struct vcpu_svm *svm = to_svm(vcpu);
1072
1073 vcpu->guest_debug = dbg->control;
1074
1075 update_db_intercept(vcpu);
d0bfb940 1076
ae675ef0
JK		 1077 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1078 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1079 else
1080 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1081
d0bfb940
JK		 1082 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1083 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1084 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1085 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1086
1087 return 0;
6aa8b732
AK		 1088}
1089
1090static void load_host_msrs(struct kvm_vcpu *vcpu)
1091{
94dfbdb3 1092#ifdef CONFIG_X86_64
a2fa3e9f 1093 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1094#endif
6aa8b732
AK		 1095}
1096
1097static void save_host_msrs(struct kvm_vcpu *vcpu)
1098{
94dfbdb3 1099#ifdef CONFIG_X86_64
a2fa3e9f 1100 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1101#endif
6aa8b732
AK		 1102}
1103
e756fc62 1104static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1105{
1106 if (svm_data->next_asid > svm_data->max_asid) {
1107 ++svm_data->asid_generation;
1108 svm_data->next_asid = 1;
a2fa3e9f 1109 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1110 }
1111
a2fa3e9f
GH		 1112 svm->asid_generation = svm_data->asid_generation;
1113 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1114}
1115
6aa8b732
AK		 1116static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1117{
42dbaa5a
JK		 1118 struct vcpu_svm *svm = to_svm(vcpu);
1119 unsigned long val;
1120
1121 switch (dr) {
1122 case 0 ... 3:
1123 val = vcpu->arch.db[dr];
1124 break;
1125 case 6:
1126 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1127 val = vcpu->arch.dr6;
1128 else
1129 val = svm->vmcb->save.dr6;
1130 break;
1131 case 7:
1132 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1133 val = vcpu->arch.dr7;
1134 else
1135 val = svm->vmcb->save.dr7;
1136 break;
1137 default:
1138 val = 0;
1139 }
1140
af9ca2d7 1141 return val;
6aa8b732
AK		 1142}
1143
1144static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1145 int *exception)
1146{
a2fa3e9f
GH		 1147 struct vcpu_svm *svm = to_svm(vcpu);
1148
42dbaa5a 1149 *exception = 0;
6aa8b732
AK		 1150
1151 switch (dr) {
1152 case 0 ... 3:
42dbaa5a
JK		 1153 vcpu->arch.db[dr] = value;
1154 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1155 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1156 return;
1157 case 4 ... 5:
42dbaa5a 1158 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1159 *exception = UD_VECTOR;
42dbaa5a
JK		 1160 return;
1161 case 6:
1162 if (value & 0xffffffff00000000ULL) {
1163 *exception = GP_VECTOR;
6aa8b732
AK		 1164 return;
1165 }
42dbaa5a
JK		 1166 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1167 return;
1168 case 7:
1169 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1170 *exception = GP_VECTOR;
1171 return;
1172 }
42dbaa5a
JK		 1173 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1174 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1175 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1176 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1177 }
6aa8b732 1178 return;
6aa8b732 1179 default:
42dbaa5a 1180 /* FIXME: Possible case? */
6aa8b732 1181 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1182 __func__, dr);
6aa8b732
AK		 1183 *exception = UD_VECTOR;
1184 return;
1185 }
1186}
1187
851ba692 1188static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1189{
6aa8b732
AK		 1190 u64 fault_address;
1191 u32 error_code;
6aa8b732 1192
a2fa3e9f
GH		 1193 fault_address = svm->vmcb->control.exit_info_2;
1194 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1195
229456fc 1196 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1197 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1198 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1199 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1200}
1201
851ba692 1202static int db_interception(struct vcpu_svm *svm)
d0bfb940 1203{
851ba692
AK		 1204 struct kvm_run *kvm_run = svm->vcpu.run;
1205
d0bfb940 1206 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1207 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1208 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1209 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1210 return 1;
1211 }
44c11430
GN		 1212
1213 if (svm->vcpu.arch.singlestep) {
1214 svm->vcpu.arch.singlestep = false;
1215 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1216 svm->vmcb->save.rflags &=
1217 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1218 update_db_intercept(&svm->vcpu);
1219 }
1220
1221 if (svm->vcpu.guest_debug &
1222 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1223 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1224 kvm_run->debug.arch.pc =
1225 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1226 kvm_run->debug.arch.exception = DB_VECTOR;
1227 return 0;
1228 }
1229
1230 return 1;
d0bfb940
JK		 1231}
1232
851ba692 1233static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1234{
851ba692
AK		 1235 struct kvm_run *kvm_run = svm->vcpu.run;
1236
d0bfb940
JK		 1237 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1238 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1239 kvm_run->debug.arch.exception = BP_VECTOR;
1240 return 0;
1241}
1242
851ba692 1243static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1244{
1245 int er;
1246
851ba692 1247 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1248 if (er != EMULATE_DONE)
7ee5d940 1249 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1250 return 1;
1251}
1252
851ba692 1253static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1254{
a2fa3e9f 1255 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1256 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1257 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1258 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1259
1260 return 1;
7807fa6c
AL		 1261}
1262
851ba692 1263static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1264{
1265 /*
1266 * On an #MC intercept the MCE handler is not called automatically in
1267 * the host. So do it by hand here.
1268 */
1269 asm volatile (
1270 "int $0x12\n");
1271 /* not sure if we ever come back to this point */
1272
1273 return 1;
1274}
1275
851ba692 1276static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1277{
851ba692
AK		 1278 struct kvm_run *kvm_run = svm->vcpu.run;
1279
46fe4ddd
JR		 1280 /*
1281 * VMCB is undefined after a SHUTDOWN intercept
1282 * so reinitialize it.
1283 */
a2fa3e9f 1284 clear_page(svm->vmcb);
e6101a96 1285 init_vmcb(svm);
46fe4ddd
JR		 1286
1287 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1288 return 0;
1289}
1290
851ba692 1291static int io_interception(struct vcpu_svm *svm)
6aa8b732 1292{
d77c26fc 1293 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1294 int size, in, string;
039576c0 1295 unsigned port;
6aa8b732 1296
e756fc62 1297 ++svm->vcpu.stat.io_exits;
6aa8b732 1298
a2fa3e9f 1299 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1300
e70669ab
LV		 1301 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1302
1303 if (string) {
3427318f 1304 if (emulate_instruction(&svm->vcpu,
851ba692 1305 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1306 return 0;
1307 return 1;
1308 }
1309
039576c0
AK		 1310 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1311 port = io_info >> 16;
1312 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1313
e93f36bc 1314 skip_emulated_instruction(&svm->vcpu);
851ba692 1315 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1316}
1317
851ba692 1318static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1319{
1320 return 1;
1321}
1322
851ba692 1323static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1324{
1325 ++svm->vcpu.stat.irq_exits;
1326 return 1;
1327}
1328
851ba692 1329static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1330{
1331 return 1;
1332}
1333
851ba692 1334static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1335{
5fdbf976 1336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1337 skip_emulated_instruction(&svm->vcpu);
1338 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1339}
1340
851ba692 1341static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1342{
5fdbf976 1343 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1344 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1345 kvm_emulate_hypercall(&svm->vcpu);
1346 return 1;
02e235bc
AK		 1347}
1348
c0725420
AG		 1349static int nested_svm_check_permissions(struct vcpu_svm *svm)
1350{
1351 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1352 || !is_paging(&svm->vcpu)) {
1353 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1354 return 1;
1355 }
1356
1357 if (svm->vmcb->save.cpl) {
1358 kvm_inject_gp(&svm->vcpu, 0);
1359 return 1;
1360 }
1361
1362 return 0;
1363}
1364
cf74a78b
AG		 1365static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1366 bool has_error_code, u32 error_code)
1367{
0295ad7d
JR		 1368 if (!is_nested(svm))
1369 return 0;
cf74a78b 1370
0295ad7d
JR		 1371 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1372 svm->vmcb->control.exit_code_hi = 0;
1373 svm->vmcb->control.exit_info_1 = error_code;
1374 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1375
410e4d57 1376 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1377}
1378
1379static inline int nested_svm_intr(struct vcpu_svm *svm)
1380{
26666957
JR		 1381 if (!is_nested(svm))
1382 return 0;
cf74a78b 1383
26666957
JR		 1384 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1385 return 0;
cf74a78b 1386
26666957
JR		 1387 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1388 return 0;
cf74a78b 1389
26666957
JR		 1390 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1391
1392 if (nested_svm_exit_handled(svm)) {
1393 nsvm_printk("VMexit -> INTR\n");
1394 return 1;
cf74a78b
AG		 1395 }
1396
1397 return 0;
1398}
1399
34f80cfa
JR		 1400static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1401{
1402 struct page *page;
1403
34f80cfa 1404 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1405 if (is_error_page(page))
1406 goto error;
1407
1408 return kmap_atomic(page, idx);
1409
1410error:
1411 kvm_release_page_clean(page);
1412 kvm_inject_gp(&svm->vcpu, 0);
1413
1414 return NULL;
1415}
1416
1417static void nested_svm_unmap(void *addr, enum km_type idx)
1418{
1419 struct page *page;
1420
1421 if (!addr)
1422 return;
1423
1424 page = kmap_atomic_to_page(addr);
1425
1426 kunmap_atomic(addr, idx);
1427 kvm_release_page_dirty(page);
1428}
1429
3d62d9aa 1430static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1431{
4c2161ae 1432 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1433 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1434 bool ret = false;
1435 u32 t0, t1;
1436 u8 *msrpm;
4c2161ae 1437
3d62d9aa
JR		 1438 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1439 return false;
1440
1441 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1442
1443 if (!msrpm)
1444 goto out;
4c2161ae
JR		 1445
1446 switch (msr) {
1447 case 0 ... 0x1fff:
1448 t0 = (msr * 2) % 8;
1449 t1 = msr / 8;
1450 break;
1451 case 0xc0000000 ... 0xc0001fff:
1452 t0 = (8192 + msr - 0xc0000000) * 2;
1453 t1 = (t0 / 8);
1454 t0 %= 8;
1455 break;
1456 case 0xc0010000 ... 0xc0011fff:
1457 t0 = (16384 + msr - 0xc0010000) * 2;
1458 t1 = (t0 / 8);
1459 t0 %= 8;
1460 break;
1461 default:
3d62d9aa
JR		 1462 ret = true;
1463 goto out;
4c2161ae 1464 }
4c2161ae 1465
3d62d9aa
JR		 1466 ret = msrpm[t1] & ((1 << param) << t0);
1467
1468out:
1469 nested_svm_unmap(msrpm, KM_USER0);
1470
1471 return ret;
4c2161ae
JR		 1472}
1473
410e4d57 1474static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1475{
cf74a78b 1476 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1477
410e4d57
JR		 1478 switch (exit_code) {
1479 case SVM_EXIT_INTR:
1480 case SVM_EXIT_NMI:
1481 return NESTED_EXIT_HOST;
cf74a78b 1482 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1483 case SVM_EXIT_NPF:
1484 if (npt_enabled)
1485 return NESTED_EXIT_HOST;
1486 break;
1487 /* When we're shadowing, trap PFs */
1488 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1489 if (!npt_enabled)
1490 return NESTED_EXIT_HOST;
1491 break;
1492 default:
1493 break;
cf74a78b
AG		 1494 }
1495
410e4d57
JR		 1496 return NESTED_EXIT_CONTINUE;
1497}
1498
1499/*
1500 * If this function returns true, this #vmexit was already handled
1501 */
1502static int nested_svm_exit_handled(struct vcpu_svm *svm)
1503{
1504 u32 exit_code = svm->vmcb->control.exit_code;
1505 int vmexit = NESTED_EXIT_HOST;
1506
cf74a78b 1507 switch (exit_code) {
9c4e40b9 1508 case SVM_EXIT_MSR:
3d62d9aa 1509 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1510 break;
cf74a78b
AG		 1511 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1512 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1513 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1514 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1515 break;
1516 }
1517 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1518 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1519 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1520 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1521 break;
1522 }
1523 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1524 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1525 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1526 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1527 break;
1528 }
1529 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1530 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1531 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1532 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1533 break;
1534 }
1535 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1536 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1537 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1538 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1539 break;
1540 }
1541 default: {
1542 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1543 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1544 if (svm->nested.intercept & exit_bits)
410e4d57 1545 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1546 }
1547 }
1548
410e4d57 1549 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1550 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1551 nested_svm_vmexit(svm);
1552 }
1553
1554 return vmexit;
cf74a78b
AG		 1555}
1556
0460a979
JR		 1557static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1558{
1559 struct vmcb_control_area *dst = &dst_vmcb->control;
1560 struct vmcb_control_area *from = &from_vmcb->control;
1561
1562 dst->intercept_cr_read = from->intercept_cr_read;
1563 dst->intercept_cr_write = from->intercept_cr_write;
1564 dst->intercept_dr_read = from->intercept_dr_read;
1565 dst->intercept_dr_write = from->intercept_dr_write;
1566 dst->intercept_exceptions = from->intercept_exceptions;
1567 dst->intercept = from->intercept;
1568 dst->iopm_base_pa = from->iopm_base_pa;
1569 dst->msrpm_base_pa = from->msrpm_base_pa;
1570 dst->tsc_offset = from->tsc_offset;
1571 dst->asid = from->asid;
1572 dst->tlb_ctl = from->tlb_ctl;
1573 dst->int_ctl = from->int_ctl;
1574 dst->int_vector = from->int_vector;
1575 dst->int_state = from->int_state;
1576 dst->exit_code = from->exit_code;
1577 dst->exit_code_hi = from->exit_code_hi;
1578 dst->exit_info_1 = from->exit_info_1;
1579 dst->exit_info_2 = from->exit_info_2;
1580 dst->exit_int_info = from->exit_int_info;
1581 dst->exit_int_info_err = from->exit_int_info_err;
1582 dst->nested_ctl = from->nested_ctl;
1583 dst->event_inj = from->event_inj;
1584 dst->event_inj_err = from->event_inj_err;
1585 dst->nested_cr3 = from->nested_cr3;
1586 dst->lbr_ctl = from->lbr_ctl;
1587}
1588
34f80cfa 1589static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1590{
34f80cfa 1591 struct vmcb *nested_vmcb;
e6aa9abd 1592 struct vmcb *hsave = svm->nested.hsave;
33740e40 1593 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1594
34f80cfa
JR		 1595 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1596 if (!nested_vmcb)
1597 return 1;
1598
cf74a78b 1599 /* Give the current vmcb to the guest */
33740e40
JR		 1600 disable_gif(svm);
1601
1602 nested_vmcb->save.es = vmcb->save.es;
1603 nested_vmcb->save.cs = vmcb->save.cs;
1604 nested_vmcb->save.ss = vmcb->save.ss;
1605 nested_vmcb->save.ds = vmcb->save.ds;
1606 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1607 nested_vmcb->save.idtr = vmcb->save.idtr;
1608 if (npt_enabled)
1609 nested_vmcb->save.cr3 = vmcb->save.cr3;
1610 nested_vmcb->save.cr2 = vmcb->save.cr2;
1611 nested_vmcb->save.rflags = vmcb->save.rflags;
1612 nested_vmcb->save.rip = vmcb->save.rip;
1613 nested_vmcb->save.rsp = vmcb->save.rsp;
1614 nested_vmcb->save.rax = vmcb->save.rax;
1615 nested_vmcb->save.dr7 = vmcb->save.dr7;
1616 nested_vmcb->save.dr6 = vmcb->save.dr6;
1617 nested_vmcb->save.cpl = vmcb->save.cpl;
1618
1619 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1620 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1621 nested_vmcb->control.int_state = vmcb->control.int_state;
1622 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1623 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1624 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1625 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1626 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1627 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1628 nested_vmcb->control.tlb_ctl = 0;
1629 nested_vmcb->control.event_inj = 0;
1630 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1631
1632 /* We always set V_INTR_MASKING and remember the old value in hflags */
1633 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1634 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1635
cf74a78b 1636 /* Restore the original control entries */
0460a979 1637 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1638
1639 /* Kill any pending exceptions */
1640 if (svm->vcpu.arch.exception.pending == true)
1641 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1642
219b65dc
AG		 1643 kvm_clear_exception_queue(&svm->vcpu);
1644 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1645
1646 /* Restore selected save entries */
1647 svm->vmcb->save.es = hsave->save.es;
1648 svm->vmcb->save.cs = hsave->save.cs;
1649 svm->vmcb->save.ss = hsave->save.ss;
1650 svm->vmcb->save.ds = hsave->save.ds;
1651 svm->vmcb->save.gdtr = hsave->save.gdtr;
1652 svm->vmcb->save.idtr = hsave->save.idtr;
1653 svm->vmcb->save.rflags = hsave->save.rflags;
1654 svm_set_efer(&svm->vcpu, hsave->save.efer);
1655 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1656 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1657 if (npt_enabled) {
1658 svm->vmcb->save.cr3 = hsave->save.cr3;
1659 svm->vcpu.arch.cr3 = hsave->save.cr3;
1660 } else {
1661 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1662 }
1663 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1664 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1665 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1666 svm->vmcb->save.dr7 = 0;
1667 svm->vmcb->save.cpl = 0;
1668 svm->vmcb->control.exit_int_info = 0;
1669
cf74a78b 1670 /* Exit nested SVM mode */
e6aa9abd 1671 svm->nested.vmcb = 0;
cf74a78b 1672
34f80cfa 1673 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1674
1675 kvm_mmu_reset_context(&svm->vcpu);
1676 kvm_mmu_load(&svm->vcpu);
1677
1678 return 0;
1679}
3d6368ef 1680
9738b2c9 1681static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1682{
9738b2c9 1683 u32 *nested_msrpm;
3d6368ef 1684 int i;
9738b2c9
JR		 1685
1686 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1687 if (!nested_msrpm)
1688 return false;
1689
3d6368ef 1690 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1691 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1692
e6aa9abd 1693 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1694
9738b2c9
JR		 1695 nested_svm_unmap(nested_msrpm, KM_USER0);
1696
1697 return true;
3d6368ef
AG		 1698}
1699
9738b2c9 1700static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1701{
9738b2c9 1702 struct vmcb *nested_vmcb;
e6aa9abd 1703 struct vmcb *hsave = svm->nested.hsave;
defbba56 1704 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1705
9738b2c9
JR		 1706 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1707 if (!nested_vmcb)
1708 return false;
1709
3d6368ef 1710 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1711 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1712
1713 /* Clear internal status */
219b65dc
AG		 1714 kvm_clear_exception_queue(&svm->vcpu);
1715 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1716
1717 /* Save the old vmcb, so we don't need to pick what we save, but
1718 can restore everything when a VMEXIT occurs */
defbba56
JR		 1719 hsave->save.es = vmcb->save.es;
1720 hsave->save.cs = vmcb->save.cs;
1721 hsave->save.ss = vmcb->save.ss;
1722 hsave->save.ds = vmcb->save.ds;
1723 hsave->save.gdtr = vmcb->save.gdtr;
1724 hsave->save.idtr = vmcb->save.idtr;
1725 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1726 hsave->save.cr0 = svm->vcpu.arch.cr0;
1727 hsave->save.cr4 = svm->vcpu.arch.cr4;
1728 hsave->save.rflags = vmcb->save.rflags;
1729 hsave->save.rip = svm->next_rip;
1730 hsave->save.rsp = vmcb->save.rsp;
1731 hsave->save.rax = vmcb->save.rax;
1732 if (npt_enabled)
1733 hsave->save.cr3 = vmcb->save.cr3;
1734 else
1735 hsave->save.cr3 = svm->vcpu.arch.cr3;
1736
0460a979 1737 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1738
1739 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1740 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1741 else
1742 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1743
1744 /* Load the nested guest state */
1745 svm->vmcb->save.es = nested_vmcb->save.es;
1746 svm->vmcb->save.cs = nested_vmcb->save.cs;
1747 svm->vmcb->save.ss = nested_vmcb->save.ss;
1748 svm->vmcb->save.ds = nested_vmcb->save.ds;
1749 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1750 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1751 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1752 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1753 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1754 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1755 if (npt_enabled) {
1756 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1757 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1758 } else {
1759 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1760 kvm_mmu_reset_context(&svm->vcpu);
1761 }
defbba56 1762 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1763 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1764 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1765 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1766 /* In case we don't even reach vcpu_run, the fields are not updated */
1767 svm->vmcb->save.rax = nested_vmcb->save.rax;
1768 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1769 svm->vmcb->save.rip = nested_vmcb->save.rip;
1770 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1771 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1772 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1773
1774 /* We don't want a nested guest to be more powerful than the guest,
1775 so all intercepts are ORed */
1776 svm->vmcb->control.intercept_cr_read |=
1777 nested_vmcb->control.intercept_cr_read;
1778 svm->vmcb->control.intercept_cr_write |=
1779 nested_vmcb->control.intercept_cr_write;
1780 svm->vmcb->control.intercept_dr_read |=
1781 nested_vmcb->control.intercept_dr_read;
1782 svm->vmcb->control.intercept_dr_write |=
1783 nested_vmcb->control.intercept_dr_write;
1784 svm->vmcb->control.intercept_exceptions |=
1785 nested_vmcb->control.intercept_exceptions;
1786
1787 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1788
e6aa9abd 1789 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1790
aad42c64
JR		 1791 /* cache intercepts */
1792 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1793 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1794 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1795 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1796 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1797 svm->nested.intercept = nested_vmcb->control.intercept;
1798
3d6368ef
AG		 1799 force_new_asid(&svm->vcpu);
1800 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1801 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1802 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1803 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1804 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1805 nested_vmcb->control.int_ctl);
1806 }
1807 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1808 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1809 else
1810 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1811
1812 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1813 nested_vmcb->control.exit_int_info,
1814 nested_vmcb->control.int_state);
1815
1816 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1817 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1818 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1819 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1820 nsvm_printk("Injecting Event: 0x%x\n",
1821 nested_vmcb->control.event_inj);
1822 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1823 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1824
9738b2c9
JR		 1825 nested_svm_unmap(nested_vmcb, KM_USER0);
1826
2af9194d 1827 enable_gif(svm);
3d6368ef 1828
9738b2c9 1829 return true;
3d6368ef
AG		 1830}
1831
9966bf68 1832static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1833{
1834 to_vmcb->save.fs = from_vmcb->save.fs;
1835 to_vmcb->save.gs = from_vmcb->save.gs;
1836 to_vmcb->save.tr = from_vmcb->save.tr;
1837 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1838 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1839 to_vmcb->save.star = from_vmcb->save.star;
1840 to_vmcb->save.lstar = from_vmcb->save.lstar;
1841 to_vmcb->save.cstar = from_vmcb->save.cstar;
1842 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1843 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1844 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1845 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1846}
1847
851ba692 1848static int vmload_interception(struct vcpu_svm *svm)
5542675b 1849{
9966bf68
JR		 1850 struct vmcb *nested_vmcb;
1851
5542675b
AG		 1852 if (nested_svm_check_permissions(svm))
1853 return 1;
1854
1855 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1856 skip_emulated_instruction(&svm->vcpu);
1857
9966bf68
JR		 1858 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1859 if (!nested_vmcb)
1860 return 1;
1861
1862 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1863 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1864
1865 return 1;
1866}
1867
851ba692 1868static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1869{
9966bf68
JR		 1870 struct vmcb *nested_vmcb;
1871
5542675b
AG		 1872 if (nested_svm_check_permissions(svm))
1873 return 1;
1874
1875 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1876 skip_emulated_instruction(&svm->vcpu);
1877
9966bf68
JR		 1878 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1879 if (!nested_vmcb)
1880 return 1;
1881
1882 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1883 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1884
1885 return 1;
1886}
1887
851ba692 1888static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef
AG		 1889{
1890 nsvm_printk("VMrun\n");
1f8da478 1891
3d6368ef
AG		 1892 if (nested_svm_check_permissions(svm))
1893 return 1;
1894
1895 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1896 skip_emulated_instruction(&svm->vcpu);
1897
9738b2c9 1898 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1899 return 1;
1900
9738b2c9 1901 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1902 goto failed;
1903
1904 return 1;
1905
1906failed:
1907
1908 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1909 svm->vmcb->control.exit_code_hi = 0;
1910 svm->vmcb->control.exit_info_1 = 0;
1911 svm->vmcb->control.exit_info_2 = 0;
1912
1913 nested_svm_vmexit(svm);
3d6368ef
AG		 1914
1915 return 1;
1916}
1917
851ba692 1918static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1919{
1920 if (nested_svm_check_permissions(svm))
1921 return 1;
1922
1923 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1924 skip_emulated_instruction(&svm->vcpu);
1925
2af9194d 1926 enable_gif(svm);
1371d904
AG		 1927
1928 return 1;
1929}
1930
851ba692 1931static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1932{
1933 if (nested_svm_check_permissions(svm))
1934 return 1;
1935
1936 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1937 skip_emulated_instruction(&svm->vcpu);
1938
2af9194d 1939 disable_gif(svm);
1371d904
AG		 1940
1941 /* After a CLGI no interrupts should come */
1942 svm_clear_vintr(svm);
1943 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1944
1945 return 1;
1946}
1947
851ba692 1948static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1949{
1950 struct kvm_vcpu *vcpu = &svm->vcpu;
1951 nsvm_printk("INVLPGA\n");
1952
1953 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1954 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1955
1956 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1957 skip_emulated_instruction(&svm->vcpu);
1958 return 1;
1959}
1960
851ba692 1961static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1962{
7ee5d940 1963 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1964 return 1;
1965}
1966
851ba692 1967static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 1968{
37817f29 1969 u16 tss_selector;
64a7ec06
GN		 1970 int reason;
1971 int int_type = svm->vmcb->control.exit_int_info &
1972 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1973 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1974 uint32_t type =
1975 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1976 uint32_t idt_v =
1977 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1978
1979 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1980
37817f29
IE		 1981 if (svm->vmcb->control.exit_info_2 &
1982 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1983 reason = TASK_SWITCH_IRET;
1984 else if (svm->vmcb->control.exit_info_2 &
1985 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1986 reason = TASK_SWITCH_JMP;
fe8e7f83 1987 else if (idt_v)
64a7ec06
GN		 1988 reason = TASK_SWITCH_GATE;
1989 else
1990 reason = TASK_SWITCH_CALL;
1991
fe8e7f83
GN		 1992 if (reason == TASK_SWITCH_GATE) {
1993 switch (type) {
1994 case SVM_EXITINTINFO_TYPE_NMI:
1995 svm->vcpu.arch.nmi_injected = false;
1996 break;
1997 case SVM_EXITINTINFO_TYPE_EXEPT:
1998 kvm_clear_exception_queue(&svm->vcpu);
1999 break;
2000 case SVM_EXITINTINFO_TYPE_INTR:
2001 kvm_clear_interrupt_queue(&svm->vcpu);
2002 break;
2003 default:
2004 break;
2005 }
2006 }
64a7ec06 2007
8317c298
GN		 2008 if (reason != TASK_SWITCH_GATE ||
2009 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2010 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2011 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2012 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2013
2014 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2015}
2016
851ba692 2017static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2018{
5fdbf976 2019 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2020 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2021 return 1;
6aa8b732
AK		 2022}
2023
851ba692 2024static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2025{
2026 ++svm->vcpu.stat.nmi_window_exits;
2027 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2028 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2029 return 1;
2030}
2031
851ba692 2032static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2033{
851ba692 2034 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2035 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2036 return 1;
2037}
2038
851ba692 2039static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2040{
851ba692 2041 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2042 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2043 return 1;
2044}
2045
851ba692 2046static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2047{
851ba692
AK		 2048 struct kvm_run *kvm_run = svm->vcpu.run;
2049
0a5fff19
GN		 2050 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2051 /* instruction emulation calls kvm_set_cr8() */
851ba692 2052 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2053 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2054 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2055 return 1;
95ba8273 2056 }
0a5fff19
GN		 2057 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2058 return 1;
1d075434
JR		 2059 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2060 return 0;
2061}
2062
6aa8b732
AK		 2063static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2064{
a2fa3e9f
GH		 2065 struct vcpu_svm *svm = to_svm(vcpu);
2066
6aa8b732 2067 switch (ecx) {
af24a4e4 2068 case MSR_IA32_TSC: {
20824f30 2069 u64 tsc_offset;
6aa8b732 2070
20824f30
JR		 2071 if (is_nested(svm))
2072 tsc_offset = svm->nested.hsave->control.tsc_offset;
2073 else
2074 tsc_offset = svm->vmcb->control.tsc_offset;
2075
2076 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2077 break;
2078 }
0e859cac 2079 case MSR_K6_STAR:
a2fa3e9f 2080 *data = svm->vmcb->save.star;
6aa8b732 2081 break;
0e859cac 2082#ifdef CONFIG_X86_64
6aa8b732 2083 case MSR_LSTAR:
a2fa3e9f 2084 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2085 break;
2086 case MSR_CSTAR:
a2fa3e9f 2087 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2088 break;
2089 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2090 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2091 break;
2092 case MSR_SYSCALL_MASK:
a2fa3e9f 2093 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2094 break;
2095#endif
2096 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2097 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2098 break;
2099 case MSR_IA32_SYSENTER_EIP:
017cb99e 2100 *data = svm->sysenter_eip;
6aa8b732
AK		 2101 break;
2102 case MSR_IA32_SYSENTER_ESP:
017cb99e 2103 *data = svm->sysenter_esp;
6aa8b732 2104 break;
a2938c80
JR		 2105 /* Nobody will change the following 5 values in the VMCB so
2106 we can safely return them on rdmsr. They will always be 0
2107 until LBRV is implemented. */
2108 case MSR_IA32_DEBUGCTLMSR:
2109 *data = svm->vmcb->save.dbgctl;
2110 break;
2111 case MSR_IA32_LASTBRANCHFROMIP:
2112 *data = svm->vmcb->save.br_from;
2113 break;
2114 case MSR_IA32_LASTBRANCHTOIP:
2115 *data = svm->vmcb->save.br_to;
2116 break;
2117 case MSR_IA32_LASTINTFROMIP:
2118 *data = svm->vmcb->save.last_excp_from;
2119 break;
2120 case MSR_IA32_LASTINTTOIP:
2121 *data = svm->vmcb->save.last_excp_to;
2122 break;
b286d5d8 2123 case MSR_VM_HSAVE_PA:
e6aa9abd 2124 *data = svm->nested.hsave_msr;
b286d5d8 2125 break;
eb6f302e
JR		 2126 case MSR_VM_CR:
2127 *data = 0;
2128 break;
c8a73f18
AG		 2129 case MSR_IA32_UCODE_REV:
2130 *data = 0x01000065;
2131 break;
6aa8b732 2132 default:
3bab1f5d 2133 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2134 }
2135 return 0;
2136}
2137
851ba692 2138static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2139{
ad312c7c 2140 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2141 u64 data;
2142
e756fc62 2143 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2144 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2145 else {
229456fc 2146 trace_kvm_msr_read(ecx, data);
af9ca2d7 2147
5fdbf976 2148 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2149 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2150 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2151 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2152 }
2153 return 1;
2154}
2155
2156static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2157{
a2fa3e9f
GH		 2158 struct vcpu_svm *svm = to_svm(vcpu);
2159
6aa8b732 2160 switch (ecx) {
af24a4e4 2161 case MSR_IA32_TSC: {
20824f30
JR		 2162 u64 tsc_offset = data - native_read_tsc();
2163 u64 g_tsc_offset = 0;
2164
2165 if (is_nested(svm)) {
2166 g_tsc_offset = svm->vmcb->control.tsc_offset -
2167 svm->nested.hsave->control.tsc_offset;
2168 svm->nested.hsave->control.tsc_offset = tsc_offset;
2169 }
2170
2171 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2172
6aa8b732
AK		 2173 break;
2174 }
0e859cac 2175 case MSR_K6_STAR:
a2fa3e9f 2176 svm->vmcb->save.star = data;
6aa8b732 2177 break;
49b14f24 2178#ifdef CONFIG_X86_64
6aa8b732 2179 case MSR_LSTAR:
a2fa3e9f 2180 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2181 break;
2182 case MSR_CSTAR:
a2fa3e9f 2183 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2184 break;
2185 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2186 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2187 break;
2188 case MSR_SYSCALL_MASK:
a2fa3e9f 2189 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2190 break;
2191#endif
2192 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2193 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2194 break;
2195 case MSR_IA32_SYSENTER_EIP:
017cb99e 2196 svm->sysenter_eip = data;
a2fa3e9f 2197 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2198 break;
2199 case MSR_IA32_SYSENTER_ESP:
017cb99e 2200 svm->sysenter_esp = data;
a2fa3e9f 2201 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2202 break;
a2938c80 2203 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2204 if (!svm_has(SVM_FEATURE_LBRV)) {
2205 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2206 __func__, data);
24e09cbf
JR		 2207 break;
2208 }
2209 if (data & DEBUGCTL_RESERVED_BITS)
2210 return 1;
2211
2212 svm->vmcb->save.dbgctl = data;
2213 if (data & (1ULL<<0))
2214 svm_enable_lbrv(svm);
2215 else
2216 svm_disable_lbrv(svm);
a2938c80 2217 break;
b286d5d8 2218 case MSR_VM_HSAVE_PA:
e6aa9abd 2219 svm->nested.hsave_msr = data;
62b9abaa 2220 break;
3c5d0a44
AG		 2221 case MSR_VM_CR:
2222 case MSR_VM_IGNNE:
3c5d0a44
AG		 2223 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2224 break;
6aa8b732 2225 default:
3bab1f5d 2226 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2227 }
2228 return 0;
2229}
2230
851ba692 2231static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2232{
ad312c7c 2233 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2234 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2235 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2236
229456fc 2237 trace_kvm_msr_write(ecx, data);
af9ca2d7 2238
5fdbf976 2239 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2240 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2241 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2242 else
e756fc62 2243 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2244 return 1;
2245}
2246
851ba692 2247static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2248{
e756fc62 2249 if (svm->vmcb->control.exit_info_1)
851ba692 2250 return wrmsr_interception(svm);
6aa8b732 2251 else
851ba692 2252 return rdmsr_interception(svm);
6aa8b732
AK		 2253}
2254
851ba692 2255static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2256{
851ba692
AK		 2257 struct kvm_run *kvm_run = svm->vcpu.run;
2258
f0b85051 2259 svm_clear_vintr(svm);
85f455f7 2260 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2261 /*
2262 * If the user space waits to inject interrupts, exit as soon as
2263 * possible
2264 */
8061823a
GN		 2265 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2266 kvm_run->request_interrupt_window &&
2267 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2268 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2269 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2270 return 0;
2271 }
2272
2273 return 1;
2274}
2275
851ba692 2276static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2277 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2278 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2279 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2280 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2281 /* for now: */
2282 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2283 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2284 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2285 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2286 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2287 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2288 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2289 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2290 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2291 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2292 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2293 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2294 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2295 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2296 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2297 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2298 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2299 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2300 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2301 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2302 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2303 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2304 [SVM_EXIT_SMI] = nop_on_interception,
2305 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2306 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2307 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2308 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2309 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2310 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2311 [SVM_EXIT_HLT] = halt_interception,
a7052897 2312 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2313 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2314 [SVM_EXIT_IOIO] = io_interception,
2315 [SVM_EXIT_MSR] = msr_interception,
2316 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2317 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2318 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2319 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2320 [SVM_EXIT_VMLOAD] = vmload_interception,
2321 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2322 [SVM_EXIT_STGI] = stgi_interception,
2323 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2324 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2325 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2326 [SVM_EXIT_MONITOR] = invalid_op_interception,
2327 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2328 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2329};
2330
851ba692 2331static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2332{
04d2cc77 2333 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2334 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2335 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2336
229456fc 2337 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2338
cf74a78b 2339 if (is_nested(svm)) {
410e4d57
JR		 2340 int vmexit;
2341
cf74a78b
AG		 2342 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2343 exit_code, svm->vmcb->control.exit_info_1,
2344 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
410e4d57
JR		 2345
2346 vmexit = nested_svm_exit_special(svm);
2347
2348 if (vmexit == NESTED_EXIT_CONTINUE)
2349 vmexit = nested_svm_exit_handled(svm);
2350
2351 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2352 return 1;
cf74a78b
AG		 2353 }
2354
a5c3832d
JR		 2355 svm_complete_interrupts(svm);
2356
709ddebf
JR		 2357 if (npt_enabled) {
2358 int mmu_reload = 0;
2359 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2360 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2361 mmu_reload = 1;
2362 }
2363 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2364 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2365 if (mmu_reload) {
2366 kvm_mmu_reset_context(vcpu);
2367 kvm_mmu_load(vcpu);
2368 }
2369 }
2370
04d2cc77
AK		 2371
2372 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2373 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2374 kvm_run->fail_entry.hardware_entry_failure_reason
2375 = svm->vmcb->control.exit_code;
2376 return 0;
2377 }
2378
a2fa3e9f 2379 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2380 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2381 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2382 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2383 "exit_code 0x%x\n",
b8688d51 2384 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2385 exit_code);
2386
9d8f549d 2387 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2388 || !svm_exit_handlers[exit_code]) {
6aa8b732 2389 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2390 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2391 return 0;
2392 }
2393
851ba692 2394 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2395}
2396
2397static void reload_tss(struct kvm_vcpu *vcpu)
2398{
2399 int cpu = raw_smp_processor_id();
2400
2401 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2402 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2403 load_TR_desc();
2404}
2405
e756fc62 2406static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2407{
2408 int cpu = raw_smp_processor_id();
2409
2410 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2411
a2fa3e9f 2412 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2413 /* FIXME: handle wraparound of asid_generation */
2414 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2415 new_asid(svm, svm_data);
6aa8b732
AK		 2416}
2417
95ba8273
GN		 2418static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2419{
2420 struct vcpu_svm *svm = to_svm(vcpu);
2421
2422 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2423 vcpu->arch.hflags |= HF_NMI_MASK;
2424 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2425 ++vcpu->stat.nmi_injections;
2426}
6aa8b732 2427
85f455f7 2428static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2429{
2430 struct vmcb_control_area *control;
2431
229456fc 2432 trace_kvm_inj_virq(irq);
af9ca2d7 2433
fa89a817 2434 ++svm->vcpu.stat.irq_injections;
e756fc62 2435 control = &svm->vmcb->control;
85f455f7 2436 control->int_vector = irq;
6aa8b732
AK		 2437 control->int_ctl &= ~V_INTR_PRIO_MASK;
2438 control->int_ctl |= V_IRQ_MASK |
2439 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2440}
2441
66fd3f7f 2442static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2443{
2444 struct vcpu_svm *svm = to_svm(vcpu);
2445
2af9194d 2446 BUG_ON(!(gif_set(svm)));
cf74a78b 2447
219b65dc
AG		 2448 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2449 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2450}
2451
95ba8273 2452static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2453{
2454 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2455
95ba8273 2456 if (irr == -1)
aaacfc9a
JR		 2457 return;
2458
95ba8273
GN		 2459 if (tpr >= irr)
2460 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2461}
aaacfc9a 2462
95ba8273
GN		 2463static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2464{
2465 struct vcpu_svm *svm = to_svm(vcpu);
2466 struct vmcb *vmcb = svm->vmcb;
2467 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2468 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2469}
2470
78646121
GN		 2471static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2472{
2473 struct vcpu_svm *svm = to_svm(vcpu);
2474 struct vmcb *vmcb = svm->vmcb;
2475 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2476 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2477 gif_set(svm) &&
108768de 2478 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
78646121
GN		 2479}
2480
9222be18 2481static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2482{
219b65dc
AG		 2483 struct vcpu_svm *svm = to_svm(vcpu);
2484 nsvm_printk("Trying to open IRQ window\n");
2485
2486 nested_svm_intr(svm);
2487
2488 /* In case GIF=0 we can't rely on the CPU to tell us when
2489 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2490 * The next time we get that intercept, this function will be
2491 * called again though and we'll get the vintr intercept. */
2af9194d 2492 if (gif_set(svm)) {
219b65dc
AG		 2493 svm_set_vintr(svm);
2494 svm_inject_irq(svm, 0x0);
2495 }
85f455f7
ED		 2496}
2497
95ba8273 2498static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2499{
04d2cc77 2500 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2501
44c11430
GN		 2502 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2503 == HF_NMI_MASK)
2504 return; /* IRET will cause a vm exit */
2505
2506 /* Something prevents NMI from been injected. Single step over
2507 possible problem (IRET or exception injection or interrupt
2508 shadow) */
2509 vcpu->arch.singlestep = true;
2510 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2511 update_db_intercept(vcpu);
c1150d8c
DL		 2512}
2513
cbc94022
IE		 2514static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2515{
2516 return 0;
2517}
2518
d9e368d6
AK		 2519static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2520{
2521 force_new_asid(vcpu);
2522}
2523
04d2cc77
AK		 2524static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2525{
2526}
2527
d7bf8221
JR		 2528static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2529{
2530 struct vcpu_svm *svm = to_svm(vcpu);
2531
2532 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2533 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2534 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2535 }
2536}
2537
649d6864
JR		 2538static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2539{
2540 struct vcpu_svm *svm = to_svm(vcpu);
2541 u64 cr8;
2542
649d6864
JR		 2543 cr8 = kvm_get_cr8(vcpu);
2544 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2545 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2546}
2547
9222be18
GN		 2548static void svm_complete_interrupts(struct vcpu_svm *svm)
2549{
2550 u8 vector;
2551 int type;
2552 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2553
44c11430
GN		 2554 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2555 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2556
9222be18
GN		 2557 svm->vcpu.arch.nmi_injected = false;
2558 kvm_clear_exception_queue(&svm->vcpu);
2559 kvm_clear_interrupt_queue(&svm->vcpu);
2560
2561 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2562 return;
2563
2564 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2565 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2566
2567 switch (type) {
2568 case SVM_EXITINTINFO_TYPE_NMI:
2569 svm->vcpu.arch.nmi_injected = true;
2570 break;
2571 case SVM_EXITINTINFO_TYPE_EXEPT:
2572 /* In case of software exception do not reinject an exception
2573 vector, but re-execute and instruction instead */
219b65dc
AG		 2574 if (is_nested(svm))
2575 break;
66fd3f7f 2576 if (kvm_exception_is_soft(vector))
9222be18
GN		 2577 break;
2578 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2579 u32 err = svm->vmcb->control.exit_int_info_err;
2580 kvm_queue_exception_e(&svm->vcpu, vector, err);
2581
2582 } else
2583 kvm_queue_exception(&svm->vcpu, vector);
2584 break;
2585 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2586 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2587 break;
2588 default:
2589 break;
2590 }
2591}
2592
80e31d4f
AK		 2593#ifdef CONFIG_X86_64
2594#define R "r"
2595#else
2596#define R "e"
2597#endif
2598
851ba692 2599static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2600{
a2fa3e9f 2601 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2602 u16 fs_selector;
2603 u16 gs_selector;
2604 u16 ldt_selector;
d9e368d6 2605
5fdbf976
MT		 2606 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2607 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2608 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2609
e756fc62 2610 pre_svm_run(svm);
6aa8b732 2611
649d6864
JR		 2612 sync_lapic_to_cr8(vcpu);
2613
6aa8b732 2614 save_host_msrs(vcpu);
d6e88aec
AK		 2615 fs_selector = kvm_read_fs();
2616 gs_selector = kvm_read_gs();
2617 ldt_selector = kvm_read_ldt();
cda0ffdd 2618 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2619 /* required for live migration with NPT */
2620 if (npt_enabled)
2621 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2622
04d2cc77
AK		 2623 clgi();
2624
2625 local_irq_enable();
36241b8c 2626
6aa8b732 2627 asm volatile (
80e31d4f
AK		 2628 "push %%"R"bp; \n\t"
2629 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2630 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2631 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2632 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2633 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2634 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2635#ifdef CONFIG_X86_64
fb3f0f51
RR		 2636 "mov %c[r8](%[svm]), %%r8 \n\t"
2637 "mov %c[r9](%[svm]), %%r9 \n\t"
2638 "mov %c[r10](%[svm]), %%r10 \n\t"
2639 "mov %c[r11](%[svm]), %%r11 \n\t"
2640 "mov %c[r12](%[svm]), %%r12 \n\t"
2641 "mov %c[r13](%[svm]), %%r13 \n\t"
2642 "mov %c[r14](%[svm]), %%r14 \n\t"
2643 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2644#endif
2645
6aa8b732 2646 /* Enter guest mode */
80e31d4f
AK		 2647 "push %%"R"ax \n\t"
2648 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2649 __ex(SVM_VMLOAD) "\n\t"
2650 __ex(SVM_VMRUN) "\n\t"
2651 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2652 "pop %%"R"ax \n\t"
6aa8b732
AK		 2653
2654 /* Save guest registers, load host registers */
80e31d4f
AK		 2655 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2656 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2657 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2658 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2659 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2660 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2661#ifdef CONFIG_X86_64
fb3f0f51
RR		 2662 "mov %%r8, %c[r8](%[svm]) \n\t"
2663 "mov %%r9, %c[r9](%[svm]) \n\t"
2664 "mov %%r10, %c[r10](%[svm]) \n\t"
2665 "mov %%r11, %c[r11](%[svm]) \n\t"
2666 "mov %%r12, %c[r12](%[svm]) \n\t"
2667 "mov %%r13, %c[r13](%[svm]) \n\t"
2668 "mov %%r14, %c[r14](%[svm]) \n\t"
2669 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2670#endif
80e31d4f 2671 "pop %%"R"bp"
6aa8b732 2672 :
fb3f0f51 2673 : [svm]"a"(svm),
6aa8b732 2674 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2675 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2676 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2677 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2678 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2679 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2680 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2681#ifdef CONFIG_X86_64
ad312c7c
ZX		 2682 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2683 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2684 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2685 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2686 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2687 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2688 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2689 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2690#endif
54a08c04 2691 : "cc", "memory"
80e31d4f 2692 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2693#ifdef CONFIG_X86_64
54a08c04
LV		 2694 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2695#endif
2696 );
6aa8b732 2697
ad312c7c 2698 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2699 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2700 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2701 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2702
d6e88aec
AK		 2703 kvm_load_fs(fs_selector);
2704 kvm_load_gs(gs_selector);
2705 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2706 load_host_msrs(vcpu);
2707
2708 reload_tss(vcpu);
2709
56ba47dd
AK		 2710 local_irq_disable();
2711
2712 stgi();
2713
d7bf8221
JR		 2714 sync_cr8_to_lapic(vcpu);
2715
a2fa3e9f 2716 svm->next_rip = 0;
9222be18 2717
6de4f3ad
AK		 2718 if (npt_enabled) {
2719 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2720 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2721 }
6aa8b732
AK		 2722}
2723
80e31d4f
AK		 2724#undef R
2725
6aa8b732
AK		 2726static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2727{
a2fa3e9f
GH		 2728 struct vcpu_svm *svm = to_svm(vcpu);
2729
709ddebf
JR		 2730 if (npt_enabled) {
2731 svm->vmcb->control.nested_cr3 = root;
2732 force_new_asid(vcpu);
2733 return;
2734 }
2735
a2fa3e9f 2736 svm->vmcb->save.cr3 = root;
6aa8b732 2737 force_new_asid(vcpu);
7807fa6c
AL		 2738
2739 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2740 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2741 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2742 vcpu->fpu_active = 0;
2743 }
6aa8b732
AK		 2744}
2745
6aa8b732
AK		 2746static int is_disabled(void)
2747{
6031a61c
JR		 2748 u64 vm_cr;
2749
2750 rdmsrl(MSR_VM_CR, vm_cr);
2751 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2752 return 1;
2753
6aa8b732
AK		 2754 return 0;
2755}
2756
102d8325
IM		 2757static void
2758svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2759{
2760 /*
2761 * Patch in the VMMCALL instruction:
2762 */
2763 hypercall[0] = 0x0f;
2764 hypercall[1] = 0x01;
2765 hypercall[2] = 0xd9;
102d8325
IM		 2766}
2767
002c7f7c
YS		 2768static void svm_check_processor_compat(void *rtn)
2769{
2770 *(int *)rtn = 0;
2771}
2772
774ead3a
AK		 2773static bool svm_cpu_has_accelerated_tpr(void)
2774{
2775 return false;
2776}
2777
67253af5
SY		 2778static int get_npt_level(void)
2779{
2780#ifdef CONFIG_X86_64
2781 return PT64_ROOT_LEVEL;
2782#else
2783 return PT32E_ROOT_LEVEL;
2784#endif
2785}
2786
4b12f0de 2787static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2788{
2789 return 0;
2790}
2791
229456fc
MT		 2792static const struct trace_print_flags svm_exit_reasons_str[] = {
2793 { SVM_EXIT_READ_CR0, "read_cr0" },
2794 { SVM_EXIT_READ_CR3, "read_cr3" },
2795 { SVM_EXIT_READ_CR4, "read_cr4" },
2796 { SVM_EXIT_READ_CR8, "read_cr8" },
2797 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2798 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2799 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2800 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2801 { SVM_EXIT_READ_DR0, "read_dr0" },
2802 { SVM_EXIT_READ_DR1, "read_dr1" },
2803 { SVM_EXIT_READ_DR2, "read_dr2" },
2804 { SVM_EXIT_READ_DR3, "read_dr3" },
2805 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2806 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2807 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2808 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2809 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2810 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2811 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2812 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2813 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2814 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2815 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2816 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2817 { SVM_EXIT_INTR, "interrupt" },
2818 { SVM_EXIT_NMI, "nmi" },
2819 { SVM_EXIT_SMI, "smi" },
2820 { SVM_EXIT_INIT, "init" },
2821 { SVM_EXIT_VINTR, "vintr" },
2822 { SVM_EXIT_CPUID, "cpuid" },
2823 { SVM_EXIT_INVD, "invd" },
2824 { SVM_EXIT_HLT, "hlt" },
2825 { SVM_EXIT_INVLPG, "invlpg" },
2826 { SVM_EXIT_INVLPGA, "invlpga" },
2827 { SVM_EXIT_IOIO, "io" },
2828 { SVM_EXIT_MSR, "msr" },
2829 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2830 { SVM_EXIT_SHUTDOWN, "shutdown" },
2831 { SVM_EXIT_VMRUN, "vmrun" },
2832 { SVM_EXIT_VMMCALL, "hypercall" },
2833 { SVM_EXIT_VMLOAD, "vmload" },
2834 { SVM_EXIT_VMSAVE, "vmsave" },
2835 { SVM_EXIT_STGI, "stgi" },
2836 { SVM_EXIT_CLGI, "clgi" },
2837 { SVM_EXIT_SKINIT, "skinit" },
2838 { SVM_EXIT_WBINVD, "wbinvd" },
2839 { SVM_EXIT_MONITOR, "monitor" },
2840 { SVM_EXIT_MWAIT, "mwait" },
2841 { SVM_EXIT_NPF, "npf" },
2842 { -1, NULL }
2843};
2844
344f414f
JR		 2845static bool svm_gb_page_enable(void)
2846{
2847 return true;
2848}
2849
cbdd1bea 2850static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2851 .cpu_has_kvm_support = has_svm,
2852 .disabled_by_bios = is_disabled,
2853 .hardware_setup = svm_hardware_setup,
2854 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2855 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2856 .hardware_enable = svm_hardware_enable,
2857 .hardware_disable = svm_hardware_disable,
774ead3a 2858 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2859
2860 .vcpu_create = svm_create_vcpu,
2861 .vcpu_free = svm_free_vcpu,
04d2cc77 2862 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2863
04d2cc77 2864 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2865 .vcpu_load = svm_vcpu_load,
2866 .vcpu_put = svm_vcpu_put,
2867
2868 .set_guest_debug = svm_guest_debug,
2869 .get_msr = svm_get_msr,
2870 .set_msr = svm_set_msr,
2871 .get_segment_base = svm_get_segment_base,
2872 .get_segment = svm_get_segment,
2873 .set_segment = svm_set_segment,
2e4d2653 2874 .get_cpl = svm_get_cpl,
1747fb71 2875 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2876 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2877 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2878 .set_cr3 = svm_set_cr3,
2879 .set_cr4 = svm_set_cr4,
2880 .set_efer = svm_set_efer,
2881 .get_idt = svm_get_idt,
2882 .set_idt = svm_set_idt,
2883 .get_gdt = svm_get_gdt,
2884 .set_gdt = svm_set_gdt,
2885 .get_dr = svm_get_dr,
2886 .set_dr = svm_set_dr,
6de4f3ad 2887 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2888 .get_rflags = svm_get_rflags,
2889 .set_rflags = svm_set_rflags,
2890
6aa8b732 2891 .tlb_flush = svm_flush_tlb,
6aa8b732 2892
6aa8b732 2893 .run = svm_vcpu_run,
04d2cc77 2894 .handle_exit = handle_exit,
6aa8b732 2895 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2896 .set_interrupt_shadow = svm_set_interrupt_shadow,
2897 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2898 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2899 .set_irq = svm_set_irq,
95ba8273 2900 .set_nmi = svm_inject_nmi,
298101da 2901 .queue_exception = svm_queue_exception,
78646121 2902 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2903 .nmi_allowed = svm_nmi_allowed,
2904 .enable_nmi_window = enable_nmi_window,
2905 .enable_irq_window = enable_irq_window,
2906 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2907
2908 .set_tss_addr = svm_set_tss_addr,
67253af5 2909 .get_tdp_level = get_npt_level,
4b12f0de 2910 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2911
2912 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2913 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2914};
2915
2916static int __init svm_init(void)
2917{
cb498ea2 2918 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2919 THIS_MODULE);
6aa8b732
AK		 2920}
2921
2922static void __exit svm_exit(void)
2923{
cb498ea2 2924 kvm_exit();
6aa8b732
AK		 2925}
2926
2927module_init(svm_init)
2928module_exit(svm_exit)
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