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KVM: Remove irq_pending bitmap
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
e495606d 18#include "kvm_svm.h"
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f
EH		 32#include <asm/virtext.h>
33
4ecac3fd
AK		 34#define __ex(x) __kvm_handle_fault_on_reboot(x)
35
6aa8b732
AK		 36MODULE_AUTHOR("Qumranet");
37MODULE_LICENSE("GPL");
38
39#define IOPM_ALLOC_ORDER 2
40#define MSRPM_ALLOC_ORDER 1
41
6aa8b732
AK		 42#define SEG_TYPE_LDT 2
43#define SEG_TYPE_BUSY_TSS16 3
44
80b7706e
JR		 45#define SVM_FEATURE_NPT (1 << 0)
46#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 47#define SVM_FEATURE_SVML (1 << 2)
80b7706e 48
24e09cbf
JR		 49#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50
c0725420
AG		 51/* Turn on to get debugging output*/
52/* #define NESTED_DEBUG */
53
54#ifdef NESTED_DEBUG
55#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56#else
57#define nsvm_printk(fmt, args...) do {} while(0)
58#endif
59
709ddebf
JR		 60/* enable NPT for AMD64 and X86 with PAE */
61#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
62static bool npt_enabled = true;
63#else
e3da3acd 64static bool npt_enabled = false;
709ddebf 65#endif
6c7dac72
JR		 66static int npt = 1;
67
68module_param(npt, int, S_IRUGO);
e3da3acd 69
236de055
AG		 70static int nested = 0;
71module_param(nested, int, S_IRUGO);
72
44874f84 73static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 74
cf74a78b
AG		 75static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
76static int nested_svm_vmexit(struct vcpu_svm *svm);
77static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
78 void *arg2, void *opaque);
79static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
80 bool has_error_code, u32 error_code);
81
a2fa3e9f
GH		 82static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
83{
fb3f0f51 84 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 85}
86
3d6368ef
AG		 87static inline bool is_nested(struct vcpu_svm *svm)
88{
89 return svm->nested_vmcb;
90}
91
4866d5e3 92static unsigned long iopm_base;
6aa8b732
AK		 93
94struct kvm_ldttss_desc {
95 u16 limit0;
96 u16 base0;
97 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
98 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
99 u32 base3;
100 u32 zero1;
101} __attribute__((packed));
102
103struct svm_cpu_data {
104 int cpu;
105
5008fdf5
AK		 106 u64 asid_generation;
107 u32 max_asid;
108 u32 next_asid;
6aa8b732
AK		 109 struct kvm_ldttss_desc *tss_desc;
110
111 struct page *save_area;
112};
113
114static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 115static uint32_t svm_features;
6aa8b732
AK		 116
117struct svm_init_data {
118 int cpu;
119 int r;
120};
121
122static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
123
9d8f549d 124#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 125#define MSRS_RANGE_SIZE 2048
126#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
127
128#define MAX_INST_SIZE 15
129
80b7706e
JR		 130static inline u32 svm_has(u32 feat)
131{
132 return svm_features & feat;
133}
134
6aa8b732
AK		 135static inline void clgi(void)
136{
4ecac3fd 137 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 138}
139
140static inline void stgi(void)
141{
4ecac3fd 142 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 143}
144
145static inline void invlpga(unsigned long addr, u32 asid)
146{
4ecac3fd 147 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 148}
149
150static inline unsigned long kvm_read_cr2(void)
151{
152 unsigned long cr2;
153
154 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
155 return cr2;
156}
157
158static inline void kvm_write_cr2(unsigned long val)
159{
160 asm volatile ("mov %0, %%cr2" :: "r" (val));
161}
162
6aa8b732
AK		 163static inline void force_new_asid(struct kvm_vcpu *vcpu)
164{
a2fa3e9f 165 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 166}
167
168static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
169{
170 force_new_asid(vcpu);
171}
172
173static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
174{
709ddebf 175 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 176 efer &= ~EFER_LME;
6aa8b732 177
9962d032 178 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 179 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 180}
181
298101da
AK		 182static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
183 bool has_error_code, u32 error_code)
184{
185 struct vcpu_svm *svm = to_svm(vcpu);
186
cf74a78b
AG		 187 /* If we are within a nested VM we'd better #VMEXIT and let the
188 guest handle the exception */
189 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
190 return;
191
298101da
AK		 192 svm->vmcb->control.event_inj = nr
193 | SVM_EVTINJ_VALID
194 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
195 | SVM_EVTINJ_TYPE_EXEPT;
196 svm->vmcb->control.event_inj_err = error_code;
197}
198
6aa8b732
AK		 199static int is_external_interrupt(u32 info)
200{
201 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
202 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
203}
204
2809f5d2
GC		 205static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
206{
207 struct vcpu_svm *svm = to_svm(vcpu);
208 u32 ret = 0;
209
210 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
211 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
212 return ret & mask;
213}
214
215static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
216{
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 if (mask == 0)
220 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
221 else
222 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
223
224}
225
6aa8b732
AK		 226static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
227{
a2fa3e9f
GH		 228 struct vcpu_svm *svm = to_svm(vcpu);
229
230 if (!svm->next_rip) {
b8688d51 231 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 232 return;
233 }
5fdbf976
MT		 234 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
235 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
236 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 237
5fdbf976 238 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 239 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 240}
241
242static int has_svm(void)
243{
63d1142f 244 const char *msg;
6aa8b732 245
63d1142f 246 if (!cpu_has_svm(&msg)) {
ff81ff10 247 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 248 return 0;
249 }
250
6aa8b732
AK		 251 return 1;
252}
253
254static void svm_hardware_disable(void *garbage)
255{
2c8dceeb 256 cpu_svm_disable();
6aa8b732
AK		 257}
258
259static void svm_hardware_enable(void *garbage)
260{
261
262 struct svm_cpu_data *svm_data;
263 uint64_t efer;
6aa8b732 264 struct desc_ptr gdt_descr;
6aa8b732
AK		 265 struct desc_struct *gdt;
266 int me = raw_smp_processor_id();
267
268 if (!has_svm()) {
269 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
270 return;
271 }
272 svm_data = per_cpu(svm_data, me);
273
274 if (!svm_data) {
275 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
276 me);
277 return;
278 }
279
280 svm_data->asid_generation = 1;
281 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
282 svm_data->next_asid = svm_data->max_asid + 1;
283
d77c26fc 284 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 285 gdt = (struct desc_struct *)gdt_descr.address;
286 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
287
288 rdmsrl(MSR_EFER, efer);
9962d032 289 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 290
291 wrmsrl(MSR_VM_HSAVE_PA,
292 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
293}
294
0da1db75
JR		 295static void svm_cpu_uninit(int cpu)
296{
297 struct svm_cpu_data *svm_data
298 = per_cpu(svm_data, raw_smp_processor_id());
299
300 if (!svm_data)
301 return;
302
303 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
304 __free_page(svm_data->save_area);
305 kfree(svm_data);
306}
307
6aa8b732
AK		 308static int svm_cpu_init(int cpu)
309{
310 struct svm_cpu_data *svm_data;
311 int r;
312
313 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
314 if (!svm_data)
315 return -ENOMEM;
316 svm_data->cpu = cpu;
317 svm_data->save_area = alloc_page(GFP_KERNEL);
318 r = -ENOMEM;
319 if (!svm_data->save_area)
320 goto err_1;
321
322 per_cpu(svm_data, cpu) = svm_data;
323
324 return 0;
325
326err_1:
327 kfree(svm_data);
328 return r;
329
330}
331
bfc733a7
RR		 332static void set_msr_interception(u32 *msrpm, unsigned msr,
333 int read, int write)
6aa8b732
AK		 334{
335 int i;
336
337 for (i = 0; i < NUM_MSR_MAPS; i++) {
338 if (msr >= msrpm_ranges[i] &&
339 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
340 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
341 msrpm_ranges[i]) * 2;
342
343 u32 *base = msrpm + (msr_offset / 32);
344 u32 msr_shift = msr_offset % 32;
345 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
346 *base = (*base & ~(0x3 << msr_shift)) |
347 (mask << msr_shift);
bfc733a7 348 return;
6aa8b732
AK		 349 }
350 }
bfc733a7 351 BUG();
6aa8b732
AK		 352}
353
f65c229c
JR		 354static void svm_vcpu_init_msrpm(u32 *msrpm)
355{
356 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
357
358#ifdef CONFIG_X86_64
359 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
360 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
361 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
362 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
363 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
364 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
365#endif
366 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
367 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
368 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
369 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
370}
371
24e09cbf
JR		 372static void svm_enable_lbrv(struct vcpu_svm *svm)
373{
374 u32 *msrpm = svm->msrpm;
375
376 svm->vmcb->control.lbr_ctl = 1;
377 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
378 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
379 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
380 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
381}
382
383static void svm_disable_lbrv(struct vcpu_svm *svm)
384{
385 u32 *msrpm = svm->msrpm;
386
387 svm->vmcb->control.lbr_ctl = 0;
388 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
389 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
390 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
391 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
392}
393
6aa8b732
AK		 394static __init int svm_hardware_setup(void)
395{
396 int cpu;
397 struct page *iopm_pages;
f65c229c 398 void *iopm_va;
6aa8b732
AK		 399 int r;
400
6aa8b732
AK		 401 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
402
403 if (!iopm_pages)
404 return -ENOMEM;
c8681339
AL		 405
406 iopm_va = page_address(iopm_pages);
407 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 408 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
409
50a37eb4
JR		 410 if (boot_cpu_has(X86_FEATURE_NX))
411 kvm_enable_efer_bits(EFER_NX);
412
1b2fd70c
AG		 413 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
414 kvm_enable_efer_bits(EFER_FFXSR);
415
236de055
AG		 416 if (nested) {
417 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
418 kvm_enable_efer_bits(EFER_SVME);
419 }
420
6aa8b732
AK		 421 for_each_online_cpu(cpu) {
422 r = svm_cpu_init(cpu);
423 if (r)
f65c229c 424 goto err;
6aa8b732 425 }
33bd6a0b
JR		 426
427 svm_features = cpuid_edx(SVM_CPUID_FUNC);
428
e3da3acd
JR		 429 if (!svm_has(SVM_FEATURE_NPT))
430 npt_enabled = false;
431
6c7dac72
JR		 432 if (npt_enabled && !npt) {
433 printk(KERN_INFO "kvm: Nested Paging disabled\n");
434 npt_enabled = false;
435 }
436
18552672 437 if (npt_enabled) {
e3da3acd 438 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 439 kvm_enable_tdp();
5f4cb662
JR		 440 } else
441 kvm_disable_tdp();
e3da3acd 442
6aa8b732
AK		 443 return 0;
444
f65c229c 445err:
6aa8b732
AK		 446 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
447 iopm_base = 0;
448 return r;
449}
450
451static __exit void svm_hardware_unsetup(void)
452{
0da1db75
JR		 453 int cpu;
454
455 for_each_online_cpu(cpu)
456 svm_cpu_uninit(cpu);
457
6aa8b732 458 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 459 iopm_base = 0;
6aa8b732
AK		 460}
461
462static void init_seg(struct vmcb_seg *seg)
463{
464 seg->selector = 0;
465 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
466 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
467 seg->limit = 0xffff;
468 seg->base = 0;
469}
470
471static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
472{
473 seg->selector = 0;
474 seg->attrib = SVM_SELECTOR_P_MASK | type;
475 seg->limit = 0xffff;
476 seg->base = 0;
477}
478
e6101a96 479static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 480{
e6101a96
JR		 481 struct vmcb_control_area *control = &svm->vmcb->control;
482 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 483
484 control->intercept_cr_read = INTERCEPT_CR0_MASK |
485 INTERCEPT_CR3_MASK |
649d6864 486 INTERCEPT_CR4_MASK;
6aa8b732
AK		 487
488 control->intercept_cr_write = INTERCEPT_CR0_MASK |
489 INTERCEPT_CR3_MASK |
80a8119c
AK		 490 INTERCEPT_CR4_MASK |
491 INTERCEPT_CR8_MASK;
6aa8b732
AK		 492
493 control->intercept_dr_read = INTERCEPT_DR0_MASK |
494 INTERCEPT_DR1_MASK |
495 INTERCEPT_DR2_MASK |
496 INTERCEPT_DR3_MASK;
497
498 control->intercept_dr_write = INTERCEPT_DR0_MASK |
499 INTERCEPT_DR1_MASK |
500 INTERCEPT_DR2_MASK |
501 INTERCEPT_DR3_MASK |
502 INTERCEPT_DR5_MASK |
503 INTERCEPT_DR7_MASK;
504
7aa81cc0 505 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 506 (1 << UD_VECTOR) |
507 (1 << MC_VECTOR);
6aa8b732
AK		 508
509
510 control->intercept = (1ULL << INTERCEPT_INTR) |
511 (1ULL << INTERCEPT_NMI) |
0152527b 512 (1ULL << INTERCEPT_SMI) |
6aa8b732 513 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 514 (1ULL << INTERCEPT_INVD) |
6aa8b732 515 (1ULL << INTERCEPT_HLT) |
a7052897 516 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 517 (1ULL << INTERCEPT_INVLPGA) |
518 (1ULL << INTERCEPT_IOIO_PROT) |
519 (1ULL << INTERCEPT_MSR_PROT) |
520 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 521 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 522 (1ULL << INTERCEPT_VMRUN) |
523 (1ULL << INTERCEPT_VMMCALL) |
524 (1ULL << INTERCEPT_VMLOAD) |
525 (1ULL << INTERCEPT_VMSAVE) |
526 (1ULL << INTERCEPT_STGI) |
527 (1ULL << INTERCEPT_CLGI) |
916ce236 528 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 529 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 530 (1ULL << INTERCEPT_MONITOR) |
531 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 532
533 control->iopm_base_pa = iopm_base;
f65c229c 534 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 535 control->tsc_offset = 0;
6aa8b732
AK		 536 control->int_ctl = V_INTR_MASKING_MASK;
537
538 init_seg(&save->es);
539 init_seg(&save->ss);
540 init_seg(&save->ds);
541 init_seg(&save->fs);
542 init_seg(&save->gs);
543
544 save->cs.selector = 0xf000;
545 /* Executable/Readable Code Segment */
546 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
547 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
548 save->cs.limit = 0xffff;
d92899a0
AK		 549 /*
550 * cs.base should really be 0xffff0000, but vmx can't handle that, so
551 * be consistent with it.
552 *
553 * Replace when we have real mode working for vmx.
554 */
555 save->cs.base = 0xf0000;
6aa8b732
AK		 556
557 save->gdtr.limit = 0xffff;
558 save->idtr.limit = 0xffff;
559
560 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
561 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
562
9962d032 563 save->efer = EFER_SVME;
d77c26fc 564 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 565 save->dr7 = 0x400;
566 save->rflags = 2;
567 save->rip = 0x0000fff0;
5fdbf976 568 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 569
570 /*
571 * cr0 val on cpu init should be 0x60000010, we enable cpu
572 * cache by default. the orderly way is to enable cache in bios.
573 */
707d92fa 574 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 575 save->cr4 = X86_CR4_PAE;
6aa8b732 576 /* rdx = ?? */
709ddebf
JR		 577
578 if (npt_enabled) {
579 /* Setup VMCB for Nested Paging */
580 control->nested_ctl = 1;
a7052897
MT		 581 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
582 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 583 control->intercept_exceptions &= ~(1 << PF_VECTOR);
584 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
585 INTERCEPT_CR3_MASK);
586 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
587 INTERCEPT_CR3_MASK);
588 save->g_pat = 0x0007040600070406ULL;
589 /* enable caching because the QEMU Bios doesn't enable it */
590 save->cr0 = X86_CR0_ET;
591 save->cr3 = 0;
592 save->cr4 = 0;
593 }
a79d2f18 594 force_new_asid(&svm->vcpu);
1371d904 595
3d6368ef 596 svm->nested_vmcb = 0;
1371d904 597 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 598}
599
e00c8cf2 600static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 601{
602 struct vcpu_svm *svm = to_svm(vcpu);
603
e6101a96 604 init_vmcb(svm);
70433389
AK		 605
606 if (vcpu->vcpu_id != 0) {
5fdbf976 607 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 608 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
609 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 610 }
5fdbf976
MT		 611 vcpu->arch.regs_avail = ~0;
612 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 613
614 return 0;
04d2cc77
AK		 615}
616
fb3f0f51 617static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 618{
a2fa3e9f 619 struct vcpu_svm *svm;
6aa8b732 620 struct page *page;
f65c229c 621 struct page *msrpm_pages;
b286d5d8 622 struct page *hsave_page;
3d6368ef 623 struct page *nested_msrpm_pages;
fb3f0f51 624 int err;
6aa8b732 625
c16f862d 626 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 627 if (!svm) {
628 err = -ENOMEM;
629 goto out;
630 }
631
632 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
633 if (err)
634 goto free_svm;
635
6aa8b732 636 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 637 if (!page) {
638 err = -ENOMEM;
639 goto uninit;
640 }
6aa8b732 641
f65c229c
JR		 642 err = -ENOMEM;
643 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
644 if (!msrpm_pages)
645 goto uninit;
3d6368ef
AG		 646
647 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
648 if (!nested_msrpm_pages)
649 goto uninit;
650
f65c229c
JR		 651 svm->msrpm = page_address(msrpm_pages);
652 svm_vcpu_init_msrpm(svm->msrpm);
653
b286d5d8
AG		 654 hsave_page = alloc_page(GFP_KERNEL);
655 if (!hsave_page)
656 goto uninit;
657 svm->hsave = page_address(hsave_page);
658
3d6368ef
AG		 659 svm->nested_msrpm = page_address(nested_msrpm_pages);
660
a2fa3e9f
GH		 661 svm->vmcb = page_address(page);
662 clear_page(svm->vmcb);
663 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
664 svm->asid_generation = 0;
e6101a96 665 init_vmcb(svm);
a2fa3e9f 666
fb3f0f51
RR		 667 fx_init(&svm->vcpu);
668 svm->vcpu.fpu_active = 1;
ad312c7c 669 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 670 if (svm->vcpu.vcpu_id == 0)
ad312c7c 671 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 672
fb3f0f51 673 return &svm->vcpu;
36241b8c 674
fb3f0f51
RR		 675uninit:
676 kvm_vcpu_uninit(&svm->vcpu);
677free_svm:
a4770347 678 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 679out:
680 return ERR_PTR(err);
6aa8b732
AK		 681}
682
683static void svm_free_vcpu(struct kvm_vcpu *vcpu)
684{
a2fa3e9f
GH		 685 struct vcpu_svm *svm = to_svm(vcpu);
686
fb3f0f51 687 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 688 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 689 __free_page(virt_to_page(svm->hsave));
3d6368ef 690 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 691 kvm_vcpu_uninit(vcpu);
a4770347 692 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 693}
694
15ad7146 695static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 696{
a2fa3e9f 697 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 698 int i;
0cc5064d 699
0cc5064d
AK		 700 if (unlikely(cpu != vcpu->cpu)) {
701 u64 tsc_this, delta;
702
703 /*
704 * Make sure that the guest sees a monotonically
705 * increasing TSC.
706 */
707 rdtscll(tsc_this);
ad312c7c 708 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 709 svm->vmcb->control.tsc_offset += delta;
0cc5064d 710 vcpu->cpu = cpu;
2f599714 711 kvm_migrate_timers(vcpu);
0cc5064d 712 }
94dfbdb3
AL		 713
714 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 715 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 716}
717
718static void svm_vcpu_put(struct kvm_vcpu *vcpu)
719{
a2fa3e9f 720 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 721 int i;
722
e1beb1d3 723 ++vcpu->stat.host_state_reload;
94dfbdb3 724 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 725 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 726
ad312c7c 727 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 728}
729
6aa8b732
AK		 730static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
731{
a2fa3e9f 732 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 733}
734
735static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
736{
a2fa3e9f 737 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 738}
739
f0b85051
AG		 740static void svm_set_vintr(struct vcpu_svm *svm)
741{
742 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
743}
744
745static void svm_clear_vintr(struct vcpu_svm *svm)
746{
747 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
748}
749
6aa8b732
AK		 750static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
751{
a2fa3e9f 752 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 753
754 switch (seg) {
755 case VCPU_SREG_CS: return &save->cs;
756 case VCPU_SREG_DS: return &save->ds;
757 case VCPU_SREG_ES: return &save->es;
758 case VCPU_SREG_FS: return &save->fs;
759 case VCPU_SREG_GS: return &save->gs;
760 case VCPU_SREG_SS: return &save->ss;
761 case VCPU_SREG_TR: return &save->tr;
762 case VCPU_SREG_LDTR: return &save->ldtr;
763 }
764 BUG();
8b6d44c7 765 return NULL;
6aa8b732
AK		 766}
767
768static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
769{
770 struct vmcb_seg *s = svm_seg(vcpu, seg);
771
772 return s->base;
773}
774
775static void svm_get_segment(struct kvm_vcpu *vcpu,
776 struct kvm_segment *var, int seg)
777{
778 struct vmcb_seg *s = svm_seg(vcpu, seg);
779
780 var->base = s->base;
781 var->limit = s->limit;
782 var->selector = s->selector;
783 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
784 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
785 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
786 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
787 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
788 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
789 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
790 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 791
19bca6ab
AP		 792 /* AMD's VMCB does not have an explicit unusable field, so emulate it
793 * for cross vendor migration purposes by "not present"
794 */
795 var->unusable = !var->present || (var->type == 0);
796
1fbdc7a5
AP		 797 switch (seg) {
798 case VCPU_SREG_CS:
799 /*
800 * SVM always stores 0 for the 'G' bit in the CS selector in
801 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
802 * Intel's VMENTRY has a check on the 'G' bit.
803 */
25022acc 804 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 805 break;
806 case VCPU_SREG_TR:
807 /*
808 * Work around a bug where the busy flag in the tr selector
809 * isn't exposed
810 */
c0d09828 811 var->type |= 0x2;
1fbdc7a5
AP		 812 break;
813 case VCPU_SREG_DS:
814 case VCPU_SREG_ES:
815 case VCPU_SREG_FS:
816 case VCPU_SREG_GS:
817 /*
818 * The accessed bit must always be set in the segment
819 * descriptor cache, although it can be cleared in the
820 * descriptor, the cached bit always remains at 1. Since
821 * Intel has a check on this, set it here to support
822 * cross-vendor migration.
823 */
824 if (!var->unusable)
825 var->type |= 0x1;
826 break;
b586eb02
AP		 827 case VCPU_SREG_SS:
828 /* On AMD CPUs sometimes the DB bit in the segment
829 * descriptor is left as 1, although the whole segment has
830 * been made unusable. Clear it here to pass an Intel VMX
831 * entry check when cross vendor migrating.
832 */
833 if (var->unusable)
834 var->db = 0;
835 break;
1fbdc7a5 836 }
6aa8b732
AK		 837}
838
2e4d2653
IE		 839static int svm_get_cpl(struct kvm_vcpu *vcpu)
840{
841 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
842
843 return save->cpl;
844}
845
6aa8b732
AK		 846static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
847{
a2fa3e9f
GH		 848 struct vcpu_svm *svm = to_svm(vcpu);
849
850 dt->limit = svm->vmcb->save.idtr.limit;
851 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 852}
853
854static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
855{
a2fa3e9f
GH		 856 struct vcpu_svm *svm = to_svm(vcpu);
857
858 svm->vmcb->save.idtr.limit = dt->limit;
859 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 860}
861
862static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
863{
a2fa3e9f
GH		 864 struct vcpu_svm *svm = to_svm(vcpu);
865
866 dt->limit = svm->vmcb->save.gdtr.limit;
867 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 868}
869
870static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
871{
a2fa3e9f
GH		 872 struct vcpu_svm *svm = to_svm(vcpu);
873
874 svm->vmcb->save.gdtr.limit = dt->limit;
875 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 876}
877
25c4c276 878static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 879{
880}
881
6aa8b732
AK		 882static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
883{
a2fa3e9f
GH		 884 struct vcpu_svm *svm = to_svm(vcpu);
885
05b3e0c2 886#ifdef CONFIG_X86_64
ad312c7c 887 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 888 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 889 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 890 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 891 }
892
d77c26fc 893 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 894 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 895 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 896 }
897 }
898#endif
709ddebf
JR		 899 if (npt_enabled)
900 goto set;
901
ad312c7c 902 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 903 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 904 vcpu->fpu_active = 1;
905 }
906
ad312c7c 907 vcpu->arch.cr0 = cr0;
707d92fa 908 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 909 if (!vcpu->fpu_active) {
910 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 911 cr0 |= X86_CR0_TS;
6b390b63 912 }
709ddebf
JR		 913set:
914 /*
915 * re-enable caching here because the QEMU bios
916 * does not do it - this results in some delay at
917 * reboot
918 */
919 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 920 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 921}
922
923static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
924{
6394b649 925 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 926 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
927
928 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
929 force_new_asid(vcpu);
6394b649 930
ec077263
JR		 931 vcpu->arch.cr4 = cr4;
932 if (!npt_enabled)
933 cr4 |= X86_CR4_PAE;
6394b649 934 cr4 |= host_cr4_mce;
ec077263 935 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 936}
937
938static void svm_set_segment(struct kvm_vcpu *vcpu,
939 struct kvm_segment *var, int seg)
940{
a2fa3e9f 941 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 942 struct vmcb_seg *s = svm_seg(vcpu, seg);
943
944 s->base = var->base;
945 s->limit = var->limit;
946 s->selector = var->selector;
947 if (var->unusable)
948 s->attrib = 0;
949 else {
950 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
951 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
952 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
953 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
954 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
955 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
956 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
957 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
958 }
959 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 960 svm->vmcb->save.cpl
961 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 962 >> SVM_SELECTOR_DPL_SHIFT) & 3;
963
964}
965
d0bfb940 966static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 967{
d0bfb940
JK		 968 int old_debug = vcpu->guest_debug;
969 struct vcpu_svm *svm = to_svm(vcpu);
970
971 vcpu->guest_debug = dbg->control;
972
973 svm->vmcb->control.intercept_exceptions &=
974 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
975 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
976 if (vcpu->guest_debug &
977 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
978 svm->vmcb->control.intercept_exceptions |=
979 1 << DB_VECTOR;
980 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
981 svm->vmcb->control.intercept_exceptions |=
982 1 << BP_VECTOR;
983 } else
984 vcpu->guest_debug = 0;
985
ae675ef0
JK		 986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
987 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
988 else
989 svm->vmcb->save.dr7 = vcpu->arch.dr7;
990
d0bfb940
JK		 991 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
992 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
993 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
994 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
995
996 return 0;
6aa8b732
AK		 997}
998
999static void load_host_msrs(struct kvm_vcpu *vcpu)
1000{
94dfbdb3 1001#ifdef CONFIG_X86_64
a2fa3e9f 1002 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1003#endif
6aa8b732
AK		 1004}
1005
1006static void save_host_msrs(struct kvm_vcpu *vcpu)
1007{
94dfbdb3 1008#ifdef CONFIG_X86_64
a2fa3e9f 1009 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1010#endif
6aa8b732
AK		 1011}
1012
e756fc62 1013static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1014{
1015 if (svm_data->next_asid > svm_data->max_asid) {
1016 ++svm_data->asid_generation;
1017 svm_data->next_asid = 1;
a2fa3e9f 1018 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1019 }
1020
e756fc62 1021 svm->vcpu.cpu = svm_data->cpu;
a2fa3e9f
GH		 1022 svm->asid_generation = svm_data->asid_generation;
1023 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1024}
1025
6aa8b732
AK		 1026static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1027{
42dbaa5a
JK		 1028 struct vcpu_svm *svm = to_svm(vcpu);
1029 unsigned long val;
1030
1031 switch (dr) {
1032 case 0 ... 3:
1033 val = vcpu->arch.db[dr];
1034 break;
1035 case 6:
1036 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1037 val = vcpu->arch.dr6;
1038 else
1039 val = svm->vmcb->save.dr6;
1040 break;
1041 case 7:
1042 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1043 val = vcpu->arch.dr7;
1044 else
1045 val = svm->vmcb->save.dr7;
1046 break;
1047 default:
1048 val = 0;
1049 }
1050
af9ca2d7
JR		 1051 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1052 return val;
6aa8b732
AK		 1053}
1054
1055static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1056 int *exception)
1057{
a2fa3e9f
GH		 1058 struct vcpu_svm *svm = to_svm(vcpu);
1059
42dbaa5a 1060 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1061
42dbaa5a 1062 *exception = 0;
6aa8b732
AK		 1063
1064 switch (dr) {
1065 case 0 ... 3:
42dbaa5a
JK		 1066 vcpu->arch.db[dr] = value;
1067 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1068 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1069 return;
1070 case 4 ... 5:
42dbaa5a 1071 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1072 *exception = UD_VECTOR;
42dbaa5a
JK		 1073 return;
1074 case 6:
1075 if (value & 0xffffffff00000000ULL) {
1076 *exception = GP_VECTOR;
6aa8b732
AK		 1077 return;
1078 }
42dbaa5a
JK		 1079 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1080 return;
1081 case 7:
1082 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1083 *exception = GP_VECTOR;
1084 return;
1085 }
42dbaa5a
JK		 1086 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1087 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1088 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1089 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1090 }
6aa8b732 1091 return;
6aa8b732 1092 default:
42dbaa5a 1093 /* FIXME: Possible case? */
6aa8b732 1094 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1095 __func__, dr);
6aa8b732
AK		 1096 *exception = UD_VECTOR;
1097 return;
1098 }
1099}
1100
e756fc62 1101static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1102{
6aa8b732
AK		 1103 u64 fault_address;
1104 u32 error_code;
6aa8b732 1105
a2fa3e9f
GH		 1106 fault_address = svm->vmcb->control.exit_info_2;
1107 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1108
1109 if (!npt_enabled)
1110 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1111 (u32)fault_address, (u32)(fault_address >> 32),
1112 handler);
d2ebb410
JR		 1113 else
1114 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1115 (u32)fault_address, (u32)(fault_address >> 32),
1116 handler);
44874f84
JR		 1117 /*
1118 * FIXME: Tis shouldn't be necessary here, but there is a flush
1119 * missing in the MMU code. Until we find this bug, flush the
1120 * complete TLB here on an NPF
1121 */
1122 if (npt_enabled)
1123 svm_flush_tlb(&svm->vcpu);
9222be18 1124 else {
3298b75c 1125 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1126 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1127 }
3067714c 1128 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1129}
1130
d0bfb940
JK		 1131static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1132{
1133 if (!(svm->vcpu.guest_debug &
1134 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1135 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1136 return 1;
1137 }
1138 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1139 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1140 kvm_run->debug.arch.exception = DB_VECTOR;
1141 return 0;
1142}
1143
1144static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1145{
1146 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1147 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1148 kvm_run->debug.arch.exception = BP_VECTOR;
1149 return 0;
1150}
1151
7aa81cc0
AL		 1152static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1153{
1154 int er;
1155
571008da 1156 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1157 if (er != EMULATE_DONE)
7ee5d940 1158 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1159 return 1;
1160}
1161
e756fc62 1162static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1163{
a2fa3e9f 1164 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1165 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1166 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1167 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1168
1169 return 1;
7807fa6c
AL		 1170}
1171
53371b50
JR		 1172static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1173{
1174 /*
1175 * On an #MC intercept the MCE handler is not called automatically in
1176 * the host. So do it by hand here.
1177 */
1178 asm volatile (
1179 "int $0x12\n");
1180 /* not sure if we ever come back to this point */
1181
1182 return 1;
1183}
1184
e756fc62 1185static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1186{
1187 /*
1188 * VMCB is undefined after a SHUTDOWN intercept
1189 * so reinitialize it.
1190 */
a2fa3e9f 1191 clear_page(svm->vmcb);
e6101a96 1192 init_vmcb(svm);
46fe4ddd
JR		 1193
1194 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1195 return 0;
1196}
1197
e756fc62 1198static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1199{
d77c26fc 1200 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1201 int size, in, string;
039576c0 1202 unsigned port;
6aa8b732 1203
e756fc62 1204 ++svm->vcpu.stat.io_exits;
6aa8b732 1205
a2fa3e9f 1206 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1207
e70669ab
LV		 1208 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1209
1210 if (string) {
3427318f
LV		 1211 if (emulate_instruction(&svm->vcpu,
1212 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1213 return 0;
1214 return 1;
1215 }
1216
039576c0
AK		 1217 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1218 port = io_info >> 16;
1219 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1220
e93f36bc 1221 skip_emulated_instruction(&svm->vcpu);
3090dd73 1222 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1223}
1224
c47f098d
JR		 1225static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1226{
af9ca2d7 1227 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1228 return 1;
1229}
1230
a0698055
JR		 1231static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1232{
1233 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1234 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1235 return 1;
1236}
1237
e756fc62 1238static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1239{
1240 return 1;
1241}
1242
e756fc62 1243static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1244{
5fdbf976 1245 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1246 skip_emulated_instruction(&svm->vcpu);
1247 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1248}
1249
e756fc62 1250static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1251{
5fdbf976 1252 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1253 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1254 kvm_emulate_hypercall(&svm->vcpu);
1255 return 1;
02e235bc
AK		 1256}
1257
c0725420
AG		 1258static int nested_svm_check_permissions(struct vcpu_svm *svm)
1259{
1260 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1261 || !is_paging(&svm->vcpu)) {
1262 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1263 return 1;
1264 }
1265
1266 if (svm->vmcb->save.cpl) {
1267 kvm_inject_gp(&svm->vcpu, 0);
1268 return 1;
1269 }
1270
1271 return 0;
1272}
1273
cf74a78b
AG		 1274static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1275 bool has_error_code, u32 error_code)
1276{
1277 if (is_nested(svm)) {
1278 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1279 svm->vmcb->control.exit_code_hi = 0;
1280 svm->vmcb->control.exit_info_1 = error_code;
1281 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1282 if (nested_svm_exit_handled(svm, false)) {
1283 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1284
1285 nested_svm_vmexit(svm);
1286 return 1;
1287 }
1288 }
1289
1290 return 0;
1291}
1292
1293static inline int nested_svm_intr(struct vcpu_svm *svm)
1294{
1295 if (is_nested(svm)) {
1296 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1297 return 0;
1298
1299 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1300 return 0;
1301
1302 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1303
1304 if (nested_svm_exit_handled(svm, false)) {
1305 nsvm_printk("VMexit -> INTR\n");
1306 nested_svm_vmexit(svm);
1307 return 1;
1308 }
1309 }
1310
1311 return 0;
1312}
1313
c0725420
AG		 1314static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1315{
1316 struct page *page;
1317
1318 down_read(&current->mm->mmap_sem);
1319 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1320 up_read(&current->mm->mmap_sem);
1321
1322 if (is_error_page(page)) {
1323 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1324 __func__, gpa);
1325 kvm_release_page_clean(page);
1326 kvm_inject_gp(&svm->vcpu, 0);
1327 return NULL;
1328 }
1329 return page;
1330}
1331
1332static int nested_svm_do(struct vcpu_svm *svm,
1333 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1334 int (*handler)(struct vcpu_svm *svm,
1335 void *arg1,
1336 void *arg2,
1337 void *opaque))
1338{
1339 struct page *arg1_page;
1340 struct page *arg2_page = NULL;
1341 void *arg1;
1342 void *arg2 = NULL;
1343 int retval;
1344
1345 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1346 if(arg1_page == NULL)
1347 return 1;
1348
1349 if (arg2_gpa) {
1350 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1351 if(arg2_page == NULL) {
1352 kvm_release_page_clean(arg1_page);
1353 return 1;
1354 }
1355 }
1356
1357 arg1 = kmap_atomic(arg1_page, KM_USER0);
1358 if (arg2_gpa)
1359 arg2 = kmap_atomic(arg2_page, KM_USER1);
1360
1361 retval = handler(svm, arg1, arg2, opaque);
1362
1363 kunmap_atomic(arg1, KM_USER0);
1364 if (arg2_gpa)
1365 kunmap_atomic(arg2, KM_USER1);
1366
1367 kvm_release_page_dirty(arg1_page);
1368 if (arg2_gpa)
1369 kvm_release_page_dirty(arg2_page);
1370
1371 return retval;
1372}
1373
cf74a78b
AG		 1374static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1375 void *arg1,
1376 void *arg2,
1377 void *opaque)
1378{
1379 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1380 bool kvm_overrides = *(bool *)opaque;
1381 u32 exit_code = svm->vmcb->control.exit_code;
1382
1383 if (kvm_overrides) {
1384 switch (exit_code) {
1385 case SVM_EXIT_INTR:
1386 case SVM_EXIT_NMI:
1387 return 0;
1388 /* For now we are always handling NPFs when using them */
1389 case SVM_EXIT_NPF:
1390 if (npt_enabled)
1391 return 0;
1392 break;
1393 /* When we're shadowing, trap PFs */
1394 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1395 if (!npt_enabled)
1396 return 0;
1397 break;
1398 default:
1399 break;
1400 }
1401 }
1402
1403 switch (exit_code) {
1404 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1405 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1406 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1407 return 1;
1408 break;
1409 }
1410 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1411 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1412 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1413 return 1;
1414 break;
1415 }
1416 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1417 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1418 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1419 return 1;
1420 break;
1421 }
1422 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1423 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1424 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1425 return 1;
1426 break;
1427 }
1428 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1429 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1430 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1431 return 1;
1432 break;
1433 }
1434 default: {
1435 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1436 nsvm_printk("exit code: 0x%x\n", exit_code);
1437 if (nested_vmcb->control.intercept & exit_bits)
1438 return 1;
1439 }
1440 }
1441
1442 return 0;
1443}
1444
1445static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1446 void *arg1, void *arg2,
1447 void *opaque)
1448{
1449 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1450 u8 *msrpm = (u8 *)arg2;
1451 u32 t0, t1;
1452 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1453 u32 param = svm->vmcb->control.exit_info_1 & 1;
1454
1455 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1456 return 0;
1457
1458 switch(msr) {
1459 case 0 ... 0x1fff:
1460 t0 = (msr * 2) % 8;
1461 t1 = msr / 8;
1462 break;
1463 case 0xc0000000 ... 0xc0001fff:
1464 t0 = (8192 + msr - 0xc0000000) * 2;
1465 t1 = (t0 / 8);
1466 t0 %= 8;
1467 break;
1468 case 0xc0010000 ... 0xc0011fff:
1469 t0 = (16384 + msr - 0xc0010000) * 2;
1470 t1 = (t0 / 8);
1471 t0 %= 8;
1472 break;
1473 default:
1474 return 1;
1475 break;
1476 }
1477 if (msrpm[t1] & ((1 << param) << t0))
1478 return 1;
1479
1480 return 0;
1481}
1482
1483static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1484{
1485 bool k = kvm_override;
1486
1487 switch (svm->vmcb->control.exit_code) {
1488 case SVM_EXIT_MSR:
1489 return nested_svm_do(svm, svm->nested_vmcb,
1490 svm->nested_vmcb_msrpm, NULL,
1491 nested_svm_exit_handled_msr);
1492 default: break;
1493 }
1494
1495 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1496 nested_svm_exit_handled_real);
1497}
1498
1499static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1500 void *arg2, void *opaque)
1501{
1502 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1503 struct vmcb *hsave = svm->hsave;
1504 u64 nested_save[] = { nested_vmcb->save.cr0,
1505 nested_vmcb->save.cr3,
1506 nested_vmcb->save.cr4,
1507 nested_vmcb->save.efer,
1508 nested_vmcb->control.intercept_cr_read,
1509 nested_vmcb->control.intercept_cr_write,
1510 nested_vmcb->control.intercept_dr_read,
1511 nested_vmcb->control.intercept_dr_write,
1512 nested_vmcb->control.intercept_exceptions,
1513 nested_vmcb->control.intercept,
1514 nested_vmcb->control.msrpm_base_pa,
1515 nested_vmcb->control.iopm_base_pa,
1516 nested_vmcb->control.tsc_offset };
1517
1518 /* Give the current vmcb to the guest */
1519 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1520 nested_vmcb->save.cr0 = nested_save[0];
1521 if (!npt_enabled)
1522 nested_vmcb->save.cr3 = nested_save[1];
1523 nested_vmcb->save.cr4 = nested_save[2];
1524 nested_vmcb->save.efer = nested_save[3];
1525 nested_vmcb->control.intercept_cr_read = nested_save[4];
1526 nested_vmcb->control.intercept_cr_write = nested_save[5];
1527 nested_vmcb->control.intercept_dr_read = nested_save[6];
1528 nested_vmcb->control.intercept_dr_write = nested_save[7];
1529 nested_vmcb->control.intercept_exceptions = nested_save[8];
1530 nested_vmcb->control.intercept = nested_save[9];
1531 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1532 nested_vmcb->control.iopm_base_pa = nested_save[11];
1533 nested_vmcb->control.tsc_offset = nested_save[12];
1534
1535 /* We always set V_INTR_MASKING and remember the old value in hflags */
1536 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1537 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1538
1539 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1540 (nested_vmcb->control.int_vector)) {
1541 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1542 nested_vmcb->control.int_vector);
1543 }
1544
1545 /* Restore the original control entries */
1546 svm->vmcb->control = hsave->control;
1547
1548 /* Kill any pending exceptions */
1549 if (svm->vcpu.arch.exception.pending == true)
1550 nsvm_printk("WARNING: Pending Exception\n");
1551 svm->vcpu.arch.exception.pending = false;
1552
1553 /* Restore selected save entries */
1554 svm->vmcb->save.es = hsave->save.es;
1555 svm->vmcb->save.cs = hsave->save.cs;
1556 svm->vmcb->save.ss = hsave->save.ss;
1557 svm->vmcb->save.ds = hsave->save.ds;
1558 svm->vmcb->save.gdtr = hsave->save.gdtr;
1559 svm->vmcb->save.idtr = hsave->save.idtr;
1560 svm->vmcb->save.rflags = hsave->save.rflags;
1561 svm_set_efer(&svm->vcpu, hsave->save.efer);
1562 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1563 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1564 if (npt_enabled) {
1565 svm->vmcb->save.cr3 = hsave->save.cr3;
1566 svm->vcpu.arch.cr3 = hsave->save.cr3;
1567 } else {
1568 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1569 }
1570 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1571 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1572 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1573 svm->vmcb->save.dr7 = 0;
1574 svm->vmcb->save.cpl = 0;
1575 svm->vmcb->control.exit_int_info = 0;
1576
1577 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1578 /* Exit nested SVM mode */
1579 svm->nested_vmcb = 0;
1580
1581 return 0;
1582}
1583
1584static int nested_svm_vmexit(struct vcpu_svm *svm)
1585{
1586 nsvm_printk("VMexit\n");
1587 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1588 NULL, nested_svm_vmexit_real))
1589 return 1;
1590
1591 kvm_mmu_reset_context(&svm->vcpu);
1592 kvm_mmu_load(&svm->vcpu);
1593
1594 return 0;
1595}
3d6368ef
AG		 1596
1597static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1598 void *arg2, void *opaque)
1599{
1600 int i;
1601 u32 *nested_msrpm = (u32*)arg1;
1602 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1603 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1604 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1605
1606 return 0;
1607}
1608
1609static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1610 void *arg2, void *opaque)
1611{
1612 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1613 struct vmcb *hsave = svm->hsave;
1614
1615 /* nested_vmcb is our indicator if nested SVM is activated */
1616 svm->nested_vmcb = svm->vmcb->save.rax;
1617
1618 /* Clear internal status */
1619 svm->vcpu.arch.exception.pending = false;
1620
1621 /* Save the old vmcb, so we don't need to pick what we save, but
1622 can restore everything when a VMEXIT occurs */
1623 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1624 /* We need to remember the original CR3 in the SPT case */
1625 if (!npt_enabled)
1626 hsave->save.cr3 = svm->vcpu.arch.cr3;
1627 hsave->save.cr4 = svm->vcpu.arch.cr4;
1628 hsave->save.rip = svm->next_rip;
1629
1630 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1631 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1632 else
1633 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1634
1635 /* Load the nested guest state */
1636 svm->vmcb->save.es = nested_vmcb->save.es;
1637 svm->vmcb->save.cs = nested_vmcb->save.cs;
1638 svm->vmcb->save.ss = nested_vmcb->save.ss;
1639 svm->vmcb->save.ds = nested_vmcb->save.ds;
1640 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1641 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1642 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1643 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1644 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1645 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1646 if (npt_enabled) {
1647 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1648 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1649 } else {
1650 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1651 kvm_mmu_reset_context(&svm->vcpu);
1652 }
1653 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1654 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1655 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1656 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1657 /* In case we don't even reach vcpu_run, the fields are not updated */
1658 svm->vmcb->save.rax = nested_vmcb->save.rax;
1659 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1660 svm->vmcb->save.rip = nested_vmcb->save.rip;
1661 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1662 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1663 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1664
1665 /* We don't want a nested guest to be more powerful than the guest,
1666 so all intercepts are ORed */
1667 svm->vmcb->control.intercept_cr_read |=
1668 nested_vmcb->control.intercept_cr_read;
1669 svm->vmcb->control.intercept_cr_write |=
1670 nested_vmcb->control.intercept_cr_write;
1671 svm->vmcb->control.intercept_dr_read |=
1672 nested_vmcb->control.intercept_dr_read;
1673 svm->vmcb->control.intercept_dr_write |=
1674 nested_vmcb->control.intercept_dr_write;
1675 svm->vmcb->control.intercept_exceptions |=
1676 nested_vmcb->control.intercept_exceptions;
1677
1678 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1679
1680 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1681
1682 force_new_asid(&svm->vcpu);
1683 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1684 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1685 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1686 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1687 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1688 nested_vmcb->control.int_ctl);
1689 }
1690 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1691 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1692 else
1693 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1694
1695 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1696 nested_vmcb->control.exit_int_info,
1697 nested_vmcb->control.int_state);
1698
1699 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1700 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1701 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1702 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1703 nsvm_printk("Injecting Event: 0x%x\n",
1704 nested_vmcb->control.event_inj);
1705 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1706 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1707
1708 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1709
1710 return 0;
1711}
1712
5542675b
AG		 1713static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1714{
1715 to_vmcb->save.fs = from_vmcb->save.fs;
1716 to_vmcb->save.gs = from_vmcb->save.gs;
1717 to_vmcb->save.tr = from_vmcb->save.tr;
1718 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1719 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1720 to_vmcb->save.star = from_vmcb->save.star;
1721 to_vmcb->save.lstar = from_vmcb->save.lstar;
1722 to_vmcb->save.cstar = from_vmcb->save.cstar;
1723 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1724 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1725 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1726 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1727
1728 return 1;
1729}
1730
1731static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1732 void *arg2, void *opaque)
1733{
1734 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1735}
1736
1737static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1738 void *arg2, void *opaque)
1739{
1740 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1741}
1742
1743static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1744{
1745 if (nested_svm_check_permissions(svm))
1746 return 1;
1747
1748 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1749 skip_emulated_instruction(&svm->vcpu);
1750
1751 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1752
1753 return 1;
1754}
1755
1756static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1757{
1758 if (nested_svm_check_permissions(svm))
1759 return 1;
1760
1761 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1762 skip_emulated_instruction(&svm->vcpu);
1763
1764 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1765
1766 return 1;
1767}
1768
3d6368ef
AG		 1769static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1770{
1771 nsvm_printk("VMrun\n");
1772 if (nested_svm_check_permissions(svm))
1773 return 1;
1774
1775 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1776 skip_emulated_instruction(&svm->vcpu);
1777
1778 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1779 NULL, nested_svm_vmrun))
1780 return 1;
1781
1782 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1783 NULL, nested_svm_vmrun_msrpm))
1784 return 1;
1785
1786 return 1;
1787}
1788
1371d904
AG		 1789static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1790{
1791 if (nested_svm_check_permissions(svm))
1792 return 1;
1793
1794 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1795 skip_emulated_instruction(&svm->vcpu);
1796
1797 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1798
1799 return 1;
1800}
1801
1802static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1803{
1804 if (nested_svm_check_permissions(svm))
1805 return 1;
1806
1807 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1808 skip_emulated_instruction(&svm->vcpu);
1809
1810 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1811
1812 /* After a CLGI no interrupts should come */
1813 svm_clear_vintr(svm);
1814 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1815
1816 return 1;
1817}
1818
e756fc62
RR		 1819static int invalid_op_interception(struct vcpu_svm *svm,
1820 struct kvm_run *kvm_run)
6aa8b732 1821{
7ee5d940 1822 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1823 return 1;
1824}
1825
e756fc62
RR		 1826static int task_switch_interception(struct vcpu_svm *svm,
1827 struct kvm_run *kvm_run)
6aa8b732 1828{
37817f29 1829 u16 tss_selector;
64a7ec06
GN		 1830 int reason;
1831 int int_type = svm->vmcb->control.exit_int_info &
1832 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1833 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1834 uint32_t type =
1835 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1836 uint32_t idt_v =
1837 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1838
1839 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1840
37817f29
IE		 1841 if (svm->vmcb->control.exit_info_2 &
1842 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1843 reason = TASK_SWITCH_IRET;
1844 else if (svm->vmcb->control.exit_info_2 &
1845 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1846 reason = TASK_SWITCH_JMP;
fe8e7f83 1847 else if (idt_v)
64a7ec06
GN		 1848 reason = TASK_SWITCH_GATE;
1849 else
1850 reason = TASK_SWITCH_CALL;
1851
fe8e7f83
GN		 1852 if (reason == TASK_SWITCH_GATE) {
1853 switch (type) {
1854 case SVM_EXITINTINFO_TYPE_NMI:
1855 svm->vcpu.arch.nmi_injected = false;
1856 break;
1857 case SVM_EXITINTINFO_TYPE_EXEPT:
1858 kvm_clear_exception_queue(&svm->vcpu);
1859 break;
1860 case SVM_EXITINTINFO_TYPE_INTR:
1861 kvm_clear_interrupt_queue(&svm->vcpu);
1862 break;
1863 default:
1864 break;
1865 }
1866 }
64a7ec06 1867
8317c298
GN		 1868 if (reason != TASK_SWITCH_GATE ||
1869 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1870 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1871 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1872 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1873 EMULTYPE_SKIP) != EMULATE_DONE)
1874 return 0;
1875 }
64a7ec06
GN		 1876
1877 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 1878}
1879
e756fc62 1880static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1881{
5fdbf976 1882 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1883 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1884 return 1;
6aa8b732
AK		 1885}
1886
95ba8273
GN		 1887static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1888{
1889 ++svm->vcpu.stat.nmi_window_exits;
1890 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1891 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
1892 return 1;
1893}
1894
a7052897
MT		 1895static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1896{
1897 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1898 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1899 return 1;
1900}
1901
e756fc62
RR		 1902static int emulate_on_interception(struct vcpu_svm *svm,
1903 struct kvm_run *kvm_run)
6aa8b732 1904{
3427318f 1905 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1906 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1907 return 1;
1908}
1909
1d075434
JR		 1910static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1911{
0a5fff19
GN		 1912 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1913 /* instruction emulation calls kvm_set_cr8() */
1d075434 1914 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 1915 if (irqchip_in_kernel(svm->vcpu.kvm)) {
1916 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 1917 return 1;
95ba8273 1918 }
0a5fff19
GN		 1919 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1920 return 1;
1d075434
JR		 1921 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1922 return 0;
1923}
1924
6aa8b732
AK		 1925static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1926{
a2fa3e9f
GH		 1927 struct vcpu_svm *svm = to_svm(vcpu);
1928
6aa8b732 1929 switch (ecx) {
6aa8b732
AK		 1930 case MSR_IA32_TIME_STAMP_COUNTER: {
1931 u64 tsc;
1932
1933 rdtscll(tsc);
a2fa3e9f 1934 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1935 break;
1936 }
0e859cac 1937 case MSR_K6_STAR:
a2fa3e9f 1938 *data = svm->vmcb->save.star;
6aa8b732 1939 break;
0e859cac 1940#ifdef CONFIG_X86_64
6aa8b732 1941 case MSR_LSTAR:
a2fa3e9f 1942 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 1943 break;
1944 case MSR_CSTAR:
a2fa3e9f 1945 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 1946 break;
1947 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1948 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 1949 break;
1950 case MSR_SYSCALL_MASK:
a2fa3e9f 1951 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 1952 break;
1953#endif
1954 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1955 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 1956 break;
1957 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1958 *data = svm->vmcb->save.sysenter_eip;
6aa8b732
AK		 1959 break;
1960 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1961 *data = svm->vmcb->save.sysenter_esp;
6aa8b732 1962 break;
a2938c80
JR		 1963 /* Nobody will change the following 5 values in the VMCB so
1964 we can safely return them on rdmsr. They will always be 0
1965 until LBRV is implemented. */
1966 case MSR_IA32_DEBUGCTLMSR:
1967 *data = svm->vmcb->save.dbgctl;
1968 break;
1969 case MSR_IA32_LASTBRANCHFROMIP:
1970 *data = svm->vmcb->save.br_from;
1971 break;
1972 case MSR_IA32_LASTBRANCHTOIP:
1973 *data = svm->vmcb->save.br_to;
1974 break;
1975 case MSR_IA32_LASTINTFROMIP:
1976 *data = svm->vmcb->save.last_excp_from;
1977 break;
1978 case MSR_IA32_LASTINTTOIP:
1979 *data = svm->vmcb->save.last_excp_to;
1980 break;
b286d5d8
AG		 1981 case MSR_VM_HSAVE_PA:
1982 *data = svm->hsave_msr;
1983 break;
eb6f302e
JR		 1984 case MSR_VM_CR:
1985 *data = 0;
1986 break;
c8a73f18
AG		 1987 case MSR_IA32_UCODE_REV:
1988 *data = 0x01000065;
1989 break;
6aa8b732 1990 default:
3bab1f5d 1991 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1992 }
1993 return 0;
1994}
1995
e756fc62 1996static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1997{
ad312c7c 1998 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 1999 u64 data;
2000
e756fc62 2001 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2002 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2003 else {
af9ca2d7
JR		 2004 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2005 (u32)(data >> 32), handler);
2006
5fdbf976 2007 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2008 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2009 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2010 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2011 }
2012 return 1;
2013}
2014
2015static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2016{
a2fa3e9f
GH		 2017 struct vcpu_svm *svm = to_svm(vcpu);
2018
6aa8b732 2019 switch (ecx) {
6aa8b732
AK		 2020 case MSR_IA32_TIME_STAMP_COUNTER: {
2021 u64 tsc;
2022
2023 rdtscll(tsc);
a2fa3e9f 2024 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2025 break;
2026 }
0e859cac 2027 case MSR_K6_STAR:
a2fa3e9f 2028 svm->vmcb->save.star = data;
6aa8b732 2029 break;
49b14f24 2030#ifdef CONFIG_X86_64
6aa8b732 2031 case MSR_LSTAR:
a2fa3e9f 2032 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2033 break;
2034 case MSR_CSTAR:
a2fa3e9f 2035 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2036 break;
2037 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2038 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2039 break;
2040 case MSR_SYSCALL_MASK:
a2fa3e9f 2041 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2042 break;
2043#endif
2044 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2045 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2046 break;
2047 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 2048 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2049 break;
2050 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 2051 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2052 break;
a2938c80 2053 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2054 if (!svm_has(SVM_FEATURE_LBRV)) {
2055 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2056 __func__, data);
24e09cbf
JR		 2057 break;
2058 }
2059 if (data & DEBUGCTL_RESERVED_BITS)
2060 return 1;
2061
2062 svm->vmcb->save.dbgctl = data;
2063 if (data & (1ULL<<0))
2064 svm_enable_lbrv(svm);
2065 else
2066 svm_disable_lbrv(svm);
a2938c80 2067 break;
62b9abaa
JR		 2068 case MSR_K7_EVNTSEL0:
2069 case MSR_K7_EVNTSEL1:
2070 case MSR_K7_EVNTSEL2:
2071 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2072 case MSR_K7_PERFCTR0:
2073 case MSR_K7_PERFCTR1:
2074 case MSR_K7_PERFCTR2:
2075 case MSR_K7_PERFCTR3:
62b9abaa 2076 /*
14ae51b6
CL		 2077 * Just discard all writes to the performance counters; this
2078 * should keep both older linux and windows 64-bit guests
2079 * happy
62b9abaa 2080 */
14ae51b6
CL		 2081 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2082
b286d5d8
AG		 2083 break;
2084 case MSR_VM_HSAVE_PA:
2085 svm->hsave_msr = data;
62b9abaa 2086 break;
6aa8b732 2087 default:
3bab1f5d 2088 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2089 }
2090 return 0;
2091}
2092
e756fc62 2093static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2094{
ad312c7c 2095 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2096 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2097 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2098
2099 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2100 handler);
2101
5fdbf976 2102 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2103 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2104 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2105 else
e756fc62 2106 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2107 return 1;
2108}
2109
e756fc62 2110static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2111{
e756fc62
RR		 2112 if (svm->vmcb->control.exit_info_1)
2113 return wrmsr_interception(svm, kvm_run);
6aa8b732 2114 else
e756fc62 2115 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2116}
2117
e756fc62 2118static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2119 struct kvm_run *kvm_run)
2120{
af9ca2d7
JR		 2121 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2122
f0b85051 2123 svm_clear_vintr(svm);
85f455f7 2124 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2125 /*
2126 * If the user space waits to inject interrupts, exit as soon as
2127 * possible
2128 */
8061823a
GN		 2129 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2130 kvm_run->request_interrupt_window &&
2131 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2132 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2133 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2134 return 0;
2135 }
2136
2137 return 1;
2138}
2139
e756fc62 2140static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2141 struct kvm_run *kvm_run) = {
2142 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2143 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2144 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2145 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2146 /* for now: */
2147 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2148 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2149 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2150 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2151 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2152 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2153 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2154 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2155 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2156 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2157 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2158 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2159 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2160 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2161 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2162 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2163 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2164 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2165 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2166 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2167 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2168 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2169 [SVM_EXIT_SMI] = nop_on_interception,
2170 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2171 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2172 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2173 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2174 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2175 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2176 [SVM_EXIT_HLT] = halt_interception,
a7052897 2177 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2178 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2179 [SVM_EXIT_IOIO] = io_interception,
2180 [SVM_EXIT_MSR] = msr_interception,
2181 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2182 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2183 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2184 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2185 [SVM_EXIT_VMLOAD] = vmload_interception,
2186 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2187 [SVM_EXIT_STGI] = stgi_interception,
2188 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2189 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2190 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2191 [SVM_EXIT_MONITOR] = invalid_op_interception,
2192 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2193 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2194};
2195
04d2cc77 2196static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2197{
04d2cc77 2198 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2199 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2200
af9ca2d7
JR		 2201 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2202 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2203
cf74a78b
AG		 2204 if (is_nested(svm)) {
2205 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2206 exit_code, svm->vmcb->control.exit_info_1,
2207 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2208 if (nested_svm_exit_handled(svm, true)) {
2209 nested_svm_vmexit(svm);
2210 nsvm_printk("-> #VMEXIT\n");
2211 return 1;
2212 }
2213 }
2214
709ddebf
JR		 2215 if (npt_enabled) {
2216 int mmu_reload = 0;
2217 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2218 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2219 mmu_reload = 1;
2220 }
2221 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2222 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2223 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2224 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2225 kvm_inject_gp(vcpu, 0);
2226 return 1;
2227 }
2228 }
2229 if (mmu_reload) {
2230 kvm_mmu_reset_context(vcpu);
2231 kvm_mmu_load(vcpu);
2232 }
2233 }
2234
04d2cc77
AK		 2235
2236 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2237 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2238 kvm_run->fail_entry.hardware_entry_failure_reason
2239 = svm->vmcb->control.exit_code;
2240 return 0;
2241 }
2242
a2fa3e9f 2243 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2244 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2245 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2246 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2247 "exit_code 0x%x\n",
b8688d51 2248 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2249 exit_code);
2250
9d8f549d 2251 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2252 || !svm_exit_handlers[exit_code]) {
6aa8b732 2253 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2254 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2255 return 0;
2256 }
2257
e756fc62 2258 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2259}
2260
2261static void reload_tss(struct kvm_vcpu *vcpu)
2262{
2263 int cpu = raw_smp_processor_id();
2264
2265 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2266 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2267 load_TR_desc();
2268}
2269
e756fc62 2270static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2271{
2272 int cpu = raw_smp_processor_id();
2273
2274 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2275
a2fa3e9f 2276 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e756fc62 2277 if (svm->vcpu.cpu != cpu ||
a2fa3e9f 2278 svm->asid_generation != svm_data->asid_generation)
e756fc62 2279 new_asid(svm, svm_data);
6aa8b732
AK		 2280}
2281
95ba8273
GN		 2282static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2283{
2284 struct vcpu_svm *svm = to_svm(vcpu);
2285
2286 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2287 vcpu->arch.hflags |= HF_NMI_MASK;
2288 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2289 ++vcpu->stat.nmi_injections;
2290}
6aa8b732 2291
85f455f7 2292static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2293{
2294 struct vmcb_control_area *control;
2295
af9ca2d7
JR		 2296 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2297
fa89a817 2298 ++svm->vcpu.stat.irq_injections;
e756fc62 2299 control = &svm->vmcb->control;
85f455f7 2300 control->int_vector = irq;
6aa8b732
AK		 2301 control->int_ctl &= ~V_INTR_PRIO_MASK;
2302 control->int_ctl |= V_IRQ_MASK |
2303 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2304}
2305
95ba8273 2306static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
9222be18 2307{
95ba8273
GN		 2308 struct vcpu_svm *svm = to_svm(vcpu);
2309
9222be18
GN		 2310 svm->vmcb->control.event_inj = nr |
2311 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2312}
2313
2a8067f1
ED		 2314static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2315{
2316 struct vcpu_svm *svm = to_svm(vcpu);
2317
cf74a78b
AG		 2318 nested_svm_intr(svm);
2319
95ba8273 2320 svm_queue_irq(vcpu, irq);
2a8067f1
ED		 2321}
2322
95ba8273 2323static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2324{
2325 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2326
95ba8273 2327 if (irr == -1)
aaacfc9a
JR		 2328 return;
2329
95ba8273
GN		 2330 if (tpr >= irr)
2331 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2332}
aaacfc9a 2333
95ba8273
GN		 2334static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2335{
2336 struct vcpu_svm *svm = to_svm(vcpu);
2337 struct vmcb *vmcb = svm->vmcb;
2338 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2339 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2340}
2341
78646121
GN		 2342static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2343{
2344 struct vcpu_svm *svm = to_svm(vcpu);
2345 struct vmcb *vmcb = svm->vmcb;
2346 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2347 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2348 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2349}
2350
9222be18 2351static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2352{
9222be18
GN		 2353 svm_set_vintr(to_svm(vcpu));
2354 svm_inject_irq(to_svm(vcpu), 0x0);
85f455f7
ED		 2355}
2356
95ba8273 2357static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2358{
04d2cc77 2359 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2360
95ba8273 2361 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
9222be18 2362 enable_irq_window(vcpu);
c1150d8c
DL		 2363}
2364
cbc94022
IE		 2365static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2366{
2367 return 0;
2368}
2369
d9e368d6
AK		 2370static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2371{
2372 force_new_asid(vcpu);
2373}
2374
04d2cc77
AK		 2375static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2376{
2377}
2378
d7bf8221
JR		 2379static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2380{
2381 struct vcpu_svm *svm = to_svm(vcpu);
2382
2383 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2384 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2385 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2386 }
2387}
2388
649d6864
JR		 2389static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2390{
2391 struct vcpu_svm *svm = to_svm(vcpu);
2392 u64 cr8;
2393
649d6864
JR		 2394 cr8 = kvm_get_cr8(vcpu);
2395 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2396 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2397}
2398
9222be18
GN		 2399static void svm_complete_interrupts(struct vcpu_svm *svm)
2400{
2401 u8 vector;
2402 int type;
2403 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2404
2405 svm->vcpu.arch.nmi_injected = false;
2406 kvm_clear_exception_queue(&svm->vcpu);
2407 kvm_clear_interrupt_queue(&svm->vcpu);
2408
2409 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2410 return;
2411
2412 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2413 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2414
2415 switch (type) {
2416 case SVM_EXITINTINFO_TYPE_NMI:
2417 svm->vcpu.arch.nmi_injected = true;
2418 break;
2419 case SVM_EXITINTINFO_TYPE_EXEPT:
2420 /* In case of software exception do not reinject an exception
2421 vector, but re-execute and instruction instead */
2422 if (vector == BP_VECTOR || vector == OF_VECTOR)
2423 break;
2424 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2425 u32 err = svm->vmcb->control.exit_int_info_err;
2426 kvm_queue_exception_e(&svm->vcpu, vector, err);
2427
2428 } else
2429 kvm_queue_exception(&svm->vcpu, vector);
2430 break;
2431 case SVM_EXITINTINFO_TYPE_INTR:
2432 kvm_queue_interrupt(&svm->vcpu, vector);
2433 break;
2434 default:
2435 break;
2436 }
2437}
2438
80e31d4f
AK		 2439#ifdef CONFIG_X86_64
2440#define R "r"
2441#else
2442#define R "e"
2443#endif
2444
04d2cc77 2445static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2446{
a2fa3e9f 2447 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2448 u16 fs_selector;
2449 u16 gs_selector;
2450 u16 ldt_selector;
d9e368d6 2451
5fdbf976
MT		 2452 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2453 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2454 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2455
e756fc62 2456 pre_svm_run(svm);
6aa8b732 2457
649d6864
JR		 2458 sync_lapic_to_cr8(vcpu);
2459
6aa8b732 2460 save_host_msrs(vcpu);
d6e88aec
AK		 2461 fs_selector = kvm_read_fs();
2462 gs_selector = kvm_read_gs();
2463 ldt_selector = kvm_read_ldt();
a2fa3e9f 2464 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2465 if (!is_nested(svm))
2466 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2467 /* required for live migration with NPT */
2468 if (npt_enabled)
2469 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2470
04d2cc77
AK		 2471 clgi();
2472
2473 local_irq_enable();
36241b8c 2474
6aa8b732 2475 asm volatile (
80e31d4f
AK		 2476 "push %%"R"bp; \n\t"
2477 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2478 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2479 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2480 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2481 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2482 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2483#ifdef CONFIG_X86_64
fb3f0f51
RR		 2484 "mov %c[r8](%[svm]), %%r8 \n\t"
2485 "mov %c[r9](%[svm]), %%r9 \n\t"
2486 "mov %c[r10](%[svm]), %%r10 \n\t"
2487 "mov %c[r11](%[svm]), %%r11 \n\t"
2488 "mov %c[r12](%[svm]), %%r12 \n\t"
2489 "mov %c[r13](%[svm]), %%r13 \n\t"
2490 "mov %c[r14](%[svm]), %%r14 \n\t"
2491 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2492#endif
2493
6aa8b732 2494 /* Enter guest mode */
80e31d4f
AK		 2495 "push %%"R"ax \n\t"
2496 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2497 __ex(SVM_VMLOAD) "\n\t"
2498 __ex(SVM_VMRUN) "\n\t"
2499 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2500 "pop %%"R"ax \n\t"
6aa8b732
AK		 2501
2502 /* Save guest registers, load host registers */
80e31d4f
AK		 2503 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2504 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2505 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2506 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2507 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2508 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2509#ifdef CONFIG_X86_64
fb3f0f51
RR		 2510 "mov %%r8, %c[r8](%[svm]) \n\t"
2511 "mov %%r9, %c[r9](%[svm]) \n\t"
2512 "mov %%r10, %c[r10](%[svm]) \n\t"
2513 "mov %%r11, %c[r11](%[svm]) \n\t"
2514 "mov %%r12, %c[r12](%[svm]) \n\t"
2515 "mov %%r13, %c[r13](%[svm]) \n\t"
2516 "mov %%r14, %c[r14](%[svm]) \n\t"
2517 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2518#endif
80e31d4f 2519 "pop %%"R"bp"
6aa8b732 2520 :
fb3f0f51 2521 : [svm]"a"(svm),
6aa8b732 2522 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2523 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2524 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2525 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2526 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2527 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2528 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2529#ifdef CONFIG_X86_64
ad312c7c
ZX		 2530 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2531 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2532 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2533 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2534 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2535 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2536 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2537 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2538#endif
54a08c04 2539 : "cc", "memory"
80e31d4f 2540 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2541#ifdef CONFIG_X86_64
54a08c04
LV		 2542 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2543#endif
2544 );
6aa8b732 2545
ad312c7c 2546 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2547 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2548 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2549 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2550
a2fa3e9f 2551 kvm_write_cr2(svm->host_cr2);
6aa8b732 2552
d6e88aec
AK		 2553 kvm_load_fs(fs_selector);
2554 kvm_load_gs(gs_selector);
2555 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2556 load_host_msrs(vcpu);
2557
2558 reload_tss(vcpu);
2559
56ba47dd
AK		 2560 local_irq_disable();
2561
2562 stgi();
2563
d7bf8221
JR		 2564 sync_cr8_to_lapic(vcpu);
2565
a2fa3e9f 2566 svm->next_rip = 0;
9222be18
GN		 2567
2568 svm_complete_interrupts(svm);
6aa8b732
AK		 2569}
2570
80e31d4f
AK		 2571#undef R
2572
6aa8b732
AK		 2573static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2574{
a2fa3e9f
GH		 2575 struct vcpu_svm *svm = to_svm(vcpu);
2576
709ddebf
JR		 2577 if (npt_enabled) {
2578 svm->vmcb->control.nested_cr3 = root;
2579 force_new_asid(vcpu);
2580 return;
2581 }
2582
a2fa3e9f 2583 svm->vmcb->save.cr3 = root;
6aa8b732 2584 force_new_asid(vcpu);
7807fa6c
AL		 2585
2586 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2587 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2588 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2589 vcpu->fpu_active = 0;
2590 }
6aa8b732
AK		 2591}
2592
6aa8b732
AK		 2593static int is_disabled(void)
2594{
6031a61c
JR		 2595 u64 vm_cr;
2596
2597 rdmsrl(MSR_VM_CR, vm_cr);
2598 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2599 return 1;
2600
6aa8b732
AK		 2601 return 0;
2602}
2603
102d8325
IM		 2604static void
2605svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2606{
2607 /*
2608 * Patch in the VMMCALL instruction:
2609 */
2610 hypercall[0] = 0x0f;
2611 hypercall[1] = 0x01;
2612 hypercall[2] = 0xd9;
102d8325
IM		 2613}
2614
002c7f7c
YS		 2615static void svm_check_processor_compat(void *rtn)
2616{
2617 *(int *)rtn = 0;
2618}
2619
774ead3a
AK		 2620static bool svm_cpu_has_accelerated_tpr(void)
2621{
2622 return false;
2623}
2624
67253af5
SY		 2625static int get_npt_level(void)
2626{
2627#ifdef CONFIG_X86_64
2628 return PT64_ROOT_LEVEL;
2629#else
2630 return PT32E_ROOT_LEVEL;
2631#endif
2632}
2633
4b12f0de 2634static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2635{
2636 return 0;
2637}
2638
cbdd1bea 2639static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2640 .cpu_has_kvm_support = has_svm,
2641 .disabled_by_bios = is_disabled,
2642 .hardware_setup = svm_hardware_setup,
2643 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2644 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2645 .hardware_enable = svm_hardware_enable,
2646 .hardware_disable = svm_hardware_disable,
774ead3a 2647 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2648
2649 .vcpu_create = svm_create_vcpu,
2650 .vcpu_free = svm_free_vcpu,
04d2cc77 2651 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2652
04d2cc77 2653 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2654 .vcpu_load = svm_vcpu_load,
2655 .vcpu_put = svm_vcpu_put,
2656
2657 .set_guest_debug = svm_guest_debug,
2658 .get_msr = svm_get_msr,
2659 .set_msr = svm_set_msr,
2660 .get_segment_base = svm_get_segment_base,
2661 .get_segment = svm_get_segment,
2662 .set_segment = svm_set_segment,
2e4d2653 2663 .get_cpl = svm_get_cpl,
1747fb71 2664 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2665 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2666 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2667 .set_cr3 = svm_set_cr3,
2668 .set_cr4 = svm_set_cr4,
2669 .set_efer = svm_set_efer,
2670 .get_idt = svm_get_idt,
2671 .set_idt = svm_set_idt,
2672 .get_gdt = svm_get_gdt,
2673 .set_gdt = svm_set_gdt,
2674 .get_dr = svm_get_dr,
2675 .set_dr = svm_set_dr,
6aa8b732
AK		 2676 .get_rflags = svm_get_rflags,
2677 .set_rflags = svm_set_rflags,
2678
6aa8b732 2679 .tlb_flush = svm_flush_tlb,
6aa8b732 2680
6aa8b732 2681 .run = svm_vcpu_run,
04d2cc77 2682 .handle_exit = handle_exit,
6aa8b732 2683 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2684 .set_interrupt_shadow = svm_set_interrupt_shadow,
2685 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2686 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2687 .set_irq = svm_set_irq,
95ba8273 2688 .set_nmi = svm_inject_nmi,
298101da 2689 .queue_exception = svm_queue_exception,
78646121 2690 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2691 .nmi_allowed = svm_nmi_allowed,
2692 .enable_nmi_window = enable_nmi_window,
2693 .enable_irq_window = enable_irq_window,
2694 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2695
2696 .set_tss_addr = svm_set_tss_addr,
67253af5 2697 .get_tdp_level = get_npt_level,
4b12f0de 2698 .get_mt_mask = svm_get_mt_mask,
6aa8b732
AK		 2699};
2700
2701static int __init svm_init(void)
2702{
cb498ea2 2703 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2704 THIS_MODULE);
6aa8b732
AK		 2705}
2706
2707static void __exit svm_exit(void)
2708{
cb498ea2 2709 kvm_exit();
6aa8b732
AK		 2710}
2711
2712module_init(svm_init)
2713module_exit(svm_exit)
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