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KVM: x86: Warn about unstable TSC
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
aad42c64
JR		 91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
e6aa9abd
JR		 99};
100
323c3d80
JR		 101#define MSRPM_OFFSETS 16
102static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
103
6c8166a7
AK		 104struct vcpu_svm {
105 struct kvm_vcpu vcpu;
106 struct vmcb *vmcb;
107 unsigned long vmcb_pa;
108 struct svm_cpu_data *svm_data;
109 uint64_t asid_generation;
110 uint64_t sysenter_esp;
111 uint64_t sysenter_eip;
112
113 u64 next_rip;
114
115 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
116 u64 host_gs_base;
6c8166a7
AK		 117
118 u32 *msrpm;
6c8166a7 119
e6aa9abd 120 struct nested_state nested;
6be7d306
JK		 121
122 bool nmi_singlestep;
66b7138f
JK		 123
124 unsigned int3_injected;
125 unsigned long int3_rip;
6c8166a7
AK		 126};
127
455716fa
JR		 128#define MSR_INVALID 0xffffffffU
129
ac72a9b7
JR		 130static struct svm_direct_access_msrs {
131 u32 index; /* Index of the MSR */
132 bool always; /* True if intercept is always on */
133} direct_access_msrs[] = {
8c06585d 134 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 135 { .index = MSR_IA32_SYSENTER_CS, .always = true },
136#ifdef CONFIG_X86_64
137 { .index = MSR_GS_BASE, .always = true },
138 { .index = MSR_FS_BASE, .always = true },
139 { .index = MSR_KERNEL_GS_BASE, .always = true },
140 { .index = MSR_LSTAR, .always = true },
141 { .index = MSR_CSTAR, .always = true },
142 { .index = MSR_SYSCALL_MASK, .always = true },
143#endif
144 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
145 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
146 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
147 { .index = MSR_IA32_LASTINTTOIP, .always = false },
148 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 149};
150
709ddebf
JR		 151/* enable NPT for AMD64 and X86 with PAE */
152#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
153static bool npt_enabled = true;
154#else
e0231715 155static bool npt_enabled;
709ddebf 156#endif
6c7dac72
JR		 157static int npt = 1;
158
159module_param(npt, int, S_IRUGO);
e3da3acd 160
4b6e4dca 161static int nested = 1;
236de055
AG		 162module_param(nested, int, S_IRUGO);
163
44874f84 164static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 165static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 166
410e4d57 167static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 168static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 169static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 170static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
171 bool has_error_code, u32 error_code);
172
a2fa3e9f
GH		 173static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 176}
177
3d6368ef
AG		 178static inline bool is_nested(struct vcpu_svm *svm)
179{
e6aa9abd 180 return svm->nested.vmcb;
3d6368ef
AG		 181}
182
2af9194d
JR		 183static inline void enable_gif(struct vcpu_svm *svm)
184{
185 svm->vcpu.arch.hflags |= HF_GIF_MASK;
186}
187
188static inline void disable_gif(struct vcpu_svm *svm)
189{
190 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
191}
192
193static inline bool gif_set(struct vcpu_svm *svm)
194{
195 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
196}
197
4866d5e3 198static unsigned long iopm_base;
6aa8b732
AK		 199
200struct kvm_ldttss_desc {
201 u16 limit0;
202 u16 base0;
e0231715
JR		 203 unsigned base1:8, type:5, dpl:2, p:1;
204 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 205 u32 base3;
206 u32 zero1;
207} __attribute__((packed));
208
209struct svm_cpu_data {
210 int cpu;
211
5008fdf5
AK		 212 u64 asid_generation;
213 u32 max_asid;
214 u32 next_asid;
6aa8b732
AK		 215 struct kvm_ldttss_desc *tss_desc;
216
217 struct page *save_area;
218};
219
220static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 221static uint32_t svm_features;
6aa8b732
AK		 222
223struct svm_init_data {
224 int cpu;
225 int r;
226};
227
228static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
229
9d8f549d 230#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 231#define MSRS_RANGE_SIZE 2048
232#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
233
455716fa
JR		 234static u32 svm_msrpm_offset(u32 msr)
235{
236 u32 offset;
237 int i;
238
239 for (i = 0; i < NUM_MSR_MAPS; i++) {
240 if (msr < msrpm_ranges[i] ||
241 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
242 continue;
243
244 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
245 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
246
247 /* Now we have the u8 offset - but need the u32 offset */
248 return offset / 4;
249 }
250
251 /* MSR not in any range */
252 return MSR_INVALID;
253}
254
6aa8b732
AK		 255#define MAX_INST_SIZE 15
256
80b7706e
JR		 257static inline u32 svm_has(u32 feat)
258{
259 return svm_features & feat;
260}
261
6aa8b732
AK		 262static inline void clgi(void)
263{
4ecac3fd 264 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 265}
266
267static inline void stgi(void)
268{
4ecac3fd 269 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 270}
271
272static inline void invlpga(unsigned long addr, u32 asid)
273{
e0231715 274 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 275}
276
6aa8b732
AK		 277static inline void force_new_asid(struct kvm_vcpu *vcpu)
278{
a2fa3e9f 279 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 280}
281
282static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
283{
284 force_new_asid(vcpu);
285}
286
287static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
288{
6dc696d4 289 vcpu->arch.efer = efer;
709ddebf 290 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 291 efer &= ~EFER_LME;
6aa8b732 292
9962d032 293 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 294}
295
6aa8b732
AK		 296static int is_external_interrupt(u32 info)
297{
298 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
299 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
300}
301
2809f5d2
GC		 302static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
303{
304 struct vcpu_svm *svm = to_svm(vcpu);
305 u32 ret = 0;
306
307 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 308 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 309 return ret & mask;
310}
311
312static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
313{
314 struct vcpu_svm *svm = to_svm(vcpu);
315
316 if (mask == 0)
317 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
318 else
319 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
320
321}
322
6aa8b732
AK		 323static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
324{
a2fa3e9f
GH		 325 struct vcpu_svm *svm = to_svm(vcpu);
326
6bc31bdc
AP		 327 if (svm->vmcb->control.next_rip != 0)
328 svm->next_rip = svm->vmcb->control.next_rip;
329
a2fa3e9f 330 if (!svm->next_rip) {
851ba692 331 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 332 EMULATE_DONE)
333 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 334 return;
335 }
5fdbf976
MT		 336 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
337 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
338 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 339
5fdbf976 340 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 341 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 342}
343
116a4752 344static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 345 bool has_error_code, u32 error_code,
346 bool reinject)
116a4752
JK		 347{
348 struct vcpu_svm *svm = to_svm(vcpu);
349
e0231715
JR		 350 /*
351 * If we are within a nested VM we'd better #VMEXIT and let the guest
352 * handle the exception
353 */
ce7ddec4
JR		 354 if (!reinject &&
355 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 356 return;
357
66b7138f
JK		 358 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
359 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
360
361 /*
362 * For guest debugging where we have to reinject #BP if some
363 * INT3 is guest-owned:
364 * Emulate nRIP by moving RIP forward. Will fail if injection
365 * raises a fault that is not intercepted. Still better than
366 * failing in all cases.
367 */
368 skip_emulated_instruction(&svm->vcpu);
369 rip = kvm_rip_read(&svm->vcpu);
370 svm->int3_rip = rip + svm->vmcb->save.cs.base;
371 svm->int3_injected = rip - old_rip;
372 }
373
116a4752
JK		 374 svm->vmcb->control.event_inj = nr
375 | SVM_EVTINJ_VALID
376 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
377 | SVM_EVTINJ_TYPE_EXEPT;
378 svm->vmcb->control.event_inj_err = error_code;
379}
380
67ec6607
JR		 381static void svm_init_erratum_383(void)
382{
383 u32 low, high;
384 int err;
385 u64 val;
386
1be85a6d 387 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 388 return;
389
390 /* Use _safe variants to not break nested virtualization */
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
392 if (err)
393 return;
394
395 val |= (1ULL << 47);
396
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
399
400 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
401
402 erratum_383_found = true;
403}
404
6aa8b732
AK		 405static int has_svm(void)
406{
63d1142f 407 const char *msg;
6aa8b732 408
63d1142f 409 if (!cpu_has_svm(&msg)) {
ff81ff10 410 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 411 return 0;
412 }
413
6aa8b732
AK		 414 return 1;
415}
416
417static void svm_hardware_disable(void *garbage)
418{
2c8dceeb 419 cpu_svm_disable();
6aa8b732
AK		 420}
421
10474ae8 422static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 423{
424
0fe1e009 425 struct svm_cpu_data *sd;
6aa8b732 426 uint64_t efer;
89a27f4d 427 struct desc_ptr gdt_descr;
6aa8b732
AK		 428 struct desc_struct *gdt;
429 int me = raw_smp_processor_id();
430
10474ae8
AG		 431 rdmsrl(MSR_EFER, efer);
432 if (efer & EFER_SVME)
433 return -EBUSY;
434
6aa8b732 435 if (!has_svm()) {
e6732a5a
ZA		 436 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
437 me);
10474ae8 438 return -EINVAL;
6aa8b732 439 }
0fe1e009 440 sd = per_cpu(svm_data, me);
6aa8b732 441
0fe1e009 442 if (!sd) {
e6732a5a 443 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 444 me);
10474ae8 445 return -EINVAL;
6aa8b732
AK		 446 }
447
0fe1e009
TH		 448 sd->asid_generation = 1;
449 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
450 sd->next_asid = sd->max_asid + 1;
6aa8b732 451
d6ab1ed4 452 native_store_gdt(&gdt_descr);
89a27f4d 453 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 454 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 455
9962d032 456 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 457
d0316554 458 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 459
67ec6607
JR		 460 svm_init_erratum_383();
461
10474ae8 462 return 0;
6aa8b732
AK		 463}
464
0da1db75
JR		 465static void svm_cpu_uninit(int cpu)
466{
0fe1e009 467 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 468
0fe1e009 469 if (!sd)
0da1db75
JR		 470 return;
471
472 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 473 __free_page(sd->save_area);
474 kfree(sd);
0da1db75
JR		 475}
476
6aa8b732
AK		 477static int svm_cpu_init(int cpu)
478{
0fe1e009 479 struct svm_cpu_data *sd;
6aa8b732
AK		 480 int r;
481
0fe1e009
TH		 482 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
483 if (!sd)
6aa8b732 484 return -ENOMEM;
0fe1e009
TH		 485 sd->cpu = cpu;
486 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 487 r = -ENOMEM;
0fe1e009 488 if (!sd->save_area)
6aa8b732
AK		 489 goto err_1;
490
0fe1e009 491 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 492
493 return 0;
494
495err_1:
0fe1e009 496 kfree(sd);
6aa8b732
AK		 497 return r;
498
499}
500
ac72a9b7
JR		 501static bool valid_msr_intercept(u32 index)
502{
503 int i;
504
505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
506 if (direct_access_msrs[i].index == index)
507 return true;
508
509 return false;
510}
511
bfc733a7
RR		 512static void set_msr_interception(u32 *msrpm, unsigned msr,
513 int read, int write)
6aa8b732 514{
455716fa
JR		 515 u8 bit_read, bit_write;
516 unsigned long tmp;
517 u32 offset;
6aa8b732 518
ac72a9b7
JR		 519 /*
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
522 */
523 WARN_ON(!valid_msr_intercept(msr));
524
455716fa
JR		 525 offset = svm_msrpm_offset(msr);
526 bit_read = 2 * (msr & 0x0f);
527 bit_write = 2 * (msr & 0x0f) + 1;
528 tmp = msrpm[offset];
529
530 BUG_ON(offset == MSR_INVALID);
531
532 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
533 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
534
535 msrpm[offset] = tmp;
6aa8b732
AK		 536}
537
f65c229c 538static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 539{
540 int i;
541
f65c229c
JR		 542 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
543
ac72a9b7
JR		 544 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
545 if (!direct_access_msrs[i].always)
546 continue;
547
548 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
549 }
f65c229c
JR		 550}
551
323c3d80
JR		 552static void add_msr_offset(u32 offset)
553{
554 int i;
555
556 for (i = 0; i < MSRPM_OFFSETS; ++i) {
557
558 /* Offset already in list? */
559 if (msrpm_offsets[i] == offset)
bfc733a7 560 return;
323c3d80
JR		 561
562 /* Slot used by another offset? */
563 if (msrpm_offsets[i] != MSR_INVALID)
564 continue;
565
566 /* Add offset to list */
567 msrpm_offsets[i] = offset;
568
569 return;
6aa8b732 570 }
323c3d80
JR		 571
572 /*
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
575 */
bfc733a7 576 BUG();
6aa8b732
AK		 577}
578
323c3d80 579static void init_msrpm_offsets(void)
f65c229c 580{
323c3d80 581 int i;
f65c229c 582
323c3d80
JR		 583 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
584
585 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
586 u32 offset;
587
588 offset = svm_msrpm_offset(direct_access_msrs[i].index);
589 BUG_ON(offset == MSR_INVALID);
590
591 add_msr_offset(offset);
592 }
f65c229c
JR		 593}
594
24e09cbf
JR		 595static void svm_enable_lbrv(struct vcpu_svm *svm)
596{
597 u32 *msrpm = svm->msrpm;
598
599 svm->vmcb->control.lbr_ctl = 1;
600 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
604}
605
606static void svm_disable_lbrv(struct vcpu_svm *svm)
607{
608 u32 *msrpm = svm->msrpm;
609
610 svm->vmcb->control.lbr_ctl = 0;
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
615}
616
6aa8b732
AK		 617static __init int svm_hardware_setup(void)
618{
619 int cpu;
620 struct page *iopm_pages;
f65c229c 621 void *iopm_va;
6aa8b732
AK		 622 int r;
623
6aa8b732
AK		 624 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
625
626 if (!iopm_pages)
627 return -ENOMEM;
c8681339
AL		 628
629 iopm_va = page_address(iopm_pages);
630 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 631 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
632
323c3d80
JR		 633 init_msrpm_offsets();
634
50a37eb4
JR		 635 if (boot_cpu_has(X86_FEATURE_NX))
636 kvm_enable_efer_bits(EFER_NX);
637
1b2fd70c
AG		 638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
639 kvm_enable_efer_bits(EFER_FFXSR);
640
236de055
AG		 641 if (nested) {
642 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 643 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 644 }
645
3230bb47 646 for_each_possible_cpu(cpu) {
6aa8b732
AK		 647 r = svm_cpu_init(cpu);
648 if (r)
f65c229c 649 goto err;
6aa8b732 650 }
33bd6a0b
JR		 651
652 svm_features = cpuid_edx(SVM_CPUID_FUNC);
653
e3da3acd
JR		 654 if (!svm_has(SVM_FEATURE_NPT))
655 npt_enabled = false;
656
6c7dac72
JR		 657 if (npt_enabled && !npt) {
658 printk(KERN_INFO "kvm: Nested Paging disabled\n");
659 npt_enabled = false;
660 }
661
18552672 662 if (npt_enabled) {
e3da3acd 663 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 664 kvm_enable_tdp();
5f4cb662
JR		 665 } else
666 kvm_disable_tdp();
e3da3acd 667
6aa8b732
AK		 668 return 0;
669
f65c229c 670err:
6aa8b732
AK		 671 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
672 iopm_base = 0;
673 return r;
674}
675
676static __exit void svm_hardware_unsetup(void)
677{
0da1db75
JR		 678 int cpu;
679
3230bb47 680 for_each_possible_cpu(cpu)
0da1db75
JR		 681 svm_cpu_uninit(cpu);
682
6aa8b732 683 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 684 iopm_base = 0;
6aa8b732
AK		 685}
686
687static void init_seg(struct vmcb_seg *seg)
688{
689 seg->selector = 0;
690 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 691 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 692 seg->limit = 0xffff;
693 seg->base = 0;
694}
695
696static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
697{
698 seg->selector = 0;
699 seg->attrib = SVM_SELECTOR_P_MASK | type;
700 seg->limit = 0xffff;
701 seg->base = 0;
702}
703
f4e1b3c8
ZA		 704static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
705{
706 struct vcpu_svm *svm = to_svm(vcpu);
707 u64 g_tsc_offset = 0;
708
709 if (is_nested(svm)) {
710 g_tsc_offset = svm->vmcb->control.tsc_offset -
711 svm->nested.hsave->control.tsc_offset;
712 svm->nested.hsave->control.tsc_offset = offset;
713 }
714
715 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
716}
717
e6101a96 718static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 719{
e6101a96
JR		 720 struct vmcb_control_area *control = &svm->vmcb->control;
721 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 722
bff78274
AK		 723 svm->vcpu.fpu_active = 1;
724
e0231715 725 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 726 INTERCEPT_CR3_MASK |
649d6864 727 INTERCEPT_CR4_MASK;
6aa8b732 728
e0231715 729 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 730 INTERCEPT_CR3_MASK |
80a8119c
AK		 731 INTERCEPT_CR4_MASK |
732 INTERCEPT_CR8_MASK;
6aa8b732 733
e0231715 734 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 735 INTERCEPT_DR1_MASK |
736 INTERCEPT_DR2_MASK |
727f5a23
JK		 737 INTERCEPT_DR3_MASK |
738 INTERCEPT_DR4_MASK |
739 INTERCEPT_DR5_MASK |
740 INTERCEPT_DR6_MASK |
741 INTERCEPT_DR7_MASK;
6aa8b732 742
e0231715 743 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 744 INTERCEPT_DR1_MASK |
745 INTERCEPT_DR2_MASK |
746 INTERCEPT_DR3_MASK |
727f5a23 747 INTERCEPT_DR4_MASK |
6aa8b732 748 INTERCEPT_DR5_MASK |
727f5a23 749 INTERCEPT_DR6_MASK |
6aa8b732
AK		 750 INTERCEPT_DR7_MASK;
751
7aa81cc0 752 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 753 (1 << UD_VECTOR) |
754 (1 << MC_VECTOR);
6aa8b732
AK		 755
756
e0231715 757 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 758 (1ULL << INTERCEPT_NMI) |
0152527b 759 (1ULL << INTERCEPT_SMI) |
d225157b 760 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 761 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 762 (1ULL << INTERCEPT_INVD) |
6aa8b732 763 (1ULL << INTERCEPT_HLT) |
a7052897 764 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 765 (1ULL << INTERCEPT_INVLPGA) |
766 (1ULL << INTERCEPT_IOIO_PROT) |
767 (1ULL << INTERCEPT_MSR_PROT) |
768 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 769 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 770 (1ULL << INTERCEPT_VMRUN) |
771 (1ULL << INTERCEPT_VMMCALL) |
772 (1ULL << INTERCEPT_VMLOAD) |
773 (1ULL << INTERCEPT_VMSAVE) |
774 (1ULL << INTERCEPT_STGI) |
775 (1ULL << INTERCEPT_CLGI) |
916ce236 776 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 777 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 778 (1ULL << INTERCEPT_MONITOR) |
779 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 780
781 control->iopm_base_pa = iopm_base;
f65c229c 782 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 783 control->int_ctl = V_INTR_MASKING_MASK;
784
785 init_seg(&save->es);
786 init_seg(&save->ss);
787 init_seg(&save->ds);
788 init_seg(&save->fs);
789 init_seg(&save->gs);
790
791 save->cs.selector = 0xf000;
792 /* Executable/Readable Code Segment */
793 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
794 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
795 save->cs.limit = 0xffff;
d92899a0
AK		 796 /*
797 * cs.base should really be 0xffff0000, but vmx can't handle that, so
798 * be consistent with it.
799 *
800 * Replace when we have real mode working for vmx.
801 */
802 save->cs.base = 0xf0000;
6aa8b732
AK		 803
804 save->gdtr.limit = 0xffff;
805 save->idtr.limit = 0xffff;
806
807 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
808 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
809
9962d032 810 save->efer = EFER_SVME;
d77c26fc 811 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 812 save->dr7 = 0x400;
813 save->rflags = 2;
814 save->rip = 0x0000fff0;
5fdbf976 815 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 816
e0231715
JR		 817 /*
818 * This is the guest-visible cr0 value.
18fa000a 819 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 820 */
18fa000a 821 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
49a9b07e 822 (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
18fa000a 823
66aee91a 824 save->cr4 = X86_CR4_PAE;
6aa8b732 825 /* rdx = ?? */
709ddebf
JR		 826
827 if (npt_enabled) {
828 /* Setup VMCB for Nested Paging */
829 control->nested_ctl = 1;
a7052897
MT		 830 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
831 (1ULL << INTERCEPT_INVLPG));
709ddebf 832 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 833 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
834 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 835 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 836 save->cr3 = 0;
837 save->cr4 = 0;
838 }
a79d2f18 839 force_new_asid(&svm->vcpu);
1371d904 840
e6aa9abd 841 svm->nested.vmcb = 0;
2af9194d
JR		 842 svm->vcpu.arch.hflags = 0;
843
565d0998
ML		 844 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
845 control->pause_filter_count = 3000;
846 control->intercept |= (1ULL << INTERCEPT_PAUSE);
847 }
848
2af9194d 849 enable_gif(svm);
6aa8b732
AK		 850}
851
e00c8cf2 852static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 853{
854 struct vcpu_svm *svm = to_svm(vcpu);
855
e6101a96 856 init_vmcb(svm);
70433389 857
c5af89b6 858 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 859 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 860 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
861 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 862 }
5fdbf976
MT		 863 vcpu->arch.regs_avail = ~0;
864 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 865
866 return 0;
04d2cc77
AK		 867}
868
fb3f0f51 869static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 870{
a2fa3e9f 871 struct vcpu_svm *svm;
6aa8b732 872 struct page *page;
f65c229c 873 struct page *msrpm_pages;
b286d5d8 874 struct page *hsave_page;
3d6368ef 875 struct page *nested_msrpm_pages;
fb3f0f51 876 int err;
6aa8b732 877
c16f862d 878 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 879 if (!svm) {
880 err = -ENOMEM;
881 goto out;
882 }
883
884 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
885 if (err)
886 goto free_svm;
887
b7af4043 888 err = -ENOMEM;
6aa8b732 889 page = alloc_page(GFP_KERNEL);
b7af4043 890 if (!page)
fb3f0f51 891 goto uninit;
6aa8b732 892
f65c229c
JR		 893 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
894 if (!msrpm_pages)
b7af4043 895 goto free_page1;
3d6368ef
AG		 896
897 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
898 if (!nested_msrpm_pages)
b7af4043 899 goto free_page2;
f65c229c 900
b286d5d8
AG		 901 hsave_page = alloc_page(GFP_KERNEL);
902 if (!hsave_page)
b7af4043
TY		 903 goto free_page3;
904
e6aa9abd 905 svm->nested.hsave = page_address(hsave_page);
b286d5d8 906
b7af4043
TY		 907 svm->msrpm = page_address(msrpm_pages);
908 svm_vcpu_init_msrpm(svm->msrpm);
909
e6aa9abd 910 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 911 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 912
a2fa3e9f
GH		 913 svm->vmcb = page_address(page);
914 clear_page(svm->vmcb);
915 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
916 svm->asid_generation = 0;
e6101a96 917 init_vmcb(svm);
99e3e30a 918 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 919
10ab25cd
JK		 920 err = fx_init(&svm->vcpu);
921 if (err)
922 goto free_page4;
923
ad312c7c 924 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 925 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 926 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 927
fb3f0f51 928 return &svm->vcpu;
36241b8c 929
10ab25cd
JK		 930free_page4:
931 __free_page(hsave_page);
b7af4043
TY		 932free_page3:
933 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
934free_page2:
935 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
936free_page1:
937 __free_page(page);
fb3f0f51
RR		 938uninit:
939 kvm_vcpu_uninit(&svm->vcpu);
940free_svm:
a4770347 941 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 942out:
943 return ERR_PTR(err);
6aa8b732
AK		 944}
945
946static void svm_free_vcpu(struct kvm_vcpu *vcpu)
947{
a2fa3e9f
GH		 948 struct vcpu_svm *svm = to_svm(vcpu);
949
fb3f0f51 950 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 951 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 952 __free_page(virt_to_page(svm->nested.hsave));
953 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 954 kvm_vcpu_uninit(vcpu);
a4770347 955 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 956}
957
15ad7146 958static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 959{
a2fa3e9f 960 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 961 int i;
0cc5064d 962
0cc5064d 963 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 964 u64 delta;
0cc5064d 965
953899b6
JR		 966 if (check_tsc_unstable()) {
967 /*
968 * Make sure that the guest sees a monotonically
969 * increasing TSC.
970 */
971 delta = vcpu->arch.host_tsc - native_read_tsc();
972 svm->vmcb->control.tsc_offset += delta;
973 if (is_nested(svm))
974 svm->nested.hsave->control.tsc_offset += delta;
975 }
0cc5064d 976 vcpu->cpu = cpu;
2f599714 977 kvm_migrate_timers(vcpu);
4b656b12 978 svm->asid_generation = 0;
0cc5064d 979 }
94dfbdb3
AL		 980
981 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 982 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 983}
984
985static void svm_vcpu_put(struct kvm_vcpu *vcpu)
986{
a2fa3e9f 987 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 988 int i;
989
e1beb1d3 990 ++vcpu->stat.host_state_reload;
94dfbdb3 991 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 992 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 993
e935d48e 994 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 995}
996
6aa8b732
AK		 997static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
998{
a2fa3e9f 999 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1000}
1001
1002static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1003{
a2fa3e9f 1004 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1005}
1006
6de4f3ad
AK		 1007static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1008{
1009 switch (reg) {
1010 case VCPU_EXREG_PDPTR:
1011 BUG_ON(!npt_enabled);
1012 load_pdptrs(vcpu, vcpu->arch.cr3);
1013 break;
1014 default:
1015 BUG();
1016 }
1017}
1018
f0b85051
AG		 1019static void svm_set_vintr(struct vcpu_svm *svm)
1020{
1021 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1022}
1023
1024static void svm_clear_vintr(struct vcpu_svm *svm)
1025{
1026 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1027}
1028
6aa8b732
AK		 1029static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1030{
a2fa3e9f 1031 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1032
1033 switch (seg) {
1034 case VCPU_SREG_CS: return &save->cs;
1035 case VCPU_SREG_DS: return &save->ds;
1036 case VCPU_SREG_ES: return &save->es;
1037 case VCPU_SREG_FS: return &save->fs;
1038 case VCPU_SREG_GS: return &save->gs;
1039 case VCPU_SREG_SS: return &save->ss;
1040 case VCPU_SREG_TR: return &save->tr;
1041 case VCPU_SREG_LDTR: return &save->ldtr;
1042 }
1043 BUG();
8b6d44c7 1044 return NULL;
6aa8b732
AK		 1045}
1046
1047static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1048{
1049 struct vmcb_seg *s = svm_seg(vcpu, seg);
1050
1051 return s->base;
1052}
1053
1054static void svm_get_segment(struct kvm_vcpu *vcpu,
1055 struct kvm_segment *var, int seg)
1056{
1057 struct vmcb_seg *s = svm_seg(vcpu, seg);
1058
1059 var->base = s->base;
1060 var->limit = s->limit;
1061 var->selector = s->selector;
1062 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1063 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1064 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1065 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1066 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1067 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1068 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1069 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1070
e0231715
JR		 1071 /*
1072 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1073 * for cross vendor migration purposes by "not present"
1074 */
1075 var->unusable = !var->present || (var->type == 0);
1076
1fbdc7a5
AP		 1077 switch (seg) {
1078 case VCPU_SREG_CS:
1079 /*
1080 * SVM always stores 0 for the 'G' bit in the CS selector in
1081 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1082 * Intel's VMENTRY has a check on the 'G' bit.
1083 */
25022acc 1084 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1085 break;
1086 case VCPU_SREG_TR:
1087 /*
1088 * Work around a bug where the busy flag in the tr selector
1089 * isn't exposed
1090 */
c0d09828 1091 var->type |= 0x2;
1fbdc7a5
AP		 1092 break;
1093 case VCPU_SREG_DS:
1094 case VCPU_SREG_ES:
1095 case VCPU_SREG_FS:
1096 case VCPU_SREG_GS:
1097 /*
1098 * The accessed bit must always be set in the segment
1099 * descriptor cache, although it can be cleared in the
1100 * descriptor, the cached bit always remains at 1. Since
1101 * Intel has a check on this, set it here to support
1102 * cross-vendor migration.
1103 */
1104 if (!var->unusable)
1105 var->type |= 0x1;
1106 break;
b586eb02 1107 case VCPU_SREG_SS:
e0231715
JR		 1108 /*
1109 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1110 * descriptor is left as 1, although the whole segment has
1111 * been made unusable. Clear it here to pass an Intel VMX
1112 * entry check when cross vendor migrating.
1113 */
1114 if (var->unusable)
1115 var->db = 0;
1116 break;
1fbdc7a5 1117 }
6aa8b732
AK		 1118}
1119
2e4d2653
IE		 1120static int svm_get_cpl(struct kvm_vcpu *vcpu)
1121{
1122 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1123
1124 return save->cpl;
1125}
1126
89a27f4d 1127static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1128{
a2fa3e9f
GH		 1129 struct vcpu_svm *svm = to_svm(vcpu);
1130
89a27f4d
GN		 1131 dt->size = svm->vmcb->save.idtr.limit;
1132 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1133}
1134
89a27f4d 1135static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1136{
a2fa3e9f
GH		 1137 struct vcpu_svm *svm = to_svm(vcpu);
1138
89a27f4d
GN		 1139 svm->vmcb->save.idtr.limit = dt->size;
1140 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1141}
1142
89a27f4d 1143static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1144{
a2fa3e9f
GH		 1145 struct vcpu_svm *svm = to_svm(vcpu);
1146
89a27f4d
GN		 1147 dt->size = svm->vmcb->save.gdtr.limit;
1148 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1149}
1150
89a27f4d 1151static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1152{
a2fa3e9f
GH		 1153 struct vcpu_svm *svm = to_svm(vcpu);
1154
89a27f4d
GN		 1155 svm->vmcb->save.gdtr.limit = dt->size;
1156 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1157}
1158
e8467fda
AK		 1159static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1160{
1161}
1162
25c4c276 1163static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1164{
1165}
1166
d225157b
AK		 1167static void update_cr0_intercept(struct vcpu_svm *svm)
1168{
66a562f7 1169 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1170 ulong gcr0 = svm->vcpu.arch.cr0;
1171 u64 *hcr0 = &svm->vmcb->save.cr0;
1172
1173 if (!svm->vcpu.fpu_active)
1174 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1175 else
1176 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1177 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1178
1179
1180 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1181 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1182 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1183 if (is_nested(svm)) {
1184 struct vmcb *hsave = svm->nested.hsave;
1185
1186 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1187 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1188 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1189 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1190 }
d225157b
AK		 1191 } else {
1192 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1193 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1194 if (is_nested(svm)) {
1195 struct vmcb *hsave = svm->nested.hsave;
1196
1197 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1198 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1199 }
d225157b
AK		 1200 }
1201}
1202
6aa8b732
AK		 1203static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1204{
a2fa3e9f
GH		 1205 struct vcpu_svm *svm = to_svm(vcpu);
1206
7f5d8b56
JR		 1207 if (is_nested(svm)) {
1208 /*
1209 * We are here because we run in nested mode, the host kvm
1210 * intercepts cr0 writes but the l1 hypervisor does not.
1211 * But the L1 hypervisor may intercept selective cr0 writes.
1212 * This needs to be checked here.
1213 */
1214 unsigned long old, new;
1215
1216 /* Remove bits that would trigger a real cr0 write intercept */
1217 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1218 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1219
1220 if (old == new) {
1221 /* cr0 write with ts and mp unchanged */
1222 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1223 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1224 return;
1225 }
1226 }
1227
05b3e0c2 1228#ifdef CONFIG_X86_64
f6801dff 1229 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1230 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1231 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1232 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1233 }
1234
d77c26fc 1235 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1236 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1237 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1238 }
1239 }
1240#endif
ad312c7c 1241 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1242
1243 if (!npt_enabled)
1244 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1245
1246 if (!vcpu->fpu_active)
334df50a 1247 cr0 |= X86_CR0_TS;
709ddebf
JR		 1248 /*
1249 * re-enable caching here because the QEMU bios
1250 * does not do it - this results in some delay at
1251 * reboot
1252 */
1253 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1254 svm->vmcb->save.cr0 = cr0;
d225157b 1255 update_cr0_intercept(svm);
6aa8b732
AK		 1256}
1257
1258static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1259{
6394b649 1260 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1261 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1262
1263 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1264 force_new_asid(vcpu);
6394b649 1265
ec077263
JR		 1266 vcpu->arch.cr4 = cr4;
1267 if (!npt_enabled)
1268 cr4 |= X86_CR4_PAE;
6394b649 1269 cr4 |= host_cr4_mce;
ec077263 1270 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1271}
1272
1273static void svm_set_segment(struct kvm_vcpu *vcpu,
1274 struct kvm_segment *var, int seg)
1275{
a2fa3e9f 1276 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1277 struct vmcb_seg *s = svm_seg(vcpu, seg);
1278
1279 s->base = var->base;
1280 s->limit = var->limit;
1281 s->selector = var->selector;
1282 if (var->unusable)
1283 s->attrib = 0;
1284 else {
1285 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1286 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1287 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1288 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1289 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1290 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1291 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1292 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1293 }
1294 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1295 svm->vmcb->save.cpl
1296 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1297 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1298
1299}
1300
44c11430 1301static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1302{
d0bfb940
JK		 1303 struct vcpu_svm *svm = to_svm(vcpu);
1304
d0bfb940
JK		 1305 svm->vmcb->control.intercept_exceptions &=
1306 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1307
6be7d306 1308 if (svm->nmi_singlestep)
44c11430
GN		 1309 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1310
d0bfb940
JK		 1311 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1312 if (vcpu->guest_debug &
1313 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1314 svm->vmcb->control.intercept_exceptions |=
1315 1 << DB_VECTOR;
1316 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1317 svm->vmcb->control.intercept_exceptions |=
1318 1 << BP_VECTOR;
1319 } else
1320 vcpu->guest_debug = 0;
44c11430
GN		 1321}
1322
355be0b9 1323static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1324{
44c11430
GN		 1325 struct vcpu_svm *svm = to_svm(vcpu);
1326
ae675ef0
JK		 1327 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1328 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1329 else
1330 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1331
355be0b9 1332 update_db_intercept(vcpu);
6aa8b732
AK		 1333}
1334
1335static void load_host_msrs(struct kvm_vcpu *vcpu)
1336{
94dfbdb3 1337#ifdef CONFIG_X86_64
a2fa3e9f 1338 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1339#endif
6aa8b732
AK		 1340}
1341
1342static void save_host_msrs(struct kvm_vcpu *vcpu)
1343{
94dfbdb3 1344#ifdef CONFIG_X86_64
a2fa3e9f 1345 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1346#endif
6aa8b732
AK		 1347}
1348
0fe1e009 1349static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1350{
0fe1e009
TH		 1351 if (sd->next_asid > sd->max_asid) {
1352 ++sd->asid_generation;
1353 sd->next_asid = 1;
a2fa3e9f 1354 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1355 }
1356
0fe1e009
TH		 1357 svm->asid_generation = sd->asid_generation;
1358 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1359}
1360
020df079 1361static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1362{
42dbaa5a 1363 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1364
020df079 1365 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1366}
1367
851ba692 1368static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1369{
6aa8b732
AK		 1370 u64 fault_address;
1371 u32 error_code;
6aa8b732 1372
a2fa3e9f
GH		 1373 fault_address = svm->vmcb->control.exit_info_2;
1374 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1375
229456fc 1376 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1377 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1378 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1379 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1380}
1381
851ba692 1382static int db_interception(struct vcpu_svm *svm)
d0bfb940 1383{
851ba692
AK		 1384 struct kvm_run *kvm_run = svm->vcpu.run;
1385
d0bfb940 1386 if (!(svm->vcpu.guest_debug &
44c11430 1387 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1388 !svm->nmi_singlestep) {
d0bfb940
JK		 1389 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1390 return 1;
1391 }
44c11430 1392
6be7d306
JK		 1393 if (svm->nmi_singlestep) {
1394 svm->nmi_singlestep = false;
44c11430
GN		 1395 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1396 svm->vmcb->save.rflags &=
1397 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1398 update_db_intercept(&svm->vcpu);
1399 }
1400
1401 if (svm->vcpu.guest_debug &
e0231715 1402 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1403 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1404 kvm_run->debug.arch.pc =
1405 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1406 kvm_run->debug.arch.exception = DB_VECTOR;
1407 return 0;
1408 }
1409
1410 return 1;
d0bfb940
JK		 1411}
1412
851ba692 1413static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1414{
851ba692
AK		 1415 struct kvm_run *kvm_run = svm->vcpu.run;
1416
d0bfb940
JK		 1417 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1418 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1419 kvm_run->debug.arch.exception = BP_VECTOR;
1420 return 0;
1421}
1422
851ba692 1423static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1424{
1425 int er;
1426
851ba692 1427 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1428 if (er != EMULATE_DONE)
7ee5d940 1429 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1430 return 1;
1431}
1432
6b52d186 1433static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1434{
6b52d186 1435 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1436 u32 excp;
1437
1438 if (is_nested(svm)) {
1439 u32 h_excp, n_excp;
1440
1441 h_excp = svm->nested.hsave->control.intercept_exceptions;
1442 n_excp = svm->nested.intercept_exceptions;
1443 h_excp &= ~(1 << NM_VECTOR);
1444 excp = h_excp | n_excp;
1445 } else {
1446 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1447 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1448 }
1449
1450 svm->vmcb->control.intercept_exceptions = excp;
1451
e756fc62 1452 svm->vcpu.fpu_active = 1;
d225157b 1453 update_cr0_intercept(svm);
6b52d186 1454}
a2fa3e9f 1455
6b52d186
AK		 1456static int nm_interception(struct vcpu_svm *svm)
1457{
1458 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1459 return 1;
7807fa6c
AL		 1460}
1461
67ec6607
JR		 1462static bool is_erratum_383(void)
1463{
1464 int err, i;
1465 u64 value;
1466
1467 if (!erratum_383_found)
1468 return false;
1469
1470 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1471 if (err)
1472 return false;
1473
1474 /* Bit 62 may or may not be set for this mce */
1475 value &= ~(1ULL << 62);
1476
1477 if (value != 0xb600000000010015ULL)
1478 return false;
1479
1480 /* Clear MCi_STATUS registers */
1481 for (i = 0; i < 6; ++i)
1482 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1483
1484 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1485 if (!err) {
1486 u32 low, high;
1487
1488 value &= ~(1ULL << 2);
1489 low = lower_32_bits(value);
1490 high = upper_32_bits(value);
1491
1492 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1493 }
1494
1495 /* Flush tlb to evict multi-match entries */
1496 __flush_tlb_all();
1497
1498 return true;
1499}
1500
fe5913e4 1501static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1502{
67ec6607
JR		 1503 if (is_erratum_383()) {
1504 /*
1505 * Erratum 383 triggered. Guest state is corrupt so kill the
1506 * guest.
1507 */
1508 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1509
a8eeb04a 1510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1511
1512 return;
1513 }
1514
53371b50
JR		 1515 /*
1516 * On an #MC intercept the MCE handler is not called automatically in
1517 * the host. So do it by hand here.
1518 */
1519 asm volatile (
1520 "int $0x12\n");
1521 /* not sure if we ever come back to this point */
1522
fe5913e4
JR		 1523 return;
1524}
1525
1526static int mc_interception(struct vcpu_svm *svm)
1527{
53371b50
JR		 1528 return 1;
1529}
1530
851ba692 1531static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1532{
851ba692
AK		 1533 struct kvm_run *kvm_run = svm->vcpu.run;
1534
46fe4ddd
JR		 1535 /*
1536 * VMCB is undefined after a SHUTDOWN intercept
1537 * so reinitialize it.
1538 */
a2fa3e9f 1539 clear_page(svm->vmcb);
e6101a96 1540 init_vmcb(svm);
46fe4ddd
JR		 1541
1542 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1543 return 0;
1544}
1545
851ba692 1546static int io_interception(struct vcpu_svm *svm)
6aa8b732 1547{
cf8f70bf 1548 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1549 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1550 int size, in, string;
039576c0 1551 unsigned port;
6aa8b732 1552
e756fc62 1553 ++svm->vcpu.stat.io_exits;
e70669ab 1554 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1555 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1556 if (string || in)
6d77dbfc 1557 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1558
039576c0
AK		 1559 port = io_info >> 16;
1560 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1561 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1562 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1563
1564 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1565}
1566
851ba692 1567static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1568{
1569 return 1;
1570}
1571
851ba692 1572static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1573{
1574 ++svm->vcpu.stat.irq_exits;
1575 return 1;
1576}
1577
851ba692 1578static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1579{
1580 return 1;
1581}
1582
851ba692 1583static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1584{
5fdbf976 1585 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1586 skip_emulated_instruction(&svm->vcpu);
1587 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1588}
1589
851ba692 1590static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1591{
5fdbf976 1592 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1593 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1594 kvm_emulate_hypercall(&svm->vcpu);
1595 return 1;
02e235bc
AK		 1596}
1597
c0725420
AG		 1598static int nested_svm_check_permissions(struct vcpu_svm *svm)
1599{
f6801dff 1600 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1601 || !is_paging(&svm->vcpu)) {
1602 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1603 return 1;
1604 }
1605
1606 if (svm->vmcb->save.cpl) {
1607 kvm_inject_gp(&svm->vcpu, 0);
1608 return 1;
1609 }
1610
1611 return 0;
1612}
1613
cf74a78b
AG		 1614static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1615 bool has_error_code, u32 error_code)
1616{
b8e88bc8
JR		 1617 int vmexit;
1618
0295ad7d
JR		 1619 if (!is_nested(svm))
1620 return 0;
cf74a78b 1621
0295ad7d
JR		 1622 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1623 svm->vmcb->control.exit_code_hi = 0;
1624 svm->vmcb->control.exit_info_1 = error_code;
1625 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1626
b8e88bc8
JR		 1627 vmexit = nested_svm_intercept(svm);
1628 if (vmexit == NESTED_EXIT_DONE)
1629 svm->nested.exit_required = true;
1630
1631 return vmexit;
cf74a78b
AG		 1632}
1633
8fe54654
JR		 1634/* This function returns true if it is save to enable the irq window */
1635static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1636{
26666957 1637 if (!is_nested(svm))
8fe54654 1638 return true;
cf74a78b 1639
26666957 1640 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1641 return true;
cf74a78b 1642
26666957 1643 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1644 return false;
cf74a78b 1645
197717d5
JR		 1646 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1647 svm->vmcb->control.exit_info_1 = 0;
1648 svm->vmcb->control.exit_info_2 = 0;
26666957 1649
cd3ff653
JR		 1650 if (svm->nested.intercept & 1ULL) {
1651 /*
1652 * The #vmexit can't be emulated here directly because this
1653 * code path runs with irqs and preemtion disabled. A
1654 * #vmexit emulation might sleep. Only signal request for
1655 * the #vmexit here.
1656 */
1657 svm->nested.exit_required = true;
236649de 1658 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1659 return false;
cf74a78b
AG		 1660 }
1661
8fe54654 1662 return true;
cf74a78b
AG		 1663}
1664
887f500c
JR		 1665/* This function returns true if it is save to enable the nmi window */
1666static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1667{
1668 if (!is_nested(svm))
1669 return true;
1670
1671 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1672 return true;
1673
1674 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1675 svm->nested.exit_required = true;
1676
1677 return false;
cf74a78b
AG		 1678}
1679
7597f129 1680static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1681{
1682 struct page *page;
1683
6c3bd3d7
JR		 1684 might_sleep();
1685
34f80cfa 1686 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1687 if (is_error_page(page))
1688 goto error;
1689
7597f129
JR		 1690 *_page = page;
1691
1692 return kmap(page);
34f80cfa
JR		 1693
1694error:
1695 kvm_release_page_clean(page);
1696 kvm_inject_gp(&svm->vcpu, 0);
1697
1698 return NULL;
1699}
1700
7597f129 1701static void nested_svm_unmap(struct page *page)
34f80cfa 1702{
7597f129 1703 kunmap(page);
34f80cfa
JR		 1704 kvm_release_page_dirty(page);
1705}
34f80cfa 1706
ce2ac085
JR		 1707static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1708{
1709 unsigned port;
1710 u8 val, bit;
1711 u64 gpa;
34f80cfa 1712
ce2ac085
JR		 1713 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1714 return NESTED_EXIT_HOST;
34f80cfa 1715
ce2ac085
JR		 1716 port = svm->vmcb->control.exit_info_1 >> 16;
1717 gpa = svm->nested.vmcb_iopm + (port / 8);
1718 bit = port % 8;
1719 val = 0;
1720
1721 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1722 val &= (1 << bit);
1723
1724 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1725}
1726
d2477826 1727static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1728{
0d6b3537
JR		 1729 u32 offset, msr, value;
1730 int write, mask;
4c2161ae 1731
3d62d9aa 1732 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1733 return NESTED_EXIT_HOST;
3d62d9aa 1734
0d6b3537
JR		 1735 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1736 offset = svm_msrpm_offset(msr);
1737 write = svm->vmcb->control.exit_info_1 & 1;
1738 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1739
0d6b3537
JR		 1740 if (offset == MSR_INVALID)
1741 return NESTED_EXIT_DONE;
4c2161ae 1742
0d6b3537
JR		 1743 /* Offset is in 32 bit units but need in 8 bit units */
1744 offset *= 4;
4c2161ae 1745
0d6b3537
JR		 1746 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1747 return NESTED_EXIT_DONE;
3d62d9aa 1748
0d6b3537 1749 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1750}
1751
410e4d57 1752static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1753{
cf74a78b 1754 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1755
410e4d57
JR		 1756 switch (exit_code) {
1757 case SVM_EXIT_INTR:
1758 case SVM_EXIT_NMI:
ff47a49b 1759 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1760 return NESTED_EXIT_HOST;
410e4d57 1761 case SVM_EXIT_NPF:
e0231715 1762 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1763 if (npt_enabled)
1764 return NESTED_EXIT_HOST;
1765 break;
410e4d57 1766 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1767 /* When we're shadowing, trap PFs */
410e4d57
JR		 1768 if (!npt_enabled)
1769 return NESTED_EXIT_HOST;
1770 break;
66a562f7
JR		 1771 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1772 nm_interception(svm);
1773 break;
410e4d57
JR		 1774 default:
1775 break;
cf74a78b
AG		 1776 }
1777
410e4d57
JR		 1778 return NESTED_EXIT_CONTINUE;
1779}
1780
1781/*
1782 * If this function returns true, this #vmexit was already handled
1783 */
b8e88bc8 1784static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1785{
1786 u32 exit_code = svm->vmcb->control.exit_code;
1787 int vmexit = NESTED_EXIT_HOST;
1788
cf74a78b 1789 switch (exit_code) {
9c4e40b9 1790 case SVM_EXIT_MSR:
3d62d9aa 1791 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1792 break;
ce2ac085
JR		 1793 case SVM_EXIT_IOIO:
1794 vmexit = nested_svm_intercept_ioio(svm);
1795 break;
cf74a78b
AG		 1796 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1797 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1798 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1799 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1800 break;
1801 }
1802 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1803 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1804 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1805 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1806 break;
1807 }
1808 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1809 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1810 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1811 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1812 break;
1813 }
1814 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1815 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1816 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1817 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1818 break;
1819 }
1820 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1821 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1822 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1823 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1824 break;
1825 }
228070b1
JR		 1826 case SVM_EXIT_ERR: {
1827 vmexit = NESTED_EXIT_DONE;
1828 break;
1829 }
cf74a78b
AG		 1830 default: {
1831 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1832 if (svm->nested.intercept & exit_bits)
410e4d57 1833 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1834 }
1835 }
1836
b8e88bc8
JR		 1837 return vmexit;
1838}
1839
1840static int nested_svm_exit_handled(struct vcpu_svm *svm)
1841{
1842 int vmexit;
1843
1844 vmexit = nested_svm_intercept(svm);
1845
1846 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1847 nested_svm_vmexit(svm);
9c4e40b9
JR		 1848
1849 return vmexit;
cf74a78b
AG		 1850}
1851
0460a979
JR		 1852static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1853{
1854 struct vmcb_control_area *dst = &dst_vmcb->control;
1855 struct vmcb_control_area *from = &from_vmcb->control;
1856
1857 dst->intercept_cr_read = from->intercept_cr_read;
1858 dst->intercept_cr_write = from->intercept_cr_write;
1859 dst->intercept_dr_read = from->intercept_dr_read;
1860 dst->intercept_dr_write = from->intercept_dr_write;
1861 dst->intercept_exceptions = from->intercept_exceptions;
1862 dst->intercept = from->intercept;
1863 dst->iopm_base_pa = from->iopm_base_pa;
1864 dst->msrpm_base_pa = from->msrpm_base_pa;
1865 dst->tsc_offset = from->tsc_offset;
1866 dst->asid = from->asid;
1867 dst->tlb_ctl = from->tlb_ctl;
1868 dst->int_ctl = from->int_ctl;
1869 dst->int_vector = from->int_vector;
1870 dst->int_state = from->int_state;
1871 dst->exit_code = from->exit_code;
1872 dst->exit_code_hi = from->exit_code_hi;
1873 dst->exit_info_1 = from->exit_info_1;
1874 dst->exit_info_2 = from->exit_info_2;
1875 dst->exit_int_info = from->exit_int_info;
1876 dst->exit_int_info_err = from->exit_int_info_err;
1877 dst->nested_ctl = from->nested_ctl;
1878 dst->event_inj = from->event_inj;
1879 dst->event_inj_err = from->event_inj_err;
1880 dst->nested_cr3 = from->nested_cr3;
1881 dst->lbr_ctl = from->lbr_ctl;
1882}
1883
34f80cfa 1884static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1885{
34f80cfa 1886 struct vmcb *nested_vmcb;
e6aa9abd 1887 struct vmcb *hsave = svm->nested.hsave;
33740e40 1888 struct vmcb *vmcb = svm->vmcb;
7597f129 1889 struct page *page;
cf74a78b 1890
17897f36
JR		 1891 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1892 vmcb->control.exit_info_1,
1893 vmcb->control.exit_info_2,
1894 vmcb->control.exit_int_info,
1895 vmcb->control.exit_int_info_err);
1896
7597f129 1897 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1898 if (!nested_vmcb)
1899 return 1;
1900
06fc7772
JR		 1901 /* Exit nested SVM mode */
1902 svm->nested.vmcb = 0;
1903
cf74a78b 1904 /* Give the current vmcb to the guest */
33740e40
JR		 1905 disable_gif(svm);
1906
1907 nested_vmcb->save.es = vmcb->save.es;
1908 nested_vmcb->save.cs = vmcb->save.cs;
1909 nested_vmcb->save.ss = vmcb->save.ss;
1910 nested_vmcb->save.ds = vmcb->save.ds;
1911 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1912 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 1913 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 1914 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1915 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1916 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1917 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1918 nested_vmcb->save.rflags = vmcb->save.rflags;
1919 nested_vmcb->save.rip = vmcb->save.rip;
1920 nested_vmcb->save.rsp = vmcb->save.rsp;
1921 nested_vmcb->save.rax = vmcb->save.rax;
1922 nested_vmcb->save.dr7 = vmcb->save.dr7;
1923 nested_vmcb->save.dr6 = vmcb->save.dr6;
1924 nested_vmcb->save.cpl = vmcb->save.cpl;
1925
1926 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1927 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1928 nested_vmcb->control.int_state = vmcb->control.int_state;
1929 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1930 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1931 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1932 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1933 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1934 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 1935 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 1936
1937 /*
1938 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1939 * to make sure that we do not lose injected events. So check event_inj
1940 * here and copy it to exit_int_info if it is valid.
1941 * Exit_int_info and event_inj can't be both valid because the case
1942 * below only happens on a VMRUN instruction intercept which has
1943 * no valid exit_int_info set.
1944 */
1945 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1946 struct vmcb_control_area *nc = &nested_vmcb->control;
1947
1948 nc->exit_int_info = vmcb->control.event_inj;
1949 nc->exit_int_info_err = vmcb->control.event_inj_err;
1950 }
1951
33740e40
JR		 1952 nested_vmcb->control.tlb_ctl = 0;
1953 nested_vmcb->control.event_inj = 0;
1954 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1955
1956 /* We always set V_INTR_MASKING and remember the old value in hflags */
1957 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1958 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1959
cf74a78b 1960 /* Restore the original control entries */
0460a979 1961 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1962
219b65dc
AG		 1963 kvm_clear_exception_queue(&svm->vcpu);
1964 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1965
1966 /* Restore selected save entries */
1967 svm->vmcb->save.es = hsave->save.es;
1968 svm->vmcb->save.cs = hsave->save.cs;
1969 svm->vmcb->save.ss = hsave->save.ss;
1970 svm->vmcb->save.ds = hsave->save.ds;
1971 svm->vmcb->save.gdtr = hsave->save.gdtr;
1972 svm->vmcb->save.idtr = hsave->save.idtr;
1973 svm->vmcb->save.rflags = hsave->save.rflags;
1974 svm_set_efer(&svm->vcpu, hsave->save.efer);
1975 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1976 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1977 if (npt_enabled) {
1978 svm->vmcb->save.cr3 = hsave->save.cr3;
1979 svm->vcpu.arch.cr3 = hsave->save.cr3;
1980 } else {
2390218b 1981 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 1982 }
1983 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1984 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1985 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1986 svm->vmcb->save.dr7 = 0;
1987 svm->vmcb->save.cpl = 0;
1988 svm->vmcb->control.exit_int_info = 0;
1989
7597f129 1990 nested_svm_unmap(page);
cf74a78b
AG		 1991
1992 kvm_mmu_reset_context(&svm->vcpu);
1993 kvm_mmu_load(&svm->vcpu);
1994
1995 return 0;
1996}
3d6368ef 1997
9738b2c9 1998static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1999{
323c3d80
JR		 2000 /*
2001 * This function merges the msr permission bitmaps of kvm and the
2002 * nested vmcb. It is omptimized in that it only merges the parts where
2003 * the kvm msr permission bitmap may contain zero bits
2004 */
3d6368ef 2005 int i;
9738b2c9 2006
323c3d80
JR		 2007 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2008 return true;
9738b2c9 2009
323c3d80
JR		 2010 for (i = 0; i < MSRPM_OFFSETS; i++) {
2011 u32 value, p;
2012 u64 offset;
9738b2c9 2013
323c3d80
JR		 2014 if (msrpm_offsets[i] == 0xffffffff)
2015 break;
3d6368ef 2016
0d6b3537
JR		 2017 p = msrpm_offsets[i];
2018 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2019
2020 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2021 return false;
2022
2023 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2024 }
3d6368ef 2025
323c3d80 2026 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2027
2028 return true;
3d6368ef
AG		 2029}
2030
52c65a30
JR		 2031static bool nested_vmcb_checks(struct vmcb *vmcb)
2032{
2033 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2034 return false;
2035
dbe77584
JR		 2036 if (vmcb->control.asid == 0)
2037 return false;
2038
52c65a30
JR		 2039 return true;
2040}
2041
9738b2c9 2042static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2043{
9738b2c9 2044 struct vmcb *nested_vmcb;
e6aa9abd 2045 struct vmcb *hsave = svm->nested.hsave;
defbba56 2046 struct vmcb *vmcb = svm->vmcb;
7597f129 2047 struct page *page;
06fc7772 2048 u64 vmcb_gpa;
3d6368ef 2049
06fc7772 2050 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2051
7597f129 2052 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2053 if (!nested_vmcb)
2054 return false;
2055
52c65a30
JR		 2056 if (!nested_vmcb_checks(nested_vmcb)) {
2057 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2058 nested_vmcb->control.exit_code_hi = 0;
2059 nested_vmcb->control.exit_info_1 = 0;
2060 nested_vmcb->control.exit_info_2 = 0;
2061
2062 nested_svm_unmap(page);
2063
2064 return false;
2065 }
2066
ecf1405d 2067 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 2068 nested_vmcb->save.rip,
2069 nested_vmcb->control.int_ctl,
2070 nested_vmcb->control.event_inj,
2071 nested_vmcb->control.nested_ctl);
2072
2e554e8d
JR		 2073 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2074 nested_vmcb->control.intercept_cr_write,
2075 nested_vmcb->control.intercept_exceptions,
2076 nested_vmcb->control.intercept);
2077
3d6368ef 2078 /* Clear internal status */
219b65dc
AG		 2079 kvm_clear_exception_queue(&svm->vcpu);
2080 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2081
e0231715
JR		 2082 /*
2083 * Save the old vmcb, so we don't need to pick what we save, but can
2084 * restore everything when a VMEXIT occurs
2085 */
defbba56
JR		 2086 hsave->save.es = vmcb->save.es;
2087 hsave->save.cs = vmcb->save.cs;
2088 hsave->save.ss = vmcb->save.ss;
2089 hsave->save.ds = vmcb->save.ds;
2090 hsave->save.gdtr = vmcb->save.gdtr;
2091 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2092 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2093 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2094 hsave->save.cr4 = svm->vcpu.arch.cr4;
2095 hsave->save.rflags = vmcb->save.rflags;
2096 hsave->save.rip = svm->next_rip;
2097 hsave->save.rsp = vmcb->save.rsp;
2098 hsave->save.rax = vmcb->save.rax;
2099 if (npt_enabled)
2100 hsave->save.cr3 = vmcb->save.cr3;
2101 else
2102 hsave->save.cr3 = svm->vcpu.arch.cr3;
2103
0460a979 2104 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2105
2106 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2107 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2108 else
2109 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2110
2111 /* Load the nested guest state */
2112 svm->vmcb->save.es = nested_vmcb->save.es;
2113 svm->vmcb->save.cs = nested_vmcb->save.cs;
2114 svm->vmcb->save.ss = nested_vmcb->save.ss;
2115 svm->vmcb->save.ds = nested_vmcb->save.ds;
2116 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2117 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2118 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2119 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2120 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2121 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2122 if (npt_enabled) {
2123 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2124 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2125 } else
2390218b 2126 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2127
2128 /* Guest paging mode is active - reset mmu */
2129 kvm_mmu_reset_context(&svm->vcpu);
2130
defbba56 2131 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2132 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2133 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2134 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2135
3d6368ef
AG		 2136 /* In case we don't even reach vcpu_run, the fields are not updated */
2137 svm->vmcb->save.rax = nested_vmcb->save.rax;
2138 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2139 svm->vmcb->save.rip = nested_vmcb->save.rip;
2140 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2141 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2142 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2143
f7138538 2144 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2145 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2146
aad42c64
JR		 2147 /* cache intercepts */
2148 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2149 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2150 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2151 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2152 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2153 svm->nested.intercept = nested_vmcb->control.intercept;
2154
3d6368ef 2155 force_new_asid(&svm->vcpu);
3d6368ef 2156 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2157 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2158 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2159 else
2160 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2161
88ab24ad
JR		 2162 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2163 /* We only want the cr8 intercept bits of the guest */
2164 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2165 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2166 }
2167
0d945bd9
JR		 2168 /* We don't want to see VMMCALLs from a nested guest */
2169 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2170
e0231715
JR		 2171 /*
2172 * We don't want a nested guest to be more powerful than the guest, so
2173 * all intercepts are ORed
2174 */
88ab24ad
JR		 2175 svm->vmcb->control.intercept_cr_read |=
2176 nested_vmcb->control.intercept_cr_read;
2177 svm->vmcb->control.intercept_cr_write |=
2178 nested_vmcb->control.intercept_cr_write;
2179 svm->vmcb->control.intercept_dr_read |=
2180 nested_vmcb->control.intercept_dr_read;
2181 svm->vmcb->control.intercept_dr_write |=
2182 nested_vmcb->control.intercept_dr_write;
2183 svm->vmcb->control.intercept_exceptions |=
2184 nested_vmcb->control.intercept_exceptions;
2185
2186 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2187
2188 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2189 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2190 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2191 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2192 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2193 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2194
7597f129 2195 nested_svm_unmap(page);
9738b2c9 2196
06fc7772
JR		 2197 /* nested_vmcb is our indicator if nested SVM is activated */
2198 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2199
2af9194d 2200 enable_gif(svm);
3d6368ef 2201
9738b2c9 2202 return true;
3d6368ef
AG		 2203}
2204
9966bf68 2205static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2206{
2207 to_vmcb->save.fs = from_vmcb->save.fs;
2208 to_vmcb->save.gs = from_vmcb->save.gs;
2209 to_vmcb->save.tr = from_vmcb->save.tr;
2210 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2211 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2212 to_vmcb->save.star = from_vmcb->save.star;
2213 to_vmcb->save.lstar = from_vmcb->save.lstar;
2214 to_vmcb->save.cstar = from_vmcb->save.cstar;
2215 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2216 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2217 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2218 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2219}
2220
851ba692 2221static int vmload_interception(struct vcpu_svm *svm)
5542675b 2222{
9966bf68 2223 struct vmcb *nested_vmcb;
7597f129 2224 struct page *page;
9966bf68 2225
5542675b
AG		 2226 if (nested_svm_check_permissions(svm))
2227 return 1;
2228
2229 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2230 skip_emulated_instruction(&svm->vcpu);
2231
7597f129 2232 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2233 if (!nested_vmcb)
2234 return 1;
2235
2236 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2237 nested_svm_unmap(page);
5542675b
AG		 2238
2239 return 1;
2240}
2241
851ba692 2242static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2243{
9966bf68 2244 struct vmcb *nested_vmcb;
7597f129 2245 struct page *page;
9966bf68 2246
5542675b
AG		 2247 if (nested_svm_check_permissions(svm))
2248 return 1;
2249
2250 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2251 skip_emulated_instruction(&svm->vcpu);
2252
7597f129 2253 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2254 if (!nested_vmcb)
2255 return 1;
2256
2257 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2258 nested_svm_unmap(page);
5542675b
AG		 2259
2260 return 1;
2261}
2262
851ba692 2263static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2264{
3d6368ef
AG		 2265 if (nested_svm_check_permissions(svm))
2266 return 1;
2267
2268 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2269 skip_emulated_instruction(&svm->vcpu);
2270
9738b2c9 2271 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2272 return 1;
2273
9738b2c9 2274 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2275 goto failed;
2276
2277 return 1;
2278
2279failed:
2280
2281 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2282 svm->vmcb->control.exit_code_hi = 0;
2283 svm->vmcb->control.exit_info_1 = 0;
2284 svm->vmcb->control.exit_info_2 = 0;
2285
2286 nested_svm_vmexit(svm);
3d6368ef
AG		 2287
2288 return 1;
2289}
2290
851ba692 2291static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2292{
2293 if (nested_svm_check_permissions(svm))
2294 return 1;
2295
2296 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2297 skip_emulated_instruction(&svm->vcpu);
2298
2af9194d 2299 enable_gif(svm);
1371d904
AG		 2300
2301 return 1;
2302}
2303
851ba692 2304static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2305{
2306 if (nested_svm_check_permissions(svm))
2307 return 1;
2308
2309 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2310 skip_emulated_instruction(&svm->vcpu);
2311
2af9194d 2312 disable_gif(svm);
1371d904
AG		 2313
2314 /* After a CLGI no interrupts should come */
2315 svm_clear_vintr(svm);
2316 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2317
2318 return 1;
2319}
2320
851ba692 2321static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2322{
2323 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2324
ec1ff790
JR		 2325 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2326 vcpu->arch.regs[VCPU_REGS_RAX]);
2327
ff092385
AG		 2328 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2329 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2330
2331 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2332 skip_emulated_instruction(&svm->vcpu);
2333 return 1;
2334}
2335
532a46b9
JR		 2336static int skinit_interception(struct vcpu_svm *svm)
2337{
2338 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2339
2340 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2341 return 1;
2342}
2343
851ba692 2344static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2345{
7ee5d940 2346 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2347 return 1;
2348}
2349
851ba692 2350static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2351{
37817f29 2352 u16 tss_selector;
64a7ec06
GN		 2353 int reason;
2354 int int_type = svm->vmcb->control.exit_int_info &
2355 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2356 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2357 uint32_t type =
2358 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2359 uint32_t idt_v =
2360 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2361 bool has_error_code = false;
2362 u32 error_code = 0;
37817f29
IE		 2363
2364 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2365
37817f29
IE		 2366 if (svm->vmcb->control.exit_info_2 &
2367 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2368 reason = TASK_SWITCH_IRET;
2369 else if (svm->vmcb->control.exit_info_2 &
2370 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2371 reason = TASK_SWITCH_JMP;
fe8e7f83 2372 else if (idt_v)
64a7ec06
GN		 2373 reason = TASK_SWITCH_GATE;
2374 else
2375 reason = TASK_SWITCH_CALL;
2376
fe8e7f83
GN		 2377 if (reason == TASK_SWITCH_GATE) {
2378 switch (type) {
2379 case SVM_EXITINTINFO_TYPE_NMI:
2380 svm->vcpu.arch.nmi_injected = false;
2381 break;
2382 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2383 if (svm->vmcb->control.exit_info_2 &
2384 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2385 has_error_code = true;
2386 error_code =
2387 (u32)svm->vmcb->control.exit_info_2;
2388 }
fe8e7f83
GN		 2389 kvm_clear_exception_queue(&svm->vcpu);
2390 break;
2391 case SVM_EXITINTINFO_TYPE_INTR:
2392 kvm_clear_interrupt_queue(&svm->vcpu);
2393 break;
2394 default:
2395 break;
2396 }
2397 }
64a7ec06 2398
8317c298
GN		 2399 if (reason != TASK_SWITCH_GATE ||
2400 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2401 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2402 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2403 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2404
acb54517
GN		 2405 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2406 has_error_code, error_code) == EMULATE_FAIL) {
2407 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2408 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2409 svm->vcpu.run->internal.ndata = 0;
2410 return 0;
2411 }
2412 return 1;
6aa8b732
AK		 2413}
2414
851ba692 2415static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2416{
5fdbf976 2417 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2418 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2419 return 1;
6aa8b732
AK		 2420}
2421
851ba692 2422static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2423{
2424 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2425 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2426 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2427 return 1;
2428}
2429
851ba692 2430static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2431{
6d77dbfc 2432 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2433}
2434
851ba692 2435static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2436{
6d77dbfc 2437 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2438}
2439
851ba692 2440static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2441{
851ba692
AK		 2442 struct kvm_run *kvm_run = svm->vcpu.run;
2443
0a5fff19
GN		 2444 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2445 /* instruction emulation calls kvm_set_cr8() */
851ba692 2446 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2447 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2448 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2449 return 1;
95ba8273 2450 }
0a5fff19
GN		 2451 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2452 return 1;
1d075434
JR		 2453 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2454 return 0;
2455}
2456
6aa8b732
AK		 2457static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2458{
a2fa3e9f
GH		 2459 struct vcpu_svm *svm = to_svm(vcpu);
2460
6aa8b732 2461 switch (ecx) {
af24a4e4 2462 case MSR_IA32_TSC: {
20824f30 2463 u64 tsc_offset;
6aa8b732 2464
20824f30
JR		 2465 if (is_nested(svm))
2466 tsc_offset = svm->nested.hsave->control.tsc_offset;
2467 else
2468 tsc_offset = svm->vmcb->control.tsc_offset;
2469
2470 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2471 break;
2472 }
8c06585d 2473 case MSR_STAR:
a2fa3e9f 2474 *data = svm->vmcb->save.star;
6aa8b732 2475 break;
0e859cac 2476#ifdef CONFIG_X86_64
6aa8b732 2477 case MSR_LSTAR:
a2fa3e9f 2478 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2479 break;
2480 case MSR_CSTAR:
a2fa3e9f 2481 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2482 break;
2483 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2484 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2485 break;
2486 case MSR_SYSCALL_MASK:
a2fa3e9f 2487 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2488 break;
2489#endif
2490 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2491 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2492 break;
2493 case MSR_IA32_SYSENTER_EIP:
017cb99e 2494 *data = svm->sysenter_eip;
6aa8b732
AK		 2495 break;
2496 case MSR_IA32_SYSENTER_ESP:
017cb99e 2497 *data = svm->sysenter_esp;
6aa8b732 2498 break;
e0231715
JR		 2499 /*
2500 * Nobody will change the following 5 values in the VMCB so we can
2501 * safely return them on rdmsr. They will always be 0 until LBRV is
2502 * implemented.
2503 */
a2938c80
JR		 2504 case MSR_IA32_DEBUGCTLMSR:
2505 *data = svm->vmcb->save.dbgctl;
2506 break;
2507 case MSR_IA32_LASTBRANCHFROMIP:
2508 *data = svm->vmcb->save.br_from;
2509 break;
2510 case MSR_IA32_LASTBRANCHTOIP:
2511 *data = svm->vmcb->save.br_to;
2512 break;
2513 case MSR_IA32_LASTINTFROMIP:
2514 *data = svm->vmcb->save.last_excp_from;
2515 break;
2516 case MSR_IA32_LASTINTTOIP:
2517 *data = svm->vmcb->save.last_excp_to;
2518 break;
b286d5d8 2519 case MSR_VM_HSAVE_PA:
e6aa9abd 2520 *data = svm->nested.hsave_msr;
b286d5d8 2521 break;
eb6f302e 2522 case MSR_VM_CR:
4a810181 2523 *data = svm->nested.vm_cr_msr;
eb6f302e 2524 break;
c8a73f18
AG		 2525 case MSR_IA32_UCODE_REV:
2526 *data = 0x01000065;
2527 break;
6aa8b732 2528 default:
3bab1f5d 2529 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2530 }
2531 return 0;
2532}
2533
851ba692 2534static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2535{
ad312c7c 2536 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2537 u64 data;
2538
59200273
AK		 2539 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2540 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2541 kvm_inject_gp(&svm->vcpu, 0);
59200273 2542 } else {
229456fc 2543 trace_kvm_msr_read(ecx, data);
af9ca2d7 2544
5fdbf976 2545 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2546 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2547 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2548 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2549 }
2550 return 1;
2551}
2552
4a810181
JR		 2553static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2554{
2555 struct vcpu_svm *svm = to_svm(vcpu);
2556 int svm_dis, chg_mask;
2557
2558 if (data & ~SVM_VM_CR_VALID_MASK)
2559 return 1;
2560
2561 chg_mask = SVM_VM_CR_VALID_MASK;
2562
2563 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2564 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2565
2566 svm->nested.vm_cr_msr &= ~chg_mask;
2567 svm->nested.vm_cr_msr |= (data & chg_mask);
2568
2569 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2570
2571 /* check for svm_disable while efer.svme is set */
2572 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2573 return 1;
2574
2575 return 0;
2576}
2577
6aa8b732
AK		 2578static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2579{
a2fa3e9f
GH		 2580 struct vcpu_svm *svm = to_svm(vcpu);
2581
6aa8b732 2582 switch (ecx) {
f4e1b3c8 2583 case MSR_IA32_TSC:
99e3e30a 2584 kvm_write_tsc(vcpu, data);
6aa8b732 2585 break;
8c06585d 2586 case MSR_STAR:
a2fa3e9f 2587 svm->vmcb->save.star = data;
6aa8b732 2588 break;
49b14f24 2589#ifdef CONFIG_X86_64
6aa8b732 2590 case MSR_LSTAR:
a2fa3e9f 2591 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2592 break;
2593 case MSR_CSTAR:
a2fa3e9f 2594 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2595 break;
2596 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2597 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2598 break;
2599 case MSR_SYSCALL_MASK:
a2fa3e9f 2600 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2601 break;
2602#endif
2603 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2604 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2605 break;
2606 case MSR_IA32_SYSENTER_EIP:
017cb99e 2607 svm->sysenter_eip = data;
a2fa3e9f 2608 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2609 break;
2610 case MSR_IA32_SYSENTER_ESP:
017cb99e 2611 svm->sysenter_esp = data;
a2fa3e9f 2612 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2613 break;
a2938c80 2614 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2615 if (!svm_has(SVM_FEATURE_LBRV)) {
2616 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2617 __func__, data);
24e09cbf
JR		 2618 break;
2619 }
2620 if (data & DEBUGCTL_RESERVED_BITS)
2621 return 1;
2622
2623 svm->vmcb->save.dbgctl = data;
2624 if (data & (1ULL<<0))
2625 svm_enable_lbrv(svm);
2626 else
2627 svm_disable_lbrv(svm);
a2938c80 2628 break;
b286d5d8 2629 case MSR_VM_HSAVE_PA:
e6aa9abd 2630 svm->nested.hsave_msr = data;
62b9abaa 2631 break;
3c5d0a44 2632 case MSR_VM_CR:
4a810181 2633 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2634 case MSR_VM_IGNNE:
3c5d0a44
AG		 2635 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2636 break;
6aa8b732 2637 default:
3bab1f5d 2638 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2639 }
2640 return 0;
2641}
2642
851ba692 2643static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2644{
ad312c7c 2645 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2646 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2647 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2648
af9ca2d7 2649
5fdbf976 2650 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2651 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2652 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2653 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2654 } else {
2655 trace_kvm_msr_write(ecx, data);
e756fc62 2656 skip_emulated_instruction(&svm->vcpu);
59200273 2657 }
6aa8b732
AK		 2658 return 1;
2659}
2660
851ba692 2661static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2662{
e756fc62 2663 if (svm->vmcb->control.exit_info_1)
851ba692 2664 return wrmsr_interception(svm);
6aa8b732 2665 else
851ba692 2666 return rdmsr_interception(svm);
6aa8b732
AK		 2667}
2668
851ba692 2669static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2670{
851ba692
AK		 2671 struct kvm_run *kvm_run = svm->vcpu.run;
2672
f0b85051 2673 svm_clear_vintr(svm);
85f455f7 2674 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2675 /*
2676 * If the user space waits to inject interrupts, exit as soon as
2677 * possible
2678 */
8061823a
GN		 2679 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2680 kvm_run->request_interrupt_window &&
2681 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2682 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2683 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2684 return 0;
2685 }
2686
2687 return 1;
2688}
2689
565d0998
ML		 2690static int pause_interception(struct vcpu_svm *svm)
2691{
2692 kvm_vcpu_on_spin(&(svm->vcpu));
2693 return 1;
2694}
2695
851ba692 2696static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2697 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2698 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2699 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2700 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2701 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2702 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2703 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2704 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2705 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2706 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2707 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2708 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2709 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2710 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2711 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2712 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2713 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2714 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2715 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2716 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2717 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2718 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2719 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2720 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2721 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2722 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2723 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2724 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2725 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2726 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2727 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2728 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2729 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2730 [SVM_EXIT_SMI] = nop_on_interception,
2731 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2732 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2733 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2734 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2735 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2736 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2737 [SVM_EXIT_HLT] = halt_interception,
a7052897 2738 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2739 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2740 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2741 [SVM_EXIT_MSR] = msr_interception,
2742 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2743 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2744 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2745 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2746 [SVM_EXIT_VMLOAD] = vmload_interception,
2747 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2748 [SVM_EXIT_STGI] = stgi_interception,
2749 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2750 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2751 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2752 [SVM_EXIT_MONITOR] = invalid_op_interception,
2753 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2754 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2755};
2756
3f10c846
JR		 2757void dump_vmcb(struct kvm_vcpu *vcpu)
2758{
2759 struct vcpu_svm *svm = to_svm(vcpu);
2760 struct vmcb_control_area *control = &svm->vmcb->control;
2761 struct vmcb_save_area *save = &svm->vmcb->save;
2762
2763 pr_err("VMCB Control Area:\n");
2764 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2765 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2766 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2767 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2768 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2769 pr_err("intercepts: %016llx\n", control->intercept);
2770 pr_err("pause filter count: %d\n", control->pause_filter_count);
2771 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2772 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2773 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2774 pr_err("asid: %d\n", control->asid);
2775 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2776 pr_err("int_ctl: %08x\n", control->int_ctl);
2777 pr_err("int_vector: %08x\n", control->int_vector);
2778 pr_err("int_state: %08x\n", control->int_state);
2779 pr_err("exit_code: %08x\n", control->exit_code);
2780 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2781 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2782 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2783 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2784 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2785 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2786 pr_err("event_inj: %08x\n", control->event_inj);
2787 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2788 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2789 pr_err("next_rip: %016llx\n", control->next_rip);
2790 pr_err("VMCB State Save Area:\n");
2791 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2792 save->es.selector, save->es.attrib,
2793 save->es.limit, save->es.base);
2794 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2795 save->cs.selector, save->cs.attrib,
2796 save->cs.limit, save->cs.base);
2797 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2798 save->ss.selector, save->ss.attrib,
2799 save->ss.limit, save->ss.base);
2800 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2801 save->ds.selector, save->ds.attrib,
2802 save->ds.limit, save->ds.base);
2803 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2804 save->fs.selector, save->fs.attrib,
2805 save->fs.limit, save->fs.base);
2806 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2807 save->gs.selector, save->gs.attrib,
2808 save->gs.limit, save->gs.base);
2809 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2810 save->gdtr.selector, save->gdtr.attrib,
2811 save->gdtr.limit, save->gdtr.base);
2812 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2813 save->ldtr.selector, save->ldtr.attrib,
2814 save->ldtr.limit, save->ldtr.base);
2815 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2816 save->idtr.selector, save->idtr.attrib,
2817 save->idtr.limit, save->idtr.base);
2818 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2819 save->tr.selector, save->tr.attrib,
2820 save->tr.limit, save->tr.base);
2821 pr_err("cpl: %d efer: %016llx\n",
2822 save->cpl, save->efer);
2823 pr_err("cr0: %016llx cr2: %016llx\n",
2824 save->cr0, save->cr2);
2825 pr_err("cr3: %016llx cr4: %016llx\n",
2826 save->cr3, save->cr4);
2827 pr_err("dr6: %016llx dr7: %016llx\n",
2828 save->dr6, save->dr7);
2829 pr_err("rip: %016llx rflags: %016llx\n",
2830 save->rip, save->rflags);
2831 pr_err("rsp: %016llx rax: %016llx\n",
2832 save->rsp, save->rax);
2833 pr_err("star: %016llx lstar: %016llx\n",
2834 save->star, save->lstar);
2835 pr_err("cstar: %016llx sfmask: %016llx\n",
2836 save->cstar, save->sfmask);
2837 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2838 save->kernel_gs_base, save->sysenter_cs);
2839 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2840 save->sysenter_esp, save->sysenter_eip);
2841 pr_err("gpat: %016llx dbgctl: %016llx\n",
2842 save->g_pat, save->dbgctl);
2843 pr_err("br_from: %016llx br_to: %016llx\n",
2844 save->br_from, save->br_to);
2845 pr_err("excp_from: %016llx excp_to: %016llx\n",
2846 save->last_excp_from, save->last_excp_to);
2847
2848}
2849
851ba692 2850static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2851{
04d2cc77 2852 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2853 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2854 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2855
5bfd8b54 2856 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2857
2be4fc7a
JR		 2858 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2859 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2860 if (npt_enabled)
2861 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2862
cd3ff653
JR		 2863 if (unlikely(svm->nested.exit_required)) {
2864 nested_svm_vmexit(svm);
2865 svm->nested.exit_required = false;
2866
2867 return 1;
2868 }
2869
cf74a78b 2870 if (is_nested(svm)) {
410e4d57
JR		 2871 int vmexit;
2872
d8cabddf
JR		 2873 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2874 svm->vmcb->control.exit_info_1,
2875 svm->vmcb->control.exit_info_2,
2876 svm->vmcb->control.exit_int_info,
2877 svm->vmcb->control.exit_int_info_err);
2878
410e4d57
JR		 2879 vmexit = nested_svm_exit_special(svm);
2880
2881 if (vmexit == NESTED_EXIT_CONTINUE)
2882 vmexit = nested_svm_exit_handled(svm);
2883
2884 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2885 return 1;
cf74a78b
AG		 2886 }
2887
a5c3832d
JR		 2888 svm_complete_interrupts(svm);
2889
04d2cc77
AK		 2890 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2891 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2892 kvm_run->fail_entry.hardware_entry_failure_reason
2893 = svm->vmcb->control.exit_code;
3f10c846
JR		 2894 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2895 dump_vmcb(vcpu);
04d2cc77
AK		 2896 return 0;
2897 }
2898
a2fa3e9f 2899 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2900 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2901 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2902 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2903 "exit_code 0x%x\n",
b8688d51 2904 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2905 exit_code);
2906
9d8f549d 2907 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2908 || !svm_exit_handlers[exit_code]) {
6aa8b732 2909 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2910 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2911 return 0;
2912 }
2913
851ba692 2914 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2915}
2916
2917static void reload_tss(struct kvm_vcpu *vcpu)
2918{
2919 int cpu = raw_smp_processor_id();
2920
0fe1e009
TH		 2921 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2922 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2923 load_TR_desc();
2924}
2925
e756fc62 2926static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2927{
2928 int cpu = raw_smp_processor_id();
2929
0fe1e009 2930 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2931
a2fa3e9f 2932 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2933 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2934 if (svm->asid_generation != sd->asid_generation)
2935 new_asid(svm, sd);
6aa8b732
AK		 2936}
2937
95ba8273
GN		 2938static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2939{
2940 struct vcpu_svm *svm = to_svm(vcpu);
2941
2942 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2943 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2944 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2945 ++vcpu->stat.nmi_injections;
2946}
6aa8b732 2947
85f455f7 2948static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2949{
2950 struct vmcb_control_area *control;
2951
e756fc62 2952 control = &svm->vmcb->control;
85f455f7 2953 control->int_vector = irq;
6aa8b732
AK		 2954 control->int_ctl &= ~V_INTR_PRIO_MASK;
2955 control->int_ctl |= V_IRQ_MASK |
2956 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2957}
2958
66fd3f7f 2959static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2960{
2961 struct vcpu_svm *svm = to_svm(vcpu);
2962
2af9194d 2963 BUG_ON(!(gif_set(svm)));
cf74a78b 2964
9fb2d2b4
GN		 2965 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2966 ++vcpu->stat.irq_injections;
2967
219b65dc
AG		 2968 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2969 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2970}
2971
95ba8273 2972static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2973{
2974 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2975
88ab24ad
JR		 2976 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2977 return;
2978
95ba8273 2979 if (irr == -1)
aaacfc9a
JR		 2980 return;
2981
95ba8273
GN		 2982 if (tpr >= irr)
2983 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2984}
aaacfc9a 2985
95ba8273
GN		 2986static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2987{
2988 struct vcpu_svm *svm = to_svm(vcpu);
2989 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2990 int ret;
2991 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2992 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2993 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2994
2995 return ret;
aaacfc9a
JR		 2996}
2997
3cfc3092
JK		 2998static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2999{
3000 struct vcpu_svm *svm = to_svm(vcpu);
3001
3002 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3003}
3004
3005static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3006{
3007 struct vcpu_svm *svm = to_svm(vcpu);
3008
3009 if (masked) {
3010 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3011 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3012 } else {
3013 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3014 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3015 }
3016}
3017
78646121
GN		 3018static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3019{
3020 struct vcpu_svm *svm = to_svm(vcpu);
3021 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3022 int ret;
3023
3024 if (!gif_set(svm) ||
3025 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3026 return 0;
3027
3028 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3029
3030 if (is_nested(svm))
3031 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3032
3033 return ret;
78646121
GN		 3034}
3035
9222be18 3036static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3037{
219b65dc 3038 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3039
e0231715
JR		 3040 /*
3041 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3042 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3043 * get that intercept, this function will be called again though and
3044 * we'll get the vintr intercept.
3045 */
8fe54654 3046 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3047 svm_set_vintr(svm);
3048 svm_inject_irq(svm, 0x0);
3049 }
85f455f7
ED		 3050}
3051
95ba8273 3052static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3053{
04d2cc77 3054 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3055
44c11430
GN		 3056 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3057 == HF_NMI_MASK)
3058 return; /* IRET will cause a vm exit */
3059
e0231715
JR		 3060 /*
3061 * Something prevents NMI from been injected. Single step over possible
3062 * problem (IRET or exception injection or interrupt shadow)
3063 */
6be7d306 3064 svm->nmi_singlestep = true;
44c11430
GN		 3065 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3066 update_db_intercept(vcpu);
c1150d8c
DL		 3067}
3068
cbc94022
IE		 3069static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3070{
3071 return 0;
3072}
3073
d9e368d6
AK		 3074static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3075{
3076 force_new_asid(vcpu);
3077}
3078
04d2cc77
AK		 3079static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3080{
3081}
3082
d7bf8221
JR		 3083static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3084{
3085 struct vcpu_svm *svm = to_svm(vcpu);
3086
88ab24ad
JR		 3087 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3088 return;
3089
d7bf8221
JR		 3090 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3091 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3092 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3093 }
3094}
3095
649d6864
JR		 3096static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3097{
3098 struct vcpu_svm *svm = to_svm(vcpu);
3099 u64 cr8;
3100
88ab24ad
JR		 3101 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3102 return;
3103
649d6864
JR		 3104 cr8 = kvm_get_cr8(vcpu);
3105 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3106 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3107}
3108
9222be18
GN		 3109static void svm_complete_interrupts(struct vcpu_svm *svm)
3110{
3111 u8 vector;
3112 int type;
3113 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3114 unsigned int3_injected = svm->int3_injected;
3115
3116 svm->int3_injected = 0;
9222be18 3117
44c11430
GN		 3118 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3119 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3120
9222be18
GN		 3121 svm->vcpu.arch.nmi_injected = false;
3122 kvm_clear_exception_queue(&svm->vcpu);
3123 kvm_clear_interrupt_queue(&svm->vcpu);
3124
3125 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3126 return;
3127
3128 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3129 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3130
3131 switch (type) {
3132 case SVM_EXITINTINFO_TYPE_NMI:
3133 svm->vcpu.arch.nmi_injected = true;
3134 break;
3135 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3136 /*
3137 * In case of software exceptions, do not reinject the vector,
3138 * but re-execute the instruction instead. Rewind RIP first
3139 * if we emulated INT3 before.
3140 */
3141 if (kvm_exception_is_soft(vector)) {
3142 if (vector == BP_VECTOR && int3_injected &&
3143 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3144 kvm_rip_write(&svm->vcpu,
3145 kvm_rip_read(&svm->vcpu) -
3146 int3_injected);
9222be18 3147 break;
66b7138f 3148 }
9222be18
GN		 3149 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3150 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3151 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3152
3153 } else
ce7ddec4 3154 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3155 break;
3156 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3157 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3158 break;
3159 default:
3160 break;
3161 }
3162}
3163
80e31d4f
AK		 3164#ifdef CONFIG_X86_64
3165#define R "r"
3166#else
3167#define R "e"
3168#endif
3169
851ba692 3170static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3171{
a2fa3e9f 3172 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3173 u16 fs_selector;
3174 u16 gs_selector;
3175 u16 ldt_selector;
d9e368d6 3176
2041a06a
JR		 3177 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3178 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3179 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3180
cd3ff653
JR		 3181 /*
3182 * A vmexit emulation is required before the vcpu can be executed
3183 * again.
3184 */
3185 if (unlikely(svm->nested.exit_required))
3186 return;
3187
e756fc62 3188 pre_svm_run(svm);
6aa8b732 3189
649d6864
JR		 3190 sync_lapic_to_cr8(vcpu);
3191
6aa8b732 3192 save_host_msrs(vcpu);
9581d442
AK		 3193 savesegment(fs, fs_selector);
3194 savesegment(gs, gs_selector);
d6e88aec 3195 ldt_selector = kvm_read_ldt();
cda0ffdd 3196 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3197 /* required for live migration with NPT */
3198 if (npt_enabled)
3199 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3200
04d2cc77
AK		 3201 clgi();
3202
3203 local_irq_enable();
36241b8c 3204
6aa8b732 3205 asm volatile (
80e31d4f
AK		 3206 "push %%"R"bp; \n\t"
3207 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3208 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3209 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3210 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3211 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3212 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3213#ifdef CONFIG_X86_64
fb3f0f51
RR		 3214 "mov %c[r8](%[svm]), %%r8 \n\t"
3215 "mov %c[r9](%[svm]), %%r9 \n\t"
3216 "mov %c[r10](%[svm]), %%r10 \n\t"
3217 "mov %c[r11](%[svm]), %%r11 \n\t"
3218 "mov %c[r12](%[svm]), %%r12 \n\t"
3219 "mov %c[r13](%[svm]), %%r13 \n\t"
3220 "mov %c[r14](%[svm]), %%r14 \n\t"
3221 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3222#endif
3223
6aa8b732 3224 /* Enter guest mode */
80e31d4f
AK		 3225 "push %%"R"ax \n\t"
3226 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3227 __ex(SVM_VMLOAD) "\n\t"
3228 __ex(SVM_VMRUN) "\n\t"
3229 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3230 "pop %%"R"ax \n\t"
6aa8b732
AK		 3231
3232 /* Save guest registers, load host registers */
80e31d4f
AK		 3233 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3234 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3235 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3236 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3237 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3238 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3239#ifdef CONFIG_X86_64
fb3f0f51
RR		 3240 "mov %%r8, %c[r8](%[svm]) \n\t"
3241 "mov %%r9, %c[r9](%[svm]) \n\t"
3242 "mov %%r10, %c[r10](%[svm]) \n\t"
3243 "mov %%r11, %c[r11](%[svm]) \n\t"
3244 "mov %%r12, %c[r12](%[svm]) \n\t"
3245 "mov %%r13, %c[r13](%[svm]) \n\t"
3246 "mov %%r14, %c[r14](%[svm]) \n\t"
3247 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3248#endif
80e31d4f 3249 "pop %%"R"bp"
6aa8b732 3250 :
fb3f0f51 3251 : [svm]"a"(svm),
6aa8b732 3252 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3253 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3254 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3255 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3256 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3257 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3258 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3259#ifdef CONFIG_X86_64
ad312c7c
ZX		 3260 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3261 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3262 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3263 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3264 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3265 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3266 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3267 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3268#endif
54a08c04 3269 : "cc", "memory"
80e31d4f 3270 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3271#ifdef CONFIG_X86_64
54a08c04
LV		 3272 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3273#endif
3274 );
6aa8b732 3275
ad312c7c 3276 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3277 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3278 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3279 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3280
6aa8b732 3281 load_host_msrs(vcpu);
9581d442
AK		 3282 loadsegment(fs, fs_selector);
3283#ifdef CONFIG_X86_64
3284 load_gs_index(gs_selector);
3285 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3286#else
3287 loadsegment(gs, gs_selector);
3288#endif
3289 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3290
3291 reload_tss(vcpu);
3292
56ba47dd
AK		 3293 local_irq_disable();
3294
3295 stgi();
3296
d7bf8221
JR		 3297 sync_cr8_to_lapic(vcpu);
3298
a2fa3e9f 3299 svm->next_rip = 0;
9222be18 3300
6de4f3ad
AK		 3301 if (npt_enabled) {
3302 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3303 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3304 }
fe5913e4
JR		 3305
3306 /*
3307 * We need to handle MC intercepts here before the vcpu has a chance to
3308 * change the physical cpu
3309 */
3310 if (unlikely(svm->vmcb->control.exit_code ==
3311 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3312 svm_handle_mce(svm);
6aa8b732
AK		 3313}
3314
80e31d4f
AK		 3315#undef R
3316
6aa8b732
AK		 3317static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3318{
a2fa3e9f
GH		 3319 struct vcpu_svm *svm = to_svm(vcpu);
3320
709ddebf
JR		 3321 if (npt_enabled) {
3322 svm->vmcb->control.nested_cr3 = root;
3323 force_new_asid(vcpu);
3324 return;
3325 }
3326
a2fa3e9f 3327 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3328 force_new_asid(vcpu);
3329}
3330
6aa8b732
AK		 3331static int is_disabled(void)
3332{
6031a61c
JR		 3333 u64 vm_cr;
3334
3335 rdmsrl(MSR_VM_CR, vm_cr);
3336 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3337 return 1;
3338
6aa8b732
AK		 3339 return 0;
3340}
3341
102d8325
IM		 3342static void
3343svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3344{
3345 /*
3346 * Patch in the VMMCALL instruction:
3347 */
3348 hypercall[0] = 0x0f;
3349 hypercall[1] = 0x01;
3350 hypercall[2] = 0xd9;
102d8325
IM		 3351}
3352
002c7f7c
YS		 3353static void svm_check_processor_compat(void *rtn)
3354{
3355 *(int *)rtn = 0;
3356}
3357
774ead3a
AK		 3358static bool svm_cpu_has_accelerated_tpr(void)
3359{
3360 return false;
3361}
3362
67253af5
SY		 3363static int get_npt_level(void)
3364{
3365#ifdef CONFIG_X86_64
3366 return PT64_ROOT_LEVEL;
3367#else
3368 return PT32E_ROOT_LEVEL;
3369#endif
3370}
3371
4b12f0de 3372static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3373{
3374 return 0;
3375}
3376
0e851880
SY		 3377static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3378{
3379}
3380
d4330ef2
JR		 3381static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3382{
c2c63a49
JR		 3383 switch (func) {
3384 case 0x8000000A:
3385 entry->eax = 1; /* SVM revision 1 */
3386 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3387 ASID emulation to nested SVM */
3388 entry->ecx = 0; /* Reserved */
7a190667
JR		 3389 entry->edx = 0; /* Per default do not support any
3390 additional features */
3391
3392 /* Support next_rip if host supports it */
3393 if (svm_has(SVM_FEATURE_NRIP))
3394 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49
JR		 3395
3396 break;
3397 }
d4330ef2
JR		 3398}
3399
229456fc 3400static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3401 { SVM_EXIT_READ_CR0, "read_cr0" },
3402 { SVM_EXIT_READ_CR3, "read_cr3" },
3403 { SVM_EXIT_READ_CR4, "read_cr4" },
3404 { SVM_EXIT_READ_CR8, "read_cr8" },
3405 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3406 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3407 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3408 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3409 { SVM_EXIT_READ_DR0, "read_dr0" },
3410 { SVM_EXIT_READ_DR1, "read_dr1" },
3411 { SVM_EXIT_READ_DR2, "read_dr2" },
3412 { SVM_EXIT_READ_DR3, "read_dr3" },
3413 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3414 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3415 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3416 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3417 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3418 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3419 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3420 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3421 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3422 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3423 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3424 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3425 { SVM_EXIT_INTR, "interrupt" },
3426 { SVM_EXIT_NMI, "nmi" },
3427 { SVM_EXIT_SMI, "smi" },
3428 { SVM_EXIT_INIT, "init" },
3429 { SVM_EXIT_VINTR, "vintr" },
3430 { SVM_EXIT_CPUID, "cpuid" },
3431 { SVM_EXIT_INVD, "invd" },
3432 { SVM_EXIT_HLT, "hlt" },
3433 { SVM_EXIT_INVLPG, "invlpg" },
3434 { SVM_EXIT_INVLPGA, "invlpga" },
3435 { SVM_EXIT_IOIO, "io" },
3436 { SVM_EXIT_MSR, "msr" },
3437 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3438 { SVM_EXIT_SHUTDOWN, "shutdown" },
3439 { SVM_EXIT_VMRUN, "vmrun" },
3440 { SVM_EXIT_VMMCALL, "hypercall" },
3441 { SVM_EXIT_VMLOAD, "vmload" },
3442 { SVM_EXIT_VMSAVE, "vmsave" },
3443 { SVM_EXIT_STGI, "stgi" },
3444 { SVM_EXIT_CLGI, "clgi" },
3445 { SVM_EXIT_SKINIT, "skinit" },
3446 { SVM_EXIT_WBINVD, "wbinvd" },
3447 { SVM_EXIT_MONITOR, "monitor" },
3448 { SVM_EXIT_MWAIT, "mwait" },
3449 { SVM_EXIT_NPF, "npf" },
3450 { -1, NULL }
3451};
3452
17cc3935 3453static int svm_get_lpage_level(void)
344f414f 3454{
17cc3935 3455 return PT_PDPE_LEVEL;
344f414f
JR		 3456}
3457
4e47c7a6
SY		 3458static bool svm_rdtscp_supported(void)
3459{
3460 return false;
3461}
3462
f5f48ee1
SY		 3463static bool svm_has_wbinvd_exit(void)
3464{
3465 return true;
3466}
3467
02daab21
AK		 3468static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3469{
3470 struct vcpu_svm *svm = to_svm(vcpu);
3471
02daab21 3472 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3473 if (is_nested(svm))
3474 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3475 update_cr0_intercept(svm);
02daab21
AK		 3476}
3477
cbdd1bea 3478static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3479 .cpu_has_kvm_support = has_svm,
3480 .disabled_by_bios = is_disabled,
3481 .hardware_setup = svm_hardware_setup,
3482 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3483 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3484 .hardware_enable = svm_hardware_enable,
3485 .hardware_disable = svm_hardware_disable,
774ead3a 3486 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3487
3488 .vcpu_create = svm_create_vcpu,
3489 .vcpu_free = svm_free_vcpu,
04d2cc77 3490 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3491
04d2cc77 3492 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3493 .vcpu_load = svm_vcpu_load,
3494 .vcpu_put = svm_vcpu_put,
3495
3496 .set_guest_debug = svm_guest_debug,
3497 .get_msr = svm_get_msr,
3498 .set_msr = svm_set_msr,
3499 .get_segment_base = svm_get_segment_base,
3500 .get_segment = svm_get_segment,
3501 .set_segment = svm_set_segment,
2e4d2653 3502 .get_cpl = svm_get_cpl,
1747fb71 3503 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3504 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3505 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3506 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3507 .set_cr3 = svm_set_cr3,
3508 .set_cr4 = svm_set_cr4,
3509 .set_efer = svm_set_efer,
3510 .get_idt = svm_get_idt,
3511 .set_idt = svm_set_idt,
3512 .get_gdt = svm_get_gdt,
3513 .set_gdt = svm_set_gdt,
020df079 3514 .set_dr7 = svm_set_dr7,
6de4f3ad 3515 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3516 .get_rflags = svm_get_rflags,
3517 .set_rflags = svm_set_rflags,
6b52d186 3518 .fpu_activate = svm_fpu_activate,
02daab21 3519 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3520
6aa8b732 3521 .tlb_flush = svm_flush_tlb,
6aa8b732 3522
6aa8b732 3523 .run = svm_vcpu_run,
04d2cc77 3524 .handle_exit = handle_exit,
6aa8b732 3525 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3526 .set_interrupt_shadow = svm_set_interrupt_shadow,
3527 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3528 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3529 .set_irq = svm_set_irq,
95ba8273 3530 .set_nmi = svm_inject_nmi,
298101da 3531 .queue_exception = svm_queue_exception,
78646121 3532 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3533 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3534 .get_nmi_mask = svm_get_nmi_mask,
3535 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3536 .enable_nmi_window = enable_nmi_window,
3537 .enable_irq_window = enable_irq_window,
3538 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3539
3540 .set_tss_addr = svm_set_tss_addr,
67253af5 3541 .get_tdp_level = get_npt_level,
4b12f0de 3542 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3543
3544 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3545 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3546
3547 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3548
3549 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3550
3551 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3552
3553 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3554
3555 .write_tsc_offset = svm_write_tsc_offset,
6aa8b732
AK		 3556};
3557
3558static int __init svm_init(void)
3559{
cb498ea2 3560 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3561 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3562}
3563
3564static void __exit svm_exit(void)
3565{
cb498ea2 3566 kvm_exit();
6aa8b732
AK		 3567}
3568
3569module_init(svm_init)
3570module_exit(svm_exit)
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