[net-next-2.6.git] / arch / x86 / kvm / i8259.c

/*
 * 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2007 Intel Corporation
 * Copyright 2009 Red Hat, Inc. and/or its affilates.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *   Port from Qemu.
 */
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include "irq.h"

#include <linux/kvm_host.h>
#include "trace.h"

static void pic_irq_request(struct kvm *kvm, int level);

static void pic_lock(struct kvm_pic *s)
	__acquires(&s->lock)
{
	raw_spin_lock(&s->lock);
}

static void pic_unlock(struct kvm_pic *s)
	__releases(&s->lock)
{
	bool wakeup = s->wakeup_needed;
	struct kvm_vcpu *vcpu, *found = NULL;
	int i;

	s->wakeup_needed = false;

	raw_spin_unlock(&s->lock);

	if (wakeup) {
		kvm_for_each_vcpu(i, vcpu, s->kvm) {
			if (kvm_apic_accept_pic_intr(vcpu)) {
				found = vcpu;
				break;
			}
		}

		if (!found)
			found = s->kvm->bsp_vcpu;

		if (!found)
			return;

		kvm_vcpu_kick(found);
	}
}

static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
{
	s->isr &= ~(1 << irq);
	s->isr_ack |= (1 << irq);
	if (s != &s->pics_state->pics[0])
		irq += 8;
	/*
	 * We are dropping lock while calling ack notifiers since ack
	 * notifier callbacks for assigned devices call into PIC recursively.
	 * Other interrupt may be delivered to PIC while lock is dropped but
	 * it should be safe since PIC state is already updated at this stage.
	 */
	pic_unlock(s->pics_state);
	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
	pic_lock(s->pics_state);
}

void kvm_pic_clear_isr_ack(struct kvm *kvm)
{
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	s->pics[0].isr_ack = 0xff;
	s->pics[1].isr_ack = 0xff;
	pic_unlock(s);
}

/*
 * set irq level. If an edge is detected, then the IRR is set to 1
 */
static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
{
	int mask, ret = 1;
	mask = 1 << irq;
	if (s->elcr & mask)	/* level triggered */
		if (level) {
			ret = !(s->irr & mask);
			s->irr |= mask;
			s->last_irr |= mask;
		} else {
			s->irr &= ~mask;
			s->last_irr &= ~mask;
		}
	else	/* edge triggered */
		if (level) {
			if ((s->last_irr & mask) == 0) {
				ret = !(s->irr & mask);
				s->irr |= mask;
			}
			s->last_irr |= mask;
		} else
			s->last_irr &= ~mask;

	return (s->imr & mask) ? -1 : ret;
}

/*
 * return the highest priority found in mask (highest = smallest
 * number). Return 8 if no irq
 */
static inline int get_priority(struct kvm_kpic_state *s, int mask)
{
	int priority;
	if (mask == 0)
		return 8;
	priority = 0;
	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
		priority++;
	return priority;
}

/*
 * return the pic wanted interrupt. return -1 if none
 */
static int pic_get_irq(struct kvm_kpic_state *s)
{
	int mask, cur_priority, priority;

	mask = s->irr & ~s->imr;
	priority = get_priority(s, mask);
	if (priority == 8)
		return -1;
	/*
	 * compute current priority. If special fully nested mode on the
	 * master, the IRQ coming from the slave is not taken into account
	 * for the priority computation.
	 */
	mask = s->isr;
	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
		mask &= ~(1 << 2);
	cur_priority = get_priority(s, mask);
	if (priority < cur_priority)
		/*
		 * higher priority found: an irq should be generated
		 */
		return (priority + s->priority_add) & 7;
	else
		return -1;
}

/*
 * raise irq to CPU if necessary. must be called every time the active
 * irq may change
 */
static void pic_update_irq(struct kvm_pic *s)
{
	int irq2, irq;

	irq2 = pic_get_irq(&s->pics[1]);
	if (irq2 >= 0) {
		/*
		 * if irq request by slave pic, signal master PIC
		 */
		pic_set_irq1(&s->pics[0], 2, 1);
		pic_set_irq1(&s->pics[0], 2, 0);
	}
	irq = pic_get_irq(&s->pics[0]);
	pic_irq_request(s->kvm, irq >= 0);
}

void kvm_pic_update_irq(struct kvm_pic *s)
{
	pic_lock(s);
	pic_update_irq(s);
	pic_unlock(s);
}

int kvm_pic_set_irq(void *opaque, int irq, int level)
{
	struct kvm_pic *s = opaque;
	int ret = -1;

	pic_lock(s);
	if (irq >= 0 && irq < PIC_NUM_PINS) {
		ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
		pic_update_irq(s);
		trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
				      s->pics[irq >> 3].imr, ret == 0);
	}
	pic_unlock(s);

	return ret;
}

/*
 * acknowledge interrupt 'irq'
 */
static inline void pic_intack(struct kvm_kpic_state *s, int irq)
{
	s->isr |= 1 << irq;
	/*
	 * We don't clear a level sensitive interrupt here
	 */
	if (!(s->elcr & (1 << irq)))
		s->irr &= ~(1 << irq);

	if (s->auto_eoi) {
		if (s->rotate_on_auto_eoi)
			s->priority_add = (irq + 1) & 7;
		pic_clear_isr(s, irq);
	}

}

int kvm_pic_read_irq(struct kvm *kvm)
{
	int irq, irq2, intno;
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	irq = pic_get_irq(&s->pics[0]);
	if (irq >= 0) {
		pic_intack(&s->pics[0], irq);
		if (irq == 2) {
			irq2 = pic_get_irq(&s->pics[1]);
			if (irq2 >= 0)
				pic_intack(&s->pics[1], irq2);
			else
				/*
				 * spurious IRQ on slave controller
				 */
				irq2 = 7;
			intno = s->pics[1].irq_base + irq2;
			irq = irq2 + 8;
		} else
			intno = s->pics[0].irq_base + irq;
	} else {
		/*
		 * spurious IRQ on host controller
		 */
		irq = 7;
		intno = s->pics[0].irq_base + irq;
	}
	pic_update_irq(s);
	pic_unlock(s);

	return intno;
}

void kvm_pic_reset(struct kvm_kpic_state *s)
{
	int irq;
	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
	u8 irr = s->irr, isr = s->imr;

	s->last_irr = 0;
	s->irr = 0;
	s->imr = 0;
	s->isr = 0;
	s->isr_ack = 0xff;
	s->priority_add = 0;
	s->irq_base = 0;
	s->read_reg_select = 0;
	s->poll = 0;
	s->special_mask = 0;
	s->init_state = 0;
	s->auto_eoi = 0;
	s->rotate_on_auto_eoi = 0;
	s->special_fully_nested_mode = 0;
	s->init4 = 0;

	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
		if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
			if (irr & (1 << irq) || isr & (1 << irq)) {
				pic_clear_isr(s, irq);
			}
	}
}

static void pic_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	int priority, cmd, irq;

	addr &= 1;
	if (addr == 0) {
		if (val & 0x10) {
			kvm_pic_reset(s);	/* init */
			/*
			 * deassert a pending interrupt
			 */
			pic_irq_request(s->pics_state->kvm, 0);
			s->init_state = 1;
			s->init4 = val & 1;
			if (val & 0x02)
				printk(KERN_ERR "single mode not supported");
			if (val & 0x08)
				printk(KERN_ERR
				       "level sensitive irq not supported");
		} else if (val & 0x08) {
			if (val & 0x04)
				s->poll = 1;
			if (val & 0x02)
				s->read_reg_select = val & 1;
			if (val & 0x40)
				s->special_mask = (val >> 5) & 1;
		} else {
			cmd = val >> 5;
			switch (cmd) {
			case 0:
			case 4:
				s->rotate_on_auto_eoi = cmd >> 2;
				break;
			case 1:	/* end of interrupt */
			case 5:
				priority = get_priority(s, s->isr);
				if (priority != 8) {
					irq = (priority + s->priority_add) & 7;
					if (cmd == 5)
						s->priority_add = (irq + 1) & 7;
					pic_clear_isr(s, irq);
					pic_update_irq(s->pics_state);
				}
				break;
			case 3:
				irq = val & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			case 6:
				s->priority_add = (val + 1) & 7;
				pic_update_irq(s->pics_state);
				break;
			case 7:
				irq = val & 7;
				s->priority_add = (irq + 1) & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			default:
				break;	/* no operation */
			}
		}
	} else
		switch (s->init_state) {
		case 0: { /* normal mode */
			u8 imr_diff = s->imr ^ val,
				off = (s == &s->pics_state->pics[0]) ? 0 : 8;
			s->imr = val;
			for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
				if (imr_diff & (1 << irq))
					kvm_fire_mask_notifiers(
						s->pics_state->kvm,
						SELECT_PIC(irq + off),
						irq + off,
						!!(s->imr & (1 << irq)));
			pic_update_irq(s->pics_state);
			break;
		}
		case 1:
			s->irq_base = val & 0xf8;
			s->init_state = 2;
			break;
		case 2:
			if (s->init4)
				s->init_state = 3;
			else
				s->init_state = 0;
			break;
		case 3:
			s->special_fully_nested_mode = (val >> 4) & 1;
			s->auto_eoi = (val >> 1) & 1;
			s->init_state = 0;
			break;
		}
}

static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
{
	int ret;

	ret = pic_get_irq(s);
	if (ret >= 0) {
		if (addr1 >> 7) {
			s->pics_state->pics[0].isr &= ~(1 << 2);
			s->pics_state->pics[0].irr &= ~(1 << 2);
		}
		s->irr &= ~(1 << ret);
		pic_clear_isr(s, ret);
		if (addr1 >> 7 || ret != 2)
			pic_update_irq(s->pics_state);
	} else {
		ret = 0x07;
		pic_update_irq(s->pics_state);
	}

	return ret;
}

static u32 pic_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	unsigned int addr;
	int ret;

	addr = addr1;
	addr &= 1;
	if (s->poll) {
		ret = pic_poll_read(s, addr1);
		s->poll = 0;
	} else
		if (addr == 0)
			if (s->read_reg_select)
				ret = s->isr;
			else
				ret = s->irr;
		else
			ret = s->imr;
	return ret;
}

static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	s->elcr = val & s->elcr_mask;
}

static u32 elcr_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	return s->elcr;
}

static int picdev_in_range(gpa_t addr)
{
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
	case 0x4d0:
	case 0x4d1:
		return 1;
	default:
		return 0;
	}
}

static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_pic, dev);
}

static int picdev_write(struct kvm_io_device *this,
			 gpa_t addr, int len, const void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = *(unsigned char *)val;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte write\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		pic_ioport_write(&s->pics[addr >> 7], addr, data);
		break;
	case 0x4d0:
	case 0x4d1:
		elcr_ioport_write(&s->pics[addr & 1], addr, data);
		break;
	}
	pic_unlock(s);
	return 0;
}

static int picdev_read(struct kvm_io_device *this,
		       gpa_t addr, int len, void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = 0;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte read\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		data = pic_ioport_read(&s->pics[addr >> 7], addr);
		break;
	case 0x4d0:
	case 0x4d1:
		data = elcr_ioport_read(&s->pics[addr & 1], addr);
		break;
	}
	*(unsigned char *)val = data;
	pic_unlock(s);
	return 0;
}

/*
 * callback when PIC0 irq status changed
 */
static void pic_irq_request(struct kvm *kvm, int level)
{
	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
	struct kvm_pic *s = pic_irqchip(kvm);
	int irq = pic_get_irq(&s->pics[0]);

	s->output = level;
	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
		s->pics[0].isr_ack &= ~(1 << irq);
		s->wakeup_needed = true;
	}
}

static const struct kvm_io_device_ops picdev_ops = {
	.read     = picdev_read,
	.write    = picdev_write,
};

struct kvm_pic *kvm_create_pic(struct kvm *kvm)
{
	struct kvm_pic *s;
	int ret;

	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	if (!s)
		return NULL;
	raw_spin_lock_init(&s->lock);
	s->kvm = kvm;
	s->pics[0].elcr_mask = 0xf8;
	s->pics[1].elcr_mask = 0xde;
	s->pics[0].pics_state = s;
	s->pics[1].pics_state = s;

	/*
	 * Initialize PIO device
	 */
	kvm_iodevice_init(&s->dev, &picdev_ops);
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kfree(s);
		return NULL;
	}

	return s;
}

void kvm_destroy_pic(struct kvm *kvm)
{
	struct kvm_pic *vpic = kvm->arch.vpic;

	if (vpic) {
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
		kvm->arch.vpic = NULL;
		kfree(vpic);
	}
}
Commit	Line	Data
85f455f7 ED	1	/*
	2	* 8259 interrupt controller emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2007 Intel Corporation
221d059d	6	* Copyright 2009 Red Hat, Inc. and/or its affilates.
85f455f7 ED	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	* Authors:
	26	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	27	* Port from Qemu.
	28	*/
	29	#include <linux/mm.h>
5a0e3ad6	30	#include <linux/slab.h>
3f353858	31	#include <linux/bitops.h>
85f455f7	32	#include "irq.h"
edf88417 AK	33
edf88417 AK	34	#include <linux/kvm_host.h>
1000ff8d	35	#include "trace.h"
85f455f7	36
073d4613 AK	37	static void pic_irq_request(struct kvm *kvm, int level);
073d4613 AK	38
50a085bd JK	39	static void pic_lock(struct kvm_pic *s)
	40	__acquires(&s->lock)
	41	{
	42	raw_spin_lock(&s->lock);
	43	}
	44
	45	static void pic_unlock(struct kvm_pic *s)
	46	__releases(&s->lock)
	47	{
	48	bool wakeup = s->wakeup_needed;
529df65e CL	49	struct kvm_vcpu vcpu, found = NULL;
529df65e CL	50	int i;
50a085bd JK	51
	52	s->wakeup_needed = false;
	53
	54	raw_spin_unlock(&s->lock);
	55
	56	if (wakeup) {
529df65e CL	57	kvm_for_each_vcpu(i, vcpu, s->kvm) {
	58	if (kvm_apic_accept_pic_intr(vcpu)) {
	59	found = vcpu;
	60	break;
	61	}
	62	}
	63
	64	if (!found)
	65	found = s->kvm->bsp_vcpu;
	66
ae0635b3 AK	67	if (!found)
	68	return;
	69
529df65e	70	kvm_vcpu_kick(found);
50a085bd JK	71	}
	72	}
	73
7edd0ce0 AK	74	static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
	75	{
	76	s->isr &= ~(1 << irq);
e4825800	77	s->isr_ack \|= (1 << irq);
938396a2 GN	78	if (s != &s->pics_state->pics[0])
938396a2 GN	79	irq += 8;
eba0226b GN	80	/*
	81	* We are dropping lock while calling ack notifiers since ack
	82	* notifier callbacks for assigned devices call into PIC recursively.
	83	* Other interrupt may be delivered to PIC while lock is dropped but
	84	* it should be safe since PIC state is already updated at this stage.
	85	*/
50a085bd	86	pic_unlock(s->pics_state);
938396a2	87	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
50a085bd	88	pic_lock(s->pics_state);
e4825800 MT	89	}
	90
	91	void kvm_pic_clear_isr_ack(struct kvm *kvm)
	92	{
	93	struct kvm_pic *s = pic_irqchip(kvm);
fa8273e9	94
50a085bd	95	pic_lock(s);
e4825800 MT	96	s->pics[0].isr_ack = 0xff;
e4825800 MT	97	s->pics[1].isr_ack = 0xff;
50a085bd	98	pic_unlock(s);
7edd0ce0 AK	99	}
7edd0ce0 AK	100
85f455f7 ED	101	/*
	102	* set irq level. If an edge is detected, then the IRR is set to 1
	103	*/
4925663a	104	static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
85f455f7	105	{
4925663a	106	int mask, ret = 1;
85f455f7 ED	107	mask = 1 << irq;
	108	if (s->elcr & mask) /* level triggered */
	109	if (level) {
4925663a	110	ret = !(s->irr & mask);
85f455f7 ED	111	s->irr \|= mask;
	112	s->last_irr \|= mask;
	113	} else {
	114	s->irr &= ~mask;
	115	s->last_irr &= ~mask;
	116	}
	117	else /* edge triggered */
	118	if (level) {
4925663a GN	119	if ((s->last_irr & mask) == 0) {
4925663a GN	120	ret = !(s->irr & mask);
85f455f7	121	s->irr \|= mask;
4925663a	122	}
85f455f7 ED	123	s->last_irr \|= mask;
	124	} else
	125	s->last_irr &= ~mask;
4925663a GN	126
4925663a GN	127	return (s->imr & mask) ? -1 : ret;
85f455f7 ED	128	}
	129
	130	/*
	131	* return the highest priority found in mask (highest = smallest
	132	* number). Return 8 if no irq
	133	*/
	134	static inline int get_priority(struct kvm_kpic_state *s, int mask)
	135	{
	136	int priority;
	137	if (mask == 0)
	138	return 8;
	139	priority = 0;
	140	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	141	priority++;
	142	return priority;
	143	}
	144
	145	/*
	146	* return the pic wanted interrupt. return -1 if none
	147	*/
	148	static int pic_get_irq(struct kvm_kpic_state *s)
	149	{
	150	int mask, cur_priority, priority;
	151
	152	mask = s->irr & ~s->imr;
	153	priority = get_priority(s, mask);
	154	if (priority == 8)
	155	return -1;
	156	/*
	157	* compute current priority. If special fully nested mode on the
	158	* master, the IRQ coming from the slave is not taken into account
	159	* for the priority computation.
	160	*/
	161	mask = s->isr;
	162	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
	163	mask &= ~(1 << 2);
	164	cur_priority = get_priority(s, mask);
	165	if (priority < cur_priority)
	166	/*
	167	* higher priority found: an irq should be generated
	168	*/
	169	return (priority + s->priority_add) & 7;
	170	else
	171	return -1;
	172	}
	173
	174	/*
	175	* raise irq to CPU if necessary. must be called every time the active
	176	* irq may change
	177	*/
	178	static void pic_update_irq(struct kvm_pic *s)
	179	{
	180	int irq2, irq;
	181
	182	irq2 = pic_get_irq(&s->pics[1]);
	183	if (irq2 >= 0) {
	184	/*
	185	* if irq request by slave pic, signal master PIC
	186	*/
	187	pic_set_irq1(&s->pics[0], 2, 1);
	188	pic_set_irq1(&s->pics[0], 2, 0);
	189	}
	190	irq = pic_get_irq(&s->pics[0]);
36633f32	191	pic_irq_request(s->kvm, irq >= 0);
85f455f7 ED	192	}
85f455f7 ED	193
6ceb9d79 HQ	194	void kvm_pic_update_irq(struct kvm_pic *s)
6ceb9d79 HQ	195	{
50a085bd	196	pic_lock(s);
6ceb9d79	197	pic_update_irq(s);
50a085bd	198	pic_unlock(s);
6ceb9d79 HQ	199	}
6ceb9d79 HQ	200
4925663a	201	int kvm_pic_set_irq(void *opaque, int irq, int level)
85f455f7 ED	202	{
85f455f7 ED	203	struct kvm_pic *s = opaque;
4925663a	204	int ret = -1;
85f455f7	205
50a085bd	206	pic_lock(s);
c65bbfa1	207	if (irq >= 0 && irq < PIC_NUM_PINS) {
4925663a	208	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
c65bbfa1	209	pic_update_irq(s);
1000ff8d GN	210	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
1000ff8d GN	211	s->pics[irq >> 3].imr, ret == 0);
c65bbfa1	212	}
50a085bd	213	pic_unlock(s);
4925663a GN	214
4925663a GN	215	return ret;
85f455f7 ED	216	}
	217
	218	/*
	219	* acknowledge interrupt 'irq'
	220	*/
	221	static inline void pic_intack(struct kvm_kpic_state *s, int irq)
	222	{
7edd0ce0	223	s->isr \|= 1 << irq;
85f455f7 ED	224	/*
	225	* We don't clear a level sensitive interrupt here
	226	*/
	227	if (!(s->elcr & (1 << irq)))
	228	s->irr &= ~(1 << irq);
eba0226b GN	229
	230	if (s->auto_eoi) {
	231	if (s->rotate_on_auto_eoi)
	232	s->priority_add = (irq + 1) & 7;
	233	pic_clear_isr(s, irq);
	234	}
	235
85f455f7 ED	236	}
85f455f7 ED	237
f5244726	238	int kvm_pic_read_irq(struct kvm *kvm)
85f455f7 ED	239	{
85f455f7 ED	240	int irq, irq2, intno;
f5244726	241	struct kvm_pic *s = pic_irqchip(kvm);
85f455f7	242
50a085bd	243	pic_lock(s);
85f455f7 ED	244	irq = pic_get_irq(&s->pics[0]);
	245	if (irq >= 0) {
	246	pic_intack(&s->pics[0], irq);
	247	if (irq == 2) {
	248	irq2 = pic_get_irq(&s->pics[1]);
	249	if (irq2 >= 0)
	250	pic_intack(&s->pics[1], irq2);
	251	else
	252	/*
	253	* spurious IRQ on slave controller
	254	*/
	255	irq2 = 7;
	256	intno = s->pics[1].irq_base + irq2;
	257	irq = irq2 + 8;
	258	} else
	259	intno = s->pics[0].irq_base + irq;
	260	} else {
	261	/*
	262	* spurious IRQ on host controller
	263	*/
	264	irq = 7;
	265	intno = s->pics[0].irq_base + irq;
	266	}
	267	pic_update_irq(s);
50a085bd	268	pic_unlock(s);
85f455f7 ED	269
	270	return intno;
	271	}
	272
2fcceae1	273	void kvm_pic_reset(struct kvm_kpic_state *s)
85f455f7	274	{
79c727d4	275	int irq;
073d4613	276	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
79c727d4	277	u8 irr = s->irr, isr = s->imr;
f5244726	278
85f455f7 ED	279	s->last_irr = 0;
	280	s->irr = 0;
	281	s->imr = 0;
	282	s->isr = 0;
e4825800	283	s->isr_ack = 0xff;
85f455f7 ED	284	s->priority_add = 0;
	285	s->irq_base = 0;
	286	s->read_reg_select = 0;
	287	s->poll = 0;
	288	s->special_mask = 0;
	289	s->init_state = 0;
	290	s->auto_eoi = 0;
	291	s->rotate_on_auto_eoi = 0;
	292	s->special_fully_nested_mode = 0;
	293	s->init4 = 0;
79c727d4 GN	294
	295	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
	296	if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
	297	if (irr & (1 << irq) \|\| isr & (1 << irq)) {
	298	pic_clear_isr(s, irq);
	299	}
	300	}
85f455f7 ED	301	}
	302
	303	static void pic_ioport_write(void *opaque, u32 addr, u32 val)
	304	{
	305	struct kvm_kpic_state *s = opaque;
	306	int priority, cmd, irq;
	307
	308	addr &= 1;
	309	if (addr == 0) {
	310	if (val & 0x10) {
2fcceae1	311	kvm_pic_reset(s); /* init */
85f455f7 ED	312	/*
	313	* deassert a pending interrupt
	314	*/
073d4613	315	pic_irq_request(s->pics_state->kvm, 0);
85f455f7 ED	316	s->init_state = 1;
	317	s->init4 = val & 1;
	318	if (val & 0x02)
	319	printk(KERN_ERR "single mode not supported");
	320	if (val & 0x08)
	321	printk(KERN_ERR
	322	"level sensitive irq not supported");
	323	} else if (val & 0x08) {
	324	if (val & 0x04)
	325	s->poll = 1;
	326	if (val & 0x02)
	327	s->read_reg_select = val & 1;
	328	if (val & 0x40)
	329	s->special_mask = (val >> 5) & 1;
	330	} else {
	331	cmd = val >> 5;
	332	switch (cmd) {
	333	case 0:
	334	case 4:
	335	s->rotate_on_auto_eoi = cmd >> 2;
	336	break;
	337	case 1: /* end of interrupt */
	338	case 5:
	339	priority = get_priority(s, s->isr);
	340	if (priority != 8) {
	341	irq = (priority + s->priority_add) & 7;
85f455f7 ED	342	if (cmd == 5)
85f455f7 ED	343	s->priority_add = (irq + 1) & 7;
eba0226b	344	pic_clear_isr(s, irq);
85f455f7 ED	345	pic_update_irq(s->pics_state);
	346	}
	347	break;
	348	case 3:
	349	irq = val & 7;
7edd0ce0	350	pic_clear_isr(s, irq);
85f455f7 ED	351	pic_update_irq(s->pics_state);
	352	break;
	353	case 6:
	354	s->priority_add = (val + 1) & 7;
	355	pic_update_irq(s->pics_state);
	356	break;
	357	case 7:
	358	irq = val & 7;
85f455f7	359	s->priority_add = (irq + 1) & 7;
7edd0ce0	360	pic_clear_isr(s, irq);
85f455f7 ED	361	pic_update_irq(s->pics_state);
	362	break;
	363	default:
	364	break; /* no operation */
	365	}
	366	}
	367	} else
	368	switch (s->init_state) {
9195c4da GN	369	case 0: { /* normal mode */
	370	u8 imr_diff = s->imr ^ val,
	371	off = (s == &s->pics_state->pics[0]) ? 0 : 8;
85f455f7	372	s->imr = val;
9195c4da GN	373	for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
	374	if (imr_diff & (1 << irq))
	375	kvm_fire_mask_notifiers(
	376	s->pics_state->kvm,
	377	SELECT_PIC(irq + off),
	378	irq + off,
	379	!!(s->imr & (1 << irq)));
85f455f7 ED	380	pic_update_irq(s->pics_state);
85f455f7 ED	381	break;
9195c4da	382	}
85f455f7 ED	383	case 1:
	384	s->irq_base = val & 0xf8;
	385	s->init_state = 2;
	386	break;
	387	case 2:
	388	if (s->init4)
	389	s->init_state = 3;
	390	else
	391	s->init_state = 0;
	392	break;
	393	case 3:
	394	s->special_fully_nested_mode = (val >> 4) & 1;
	395	s->auto_eoi = (val >> 1) & 1;
	396	s->init_state = 0;
	397	break;
	398	}
	399	}
	400
	401	static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
	402	{
	403	int ret;
	404
	405	ret = pic_get_irq(s);
	406	if (ret >= 0) {
	407	if (addr1 >> 7) {
	408	s->pics_state->pics[0].isr &= ~(1 << 2);
	409	s->pics_state->pics[0].irr &= ~(1 << 2);
	410	}
	411	s->irr &= ~(1 << ret);
7edd0ce0	412	pic_clear_isr(s, ret);
85f455f7 ED	413	if (addr1 >> 7 \|\| ret != 2)
	414	pic_update_irq(s->pics_state);
	415	} else {
	416	ret = 0x07;
	417	pic_update_irq(s->pics_state);
	418	}
	419
	420	return ret;
	421	}
	422
	423	static u32 pic_ioport_read(void *opaque, u32 addr1)
	424	{
	425	struct kvm_kpic_state *s = opaque;
	426	unsigned int addr;
	427	int ret;
	428
	429	addr = addr1;
	430	addr &= 1;
	431	if (s->poll) {
	432	ret = pic_poll_read(s, addr1);
	433	s->poll = 0;
	434	} else
	435	if (addr == 0)
	436	if (s->read_reg_select)
	437	ret = s->isr;
	438	else
	439	ret = s->irr;
	440	else
	441	ret = s->imr;
	442	return ret;
	443	}
	444
	445	static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
	446	{
	447	struct kvm_kpic_state *s = opaque;
	448	s->elcr = val & s->elcr_mask;
	449	}
	450
	451	static u32 elcr_ioport_read(void *opaque, u32 addr1)
	452	{
	453	struct kvm_kpic_state *s = opaque;
	454	return s->elcr;
	455	}
	456
bda9020e	457	static int picdev_in_range(gpa_t addr)
85f455f7 ED	458	{
	459	switch (addr) {
	460	case 0x20:
	461	case 0x21:
	462	case 0xa0:
	463	case 0xa1:
	464	case 0x4d0:
	465	case 0x4d1:
	466	return 1;
	467	default:
	468	return 0;
	469	}
	470	}
	471
d76685c4 GH	472	static inline struct kvm_pic to_pic(struct kvm_io_device dev)
	473	{
	474	return container_of(dev, struct kvm_pic, dev);
	475	}
	476
bda9020e	477	static int picdev_write(struct kvm_io_device *this,
85f455f7 ED	478	gpa_t addr, int len, const void *val)
85f455f7 ED	479	{
d76685c4	480	struct kvm_pic *s = to_pic(this);
85f455f7	481	unsigned char data = (unsigned char )val;
bda9020e MT	482	if (!picdev_in_range(addr))
bda9020e MT	483	return -EOPNOTSUPP;
85f455f7 ED	484
	485	if (len != 1) {
	486	if (printk_ratelimit())
	487	printk(KERN_ERR "PIC: non byte write\n");
bda9020e	488	return 0;
85f455f7	489	}
50a085bd	490	pic_lock(s);
85f455f7 ED	491	switch (addr) {
	492	case 0x20:
	493	case 0x21:
	494	case 0xa0:
	495	case 0xa1:
	496	pic_ioport_write(&s->pics[addr >> 7], addr, data);
	497	break;
	498	case 0x4d0:
	499	case 0x4d1:
	500	elcr_ioport_write(&s->pics[addr & 1], addr, data);
	501	break;
	502	}
50a085bd	503	pic_unlock(s);
bda9020e	504	return 0;
85f455f7 ED	505	}
85f455f7 ED	506
bda9020e MT	507	static int picdev_read(struct kvm_io_device *this,
bda9020e MT	508	gpa_t addr, int len, void *val)
85f455f7	509	{
d76685c4	510	struct kvm_pic *s = to_pic(this);
85f455f7	511	unsigned char data = 0;
bda9020e MT	512	if (!picdev_in_range(addr))
bda9020e MT	513	return -EOPNOTSUPP;
85f455f7 ED	514
	515	if (len != 1) {
	516	if (printk_ratelimit())
	517	printk(KERN_ERR "PIC: non byte read\n");
bda9020e	518	return 0;
85f455f7	519	}
50a085bd	520	pic_lock(s);
85f455f7 ED	521	switch (addr) {
	522	case 0x20:
	523	case 0x21:
	524	case 0xa0:
	525	case 0xa1:
	526	data = pic_ioport_read(&s->pics[addr >> 7], addr);
	527	break;
	528	case 0x4d0:
	529	case 0x4d1:
	530	data = elcr_ioport_read(&s->pics[addr & 1], addr);
	531	break;
	532	}
	533	(unsigned char )val = data;
50a085bd	534	pic_unlock(s);
bda9020e	535	return 0;
85f455f7 ED	536	}
	537
	538	/*
	539	* callback when PIC0 irq status changed
	540	*/
073d4613	541	static void pic_irq_request(struct kvm *kvm, int level)
85f455f7	542	{
c5af89b6	543	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
e4825800 MT	544	struct kvm_pic *s = pic_irqchip(kvm);
e4825800 MT	545	int irq = pic_get_irq(&s->pics[0]);
85f455f7	546
e4825800 MT	547	s->output = level;
	548	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
	549	s->pics[0].isr_ack &= ~(1 << irq);
50a085bd	550	s->wakeup_needed = true;
e4825800	551	}
85f455f7 ED	552	}
85f455f7 ED	553
d76685c4 GH	554	static const struct kvm_io_device_ops picdev_ops = {
	555	.read = picdev_read,
	556	.write = picdev_write,
d76685c4 GH	557	};
d76685c4 GH	558
85f455f7 ED	559	struct kvm_pic kvm_create_pic(struct kvm kvm)
	560	{
	561	struct kvm_pic *s;
090b7aff GH	562	int ret;
090b7aff GH	563
85f455f7 ED	564	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	565	if (!s)
	566	return NULL;
fa8273e9	567	raw_spin_lock_init(&s->lock);
3f353858	568	s->kvm = kvm;
85f455f7 ED	569	s->pics[0].elcr_mask = 0xf8;
85f455f7 ED	570	s->pics[1].elcr_mask = 0xde;
85f455f7 ED	571	s->pics[0].pics_state = s;
	572	s->pics[1].pics_state = s;
	573
	574	/*
	575	* Initialize PIO device
	576	*/
d76685c4	577	kvm_iodevice_init(&s->dev, &picdev_ops);
79fac95e	578	mutex_lock(&kvm->slots_lock);
e93f8a0f	579	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
79fac95e	580	mutex_unlock(&kvm->slots_lock);
090b7aff GH	581	if (ret < 0) {
	582	kfree(s);
	583	return NULL;
	584	}
	585
85f455f7 ED	586	return s;
85f455f7 ED	587	}
72bb2fcd WY	588
	589	void kvm_destroy_pic(struct kvm *kvm)
	590	{
	591	struct kvm_pic *vpic = kvm->arch.vpic;
	592
	593	if (vpic) {
	594	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
	595	kvm->arch.vpic = NULL;
	596	kfree(vpic);
	597	}
	598	}