[net-next-2.6.git] / arch / x86 / kvm / i8254.c

/*
 * 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2006 Intel Corporation
 * Copyright (c) 2007 Keir Fraser, XenSource Inc
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 * Authors:
 *   Sheng Yang <sheng.yang@intel.com>
 *   Based on QEMU and Xen.
 */

#include <linux/kvm_host.h>

#include "irq.h"
#include "i8254.h"

#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

/* Compute with 96 bit intermediate result: (a*b)/c */
static u64 muldiv64(u64 a, u32 b, u32 c)
{
	union {
		u64 ll;
		struct {
			u32 low, high;
		} l;
	} u, res;
	u64 rl, rh;

	u.ll = a;
	rl = (u64)u.l.low * (u64)b;
	rh = (u64)u.l.high * (u64)b;
	rh += (rl >> 32);
	res.l.high = div64_u64(rh, c);
	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
	return res.ll;
}

static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	switch (c->mode) {
	default:
	case 0:
	case 4:
		/* XXX: just disable/enable counting */
		break;
	case 1:
	case 2:
	case 3:
	case 5:
		/* Restart counting on rising edge. */
		if (c->gate < val)
			c->count_load_time = ktime_get();
		break;
	}

	c->gate = val;
}

static int pit_get_gate(struct kvm *kvm, int channel)
{
	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	return kvm->arch.vpit->pit_state.channels[channel].gate;
}

static s64 __kpit_elapsed(struct kvm *kvm)
{
	s64 elapsed;
	ktime_t remaining;
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	remaining = hrtimer_expires_remaining(&ps->pit_timer.timer);
	if (ktime_to_ns(remaining) < 0)
		remaining = ktime_set(0, 0);

	elapsed = ps->pit_timer.period;
	if (ktime_to_ns(remaining) <= ps->pit_timer.period)
		elapsed = ps->pit_timer.period - ktime_to_ns(remaining);

	return elapsed;
}

static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c,
			int channel)
{
	if (channel == 0)
		return __kpit_elapsed(kvm);

	return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
}

static int pit_get_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int counter;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = kpit_elapsed(kvm, c, channel);
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	case 0:
	case 1:
	case 4:
	case 5:
		counter = (c->count - d) & 0xffff;
		break;
	case 3:
		/* XXX: may be incorrect for odd counts */
		counter = c->count - (mod_64((2 * d), c->count));
		break;
	default:
		counter = c->count - mod_64(d, c->count);
		break;
	}
	return counter;
}

static int pit_get_out(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int out;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = kpit_elapsed(kvm, c, channel);
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	default:
	case 0:
		out = (d >= c->count);
		break;
	case 1:
		out = (d < c->count);
		break;
	case 2:
		out = ((mod_64(d, c->count) == 0) && (d != 0));
		break;
	case 3:
		out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
		break;
	case 4:
	case 5:
		out = (d == c->count);
		break;
	}

	return out;
}

static void pit_latch_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->count_latched) {
		c->latched_count = pit_get_count(kvm, channel);
		c->count_latched = c->rw_mode;
	}
}

static void pit_latch_status(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->status_latched) {
		/* TODO: Return NULL COUNT (bit 6). */
		c->status = ((pit_get_out(kvm, channel) << 7) |
				(c->rw_mode << 4) |
				(c->mode << 1) |
				c->bcd);
		c->status_latched = 1;
	}
}

int pit_has_pending_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;

	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
		return atomic_read(&pit->pit_state.pit_timer.pending);
	return 0;
}

static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
{
	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
						 irq_ack_notifier);
	spin_lock(&ps->inject_lock);
	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
		atomic_inc(&ps->pit_timer.pending);
	ps->irq_ack = 1;
	spin_unlock(&ps->inject_lock);
}

void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct hrtimer *timer;

	if (vcpu->vcpu_id != 0 || !pit)
		return;

	timer = &pit->pit_state.pit_timer.timer;
	if (hrtimer_cancel(timer))
		hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
}

static void destroy_pit_timer(struct kvm_timer *pt)
{
	pr_debug("pit: execute del timer!\n");
	hrtimer_cancel(&pt->timer);
}

static bool kpit_is_periodic(struct kvm_timer *ktimer)
{
	struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
						 pit_timer);
	return ps->is_periodic;
}

struct kvm_timer_ops kpit_ops = {
	.is_periodic = kpit_is_periodic,
};

static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
{
	struct kvm_timer *pt = &ps->pit_timer;
	s64 interval;

	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);

	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);

	/* TODO The new value only affected after the retriggered */
	hrtimer_cancel(&pt->timer);
	pt->period = (is_period == 0) ? 0 : interval;
	ps->is_periodic = is_period;

	pt->timer.function = kvm_timer_fn;
	pt->t_ops = &kpit_ops;
	pt->kvm = ps->pit->kvm;
	pt->vcpu_id = 0;

	atomic_set(&pt->pending, 0);
	ps->irq_ack = 1;

	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
		      HRTIMER_MODE_ABS);
}

static void pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	WARN_ON(!mutex_is_locked(&ps->lock));

	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);

	/*
	 * Though spec said the state of 8254 is undefined after power-up,
	 * seems some tricky OS like Windows XP depends on IRQ0 interrupt
	 * when booting up.
	 * So here setting initialize rate for it, and not a specific number
	 */
	if (val == 0)
		val = 0x10000;

	ps->channels[channel].count = val;

	if (channel != 0) {
		ps->channels[channel].count_load_time = ktime_get();
		return;
	}

	/* Two types of timer
	 * mode 1 is one shot, mode 2 is period, otherwise del timer */
	switch (ps->channels[0].mode) {
	case 1:
        /* FIXME: enhance mode 4 precision */
	case 4:
		create_pit_timer(ps, val, 0);
		break;
	case 2:
	case 3:
		create_pit_timer(ps, val, 1);
		break;
	default:
		destroy_pit_timer(&ps->pit_timer);
	}
}

void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	pit_load_count(kvm, channel, val);
	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
}

static void pit_ioport_write(struct kvm_io_device *this,
			     gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int channel, access;
	struct kvm_kpit_channel_state *s;
	u32 val = *(u32 *) data;

	val  &= 0xff;
	addr &= KVM_PIT_CHANNEL_MASK;

	mutex_lock(&pit_state->lock);

	if (val != 0)
		pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
			  (unsigned int)addr, len, val);

	if (addr == 3) {
		channel = val >> 6;
		if (channel == 3) {
			/* Read-Back Command. */
			for (channel = 0; channel < 3; channel++) {
				s = &pit_state->channels[channel];
				if (val & (2 << channel)) {
					if (!(val & 0x20))
						pit_latch_count(kvm, channel);
					if (!(val & 0x10))
						pit_latch_status(kvm, channel);
				}
			}
		} else {
			/* Select Counter <channel>. */
			s = &pit_state->channels[channel];
			access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
			if (access == 0) {
				pit_latch_count(kvm, channel);
			} else {
				s->rw_mode = access;
				s->read_state = access;
				s->write_state = access;
				s->mode = (val >> 1) & 7;
				if (s->mode > 5)
					s->mode -= 4;
				s->bcd = val & 1;
			}
		}
	} else {
		/* Write Count. */
		s = &pit_state->channels[addr];
		switch (s->write_state) {
		default:
		case RW_STATE_LSB:
			pit_load_count(kvm, addr, val);
			break;
		case RW_STATE_MSB:
			pit_load_count(kvm, addr, val << 8);
			break;
		case RW_STATE_WORD0:
			s->write_latch = val;
			s->write_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			pit_load_count(kvm, addr, s->write_latch | (val << 8));
			s->write_state = RW_STATE_WORD0;
			break;
		}
	}

	mutex_unlock(&pit_state->lock);
}

static void pit_ioport_read(struct kvm_io_device *this,
			    gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int ret, count;
	struct kvm_kpit_channel_state *s;

	addr &= KVM_PIT_CHANNEL_MASK;
	s = &pit_state->channels[addr];

	mutex_lock(&pit_state->lock);

	if (s->status_latched) {
		s->status_latched = 0;
		ret = s->status;
	} else if (s->count_latched) {
		switch (s->count_latched) {
		default:
		case RW_STATE_LSB:
			ret = s->latched_count & 0xff;
			s->count_latched = 0;
			break;
		case RW_STATE_MSB:
			ret = s->latched_count >> 8;
			s->count_latched = 0;
			break;
		case RW_STATE_WORD0:
			ret = s->latched_count & 0xff;
			s->count_latched = RW_STATE_MSB;
			break;
		}
	} else {
		switch (s->read_state) {
		default:
		case RW_STATE_LSB:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			break;
		case RW_STATE_MSB:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			break;
		case RW_STATE_WORD0:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			s->read_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			s->read_state = RW_STATE_WORD0;
			break;
		}
	}

	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);

	mutex_unlock(&pit_state->lock);
}

static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
			int len, int is_write)
{
	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
		(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
}

static void speaker_ioport_write(struct kvm_io_device *this,
				 gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	u32 val = *(u32 *) data;

	mutex_lock(&pit_state->lock);
	pit_state->speaker_data_on = (val >> 1) & 1;
	pit_set_gate(kvm, 2, val & 1);
	mutex_unlock(&pit_state->lock);
}

static void speaker_ioport_read(struct kvm_io_device *this,
				gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	unsigned int refresh_clock;
	int ret;

	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;

	mutex_lock(&pit_state->lock);
	ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
		(pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);
	mutex_unlock(&pit_state->lock);
}

static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
			    int len, int is_write)
{
	return (addr == KVM_SPEAKER_BASE_ADDRESS);
}

void kvm_pit_reset(struct kvm_pit *pit)
{
	int i;
	struct kvm_kpit_channel_state *c;

	mutex_lock(&pit->pit_state.lock);
	for (i = 0; i < 3; i++) {
		c = &pit->pit_state.channels[i];
		c->mode = 0xff;
		c->gate = (i != 2);
		pit_load_count(pit->kvm, i, 0);
	}
	mutex_unlock(&pit->pit_state.lock);

	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	pit->pit_state.irq_ack = 1;
}

static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
{
	struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);

	if (!mask) {
		atomic_set(&pit->pit_state.pit_timer.pending, 0);
		pit->pit_state.irq_ack = 1;
	}
}

struct kvm_pit *kvm_create_pit(struct kvm *kvm)
{
	struct kvm_pit *pit;
	struct kvm_kpit_state *pit_state;

	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	if (!pit)
		return NULL;

	pit->irq_source_id = kvm_request_irq_source_id(kvm);
	if (pit->irq_source_id < 0) {
		kfree(pit);
		return NULL;
	}

	mutex_init(&pit->pit_state.lock);
	mutex_lock(&pit->pit_state.lock);
	spin_lock_init(&pit->pit_state.inject_lock);

	/* Initialize PIO device */
	pit->dev.read = pit_ioport_read;
	pit->dev.write = pit_ioport_write;
	pit->dev.in_range = pit_in_range;
	pit->dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);

	pit->speaker_dev.read = speaker_ioport_read;
	pit->speaker_dev.write = speaker_ioport_write;
	pit->speaker_dev.in_range = speaker_in_range;
	pit->speaker_dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);

	kvm->arch.vpit = pit;
	pit->kvm = kvm;

	pit_state = &pit->pit_state;
	pit_state->pit = pit;
	hrtimer_init(&pit_state->pit_timer.timer,
		     CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	pit_state->irq_ack_notifier.gsi = 0;
	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
	pit_state->pit_timer.reinject = true;
	mutex_unlock(&pit->pit_state.lock);

	kvm_pit_reset(pit);

	pit->mask_notifier.func = pit_mask_notifer;
	kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);

	return pit;
}

void kvm_free_pit(struct kvm *kvm)
{
	struct hrtimer *timer;

	if (kvm->arch.vpit) {
		kvm_unregister_irq_mask_notifier(kvm, 0,
					       &kvm->arch.vpit->mask_notifier);
		mutex_lock(&kvm->arch.vpit->pit_state.lock);
		timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
		hrtimer_cancel(timer);
		kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
		mutex_unlock(&kvm->arch.vpit->pit_state.lock);
		kfree(kvm->arch.vpit);
	}
}

static void __inject_pit_timer_intr(struct kvm *kvm)
{
	struct kvm_vcpu *vcpu;
	int i;

	mutex_lock(&kvm->lock);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
	mutex_unlock(&kvm->lock);

	/*
	 * Provides NMI watchdog support via Virtual Wire mode.
	 * The route is: PIT -> PIC -> LVT0 in NMI mode.
	 *
	 * Note: Our Virtual Wire implementation is simplified, only
	 * propagating PIT interrupts to all VCPUs when they have set
	 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
	 * VCPU0, and only if its LVT0 is in EXTINT mode.
	 */
	if (kvm->arch.vapics_in_nmi_mode > 0)
		for (i = 0; i < KVM_MAX_VCPUS; ++i) {
			vcpu = kvm->vcpus[i];
			if (vcpu)
				kvm_apic_nmi_wd_deliver(vcpu);
		}
}

void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kpit_state *ps;

	if (vcpu && pit) {
		int inject = 0;
		ps = &pit->pit_state;

		/* Try to inject pending interrupts when
		 * last one has been acked.
		 */
		spin_lock(&ps->inject_lock);
		if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
			ps->irq_ack = 0;
			inject = 1;
		}
		spin_unlock(&ps->inject_lock);
		if (inject)
			__inject_pit_timer_intr(kvm);
	}
}
Commit	Line	Data
7837699f SY	1	/*
	2	* 8253/8254 interval timer emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2006 Intel Corporation
	6	* Copyright (c) 2007 Keir Fraser, XenSource Inc
	7	* Copyright (c) 2008 Intel Corporation
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Sheng Yang <sheng.yang@intel.com>
	29	* Based on QEMU and Xen.
	30	*/
	31
	32	#include <linux/kvm_host.h>
	33
	34	#include "irq.h"
	35	#include "i8254.h"
	36
	37	#ifndef CONFIG_X86_64
6f6d6a1a	38	#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
7837699f SY	39	#else
	40	#define mod_64(x, y) ((x) % (y))
	41	#endif
	42
	43	#define RW_STATE_LSB 1
	44	#define RW_STATE_MSB 2
	45	#define RW_STATE_WORD0 3
	46	#define RW_STATE_WORD1 4
	47
	48	/* Compute with 96 bit intermediate result: (ab)/c /
	49	static u64 muldiv64(u64 a, u32 b, u32 c)
	50	{
	51	union {
	52	u64 ll;
	53	struct {
	54	u32 low, high;
	55	} l;
	56	} u, res;
	57	u64 rl, rh;
	58
	59	u.ll = a;
	60	rl = (u64)u.l.low * (u64)b;
	61	rh = (u64)u.l.high * (u64)b;
	62	rh += (rl >> 32);
6f6d6a1a RZ	63	res.l.high = div64_u64(rh, c);
6f6d6a1a RZ	64	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
7837699f SY	65	return res.ll;
	66	}
	67
	68	static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
	69	{
	70	struct kvm_kpit_channel_state *c =
	71	&kvm->arch.vpit->pit_state.channels[channel];
	72
	73	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	74
	75	switch (c->mode) {
	76	default:
	77	case 0:
	78	case 4:
	79	/* XXX: just disable/enable counting */
	80	break;
	81	case 1:
	82	case 2:
	83	case 3:
	84	case 5:
	85	/* Restart counting on rising edge. */
	86	if (c->gate < val)
	87	c->count_load_time = ktime_get();
	88	break;
	89	}
	90
	91	c->gate = val;
	92	}
	93
8b2cf73c	94	static int pit_get_gate(struct kvm *kvm, int channel)
7837699f SY	95	{
	96	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	97
	98	return kvm->arch.vpit->pit_state.channels[channel].gate;
	99	}
	100
fd668423 MT	101	static s64 __kpit_elapsed(struct kvm *kvm)
	102	{
	103	s64 elapsed;
	104	ktime_t remaining;
	105	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	106
	107	remaining = hrtimer_expires_remaining(&ps->pit_timer.timer);
	108	if (ktime_to_ns(remaining) < 0)
	109	remaining = ktime_set(0, 0);
	110
	111	elapsed = ps->pit_timer.period;
	112	if (ktime_to_ns(remaining) <= ps->pit_timer.period)
	113	elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
	114
	115	return elapsed;
	116	}
	117
	118	static s64 kpit_elapsed(struct kvm kvm, struct kvm_kpit_channel_state c,
	119	int channel)
	120	{
	121	if (channel == 0)
	122	return __kpit_elapsed(kvm);
	123
	124	return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	125	}
	126
7837699f SY	127	static int pit_get_count(struct kvm *kvm, int channel)
	128	{
	129	struct kvm_kpit_channel_state *c =
	130	&kvm->arch.vpit->pit_state.channels[channel];
	131	s64 d, t;
	132	int counter;
	133
	134	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	135
fd668423	136	t = kpit_elapsed(kvm, c, channel);
7837699f SY	137	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	138
	139	switch (c->mode) {
	140	case 0:
	141	case 1:
	142	case 4:
	143	case 5:
	144	counter = (c->count - d) & 0xffff;
	145	break;
	146	case 3:
	147	/* XXX: may be incorrect for odd counts */
	148	counter = c->count - (mod_64((2 * d), c->count));
	149	break;
	150	default:
	151	counter = c->count - mod_64(d, c->count);
	152	break;
	153	}
	154	return counter;
	155	}
	156
	157	static int pit_get_out(struct kvm *kvm, int channel)
	158	{
	159	struct kvm_kpit_channel_state *c =
	160	&kvm->arch.vpit->pit_state.channels[channel];
	161	s64 d, t;
	162	int out;
	163
	164	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	165
fd668423	166	t = kpit_elapsed(kvm, c, channel);
7837699f SY	167	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	168
	169	switch (c->mode) {
	170	default:
	171	case 0:
	172	out = (d >= c->count);
	173	break;
	174	case 1:
	175	out = (d < c->count);
	176	break;
	177	case 2:
	178	out = ((mod_64(d, c->count) == 0) && (d != 0));
	179	break;
	180	case 3:
	181	out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
	182	break;
	183	case 4:
	184	case 5:
	185	out = (d == c->count);
	186	break;
	187	}
	188
	189	return out;
	190	}
	191
	192	static void pit_latch_count(struct kvm *kvm, int channel)
	193	{
	194	struct kvm_kpit_channel_state *c =
	195	&kvm->arch.vpit->pit_state.channels[channel];
	196
	197	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	198
	199	if (!c->count_latched) {
	200	c->latched_count = pit_get_count(kvm, channel);
	201	c->count_latched = c->rw_mode;
	202	}
	203	}
	204
	205	static void pit_latch_status(struct kvm *kvm, int channel)
	206	{
	207	struct kvm_kpit_channel_state *c =
	208	&kvm->arch.vpit->pit_state.channels[channel];
	209
	210	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	211
	212	if (!c->status_latched) {
	213	/* TODO: Return NULL COUNT (bit 6). */
	214	c->status = ((pit_get_out(kvm, channel) << 7) \|
	215	(c->rw_mode << 4) \|
	216	(c->mode << 1) \|
	217	c->bcd);
	218	c->status_latched = 1;
	219	}
	220	}
	221
3d80840d MT	222	int pit_has_pending_timer(struct kvm_vcpu *vcpu)
	223	{
	224	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	225
3cf57fed	226	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
3d80840d	227	return atomic_read(&pit->pit_state.pit_timer.pending);
3d80840d MT	228	return 0;
	229	}
	230
ee032c99	231	static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
3cf57fed MT	232	{
	233	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
	234	irq_ack_notifier);
	235	spin_lock(&ps->inject_lock);
	236	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
dc7404ce	237	atomic_inc(&ps->pit_timer.pending);
3cf57fed MT	238	ps->irq_ack = 1;
	239	spin_unlock(&ps->inject_lock);
	240	}
	241
2f599714 MT	242	void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
	243	{
	244	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	245	struct hrtimer *timer;
	246
	247	if (vcpu->vcpu_id != 0 \|\| !pit)
	248	return;
	249
	250	timer = &pit->pit_state.pit_timer.timer;
	251	if (hrtimer_cancel(timer))
beb20d52	252	hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
2f599714 MT	253	}
2f599714 MT	254
d3c7b77d	255	static void destroy_pit_timer(struct kvm_timer *pt)
7837699f SY	256	{
	257	pr_debug("pit: execute del timer!\n");
	258	hrtimer_cancel(&pt->timer);
	259	}
	260
d3c7b77d MT	261	static bool kpit_is_periodic(struct kvm_timer *ktimer)
	262	{
	263	struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
	264	pit_timer);
	265	return ps->is_periodic;
	266	}
	267
	268	struct kvm_timer_ops kpit_ops = {
	269	.is_periodic = kpit_is_periodic,
	270	};
	271
3cf57fed	272	static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
7837699f	273	{
d3c7b77d	274	struct kvm_timer *pt = &ps->pit_timer;
7837699f SY	275	s64 interval;
	276
	277	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
	278
	279	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
	280
	281	/* TODO The new value only affected after the retriggered */
	282	hrtimer_cancel(&pt->timer);
	283	pt->period = (is_period == 0) ? 0 : interval;
d3c7b77d MT	284	ps->is_periodic = is_period;
	285
	286	pt->timer.function = kvm_timer_fn;
	287	pt->t_ops = &kpit_ops;
	288	pt->kvm = ps->pit->kvm;
	289	pt->vcpu_id = 0;
	290
7837699f	291	atomic_set(&pt->pending, 0);
3cf57fed	292	ps->irq_ack = 1;
7837699f SY	293
	294	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
	295	HRTIMER_MODE_ABS);
	296	}
	297
	298	static void pit_load_count(struct kvm *kvm, int channel, u32 val)
	299	{
	300	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	301
	302	WARN_ON(!mutex_is_locked(&ps->lock));
	303
	304	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
	305
	306	/*
	307	* Though spec said the state of 8254 is undefined after power-up,
	308	* seems some tricky OS like Windows XP depends on IRQ0 interrupt
	309	* when booting up.
	310	* So here setting initialize rate for it, and not a specific number
	311	*/
	312	if (val == 0)
	313	val = 0x10000;
	314
7837699f SY	315	ps->channels[channel].count = val;
7837699f SY	316
fd668423 MT	317	if (channel != 0) {
fd668423 MT	318	ps->channels[channel].count_load_time = ktime_get();
7837699f	319	return;
fd668423	320	}
7837699f SY	321
	322	/* Two types of timer
	323	* mode 1 is one shot, mode 2 is period, otherwise del timer */
	324	switch (ps->channels[0].mode) {
	325	case 1:
ece15bab MT	326	/* FIXME: enhance mode 4 precision */
ece15bab MT	327	case 4:
3cf57fed	328	create_pit_timer(ps, val, 0);
7837699f SY	329	break;
7837699f SY	330	case 2:
f6975545	331	case 3:
3cf57fed	332	create_pit_timer(ps, val, 1);
7837699f SY	333	break;
	334	default:
	335	destroy_pit_timer(&ps->pit_timer);
	336	}
	337	}
	338
e0f63cb9 SY	339	void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
	340	{
	341	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	342	pit_load_count(kvm, channel, val);
	343	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	344	}
	345
7837699f SY	346	static void pit_ioport_write(struct kvm_io_device *this,
	347	gpa_t addr, int len, const void *data)
	348	{
	349	struct kvm_pit pit = (struct kvm_pit )this->private;
	350	struct kvm_kpit_state *pit_state = &pit->pit_state;
	351	struct kvm *kvm = pit->kvm;
	352	int channel, access;
	353	struct kvm_kpit_channel_state *s;
	354	u32 val = (u32 ) data;
	355
	356	val &= 0xff;
	357	addr &= KVM_PIT_CHANNEL_MASK;
	358
	359	mutex_lock(&pit_state->lock);
	360
	361	if (val != 0)
	362	pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
	363	(unsigned int)addr, len, val);
	364
	365	if (addr == 3) {
	366	channel = val >> 6;
	367	if (channel == 3) {
	368	/* Read-Back Command. */
	369	for (channel = 0; channel < 3; channel++) {
	370	s = &pit_state->channels[channel];
	371	if (val & (2 << channel)) {
	372	if (!(val & 0x20))
	373	pit_latch_count(kvm, channel);
	374	if (!(val & 0x10))
	375	pit_latch_status(kvm, channel);
	376	}
	377	}
	378	} else {
	379	/* Select Counter <channel>. */
	380	s = &pit_state->channels[channel];
	381	access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
	382	if (access == 0) {
	383	pit_latch_count(kvm, channel);
	384	} else {
	385	s->rw_mode = access;
	386	s->read_state = access;
	387	s->write_state = access;
	388	s->mode = (val >> 1) & 7;
	389	if (s->mode > 5)
	390	s->mode -= 4;
	391	s->bcd = val & 1;
	392	}
	393	}
	394	} else {
	395	/* Write Count. */
	396	s = &pit_state->channels[addr];
	397	switch (s->write_state) {
	398	default:
	399	case RW_STATE_LSB:
	400	pit_load_count(kvm, addr, val);
	401	break;
	402	case RW_STATE_MSB:
	403	pit_load_count(kvm, addr, val << 8);
	404	break;
	405	case RW_STATE_WORD0:
	406	s->write_latch = val;
	407	s->write_state = RW_STATE_WORD1;
	408	break;
	409	case RW_STATE_WORD1:
410	pit_load_count(kvm, addr, s->write_latch \| (val << 8));
411	s->write_state = RW_STATE_WORD0;
412	break;
413	}
414	}
415
416	mutex_unlock(&pit_state->lock);
417	}
418
419	static void pit_ioport_read(struct kvm_io_device *this,
420	gpa_t addr, int len, void *data)
421	{
422	struct kvm_pit pit = (struct kvm_pit )this->private;
423	struct kvm_kpit_state *pit_state = &pit->pit_state;
424	struct kvm *kvm = pit->kvm;
425	int ret, count;
426	struct kvm_kpit_channel_state *s;
427
428	addr &= KVM_PIT_CHANNEL_MASK;
429	s = &pit_state->channels[addr];
430
431	mutex_lock(&pit_state->lock);
432
433	if (s->status_latched) {
434	s->status_latched = 0;
435	ret = s->status;
436	} else if (s->count_latched) {
437	switch (s->count_latched) {
438	default:
439	case RW_STATE_LSB:
440	ret = s->latched_count & 0xff;
441	s->count_latched = 0;
442	break;
443	case RW_STATE_MSB:
444	ret = s->latched_count >> 8;
445	s->count_latched = 0;
446	break;
447	case RW_STATE_WORD0:
448	ret = s->latched_count & 0xff;
449	s->count_latched = RW_STATE_MSB;
450	break;
451	}
452	} else {
453	switch (s->read_state) {
454	default:
455	case RW_STATE_LSB:
456	count = pit_get_count(kvm, addr);
457	ret = count & 0xff;
458	break;
459	case RW_STATE_MSB:
460	count = pit_get_count(kvm, addr);
461	ret = (count >> 8) & 0xff;
462	break;
463	case RW_STATE_WORD0:
464	count = pit_get_count(kvm, addr);
465	ret = count & 0xff;
466	s->read_state = RW_STATE_WORD1;
467	break;
468	case RW_STATE_WORD1:
469	count = pit_get_count(kvm, addr);
470	ret = (count >> 8) & 0xff;
471	s->read_state = RW_STATE_WORD0;
472	break;
473	}
474	}
475
476	if (len > sizeof(ret))
477	len = sizeof(ret);
478	memcpy(data, (char *)&ret, len);
479
480	mutex_unlock(&pit_state->lock);
481	}
482
92760499 LV	483	static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	484	int len, int is_write)
7837699f SY	485	{
	486	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
	487	(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
	488	}
	489
	490	static void speaker_ioport_write(struct kvm_io_device *this,
	491	gpa_t addr, int len, const void *data)
	492	{
	493	struct kvm_pit pit = (struct kvm_pit )this->private;
	494	struct kvm_kpit_state *pit_state = &pit->pit_state;
	495	struct kvm *kvm = pit->kvm;
	496	u32 val = (u32 ) data;
	497
	498	mutex_lock(&pit_state->lock);
	499	pit_state->speaker_data_on = (val >> 1) & 1;
	500	pit_set_gate(kvm, 2, val & 1);
	501	mutex_unlock(&pit_state->lock);
	502	}
	503
	504	static void speaker_ioport_read(struct kvm_io_device *this,
	505	gpa_t addr, int len, void *data)
	506	{
	507	struct kvm_pit pit = (struct kvm_pit )this->private;
	508	struct kvm_kpit_state *pit_state = &pit->pit_state;
	509	struct kvm *kvm = pit->kvm;
	510	unsigned int refresh_clock;
	511	int ret;
	512
	513	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	514	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
	515
	516	mutex_lock(&pit_state->lock);
	517	ret = ((pit_state->speaker_data_on << 1) \| pit_get_gate(kvm, 2) \|
	518	(pit_get_out(kvm, 2) << 5) \| (refresh_clock << 4));
	519	if (len > sizeof(ret))
	520	len = sizeof(ret);
	521	memcpy(data, (char *)&ret, len);
	522	mutex_unlock(&pit_state->lock);
	523	}
	524
92760499 LV	525	static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	526	int len, int is_write)
7837699f SY	527	{
	528	return (addr == KVM_SPEAKER_BASE_ADDRESS);
	529	}
	530
308b0f23	531	void kvm_pit_reset(struct kvm_pit *pit)
7837699f SY	532	{
7837699f SY	533	int i;
308b0f23 SY	534	struct kvm_kpit_channel_state *c;
	535
	536	mutex_lock(&pit->pit_state.lock);
	537	for (i = 0; i < 3; i++) {
	538	c = &pit->pit_state.channels[i];
	539	c->mode = 0xff;
	540	c->gate = (i != 2);
	541	pit_load_count(pit->kvm, i, 0);
	542	}
	543	mutex_unlock(&pit->pit_state.lock);
	544
	545	atomic_set(&pit->pit_state.pit_timer.pending, 0);
3cf57fed	546	pit->pit_state.irq_ack = 1;
308b0f23 SY	547	}
308b0f23 SY	548
4780c659 AK	549	static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
	550	{
	551	struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
	552
	553	if (!mask) {
	554	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	555	pit->pit_state.irq_ack = 1;
	556	}
	557	}
	558
308b0f23 SY	559	struct kvm_pit kvm_create_pit(struct kvm kvm)
308b0f23 SY	560	{
7837699f SY	561	struct kvm_pit *pit;
7837699f SY	562	struct kvm_kpit_state *pit_state;
7837699f SY	563
	564	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	565	if (!pit)
	566	return NULL;
	567
5550af4d	568	pit->irq_source_id = kvm_request_irq_source_id(kvm);
e17d1dc0 AK	569	if (pit->irq_source_id < 0) {
e17d1dc0 AK	570	kfree(pit);
5550af4d	571	return NULL;
e17d1dc0	572	}
5550af4d	573
7837699f SY	574	mutex_init(&pit->pit_state.lock);
7837699f SY	575	mutex_lock(&pit->pit_state.lock);
3cf57fed	576	spin_lock_init(&pit->pit_state.inject_lock);
7837699f SY	577
	578	/* Initialize PIO device */
	579	pit->dev.read = pit_ioport_read;
	580	pit->dev.write = pit_ioport_write;
	581	pit->dev.in_range = pit_in_range;
	582	pit->dev.private = pit;
	583	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
	584
	585	pit->speaker_dev.read = speaker_ioport_read;
	586	pit->speaker_dev.write = speaker_ioport_write;
	587	pit->speaker_dev.in_range = speaker_in_range;
	588	pit->speaker_dev.private = pit;
	589	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
	590
	591	kvm->arch.vpit = pit;
	592	pit->kvm = kvm;
	593
	594	pit_state = &pit->pit_state;
	595	pit_state->pit = pit;
	596	hrtimer_init(&pit_state->pit_timer.timer,
	597	CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
3cf57fed MT	598	pit_state->irq_ack_notifier.gsi = 0;
	599	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	600	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
52d939a0	601	pit_state->pit_timer.reinject = true;
7837699f SY	602	mutex_unlock(&pit->pit_state.lock);
7837699f SY	603
308b0f23	604	kvm_pit_reset(pit);
7837699f	605
4780c659 AK	606	pit->mask_notifier.func = pit_mask_notifer;
	607	kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
	608
7837699f SY	609	return pit;
	610	}
	611
	612	void kvm_free_pit(struct kvm *kvm)
	613	{
	614	struct hrtimer *timer;
	615
	616	if (kvm->arch.vpit) {
4780c659 AK	617	kvm_unregister_irq_mask_notifier(kvm, 0,
4780c659 AK	618	&kvm->arch.vpit->mask_notifier);
7837699f SY	619	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	620	timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
	621	hrtimer_cancel(timer);
5550af4d	622	kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
7837699f SY	623	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	624	kfree(kvm->arch.vpit);
	625	}
	626	}
	627
8b2cf73c	628	static void __inject_pit_timer_intr(struct kvm *kvm)
7837699f	629	{
23930f95 JK	630	struct kvm_vcpu *vcpu;
	631	int i;
	632
7837699f	633	mutex_lock(&kvm->lock);
5550af4d SY	634	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
5550af4d SY	635	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
7837699f	636	mutex_unlock(&kvm->lock);
23930f95 JK	637
23930f95 JK	638	/*
8fdb2351 JK	639	* Provides NMI watchdog support via Virtual Wire mode.
	640	* The route is: PIT -> PIC -> LVT0 in NMI mode.
	641	*
	642	* Note: Our Virtual Wire implementation is simplified, only
	643	* propagating PIT interrupts to all VCPUs when they have set
	644	* LVT0 to NMI delivery. Other PIC interrupts are just sent to
	645	* VCPU0, and only if its LVT0 is in EXTINT mode.
23930f95	646	*/
cc6e462c JK	647	if (kvm->arch.vapics_in_nmi_mode > 0)
	648	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
	649	vcpu = kvm->vcpus[i];
	650	if (vcpu)
	651	kvm_apic_nmi_wd_deliver(vcpu);
	652	}
7837699f SY	653	}
	654
	655	void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
	656	{
	657	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	658	struct kvm *kvm = vcpu->kvm;
	659	struct kvm_kpit_state *ps;
	660
	661	if (vcpu && pit) {
3cf57fed	662	int inject = 0;
7837699f SY	663	ps = &pit->pit_state;
7837699f SY	664
3cf57fed MT	665	/* Try to inject pending interrupts when
	666	* last one has been acked.
	667	*/
	668	spin_lock(&ps->inject_lock);
	669	if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
	670	ps->irq_ack = 0;
	671	inject = 1;
7837699f	672	}
3cf57fed MT	673	spin_unlock(&ps->inject_lock);
	674	if (inject)
	675	__inject_pit_timer_intr(kvm);
7837699f SY	676	}
7837699f SY	677	}