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Merge branch 'fix/asoc' into for-linus
[net-next-2.6.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
49#define ByteOp (1<<0) /* 8-bit operands. */
50/* Destination operand type. */
51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
9c9fddd0 54#define DstAcc (4<<1) /* Destination Accumulator */
a682e354 55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
6550e1f1 56#define DstMem64 (6<<1) /* 64bit memory operand */
9c9fddd0 57#define DstMask (7<<1)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
85#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 86/* Misc flags */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Mask (7<<29)
6aa8b732 96
43bb19cd 97enum {
1d6ad207 98 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 99 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 100 Group8, Group9,
43bb19cd
AK		 101};
102
45ed60b3 103static u32 opcode_table[256] = {
6aa8b732 104 /* 0x00 - 0x07 */
d380a5e4 105 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 109 /* 0x08 - 0x0F */
d380a5e4 110 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
113 ImplicitOps | Stack | No64, 0,
6aa8b732 114 /* 0x10 - 0x17 */
d380a5e4 115 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 117 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 118 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 119 /* 0x18 - 0x1F */
d380a5e4 120 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 122 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 123 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 124 /* 0x20 - 0x27 */
d380a5e4 125 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
e97e883f 127 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 128 /* 0x28 - 0x2F */
d380a5e4 129 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
abc19083 131 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 132 /* 0x30 - 0x37 */
d380a5e4 133 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 134 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
222b7c52 135 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 136 /* 0x38 - 0x3F */
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 139 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
140 0, 0,
d77a2507 141 /* 0x40 - 0x47 */
33615aa9 142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 143 /* 0x48 - 0x4F */
33615aa9 144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 145 /* 0x50 - 0x57 */
6e3d5dfb
AK		 146 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
147 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 148 /* 0x58 - 0x5F */
6e3d5dfb
AK		 149 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
150 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 151 /* 0x60 - 0x67 */
abcf14b5
MG		 152 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
153 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 154 0, 0, 0, 0,
155 /* 0x68 - 0x6F */
91ed7a0e 156 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 157 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
158 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
55bebde4 159 /* 0x70 - 0x77 */
b2833e3c
GN		 160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 162 /* 0x78 - 0x7F */
b2833e3c
GN		 163 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
164 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 165 /* 0x80 - 0x87 */
1d6ad207
AK		 166 Group | Group1_80, Group | Group1_81,
167 Group | Group1_82, Group | Group1_83,
6aa8b732 168 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 169 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 170 /* 0x88 - 0x8F */
171 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
172 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
b16b2b7b 173 DstMem | SrcNone | ModRM | Mov, ModRM | DstReg,
a5046e6c 174 ImplicitOps | SrcMem16 | ModRM, Group | Group1A,
b13354f8
MG		 175 /* 0x90 - 0x97 */
176 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
177 /* 0x98 - 0x9F */
414e6277 178 0, 0, SrcImmFAddr | No64, 0,
0654169e 179 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 180 /* 0xA0 - 0xA7 */
5d55f299
WY		 181 ByteOp | DstAcc | SrcMem | Mov | MemAbs, DstAcc | SrcMem | Mov | MemAbs,
182 ByteOp | DstMem | SrcAcc | Mov | MemAbs, DstMem | SrcAcc | Mov | MemAbs,
a682e354
GN		 183 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
184 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 185 /* 0xA8 - 0xAF */
dfb507c4 186 DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
a682e354
GN		 187 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
188 ByteOp | DstDI | String, DstDI | String,
a5e2e82b
MG		 189 /* 0xB0 - 0xB7 */
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
193 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
194 /* 0xB8 - 0xBF */
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
197 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
198 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 199 /* 0xC0 - 0xC7 */
d9413cd7 200 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 201 0, ImplicitOps | Stack, 0, 0,
d9413cd7 202 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 203 /* 0xC8 - 0xCF */
e637b823 204 0, 0, 0, ImplicitOps | Stack,
d8769fed 205 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 206 /* 0xD0 - 0xD7 */
207 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
208 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
209 0, 0, 0, 0,
210 /* 0xD8 - 0xDF */
211 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 212 /* 0xE0 - 0xE7 */
a6a3034c 213 0, 0, 0, 0,
cf8f70bf
GN		 214 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
215 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 216 /* 0xE8 - 0xEF */
d53c4777 217 SrcImm | Stack, SrcImm | ImplicitOps,
414e6277 218 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 219 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
220 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 221 /* 0xF0 - 0xF7 */
222 0, 0, 0, 0,
e92805ac 223 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 224 /* 0xF8 - 0xFF */
b284be57 225 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 226 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 227};
228
45ed60b3 229static u32 twobyte_table[256] = {
6aa8b732 230 /* 0x00 - 0x0F */
e92805ac
GN		 231 0, Group | GroupDual | Group7, 0, 0,
232 0, ImplicitOps, ImplicitOps | Priv, 0,
233 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
234 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 235 /* 0x10 - 0x1F */
236 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
237 /* 0x20 - 0x2F */
e92805ac
GN		 238 ModRM | ImplicitOps | Priv, ModRM | Priv,
239 ModRM | ImplicitOps | Priv, ModRM | Priv,
240 0, 0, 0, 0,
6aa8b732
AK		 241 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0x30 - 0x3F */
e92805ac
GN		 243 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
244 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 245 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 246 /* 0x40 - 0x47 */
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 /* 0x48 - 0x4F */
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
255 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
256 /* 0x50 - 0x5F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x60 - 0x6F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x70 - 0x7F */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0x80 - 0x8F */
b2833e3c
GN		 263 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
264 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 265 /* 0x90 - 0x9F */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
267 /* 0xA0 - 0xA7 */
0934ac9d
MG		 268 ImplicitOps | Stack, ImplicitOps | Stack,
269 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 270 DstMem | SrcReg | Src2ImmByte | ModRM,
271 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 272 /* 0xA8 - 0xAF */
0934ac9d 273 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 274 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 275 DstMem | SrcReg | Src2ImmByte | ModRM,
276 DstMem | SrcReg | Src2CL | ModRM,
277 ModRM, 0,
6aa8b732 278 /* 0xB0 - 0xB7 */
d380a5e4
GN		 279 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
280 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 281 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
282 DstReg | SrcMem16 | ModRM | Mov,
283 /* 0xB8 - 0xBF */
d380a5e4
GN		 284 0, 0,
285 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 286 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
287 DstReg | SrcMem16 | ModRM | Mov,
288 /* 0xC0 - 0xCF */
60a29d4e
GN		 289 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
290 0, 0, 0, Group | GroupDual | Group9,
a012e65a 291 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 292 /* 0xD0 - 0xDF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xE0 - 0xEF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 /* 0xF0 - 0xFF */
297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
298};
299
45ed60b3 300static u32 group_table[] = {
1d6ad207 301 [Group1_80*8] =
d380a5e4
GN		 302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM | Lock,
308 ByteOp | DstMem | SrcImm | ModRM | Lock,
309 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 310 [Group1_81*8] =
d380a5e4
GN		 311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM | Lock,
317 DstMem | SrcImm | ModRM | Lock,
318 DstMem | SrcImm | ModRM,
1d6ad207 319 [Group1_82*8] =
e424e191
GN		 320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
326 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
327 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 328 [Group1_83*8] =
d380a5e4
GN		 329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM | Lock,
335 DstMem | SrcImmByte | ModRM | Lock,
336 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 337 [Group1A*8] =
338 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19 339 [Group3_Byte*8] =
7d5993d6 340 ByteOp | SrcImm | DstMem | ModRM, ByteOp | SrcImm | DstMem | ModRM,
7d858a19
AK		 341 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
342 0, 0, 0, 0,
343 [Group3*8] =
7d5993d6 344 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
6eb06cb2 345 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 346 0, 0, 0, 0,
fd60754e 347 [Group4*8] =
c0e0608c 348 ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock,
fd60754e
AK		 349 0, 0, 0, 0, 0, 0,
350 [Group5*8] =
c0e0608c 351 DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock,
d19292e4 352 SrcMem | ModRM | Stack, 0,
414e6277 353 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
ea79849d 354 SrcMem | ModRM | Stack, 0,
d95058a1 355 [Group7*8] =
e92805ac 356 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 357 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 358 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 359 [Group8*8] =
360 0, 0, 0, 0,
d380a5e4
GN		 361 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
362 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 363 [Group9*8] =
6550e1f1 364 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 365};
366
45ed60b3 367static u32 group2_table[] = {
d95058a1 368 [Group7*8] =
835e6b80 369 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 370 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 371 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 372 [Group9*8] =
373 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 374};
375
6aa8b732 376/* EFLAGS bit definitions. */
d4c6a154
GN		 377#define EFLG_ID (1<<21)
378#define EFLG_VIP (1<<20)
379#define EFLG_VIF (1<<19)
380#define EFLG_AC (1<<18)
b1d86143
AP		 381#define EFLG_VM (1<<17)
382#define EFLG_RF (1<<16)
d4c6a154
GN		 383#define EFLG_IOPL (3<<12)
384#define EFLG_NT (1<<14)
6aa8b732
AK		 385#define EFLG_OF (1<<11)
386#define EFLG_DF (1<<10)
b1d86143 387#define EFLG_IF (1<<9)
d4c6a154 388#define EFLG_TF (1<<8)
6aa8b732
AK		 389#define EFLG_SF (1<<7)
390#define EFLG_ZF (1<<6)
391#define EFLG_AF (1<<4)
392#define EFLG_PF (1<<2)
393#define EFLG_CF (1<<0)
394
395/*
396 * Instruction emulation:
397 * Most instructions are emulated directly via a fragment of inline assembly
398 * code. This allows us to save/restore EFLAGS and thus very easily pick up
399 * any modified flags.
400 */
401
05b3e0c2 402#if defined(CONFIG_X86_64)
6aa8b732
AK		 403#define _LO32 "k" /* force 32-bit operand */
404#define _STK "%%rsp" /* stack pointer */
405#elif defined(__i386__)
406#define _LO32 "" /* force 32-bit operand */
407#define _STK "%%esp" /* stack pointer */
408#endif
409
410/*
411 * These EFLAGS bits are restored from saved value during emulation, and
412 * any changes are written back to the saved value after emulation.
413 */
414#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
415
416/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 417#define _PRE_EFLAGS(_sav, _msk, _tmp) \
418 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
419 "movl %"_sav",%"_LO32 _tmp"; " \
420 "push %"_tmp"; " \
421 "push %"_tmp"; " \
422 "movl %"_msk",%"_LO32 _tmp"; " \
423 "andl %"_LO32 _tmp",("_STK"); " \
424 "pushf; " \
425 "notl %"_LO32 _tmp"; " \
426 "andl %"_LO32 _tmp",("_STK"); " \
427 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
428 "pop %"_tmp"; " \
429 "orl %"_LO32 _tmp",("_STK"); " \
430 "popf; " \
431 "pop %"_sav"; "
6aa8b732
AK		 432
433/* After executing instruction: write-back necessary bits in EFLAGS. */
434#define _POST_EFLAGS(_sav, _msk, _tmp) \
435 /* _sav |= EFLAGS & _msk; */ \
436 "pushf; " \
437 "pop %"_tmp"; " \
438 "andl %"_msk",%"_LO32 _tmp"; " \
439 "orl %"_LO32 _tmp",%"_sav"; "
440
dda96d8f
AK		 441#ifdef CONFIG_X86_64
442#define ON64(x) x
443#else
444#define ON64(x)
445#endif
446
6b7ad61f
AK		 447#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
448 do { \
449 __asm__ __volatile__ ( \
450 _PRE_EFLAGS("0", "4", "2") \
451 _op _suffix " %"_x"3,%1; " \
452 _POST_EFLAGS("0", "4", "2") \
453 : "=m" (_eflags), "=m" ((_dst).val), \
454 "=&r" (_tmp) \
455 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 456 } while (0)
6b7ad61f
AK		 457
458
6aa8b732
AK		 459/* Raw emulation: instruction has two explicit operands. */
460#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 461 do { \
462 unsigned long _tmp; \
463 \
464 switch ((_dst).bytes) { \
465 case 2: \
466 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
467 break; \
468 case 4: \
469 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
470 break; \
471 case 8: \
472 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
473 break; \
474 } \
6aa8b732
AK		 475 } while (0)
476
477#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
478 do { \
6b7ad61f 479 unsigned long _tmp; \
d77c26fc 480 switch ((_dst).bytes) { \
6aa8b732 481 case 1: \
6b7ad61f 482 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 483 break; \
484 default: \
485 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
486 _wx, _wy, _lx, _ly, _qx, _qy); \
487 break; \
488 } \
489 } while (0)
490
491/* Source operand is byte-sized and may be restricted to just %cl. */
492#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
493 __emulate_2op(_op, _src, _dst, _eflags, \
494 "b", "c", "b", "c", "b", "c", "b", "c")
495
496/* Source operand is byte, word, long or quad sized. */
497#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
498 __emulate_2op(_op, _src, _dst, _eflags, \
499 "b", "q", "w", "r", _LO32, "r", "", "r")
500
501/* Source operand is word, long or quad sized. */
502#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
503 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
504 "w", "r", _LO32, "r", "", "r")
505
d175226a
GT		 506/* Instruction has three operands and one operand is stored in ECX register */
507#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
508 do { \
509 unsigned long _tmp; \
510 _type _clv = (_cl).val; \
511 _type _srcv = (_src).val; \
512 _type _dstv = (_dst).val; \
513 \
514 __asm__ __volatile__ ( \
515 _PRE_EFLAGS("0", "5", "2") \
516 _op _suffix " %4,%1 \n" \
517 _POST_EFLAGS("0", "5", "2") \
518 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
519 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
520 ); \
521 \
522 (_cl).val = (unsigned long) _clv; \
523 (_src).val = (unsigned long) _srcv; \
524 (_dst).val = (unsigned long) _dstv; \
525 } while (0)
526
527#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
528 do { \
529 switch ((_dst).bytes) { \
530 case 2: \
531 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
532 "w", unsigned short); \
533 break; \
534 case 4: \
535 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
536 "l", unsigned int); \
537 break; \
538 case 8: \
539 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
540 "q", unsigned long)); \
541 break; \
542 } \
543 } while (0)
544
dda96d8f 545#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 546 do { \
547 unsigned long _tmp; \
548 \
dda96d8f
AK		 549 __asm__ __volatile__ ( \
550 _PRE_EFLAGS("0", "3", "2") \
551 _op _suffix " %1; " \
552 _POST_EFLAGS("0", "3", "2") \
553 : "=m" (_eflags), "+m" ((_dst).val), \
554 "=&r" (_tmp) \
555 : "i" (EFLAGS_MASK)); \
556 } while (0)
557
558/* Instruction has only one explicit operand (no source operand). */
559#define emulate_1op(_op, _dst, _eflags) \
560 do { \
d77c26fc 561 switch ((_dst).bytes) { \
dda96d8f
AK		 562 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
563 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
564 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
565 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 566 } \
567 } while (0)
568
6aa8b732
AK		 569/* Fetch next part of the instruction being emulated. */
570#define insn_fetch(_type, _size, _eip) \
571({ unsigned long _x; \
62266869 572 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 573 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 574 goto done; \
575 (_eip) += (_size); \
576 (_type)_x; \
577})
578
414e6277
GN		 579#define insn_fetch_arr(_arr, _size, _eip) \
580({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
581 if (rc != X86EMUL_CONTINUE) \
582 goto done; \
583 (_eip) += (_size); \
584})
585
ddcb2885
HH		 586static inline unsigned long ad_mask(struct decode_cache *c)
587{
588 return (1UL << (c->ad_bytes << 3)) - 1;
589}
590
6aa8b732 591/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 592static inline unsigned long
593address_mask(struct decode_cache *c, unsigned long reg)
594{
595 if (c->ad_bytes == sizeof(unsigned long))
596 return reg;
597 else
598 return reg & ad_mask(c);
599}
600
601static inline unsigned long
602register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
603{
604 return base + address_mask(c, reg);
605}
606
7a957275
HH		 607static inline void
608register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
609{
610 if (c->ad_bytes == sizeof(unsigned long))
611 *reg += inc;
612 else
613 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
614}
6aa8b732 615
7a957275
HH		 616static inline void jmp_rel(struct decode_cache *c, int rel)
617{
618 register_address_increment(c, &c->eip, rel);
619}
098c937b 620
7a5b56df
AK		 621static void set_seg_override(struct decode_cache *c, int seg)
622{
623 c->has_seg_override = true;
624 c->seg_override = seg;
625}
626
79168fd1
GN		 627static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
628 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 629{
630 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
631 return 0;
632
79168fd1 633 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 634}
635
636static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 637 struct x86_emulate_ops *ops,
7a5b56df
AK		 638 struct decode_cache *c)
639{
640 if (!c->has_seg_override)
641 return 0;
642
79168fd1 643 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 644}
645
79168fd1
GN		 646static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
647 struct x86_emulate_ops *ops)
7a5b56df 648{
79168fd1 649 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 650}
651
79168fd1
GN		 652static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops)
7a5b56df 654{
79168fd1 655 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 656}
657
54b8486f
GN		 658static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
659 u32 error, bool valid)
660{
661 ctxt->exception = vec;
662 ctxt->error_code = error;
663 ctxt->error_code_valid = valid;
664 ctxt->restart = false;
665}
666
667static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
668{
669 emulate_exception(ctxt, GP_VECTOR, err, true);
670}
671
672static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
673 int err)
674{
675 ctxt->cr2 = addr;
676 emulate_exception(ctxt, PF_VECTOR, err, true);
677}
678
679static void emulate_ud(struct x86_emulate_ctxt *ctxt)
680{
681 emulate_exception(ctxt, UD_VECTOR, 0, false);
682}
683
684static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
685{
686 emulate_exception(ctxt, TS_VECTOR, err, true);
687}
688
62266869
AK		 689static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
690 struct x86_emulate_ops *ops,
2fb53ad8 691 unsigned long eip, u8 *dest)
62266869
AK		 692{
693 struct fetch_cache *fc = &ctxt->decode.fetch;
694 int rc;
2fb53ad8 695 int size, cur_size;
62266869 696
2fb53ad8
AK		 697 if (eip == fc->end) {
698 cur_size = fc->end - fc->start;
699 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
700 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
701 size, ctxt->vcpu, NULL);
3e2815e9 702 if (rc != X86EMUL_CONTINUE)
62266869 703 return rc;
2fb53ad8 704 fc->end += size;
62266869 705 }
2fb53ad8 706 *dest = fc->data[eip - fc->start];
3e2815e9 707 return X86EMUL_CONTINUE;
62266869
AK		 708}
709
710static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 unsigned long eip, void *dest, unsigned size)
713{
3e2815e9 714 int rc;
62266869 715
eb3c79e6 716 /* x86 instructions are limited to 15 bytes. */
063db061 717 if (eip + size - ctxt->eip > 15)
eb3c79e6 718 return X86EMUL_UNHANDLEABLE;
62266869
AK		 719 while (size--) {
720 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 721 if (rc != X86EMUL_CONTINUE)
62266869
AK		 722 return rc;
723 }
3e2815e9 724 return X86EMUL_CONTINUE;
62266869
AK		 725}
726
1e3c5cb0
RR		 727/*
728 * Given the 'reg' portion of a ModRM byte, and a register block, return a
729 * pointer into the block that addresses the relevant register.
730 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
731 */
732static void *decode_register(u8 modrm_reg, unsigned long *regs,
733 int highbyte_regs)
6aa8b732
AK		 734{
735 void *p;
736
737 p = &regs[modrm_reg];
738 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
739 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
740 return p;
741}
742
743static int read_descriptor(struct x86_emulate_ctxt *ctxt,
744 struct x86_emulate_ops *ops,
745 void *ptr,
746 u16 *size, unsigned long *address, int op_bytes)
747{
748 int rc;
749
750 if (op_bytes == 2)
751 op_bytes = 3;
752 *address = 0;
cebff02b 753 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 754 ctxt->vcpu, NULL);
1b30eaa8 755 if (rc != X86EMUL_CONTINUE)
6aa8b732 756 return rc;
cebff02b 757 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 758 ctxt->vcpu, NULL);
6aa8b732
AK		 759 return rc;
760}
761
bbe9abbd
NK		 762static int test_cc(unsigned int condition, unsigned int flags)
763{
764 int rc = 0;
765
766 switch ((condition & 15) >> 1) {
767 case 0: /* o */
768 rc |= (flags & EFLG_OF);
769 break;
770 case 1: /* b/c/nae */
771 rc |= (flags & EFLG_CF);
772 break;
773 case 2: /* z/e */
774 rc |= (flags & EFLG_ZF);
775 break;
776 case 3: /* be/na */
777 rc |= (flags & (EFLG_CF|EFLG_ZF));
778 break;
779 case 4: /* s */
780 rc |= (flags & EFLG_SF);
781 break;
782 case 5: /* p/pe */
783 rc |= (flags & EFLG_PF);
784 break;
785 case 7: /* le/ng */
786 rc |= (flags & EFLG_ZF);
787 /* fall through */
788 case 6: /* l/nge */
789 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
790 break;
791 }
792
793 /* Odd condition identifiers (lsb == 1) have inverted sense. */
794 return (!!rc ^ (condition & 1));
795}
796
3c118e24
AK		 797static void decode_register_operand(struct operand *op,
798 struct decode_cache *c,
3c118e24
AK		 799 int inhibit_bytereg)
800{
33615aa9 801 unsigned reg = c->modrm_reg;
9f1ef3f8 802 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 803
804 if (!(c->d & ModRM))
805 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 806 op->type = OP_REG;
807 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 808 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 809 op->val = *(u8 *)op->ptr;
810 op->bytes = 1;
811 } else {
33615aa9 812 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 813 op->bytes = c->op_bytes;
814 switch (op->bytes) {
815 case 2:
816 op->val = *(u16 *)op->ptr;
817 break;
818 case 4:
819 op->val = *(u32 *)op->ptr;
820 break;
821 case 8:
822 op->val = *(u64 *) op->ptr;
823 break;
824 }
825 }
826 op->orig_val = op->val;
827}
828
1c73ef66
AK		 829static int decode_modrm(struct x86_emulate_ctxt *ctxt,
830 struct x86_emulate_ops *ops)
831{
832 struct decode_cache *c = &ctxt->decode;
833 u8 sib;
f5b4edcd 834 int index_reg = 0, base_reg = 0, scale;
3e2815e9 835 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 836
837 if (c->rex_prefix) {
838 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
839 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
840 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
841 }
842
843 c->modrm = insn_fetch(u8, 1, c->eip);
844 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
845 c->modrm_reg |= (c->modrm & 0x38) >> 3;
846 c->modrm_rm |= (c->modrm & 0x07);
847 c->modrm_ea = 0;
848 c->use_modrm_ea = 1;
849
850 if (c->modrm_mod == 3) {
107d6d2e
AK		 851 c->modrm_ptr = decode_register(c->modrm_rm,
852 c->regs, c->d & ByteOp);
853 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 854 return rc;
855 }
856
857 if (c->ad_bytes == 2) {
858 unsigned bx = c->regs[VCPU_REGS_RBX];
859 unsigned bp = c->regs[VCPU_REGS_RBP];
860 unsigned si = c->regs[VCPU_REGS_RSI];
861 unsigned di = c->regs[VCPU_REGS_RDI];
862
863 /* 16-bit ModR/M decode. */
864 switch (c->modrm_mod) {
865 case 0:
866 if (c->modrm_rm == 6)
867 c->modrm_ea += insn_fetch(u16, 2, c->eip);
868 break;
869 case 1:
870 c->modrm_ea += insn_fetch(s8, 1, c->eip);
871 break;
872 case 2:
873 c->modrm_ea += insn_fetch(u16, 2, c->eip);
874 break;
875 }
876 switch (c->modrm_rm) {
877 case 0:
878 c->modrm_ea += bx + si;
879 break;
880 case 1:
881 c->modrm_ea += bx + di;
882 break;
883 case 2:
884 c->modrm_ea += bp + si;
885 break;
886 case 3:
887 c->modrm_ea += bp + di;
888 break;
889 case 4:
890 c->modrm_ea += si;
891 break;
892 case 5:
893 c->modrm_ea += di;
894 break;
895 case 6:
896 if (c->modrm_mod != 0)
897 c->modrm_ea += bp;
898 break;
899 case 7:
900 c->modrm_ea += bx;
901 break;
902 }
903 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
904 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 905 if (!c->has_seg_override)
906 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 907 c->modrm_ea = (u16)c->modrm_ea;
908 } else {
909 /* 32/64-bit ModR/M decode. */
84411d85 910 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 911 sib = insn_fetch(u8, 1, c->eip);
912 index_reg |= (sib >> 3) & 7;
913 base_reg |= sib & 7;
914 scale = sib >> 6;
915
dc71d0f1
AK		 916 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
917 c->modrm_ea += insn_fetch(s32, 4, c->eip);
918 else
1c73ef66 919 c->modrm_ea += c->regs[base_reg];
dc71d0f1 920 if (index_reg != 4)
1c73ef66 921 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 922 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
923 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 924 c->rip_relative = 1;
84411d85 925 } else
1c73ef66 926 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 927 switch (c->modrm_mod) {
928 case 0:
929 if (c->modrm_rm == 5)
930 c->modrm_ea += insn_fetch(s32, 4, c->eip);
931 break;
932 case 1:
933 c->modrm_ea += insn_fetch(s8, 1, c->eip);
934 break;
935 case 2:
936 c->modrm_ea += insn_fetch(s32, 4, c->eip);
937 break;
938 }
939 }
1c73ef66
AK		 940done:
941 return rc;
942}
943
944static int decode_abs(struct x86_emulate_ctxt *ctxt,
945 struct x86_emulate_ops *ops)
946{
947 struct decode_cache *c = &ctxt->decode;
3e2815e9 948 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 949
950 switch (c->ad_bytes) {
951 case 2:
952 c->modrm_ea = insn_fetch(u16, 2, c->eip);
953 break;
954 case 4:
955 c->modrm_ea = insn_fetch(u32, 4, c->eip);
956 break;
957 case 8:
958 c->modrm_ea = insn_fetch(u64, 8, c->eip);
959 break;
960 }
961done:
962 return rc;
963}
964
6aa8b732 965int
8b4caf66 966x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 967{
e4e03ded 968 struct decode_cache *c = &ctxt->decode;
3e2815e9 969 int rc = X86EMUL_CONTINUE;
6aa8b732 970 int mode = ctxt->mode;
e09d082c 971 int def_op_bytes, def_ad_bytes, group;
6aa8b732 972
6aa8b732 973
5cd21917
GN		 974 /* we cannot decode insn before we complete previous rep insn */
975 WARN_ON(ctxt->restart);
976
063db061 977 c->eip = ctxt->eip;
2fb53ad8 978 c->fetch.start = c->fetch.end = c->eip;
79168fd1 979 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 980
981 switch (mode) {
982 case X86EMUL_MODE_REAL:
a0044755 983 case X86EMUL_MODE_VM86:
6aa8b732 984 case X86EMUL_MODE_PROT16:
f21b8bf4 985 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 986 break;
987 case X86EMUL_MODE_PROT32:
f21b8bf4 988 def_op_bytes = def_ad_bytes = 4;
6aa8b732 989 break;
05b3e0c2 990#ifdef CONFIG_X86_64
6aa8b732 991 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 992 def_op_bytes = 4;
993 def_ad_bytes = 8;
6aa8b732
AK		 994 break;
995#endif
996 default:
997 return -1;
998 }
999
f21b8bf4
AK		 1000 c->op_bytes = def_op_bytes;
1001 c->ad_bytes = def_ad_bytes;
1002
6aa8b732 1003 /* Legacy prefixes. */
b4c6abfe 1004 for (;;) {
e4e03ded 1005 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 1006 case 0x66: /* operand-size override */
f21b8bf4
AK		 1007 /* switch between 2/4 bytes */
1008 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 1009 break;
1010 case 0x67: /* address-size override */
1011 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 1012 /* switch between 4/8 bytes */
f21b8bf4 1013 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 1014 else
e4e03ded 1015 /* switch between 2/4 bytes */
f21b8bf4 1016 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 1017 break;
7a5b56df 1018 case 0x26: /* ES override */
6aa8b732 1019 case 0x2e: /* CS override */
7a5b56df 1020 case 0x36: /* SS override */
6aa8b732 1021 case 0x3e: /* DS override */
7a5b56df 1022 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1023 break;
1024 case 0x64: /* FS override */
6aa8b732 1025 case 0x65: /* GS override */
7a5b56df 1026 set_seg_override(c, c->b & 7);
6aa8b732 1027 break;
b4c6abfe
LV		 1028 case 0x40 ... 0x4f: /* REX */
1029 if (mode != X86EMUL_MODE_PROT64)
1030 goto done_prefixes;
33615aa9 1031 c->rex_prefix = c->b;
b4c6abfe 1032 continue;
6aa8b732 1033 case 0xf0: /* LOCK */
e4e03ded 1034 c->lock_prefix = 1;
6aa8b732 1035 break;
ae6200ba 1036 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1037 c->rep_prefix = REPNE_PREFIX;
1038 break;
6aa8b732 1039 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1040 c->rep_prefix = REPE_PREFIX;
6aa8b732 1041 break;
6aa8b732
AK		 1042 default:
1043 goto done_prefixes;
1044 }
b4c6abfe
LV		 1045
1046 /* Any legacy prefix after a REX prefix nullifies its effect. */
1047
33615aa9 1048 c->rex_prefix = 0;
6aa8b732
AK		 1049 }
1050
1051done_prefixes:
1052
1053 /* REX prefix. */
1c73ef66 1054 if (c->rex_prefix)
33615aa9 1055 if (c->rex_prefix & 8)
e4e03ded 1056 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1057
1058 /* Opcode byte(s). */
e4e03ded
LV		 1059 c->d = opcode_table[c->b];
1060 if (c->d == 0) {
6aa8b732 1061 /* Two-byte opcode? */
e4e03ded
LV		 1062 if (c->b == 0x0f) {
1063 c->twobyte = 1;
1064 c->b = insn_fetch(u8, 1, c->eip);
1065 c->d = twobyte_table[c->b];
6aa8b732 1066 }
e09d082c 1067 }
6aa8b732 1068
e09d082c
AK		 1069 if (c->d & Group) {
1070 group = c->d & GroupMask;
1071 c->modrm = insn_fetch(u8, 1, c->eip);
1072 --c->eip;
1073
1074 group = (group << 3) + ((c->modrm >> 3) & 7);
1075 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1076 c->d = group2_table[group];
1077 else
1078 c->d = group_table[group];
1079 }
1080
1081 /* Unrecognised? */
1082 if (c->d == 0) {
1083 DPRINTF("Cannot emulate %02x\n", c->b);
1084 return -1;
6aa8b732
AK		 1085 }
1086
6e3d5dfb
AK		 1087 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1088 c->op_bytes = 8;
1089
6aa8b732 1090 /* ModRM and SIB bytes. */
1c73ef66
AK		 1091 if (c->d & ModRM)
1092 rc = decode_modrm(ctxt, ops);
1093 else if (c->d & MemAbs)
1094 rc = decode_abs(ctxt, ops);
3e2815e9 1095 if (rc != X86EMUL_CONTINUE)
1c73ef66 1096 goto done;
6aa8b732 1097
7a5b56df
AK		 1098 if (!c->has_seg_override)
1099 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1100
7a5b56df 1101 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1102 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1103
1104 if (c->ad_bytes != 8)
1105 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1106
1107 if (c->rip_relative)
1108 c->modrm_ea += c->eip;
1109
6aa8b732
AK		 1110 /*
1111 * Decode and fetch the source operand: register, memory
1112 * or immediate.
1113 */
e4e03ded 1114 switch (c->d & SrcMask) {
6aa8b732
AK		 1115 case SrcNone:
1116 break;
1117 case SrcReg:
9f1ef3f8 1118 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1119 break;
1120 case SrcMem16:
e4e03ded 1121 c->src.bytes = 2;
6aa8b732
AK		 1122 goto srcmem_common;
1123 case SrcMem32:
e4e03ded 1124 c->src.bytes = 4;
6aa8b732
AK		 1125 goto srcmem_common;
1126 case SrcMem:
e4e03ded
LV		 1127 c->src.bytes = (c->d & ByteOp) ? 1 :
1128 c->op_bytes;
b85b9ee9 1129 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1130 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1131 break;
d77c26fc 1132 srcmem_common:
4e62417b
AJ		 1133 /*
1134 * For instructions with a ModR/M byte, switch to register
1135 * access if Mod = 3.
1136 */
e4e03ded
LV		 1137 if ((c->d & ModRM) && c->modrm_mod == 3) {
1138 c->src.type = OP_REG;
66b85505 1139 c->src.val = c->modrm_val;
107d6d2e 1140 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1141 break;
1142 }
e4e03ded 1143 c->src.type = OP_MEM;
69f55cb1
GN		 1144 c->src.ptr = (unsigned long *)c->modrm_ea;
1145 c->src.val = 0;
6aa8b732
AK		 1146 break;
1147 case SrcImm:
c9eaf20f 1148 case SrcImmU:
e4e03ded
LV		 1149 c->src.type = OP_IMM;
1150 c->src.ptr = (unsigned long *)c->eip;
1151 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1152 if (c->src.bytes == 8)
1153 c->src.bytes = 4;
6aa8b732 1154 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1155 switch (c->src.bytes) {
6aa8b732 1156 case 1:
e4e03ded 1157 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1158 break;
1159 case 2:
e4e03ded 1160 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1161 break;
1162 case 4:
e4e03ded 1163 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1164 break;
1165 }
c9eaf20f
AK		 1166 if ((c->d & SrcMask) == SrcImmU) {
1167 switch (c->src.bytes) {
1168 case 1:
1169 c->src.val &= 0xff;
1170 break;
1171 case 2:
1172 c->src.val &= 0xffff;
1173 break;
1174 case 4:
1175 c->src.val &= 0xffffffff;
1176 break;
1177 }
1178 }
6aa8b732
AK		 1179 break;
1180 case SrcImmByte:
341de7e3 1181 case SrcImmUByte:
e4e03ded
LV		 1182 c->src.type = OP_IMM;
1183 c->src.ptr = (unsigned long *)c->eip;
1184 c->src.bytes = 1;
341de7e3
GN		 1185 if ((c->d & SrcMask) == SrcImmByte)
1186 c->src.val = insn_fetch(s8, 1, c->eip);
1187 else
1188 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1189 break;
5d55f299
WY		 1190 case SrcAcc:
1191 c->src.type = OP_REG;
1192 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1193 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1194 switch (c->src.bytes) {
1195 case 1:
1196 c->src.val = *(u8 *)c->src.ptr;
1197 break;
1198 case 2:
1199 c->src.val = *(u16 *)c->src.ptr;
1200 break;
1201 case 4:
1202 c->src.val = *(u32 *)c->src.ptr;
1203 break;
1204 case 8:
1205 c->src.val = *(u64 *)c->src.ptr;
1206 break;
1207 }
1208 break;
bfcadf83
GT		 1209 case SrcOne:
1210 c->src.bytes = 1;
1211 c->src.val = 1;
1212 break;
a682e354
GN		 1213 case SrcSI:
1214 c->src.type = OP_MEM;
1215 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1216 c->src.ptr = (unsigned long *)
79168fd1 1217 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1218 c->regs[VCPU_REGS_RSI]);
1219 c->src.val = 0;
1220 break;
414e6277
GN		 1221 case SrcImmFAddr:
1222 c->src.type = OP_IMM;
1223 c->src.ptr = (unsigned long *)c->eip;
1224 c->src.bytes = c->op_bytes + 2;
1225 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1226 break;
1227 case SrcMemFAddr:
1228 c->src.type = OP_MEM;
1229 c->src.ptr = (unsigned long *)c->modrm_ea;
1230 c->src.bytes = c->op_bytes + 2;
1231 break;
6aa8b732
AK		 1232 }
1233
0dc8d10f
GT		 1234 /*
1235 * Decode and fetch the second source operand: register, memory
1236 * or immediate.
1237 */
1238 switch (c->d & Src2Mask) {
1239 case Src2None:
1240 break;
1241 case Src2CL:
1242 c->src2.bytes = 1;
1243 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1244 break;
1245 case Src2ImmByte:
1246 c->src2.type = OP_IMM;
1247 c->src2.ptr = (unsigned long *)c->eip;
1248 c->src2.bytes = 1;
1249 c->src2.val = insn_fetch(u8, 1, c->eip);
1250 break;
1251 case Src2One:
1252 c->src2.bytes = 1;
1253 c->src2.val = 1;
1254 break;
1255 }
1256
038e51de 1257 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1258 switch (c->d & DstMask) {
038e51de
AK		 1259 case ImplicitOps:
1260 /* Special instructions do their own operand decoding. */
8b4caf66 1261 return 0;
038e51de 1262 case DstReg:
9f1ef3f8 1263 decode_register_operand(&c->dst, c,
3c118e24 1264 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1265 break;
1266 case DstMem:
6550e1f1 1267 case DstMem64:
e4e03ded 1268 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1269 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1270 c->dst.type = OP_REG;
66b85505 1271 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1272 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1273 break;
1274 }
8b4caf66 1275 c->dst.type = OP_MEM;
69f55cb1 1276 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1277 if ((c->d & DstMask) == DstMem64)
1278 c->dst.bytes = 8;
1279 else
1280 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1281 c->dst.val = 0;
1282 if (c->d & BitOp) {
1283 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1284
1285 c->dst.ptr = (void *)c->dst.ptr +
1286 (c->src.val & mask) / 8;
1287 }
8b4caf66 1288 break;
9c9fddd0
GT		 1289 case DstAcc:
1290 c->dst.type = OP_REG;
d6d367d6 1291 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1292 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1293 switch (c->dst.bytes) {
9c9fddd0
GT		 1294 case 1:
1295 c->dst.val = *(u8 *)c->dst.ptr;
1296 break;
1297 case 2:
1298 c->dst.val = *(u16 *)c->dst.ptr;
1299 break;
1300 case 4:
1301 c->dst.val = *(u32 *)c->dst.ptr;
1302 break;
d6d367d6
GN		 1303 case 8:
1304 c->dst.val = *(u64 *)c->dst.ptr;
1305 break;
9c9fddd0
GT		 1306 }
1307 c->dst.orig_val = c->dst.val;
1308 break;
a682e354
GN		 1309 case DstDI:
1310 c->dst.type = OP_MEM;
1311 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1312 c->dst.ptr = (unsigned long *)
79168fd1 1313 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1314 c->regs[VCPU_REGS_RDI]);
1315 c->dst.val = 0;
1316 break;
8b4caf66
LV		 1317 }
1318
1319done:
1320 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1321}
1322
9de41573
GN		 1323static int read_emulated(struct x86_emulate_ctxt *ctxt,
1324 struct x86_emulate_ops *ops,
1325 unsigned long addr, void *dest, unsigned size)
1326{
1327 int rc;
1328 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1329 u32 err;
9de41573
GN		 1330
1331 while (size) {
1332 int n = min(size, 8u);
1333 size -= n;
1334 if (mc->pos < mc->end)
1335 goto read_cached;
1336
8fe681e9
GN		 1337 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1338 ctxt->vcpu);
1339 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1340 emulate_pf(ctxt, addr, err);
9de41573
GN		 1341 if (rc != X86EMUL_CONTINUE)
1342 return rc;
1343 mc->end += n;
1344
1345 read_cached:
1346 memcpy(dest, mc->data + mc->pos, n);
1347 mc->pos += n;
1348 dest += n;
1349 addr += n;
1350 }
1351 return X86EMUL_CONTINUE;
1352}
1353
7b262e90
GN		 1354static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1355 struct x86_emulate_ops *ops,
1356 unsigned int size, unsigned short port,
1357 void *dest)
1358{
1359 struct read_cache *rc = &ctxt->decode.io_read;
1360
1361 if (rc->pos == rc->end) { /* refill pio read ahead */
1362 struct decode_cache *c = &ctxt->decode;
1363 unsigned int in_page, n;
1364 unsigned int count = c->rep_prefix ?
1365 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1366 in_page = (ctxt->eflags & EFLG_DF) ?
1367 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1368 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1369 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1370 count);
1371 if (n == 0)
1372 n = 1;
1373 rc->pos = rc->end = 0;
1374 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1375 return 0;
1376 rc->end = n * size;
1377 }
1378
1379 memcpy(dest, rc->data + rc->pos, size);
1380 rc->pos += size;
1381 return 1;
1382}
1383
38ba30ba
GN		 1384static u32 desc_limit_scaled(struct desc_struct *desc)
1385{
1386 u32 limit = get_desc_limit(desc);
1387
1388 return desc->g ? (limit << 12) | 0xfff : limit;
1389}
1390
1391static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1392 struct x86_emulate_ops *ops,
1393 u16 selector, struct desc_ptr *dt)
1394{
1395 if (selector & 1 << 2) {
1396 struct desc_struct desc;
1397 memset (dt, 0, sizeof *dt);
1398 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1399 return;
1400
1401 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1402 dt->address = get_desc_base(&desc);
1403 } else
1404 ops->get_gdt(dt, ctxt->vcpu);
1405}
1406
1407/* allowed just for 8 bytes segments */
1408static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1409 struct x86_emulate_ops *ops,
1410 u16 selector, struct desc_struct *desc)
1411{
1412 struct desc_ptr dt;
1413 u16 index = selector >> 3;
1414 int ret;
1415 u32 err;
1416 ulong addr;
1417
1418 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1419
1420 if (dt.size < index * 8 + 7) {
54b8486f 1421 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1422 return X86EMUL_PROPAGATE_FAULT;
1423 }
1424 addr = dt.address + index * 8;
1425 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1426 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1427 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1428
1429 return ret;
1430}
1431
1432/* allowed just for 8 bytes segments */
1433static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1434 struct x86_emulate_ops *ops,
1435 u16 selector, struct desc_struct *desc)
1436{
1437 struct desc_ptr dt;
1438 u16 index = selector >> 3;
1439 u32 err;
1440 ulong addr;
1441 int ret;
1442
1443 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1444
1445 if (dt.size < index * 8 + 7) {
54b8486f 1446 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1447 return X86EMUL_PROPAGATE_FAULT;
1448 }
1449
1450 addr = dt.address + index * 8;
1451 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1452 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1453 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1454
1455 return ret;
1456}
1457
1458static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1459 struct x86_emulate_ops *ops,
1460 u16 selector, int seg)
1461{
1462 struct desc_struct seg_desc;
1463 u8 dpl, rpl, cpl;
1464 unsigned err_vec = GP_VECTOR;
1465 u32 err_code = 0;
1466 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1467 int ret;
1468
1469 memset(&seg_desc, 0, sizeof seg_desc);
1470
1471 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1472 || ctxt->mode == X86EMUL_MODE_REAL) {
1473 /* set real mode segment descriptor */
1474 set_desc_base(&seg_desc, selector << 4);
1475 set_desc_limit(&seg_desc, 0xffff);
1476 seg_desc.type = 3;
1477 seg_desc.p = 1;
1478 seg_desc.s = 1;
1479 goto load;
1480 }
1481
1482 /* NULL selector is not valid for TR, CS and SS */
1483 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1484 && null_selector)
1485 goto exception;
1486
1487 /* TR should be in GDT only */
1488 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1489 goto exception;
1490
1491 if (null_selector) /* for NULL selector skip all following checks */
1492 goto load;
1493
1494 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1495 if (ret != X86EMUL_CONTINUE)
1496 return ret;
1497
1498 err_code = selector & 0xfffc;
1499 err_vec = GP_VECTOR;
1500
1501 /* can't load system descriptor into segment selecor */
1502 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1503 goto exception;
1504
1505 if (!seg_desc.p) {
1506 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1507 goto exception;
1508 }
1509
1510 rpl = selector & 3;
1511 dpl = seg_desc.dpl;
1512 cpl = ops->cpl(ctxt->vcpu);
1513
1514 switch (seg) {
1515 case VCPU_SREG_SS:
1516 /*
1517 * segment is not a writable data segment or segment
1518 * selector's RPL != CPL or segment selector's RPL != CPL
1519 */
1520 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1521 goto exception;
1522 break;
1523 case VCPU_SREG_CS:
1524 if (!(seg_desc.type & 8))
1525 goto exception;
1526
1527 if (seg_desc.type & 4) {
1528 /* conforming */
1529 if (dpl > cpl)
1530 goto exception;
1531 } else {
1532 /* nonconforming */
1533 if (rpl > cpl || dpl != cpl)
1534 goto exception;
1535 }
1536 /* CS(RPL) <- CPL */
1537 selector = (selector & 0xfffc) | cpl;
1538 break;
1539 case VCPU_SREG_TR:
1540 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1541 goto exception;
1542 break;
1543 case VCPU_SREG_LDTR:
1544 if (seg_desc.s || seg_desc.type != 2)
1545 goto exception;
1546 break;
1547 default: /* DS, ES, FS, or GS */
1548 /*
1549 * segment is not a data or readable code segment or
1550 * ((segment is a data or nonconforming code segment)
1551 * and (both RPL and CPL > DPL))
1552 */
1553 if ((seg_desc.type & 0xa) == 0x8 ||
1554 (((seg_desc.type & 0xc) != 0xc) &&
1555 (rpl > dpl && cpl > dpl)))
1556 goto exception;
1557 break;
1558 }
1559
1560 if (seg_desc.s) {
1561 /* mark segment as accessed */
1562 seg_desc.type |= 1;
1563 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1564 if (ret != X86EMUL_CONTINUE)
1565 return ret;
1566 }
1567load:
1568 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1569 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1570 return X86EMUL_CONTINUE;
1571exception:
54b8486f 1572 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1573 return X86EMUL_PROPAGATE_FAULT;
1574}
1575
c37eda13
WY		 1576static inline int writeback(struct x86_emulate_ctxt *ctxt,
1577 struct x86_emulate_ops *ops)
1578{
1579 int rc;
1580 struct decode_cache *c = &ctxt->decode;
1581 u32 err;
1582
1583 switch (c->dst.type) {
1584 case OP_REG:
1585 /* The 4-byte case *is* correct:
1586 * in 64-bit mode we zero-extend.
1587 */
1588 switch (c->dst.bytes) {
1589 case 1:
1590 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1591 break;
1592 case 2:
1593 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1594 break;
1595 case 4:
1596 *c->dst.ptr = (u32)c->dst.val;
1597 break; /* 64b: zero-ext */
1598 case 8:
1599 *c->dst.ptr = c->dst.val;
1600 break;
1601 }
1602 break;
1603 case OP_MEM:
1604 if (c->lock_prefix)
1605 rc = ops->cmpxchg_emulated(
1606 (unsigned long)c->dst.ptr,
1607 &c->dst.orig_val,
1608 &c->dst.val,
1609 c->dst.bytes,
1610 &err,
1611 ctxt->vcpu);
1612 else
1613 rc = ops->write_emulated(
1614 (unsigned long)c->dst.ptr,
1615 &c->dst.val,
1616 c->dst.bytes,
1617 &err,
1618 ctxt->vcpu);
1619 if (rc == X86EMUL_PROPAGATE_FAULT)
1620 emulate_pf(ctxt,
1621 (unsigned long)c->dst.ptr, err);
1622 if (rc != X86EMUL_CONTINUE)
1623 return rc;
1624 break;
1625 case OP_NONE:
1626 /* no writeback */
1627 break;
1628 default:
1629 break;
1630 }
1631 return X86EMUL_CONTINUE;
1632}
1633
79168fd1
GN		 1634static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1635 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1636{
1637 struct decode_cache *c = &ctxt->decode;
1638
1639 c->dst.type = OP_MEM;
1640 c->dst.bytes = c->op_bytes;
1641 c->dst.val = c->src.val;
7a957275 1642 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1643 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1644 c->regs[VCPU_REGS_RSP]);
1645}
1646
faa5a3ae 1647static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1648 struct x86_emulate_ops *ops,
1649 void *dest, int len)
8cdbd2c9
LV		 1650{
1651 struct decode_cache *c = &ctxt->decode;
1652 int rc;
1653
79168fd1 1654 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1655 c->regs[VCPU_REGS_RSP]),
1656 dest, len);
b60d513c 1657 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1658 return rc;
1659
350f69dc 1660 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1661 return rc;
1662}
8cdbd2c9 1663
d4c6a154
GN		 1664static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1665 struct x86_emulate_ops *ops,
1666 void *dest, int len)
1667{
1668 int rc;
1669 unsigned long val, change_mask;
1670 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1671 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1672
1673 rc = emulate_pop(ctxt, ops, &val, len);
1674 if (rc != X86EMUL_CONTINUE)
1675 return rc;
1676
1677 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1678 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1679
1680 switch(ctxt->mode) {
1681 case X86EMUL_MODE_PROT64:
1682 case X86EMUL_MODE_PROT32:
1683 case X86EMUL_MODE_PROT16:
1684 if (cpl == 0)
1685 change_mask |= EFLG_IOPL;
1686 if (cpl <= iopl)
1687 change_mask |= EFLG_IF;
1688 break;
1689 case X86EMUL_MODE_VM86:
1690 if (iopl < 3) {
54b8486f 1691 emulate_gp(ctxt, 0);
d4c6a154
GN		 1692 return X86EMUL_PROPAGATE_FAULT;
1693 }
1694 change_mask |= EFLG_IF;
1695 break;
1696 default: /* real mode */
1697 change_mask |= (EFLG_IOPL | EFLG_IF);
1698 break;
1699 }
1700
1701 *(unsigned long *)dest =
1702 (ctxt->eflags & ~change_mask) | (val & change_mask);
1703
1704 return rc;
1705}
1706
79168fd1
GN		 1707static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1708 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1709{
1710 struct decode_cache *c = &ctxt->decode;
0934ac9d 1711
79168fd1 1712 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1713
79168fd1 1714 emulate_push(ctxt, ops);
0934ac9d
MG		 1715}
1716
1717static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1718 struct x86_emulate_ops *ops, int seg)
1719{
1720 struct decode_cache *c = &ctxt->decode;
1721 unsigned long selector;
1722 int rc;
1723
1724 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1725 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1726 return rc;
1727
2e873022 1728 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1729 return rc;
1730}
1731
c37eda13 1732static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1733 struct x86_emulate_ops *ops)
abcf14b5
MG		 1734{
1735 struct decode_cache *c = &ctxt->decode;
1736 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1737 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1738 int reg = VCPU_REGS_RAX;
1739
1740 while (reg <= VCPU_REGS_RDI) {
1741 (reg == VCPU_REGS_RSP) ?
1742 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1743
79168fd1 1744 emulate_push(ctxt, ops);
c37eda13
WY		 1745
1746 rc = writeback(ctxt, ops);
1747 if (rc != X86EMUL_CONTINUE)
1748 return rc;
1749
abcf14b5
MG		 1750 ++reg;
1751 }
c37eda13
WY		 1752
1753 /* Disable writeback. */
1754 c->dst.type = OP_NONE;
1755
1756 return rc;
abcf14b5
MG		 1757}
1758
1759static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1760 struct x86_emulate_ops *ops)
1761{
1762 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1763 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1764 int reg = VCPU_REGS_RDI;
1765
1766 while (reg >= VCPU_REGS_RAX) {
1767 if (reg == VCPU_REGS_RSP) {
1768 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1769 c->op_bytes);
1770 --reg;
1771 }
1772
1773 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1774 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1775 break;
1776 --reg;
1777 }
1778 return rc;
1779}
1780
faa5a3ae
AK		 1781static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1782 struct x86_emulate_ops *ops)
1783{
1784 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1785
1b30eaa8 1786 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1787}
1788
05f086f8 1789static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1790{
05f086f8 1791 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1792 switch (c->modrm_reg) {
1793 case 0: /* rol */
05f086f8 1794 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1795 break;
1796 case 1: /* ror */
05f086f8 1797 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1798 break;
1799 case 2: /* rcl */
05f086f8 1800 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1801 break;
1802 case 3: /* rcr */
05f086f8 1803 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1804 break;
1805 case 4: /* sal/shl */
1806 case 6: /* sal/shl */
05f086f8 1807 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1808 break;
1809 case 5: /* shr */
05f086f8 1810 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1811 break;
1812 case 7: /* sar */
05f086f8 1813 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1814 break;
1815 }
1816}
1817
1818static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1819 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1820{
1821 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1822
1823 switch (c->modrm_reg) {
1824 case 0 ... 1: /* test */
05f086f8 1825 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1826 break;
1827 case 2: /* not */
1828 c->dst.val = ~c->dst.val;
1829 break;
1830 case 3: /* neg */
05f086f8 1831 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1832 break;
1833 default:
aca06a83 1834 return 0;
8cdbd2c9 1835 }
aca06a83 1836 return 1;
8cdbd2c9
LV		 1837}
1838
1839static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1840 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1841{
1842 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1843
1844 switch (c->modrm_reg) {
1845 case 0: /* inc */
05f086f8 1846 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1847 break;
1848 case 1: /* dec */
05f086f8 1849 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1850 break;
d19292e4
MG		 1851 case 2: /* call near abs */ {
1852 long int old_eip;
1853 old_eip = c->eip;
1854 c->eip = c->src.val;
1855 c->src.val = old_eip;
79168fd1 1856 emulate_push(ctxt, ops);
d19292e4
MG		 1857 break;
1858 }
8cdbd2c9 1859 case 4: /* jmp abs */
fd60754e 1860 c->eip = c->src.val;
8cdbd2c9
LV		 1861 break;
1862 case 6: /* push */
79168fd1 1863 emulate_push(ctxt, ops);
8cdbd2c9 1864 break;
8cdbd2c9 1865 }
1b30eaa8 1866 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1867}
1868
1869static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1870 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1871{
1872 struct decode_cache *c = &ctxt->decode;
16518d5a 1873 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1874
1875 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1876 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1877 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1878 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1879 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1880 } else {
16518d5a
AK		 1881 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1882 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1883
05f086f8 1884 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1885 }
1b30eaa8 1886 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1887}
1888
a77ab5ea
AK		 1889static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1890 struct x86_emulate_ops *ops)
1891{
1892 struct decode_cache *c = &ctxt->decode;
1893 int rc;
1894 unsigned long cs;
1895
1896 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1897 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1898 return rc;
1899 if (c->op_bytes == 4)
1900 c->eip = (u32)c->eip;
1901 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1902 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1903 return rc;
2e873022 1904 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1905 return rc;
1906}
1907
e66bb2cc
AP		 1908static inline void
1909setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1910 struct x86_emulate_ops *ops, struct desc_struct *cs,
1911 struct desc_struct *ss)
e66bb2cc 1912{
79168fd1
GN		 1913 memset(cs, 0, sizeof(struct desc_struct));
1914 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1915 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1916
1917 cs->l = 0; /* will be adjusted later */
79168fd1 1918 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1919 cs->g = 1; /* 4kb granularity */
79168fd1 1920 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1921 cs->type = 0x0b; /* Read, Execute, Accessed */
1922 cs->s = 1;
1923 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1924 cs->p = 1;
1925 cs->d = 1;
e66bb2cc 1926
79168fd1
GN		 1927 set_desc_base(ss, 0); /* flat segment */
1928 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1929 ss->g = 1; /* 4kb granularity */
1930 ss->s = 1;
1931 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1932 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1933 ss->dpl = 0;
79168fd1 1934 ss->p = 1;
e66bb2cc
AP		 1935}
1936
1937static int
3fb1b5db 1938emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1939{
1940 struct decode_cache *c = &ctxt->decode;
79168fd1 1941 struct desc_struct cs, ss;
e66bb2cc 1942 u64 msr_data;
79168fd1 1943 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1944
1945 /* syscall is not available in real mode */
2e901c4c
GN		 1946 if (ctxt->mode == X86EMUL_MODE_REAL ||
1947 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1948 emulate_ud(ctxt);
2e901c4c
GN		 1949 return X86EMUL_PROPAGATE_FAULT;
1950 }
e66bb2cc 1951
79168fd1 1952 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1953
3fb1b5db 1954 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1955 msr_data >>= 32;
79168fd1
GN		 1956 cs_sel = (u16)(msr_data & 0xfffc);
1957 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1958
1959 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1960 cs.d = 0;
e66bb2cc
AP		 1961 cs.l = 1;
1962 }
79168fd1
GN		 1963 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1964 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1965 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1966 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1967
1968 c->regs[VCPU_REGS_RCX] = c->eip;
1969 if (is_long_mode(ctxt->vcpu)) {
1970#ifdef CONFIG_X86_64
1971 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1972
3fb1b5db
GN		 1973 ops->get_msr(ctxt->vcpu,
1974 ctxt->mode == X86EMUL_MODE_PROT64 ?
1975 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1976 c->eip = msr_data;
1977
3fb1b5db 1978 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1979 ctxt->eflags &= ~(msr_data | EFLG_RF);
1980#endif
1981 } else {
1982 /* legacy mode */
3fb1b5db 1983 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1984 c->eip = (u32)msr_data;
1985
1986 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1987 }
1988
e54cfa97 1989 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1990}
1991
8c604352 1992static int
3fb1b5db 1993emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1994{
1995 struct decode_cache *c = &ctxt->decode;
79168fd1 1996 struct desc_struct cs, ss;
8c604352 1997 u64 msr_data;
79168fd1 1998 u16 cs_sel, ss_sel;
8c604352 1999
a0044755
GN		 2000 /* inject #GP if in real mode */
2001 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2002 emulate_gp(ctxt, 0);
2e901c4c 2003 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2004 }
2005
2006 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2007 * Therefore, we inject an #UD.
2008 */
2e901c4c 2009 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2010 emulate_ud(ctxt);
2e901c4c
GN		 2011 return X86EMUL_PROPAGATE_FAULT;
2012 }
8c604352 2013
79168fd1 2014 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2015
3fb1b5db 2016 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2017 switch (ctxt->mode) {
2018 case X86EMUL_MODE_PROT32:
2019 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2020 emulate_gp(ctxt, 0);
e54cfa97 2021 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2022 }
2023 break;
2024 case X86EMUL_MODE_PROT64:
2025 if (msr_data == 0x0) {
54b8486f 2026 emulate_gp(ctxt, 0);
e54cfa97 2027 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2028 }
2029 break;
2030 }
2031
2032 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2033 cs_sel = (u16)msr_data;
2034 cs_sel &= ~SELECTOR_RPL_MASK;
2035 ss_sel = cs_sel + 8;
2036 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2037 if (ctxt->mode == X86EMUL_MODE_PROT64
2038 || is_long_mode(ctxt->vcpu)) {
79168fd1 2039 cs.d = 0;
8c604352
AP		 2040 cs.l = 1;
2041 }
2042
79168fd1
GN		 2043 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2044 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2045 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2046 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2047
3fb1b5db 2048 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2049 c->eip = msr_data;
2050
3fb1b5db 2051 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2052 c->regs[VCPU_REGS_RSP] = msr_data;
2053
e54cfa97 2054 return X86EMUL_CONTINUE;
8c604352
AP		 2055}
2056
4668f050 2057static int
3fb1b5db 2058emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2059{
2060 struct decode_cache *c = &ctxt->decode;
79168fd1 2061 struct desc_struct cs, ss;
4668f050
AP		 2062 u64 msr_data;
2063 int usermode;
79168fd1 2064 u16 cs_sel, ss_sel;
4668f050 2065
a0044755
GN		 2066 /* inject #GP if in real mode or Virtual 8086 mode */
2067 if (ctxt->mode == X86EMUL_MODE_REAL ||
2068 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2069 emulate_gp(ctxt, 0);
2e901c4c 2070 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2071 }
2072
79168fd1 2073 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2074
2075 if ((c->rex_prefix & 0x8) != 0x0)
2076 usermode = X86EMUL_MODE_PROT64;
2077 else
2078 usermode = X86EMUL_MODE_PROT32;
2079
2080 cs.dpl = 3;
2081 ss.dpl = 3;
3fb1b5db 2082 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2083 switch (usermode) {
2084 case X86EMUL_MODE_PROT32:
79168fd1 2085 cs_sel = (u16)(msr_data + 16);
4668f050 2086 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2087 emulate_gp(ctxt, 0);
e54cfa97 2088 return X86EMUL_PROPAGATE_FAULT;
4668f050 2089 }
79168fd1 2090 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2091 break;
2092 case X86EMUL_MODE_PROT64:
79168fd1 2093 cs_sel = (u16)(msr_data + 32);
4668f050 2094 if (msr_data == 0x0) {
54b8486f 2095 emulate_gp(ctxt, 0);
e54cfa97 2096 return X86EMUL_PROPAGATE_FAULT;
4668f050 2097 }
79168fd1
GN		 2098 ss_sel = cs_sel + 8;
2099 cs.d = 0;
4668f050
AP		 2100 cs.l = 1;
2101 break;
2102 }
79168fd1
GN		 2103 cs_sel |= SELECTOR_RPL_MASK;
2104 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2105
79168fd1
GN		 2106 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2107 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2108 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2109 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2110
bdb475a3
GN		 2111 c->eip = c->regs[VCPU_REGS_RDX];
2112 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2113
e54cfa97 2114 return X86EMUL_CONTINUE;
4668f050
AP		 2115}
2116
9c537244
GN		 2117static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2118 struct x86_emulate_ops *ops)
f850e2e6
GN		 2119{
2120 int iopl;
2121 if (ctxt->mode == X86EMUL_MODE_REAL)
2122 return false;
2123 if (ctxt->mode == X86EMUL_MODE_VM86)
2124 return true;
2125 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2126 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2127}
2128
2129static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2130 struct x86_emulate_ops *ops,
2131 u16 port, u16 len)
2132{
79168fd1 2133 struct desc_struct tr_seg;
f850e2e6
GN		 2134 int r;
2135 u16 io_bitmap_ptr;
2136 u8 perm, bit_idx = port & 0x7;
2137 unsigned mask = (1 << len) - 1;
2138
79168fd1
GN		 2139 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2140 if (!tr_seg.p)
f850e2e6 2141 return false;
79168fd1 2142 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2143 return false;
79168fd1
GN		 2144 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2145 ctxt->vcpu, NULL);
f850e2e6
GN		 2146 if (r != X86EMUL_CONTINUE)
2147 return false;
79168fd1 2148 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2149 return false;
79168fd1
GN		 2150 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2151 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2152 if (r != X86EMUL_CONTINUE)
2153 return false;
2154 if ((perm >> bit_idx) & mask)
2155 return false;
2156 return true;
2157}
2158
2159static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2160 struct x86_emulate_ops *ops,
2161 u16 port, u16 len)
2162{
9c537244 2163 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2164 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2165 return false;
2166 return true;
2167}
2168
38ba30ba
GN		 2169static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2170 struct x86_emulate_ops *ops,
2171 struct tss_segment_16 *tss)
2172{
2173 struct decode_cache *c = &ctxt->decode;
2174
2175 tss->ip = c->eip;
2176 tss->flag = ctxt->eflags;
2177 tss->ax = c->regs[VCPU_REGS_RAX];
2178 tss->cx = c->regs[VCPU_REGS_RCX];
2179 tss->dx = c->regs[VCPU_REGS_RDX];
2180 tss->bx = c->regs[VCPU_REGS_RBX];
2181 tss->sp = c->regs[VCPU_REGS_RSP];
2182 tss->bp = c->regs[VCPU_REGS_RBP];
2183 tss->si = c->regs[VCPU_REGS_RSI];
2184 tss->di = c->regs[VCPU_REGS_RDI];
2185
2186 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2187 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2188 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2189 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2190 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2191}
2192
2193static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2194 struct x86_emulate_ops *ops,
2195 struct tss_segment_16 *tss)
2196{
2197 struct decode_cache *c = &ctxt->decode;
2198 int ret;
2199
2200 c->eip = tss->ip;
2201 ctxt->eflags = tss->flag | 2;
2202 c->regs[VCPU_REGS_RAX] = tss->ax;
2203 c->regs[VCPU_REGS_RCX] = tss->cx;
2204 c->regs[VCPU_REGS_RDX] = tss->dx;
2205 c->regs[VCPU_REGS_RBX] = tss->bx;
2206 c->regs[VCPU_REGS_RSP] = tss->sp;
2207 c->regs[VCPU_REGS_RBP] = tss->bp;
2208 c->regs[VCPU_REGS_RSI] = tss->si;
2209 c->regs[VCPU_REGS_RDI] = tss->di;
2210
2211 /*
2212 * SDM says that segment selectors are loaded before segment
2213 * descriptors
2214 */
2215 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2216 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2217 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2218 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2219 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2220
2221 /*
2222 * Now load segment descriptors. If fault happenes at this stage
2223 * it is handled in a context of new task
2224 */
2225 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2226 if (ret != X86EMUL_CONTINUE)
2227 return ret;
2228 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2229 if (ret != X86EMUL_CONTINUE)
2230 return ret;
2231 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2232 if (ret != X86EMUL_CONTINUE)
2233 return ret;
2234 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2235 if (ret != X86EMUL_CONTINUE)
2236 return ret;
2237 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2238 if (ret != X86EMUL_CONTINUE)
2239 return ret;
2240
2241 return X86EMUL_CONTINUE;
2242}
2243
2244static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2245 struct x86_emulate_ops *ops,
2246 u16 tss_selector, u16 old_tss_sel,
2247 ulong old_tss_base, struct desc_struct *new_desc)
2248{
2249 struct tss_segment_16 tss_seg;
2250 int ret;
2251 u32 err, new_tss_base = get_desc_base(new_desc);
2252
2253 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2254 &err);
2255 if (ret == X86EMUL_PROPAGATE_FAULT) {
2256 /* FIXME: need to provide precise fault address */
54b8486f 2257 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2258 return ret;
2259 }
2260
2261 save_state_to_tss16(ctxt, ops, &tss_seg);
2262
2263 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2264 &err);
2265 if (ret == X86EMUL_PROPAGATE_FAULT) {
2266 /* FIXME: need to provide precise fault address */
54b8486f 2267 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2268 return ret;
2269 }
2270
2271 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2272 &err);
2273 if (ret == X86EMUL_PROPAGATE_FAULT) {
2274 /* FIXME: need to provide precise fault address */
54b8486f 2275 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2276 return ret;
2277 }
2278
2279 if (old_tss_sel != 0xffff) {
2280 tss_seg.prev_task_link = old_tss_sel;
2281
2282 ret = ops->write_std(new_tss_base,
2283 &tss_seg.prev_task_link,
2284 sizeof tss_seg.prev_task_link,
2285 ctxt->vcpu, &err);
2286 if (ret == X86EMUL_PROPAGATE_FAULT) {
2287 /* FIXME: need to provide precise fault address */
54b8486f 2288 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2289 return ret;
2290 }
2291 }
2292
2293 return load_state_from_tss16(ctxt, ops, &tss_seg);
2294}
2295
2296static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2297 struct x86_emulate_ops *ops,
2298 struct tss_segment_32 *tss)
2299{
2300 struct decode_cache *c = &ctxt->decode;
2301
2302 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2303 tss->eip = c->eip;
2304 tss->eflags = ctxt->eflags;
2305 tss->eax = c->regs[VCPU_REGS_RAX];
2306 tss->ecx = c->regs[VCPU_REGS_RCX];
2307 tss->edx = c->regs[VCPU_REGS_RDX];
2308 tss->ebx = c->regs[VCPU_REGS_RBX];
2309 tss->esp = c->regs[VCPU_REGS_RSP];
2310 tss->ebp = c->regs[VCPU_REGS_RBP];
2311 tss->esi = c->regs[VCPU_REGS_RSI];
2312 tss->edi = c->regs[VCPU_REGS_RDI];
2313
2314 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2315 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2316 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2317 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2318 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2319 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2320 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2321}
2322
2323static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2324 struct x86_emulate_ops *ops,
2325 struct tss_segment_32 *tss)
2326{
2327 struct decode_cache *c = &ctxt->decode;
2328 int ret;
2329
0f12244f 2330 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2331 emulate_gp(ctxt, 0);
0f12244f
GN		 2332 return X86EMUL_PROPAGATE_FAULT;
2333 }
38ba30ba
GN		 2334 c->eip = tss->eip;
2335 ctxt->eflags = tss->eflags | 2;
2336 c->regs[VCPU_REGS_RAX] = tss->eax;
2337 c->regs[VCPU_REGS_RCX] = tss->ecx;
2338 c->regs[VCPU_REGS_RDX] = tss->edx;
2339 c->regs[VCPU_REGS_RBX] = tss->ebx;
2340 c->regs[VCPU_REGS_RSP] = tss->esp;
2341 c->regs[VCPU_REGS_RBP] = tss->ebp;
2342 c->regs[VCPU_REGS_RSI] = tss->esi;
2343 c->regs[VCPU_REGS_RDI] = tss->edi;
2344
2345 /*
2346 * SDM says that segment selectors are loaded before segment
2347 * descriptors
2348 */
2349 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2350 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2351 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2352 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2353 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2354 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2355 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2356
2357 /*
2358 * Now load segment descriptors. If fault happenes at this stage
2359 * it is handled in a context of new task
2360 */
2361 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2362 if (ret != X86EMUL_CONTINUE)
2363 return ret;
2364 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2365 if (ret != X86EMUL_CONTINUE)
2366 return ret;
2367 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2368 if (ret != X86EMUL_CONTINUE)
2369 return ret;
2370 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2371 if (ret != X86EMUL_CONTINUE)
2372 return ret;
2373 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2374 if (ret != X86EMUL_CONTINUE)
2375 return ret;
2376 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2377 if (ret != X86EMUL_CONTINUE)
2378 return ret;
2379 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2380 if (ret != X86EMUL_CONTINUE)
2381 return ret;
2382
2383 return X86EMUL_CONTINUE;
2384}
2385
2386static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2387 struct x86_emulate_ops *ops,
2388 u16 tss_selector, u16 old_tss_sel,
2389 ulong old_tss_base, struct desc_struct *new_desc)
2390{
2391 struct tss_segment_32 tss_seg;
2392 int ret;
2393 u32 err, new_tss_base = get_desc_base(new_desc);
2394
2395 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2396 &err);
2397 if (ret == X86EMUL_PROPAGATE_FAULT) {
2398 /* FIXME: need to provide precise fault address */
54b8486f 2399 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2400 return ret;
2401 }
2402
2403 save_state_to_tss32(ctxt, ops, &tss_seg);
2404
2405 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2406 &err);
2407 if (ret == X86EMUL_PROPAGATE_FAULT) {
2408 /* FIXME: need to provide precise fault address */
54b8486f 2409 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2410 return ret;
2411 }
2412
2413 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2414 &err);
2415 if (ret == X86EMUL_PROPAGATE_FAULT) {
2416 /* FIXME: need to provide precise fault address */
54b8486f 2417 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2418 return ret;
2419 }
2420
2421 if (old_tss_sel != 0xffff) {
2422 tss_seg.prev_task_link = old_tss_sel;
2423
2424 ret = ops->write_std(new_tss_base,
2425 &tss_seg.prev_task_link,
2426 sizeof tss_seg.prev_task_link,
2427 ctxt->vcpu, &err);
2428 if (ret == X86EMUL_PROPAGATE_FAULT) {
2429 /* FIXME: need to provide precise fault address */
54b8486f 2430 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2431 return ret;
2432 }
2433 }
2434
2435 return load_state_from_tss32(ctxt, ops, &tss_seg);
2436}
2437
2438static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2439 struct x86_emulate_ops *ops,
2440 u16 tss_selector, int reason,
2441 bool has_error_code, u32 error_code)
38ba30ba
GN		 2442{
2443 struct desc_struct curr_tss_desc, next_tss_desc;
2444 int ret;
2445 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2446 ulong old_tss_base =
5951c442 2447 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2448 u32 desc_limit;
38ba30ba
GN		 2449
2450 /* FIXME: old_tss_base == ~0 ? */
2451
2452 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
2455 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2456 if (ret != X86EMUL_CONTINUE)
2457 return ret;
2458
2459 /* FIXME: check that next_tss_desc is tss */
2460
2461 if (reason != TASK_SWITCH_IRET) {
2462 if ((tss_selector & 3) > next_tss_desc.dpl ||
2463 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2464 emulate_gp(ctxt, 0);
38ba30ba
GN		 2465 return X86EMUL_PROPAGATE_FAULT;
2466 }
2467 }
2468
ceffb459
GN		 2469 desc_limit = desc_limit_scaled(&next_tss_desc);
2470 if (!next_tss_desc.p ||
2471 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2472 desc_limit < 0x2b)) {
54b8486f 2473 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2474 return X86EMUL_PROPAGATE_FAULT;
2475 }
2476
2477 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2478 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2479 write_segment_descriptor(ctxt, ops, old_tss_sel,
2480 &curr_tss_desc);
2481 }
2482
2483 if (reason == TASK_SWITCH_IRET)
2484 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2485
2486 /* set back link to prev task only if NT bit is set in eflags
2487 note that old_tss_sel is not used afetr this point */
2488 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2489 old_tss_sel = 0xffff;
2490
2491 if (next_tss_desc.type & 8)
2492 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2493 old_tss_base, &next_tss_desc);
2494 else
2495 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2496 old_tss_base, &next_tss_desc);
0760d448
JK		 2497 if (ret != X86EMUL_CONTINUE)
2498 return ret;
38ba30ba
GN		 2499
2500 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2501 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2502
2503 if (reason != TASK_SWITCH_IRET) {
2504 next_tss_desc.type |= (1 << 1); /* set busy flag */
2505 write_segment_descriptor(ctxt, ops, tss_selector,
2506 &next_tss_desc);
2507 }
2508
2509 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2510 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2511 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2512
e269fb21
JK		 2513 if (has_error_code) {
2514 struct decode_cache *c = &ctxt->decode;
2515
2516 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2517 c->lock_prefix = 0;
2518 c->src.val = (unsigned long) error_code;
79168fd1 2519 emulate_push(ctxt, ops);
e269fb21
JK		 2520 }
2521
38ba30ba
GN		 2522 return ret;
2523}
2524
2525int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2526 struct x86_emulate_ops *ops,
e269fb21
JK		 2527 u16 tss_selector, int reason,
2528 bool has_error_code, u32 error_code)
38ba30ba
GN		 2529{
2530 struct decode_cache *c = &ctxt->decode;
2531 int rc;
2532
38ba30ba 2533 c->eip = ctxt->eip;
e269fb21 2534 c->dst.type = OP_NONE;
38ba30ba 2535
e269fb21
JK		 2536 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2537 has_error_code, error_code);
38ba30ba
GN		 2538
2539 if (rc == X86EMUL_CONTINUE) {
e269fb21 2540 rc = writeback(ctxt, ops);
95c55886
GN		 2541 if (rc == X86EMUL_CONTINUE)
2542 ctxt->eip = c->eip;
38ba30ba
GN		 2543 }
2544
19d04437 2545 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2546}
2547
a682e354 2548static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2549 int reg, struct operand *op)
a682e354
GN		 2550{
2551 struct decode_cache *c = &ctxt->decode;
2552 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2553
d9271123
GN		 2554 register_address_increment(c, &c->regs[reg], df * op->bytes);
2555 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2556}
2557
8b4caf66 2558int
1be3aa47 2559x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2560{
8b4caf66 2561 u64 msr_data;
8b4caf66 2562 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2563 int rc = X86EMUL_CONTINUE;
5cd21917 2564 int saved_dst_type = c->dst.type;
8b4caf66 2565
9de41573 2566 ctxt->decode.mem_read.pos = 0;
310b5d30 2567
1161624f 2568 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2569 emulate_ud(ctxt);
1161624f
GN		 2570 goto done;
2571 }
2572
d380a5e4 2573 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2574 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2575 emulate_ud(ctxt);
d380a5e4
GN		 2576 goto done;
2577 }
2578
e92805ac 2579 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2580 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2581 emulate_gp(ctxt, 0);
e92805ac
GN		 2582 goto done;
2583 }
2584
b9fa9d6b 2585 if (c->rep_prefix && (c->d & String)) {
5cd21917 2586 ctxt->restart = true;
b9fa9d6b 2587 /* All REP prefixes have the same first termination condition */
c73e197b 2588 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2589 string_done:
2590 ctxt->restart = false;
95c55886 2591 ctxt->eip = c->eip;
b9fa9d6b
AK		 2592 goto done;
2593 }
2594 /* The second termination condition only applies for REPE
2595 * and REPNE. Test if the repeat string operation prefix is
2596 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2597 * corresponding termination condition according to:
2598 * - if REPE/REPZ and ZF = 0 then done
2599 * - if REPNE/REPNZ and ZF = 1 then done
2600 */
2601 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2602 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2603 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2604 ((ctxt->eflags & EFLG_ZF) == 0))
2605 goto string_done;
b9fa9d6b 2606 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2607 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2608 goto string_done;
b9fa9d6b 2609 }
063db061 2610 c->eip = ctxt->eip;
b9fa9d6b
AK		 2611 }
2612
8b4caf66 2613 if (c->src.type == OP_MEM) {
9de41573 2614 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2615 c->src.valptr, c->src.bytes);
b60d513c 2616 if (rc != X86EMUL_CONTINUE)
8b4caf66 2617 goto done;
16518d5a 2618 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2619 }
2620
e35b7b9c 2621 if (c->src2.type == OP_MEM) {
9de41573
GN		 2622 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2623 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2624 if (rc != X86EMUL_CONTINUE)
2625 goto done;
2626 }
2627
8b4caf66
LV		 2628 if ((c->d & DstMask) == ImplicitOps)
2629 goto special_insn;
2630
2631
69f55cb1
GN		 2632 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2633 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2634 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2635 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2636 if (rc != X86EMUL_CONTINUE)
2637 goto done;
038e51de 2638 }
e4e03ded 2639 c->dst.orig_val = c->dst.val;
038e51de 2640
018a98db
AK		 2641special_insn:
2642
e4e03ded 2643 if (c->twobyte)
6aa8b732
AK		 2644 goto twobyte_insn;
2645
e4e03ded 2646 switch (c->b) {
6aa8b732
AK		 2647 case 0x00 ... 0x05:
2648 add: /* add */
05f086f8 2649 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2650 break;
0934ac9d 2651 case 0x06: /* push es */
79168fd1 2652 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2653 break;
2654 case 0x07: /* pop es */
0934ac9d 2655 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2656 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2657 goto done;
2658 break;
6aa8b732
AK		 2659 case 0x08 ... 0x0d:
2660 or: /* or */
05f086f8 2661 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2662 break;
0934ac9d 2663 case 0x0e: /* push cs */
79168fd1 2664 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2665 break;
6aa8b732
AK		 2666 case 0x10 ... 0x15:
2667 adc: /* adc */
05f086f8 2668 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2669 break;
0934ac9d 2670 case 0x16: /* push ss */
79168fd1 2671 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2672 break;
2673 case 0x17: /* pop ss */
0934ac9d 2674 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2675 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2676 goto done;
2677 break;
6aa8b732
AK		 2678 case 0x18 ... 0x1d:
2679 sbb: /* sbb */
05f086f8 2680 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2681 break;
0934ac9d 2682 case 0x1e: /* push ds */
79168fd1 2683 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2684 break;
2685 case 0x1f: /* pop ds */
0934ac9d 2686 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2687 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2688 goto done;
2689 break;
aa3a816b 2690 case 0x20 ... 0x25:
6aa8b732 2691 and: /* and */
05f086f8 2692 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2693 break;
2694 case 0x28 ... 0x2d:
2695 sub: /* sub */
05f086f8 2696 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2697 break;
2698 case 0x30 ... 0x35:
2699 xor: /* xor */
05f086f8 2700 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2701 break;
2702 case 0x38 ... 0x3d:
2703 cmp: /* cmp */
05f086f8 2704 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2705 break;
33615aa9
AK		 2706 case 0x40 ... 0x47: /* inc r16/r32 */
2707 emulate_1op("inc", c->dst, ctxt->eflags);
2708 break;
2709 case 0x48 ... 0x4f: /* dec r16/r32 */
2710 emulate_1op("dec", c->dst, ctxt->eflags);
2711 break;
2712 case 0x50 ... 0x57: /* push reg */
79168fd1 2713 emulate_push(ctxt, ops);
33615aa9
AK		 2714 break;
2715 case 0x58 ... 0x5f: /* pop reg */
2716 pop_instruction:
350f69dc 2717 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2718 if (rc != X86EMUL_CONTINUE)
33615aa9 2719 goto done;
33615aa9 2720 break;
abcf14b5 2721 case 0x60: /* pusha */
c37eda13
WY		 2722 rc = emulate_pusha(ctxt, ops);
2723 if (rc != X86EMUL_CONTINUE)
2724 goto done;
abcf14b5
MG		 2725 break;
2726 case 0x61: /* popa */
2727 rc = emulate_popa(ctxt, ops);
1b30eaa8 2728 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2729 goto done;
2730 break;
6aa8b732 2731 case 0x63: /* movsxd */
8b4caf66 2732 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2733 goto cannot_emulate;
e4e03ded 2734 c->dst.val = (s32) c->src.val;
6aa8b732 2735 break;
91ed7a0e 2736 case 0x68: /* push imm */
018a98db 2737 case 0x6a: /* push imm8 */
79168fd1 2738 emulate_push(ctxt, ops);
018a98db
AK		 2739 break;
2740 case 0x6c: /* insb */
2741 case 0x6d: /* insw/insd */
7972995b 2742 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2743 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2744 c->dst.bytes)) {
54b8486f 2745 emulate_gp(ctxt, 0);
f850e2e6
GN		 2746 goto done;
2747 }
7b262e90
GN		 2748 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2749 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2750 goto done; /* IO is needed, skip writeback */
2751 break;
018a98db
AK		 2752 case 0x6e: /* outsb */
2753 case 0x6f: /* outsw/outsd */
7972995b 2754 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2755 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2756 c->src.bytes)) {
54b8486f 2757 emulate_gp(ctxt, 0);
f850e2e6
GN		 2758 goto done;
2759 }
7972995b
GN		 2760 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2761 &c->src.val, 1, ctxt->vcpu);
2762
2763 c->dst.type = OP_NONE; /* nothing to writeback */
2764 break;
b2833e3c 2765 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2766 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2767 jmp_rel(c, c->src.val);
018a98db 2768 break;
6aa8b732 2769 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2770 switch (c->modrm_reg) {
6aa8b732
AK		 2771 case 0:
2772 goto add;
2773 case 1:
2774 goto or;
2775 case 2:
2776 goto adc;
2777 case 3:
2778 goto sbb;
2779 case 4:
2780 goto and;
2781 case 5:
2782 goto sub;
2783 case 6:
2784 goto xor;
2785 case 7:
2786 goto cmp;
2787 }
2788 break;
2789 case 0x84 ... 0x85:
dfb507c4 2790 test:
05f086f8 2791 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2792 break;
2793 case 0x86 ... 0x87: /* xchg */
b13354f8 2794 xchg:
6aa8b732 2795 /* Write back the register source. */
e4e03ded 2796 switch (c->dst.bytes) {
6aa8b732 2797 case 1:
e4e03ded 2798 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2799 break;
2800 case 2:
e4e03ded 2801 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2802 break;
2803 case 4:
e4e03ded 2804 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2805 break; /* 64b reg: zero-extend */
2806 case 8:
e4e03ded 2807 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2808 break;
2809 }
2810 /*
2811 * Write back the memory destination with implicit LOCK
2812 * prefix.
2813 */
e4e03ded
LV		 2814 c->dst.val = c->src.val;
2815 c->lock_prefix = 1;
6aa8b732 2816 break;
6aa8b732 2817 case 0x88 ... 0x8b: /* mov */
7de75248 2818 goto mov;
79168fd1
GN		 2819 case 0x8c: /* mov r/m, sreg */
2820 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2821 emulate_ud(ctxt);
5e3ae6c5 2822 goto done;
38d5bc6d 2823 }
79168fd1 2824 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2825 break;
7e0b54b1 2826 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2827 c->dst.val = c->modrm_ea;
7e0b54b1 2828 break;
4257198a
GT		 2829 case 0x8e: { /* mov seg, r/m16 */
2830 uint16_t sel;
4257198a
GT		 2831
2832 sel = c->src.val;
8b9f4414 2833
c697518a
GN		 2834 if (c->modrm_reg == VCPU_SREG_CS ||
2835 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2836 emulate_ud(ctxt);
8b9f4414
GN		 2837 goto done;
2838 }
2839
310b5d30 2840 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2841 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2842
2e873022 2843 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2844
2845 c->dst.type = OP_NONE; /* Disable writeback. */
2846 break;
2847 }
6aa8b732 2848 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2849 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2850 if (rc != X86EMUL_CONTINUE)
6aa8b732 2851 goto done;
6aa8b732 2852 break;
b13354f8 2853 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2854 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2855 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2856 break;
2857 }
2858 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2859 c->src.type = OP_REG;
2860 c->src.bytes = c->op_bytes;
b13354f8
MG		 2861 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2862 c->src.val = *(c->src.ptr);
2863 goto xchg;
fd2a7608 2864 case 0x9c: /* pushf */
05f086f8 2865 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2866 emulate_push(ctxt, ops);
8cdbd2c9 2867 break;
535eabcf 2868 case 0x9d: /* popf */
2b48cc75 2869 c->dst.type = OP_REG;
05f086f8 2870 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2871 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2872 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2873 if (rc != X86EMUL_CONTINUE)
2874 goto done;
2875 break;
5d55f299 2876 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2877 case 0xa4 ... 0xa5: /* movs */
a682e354 2878 goto mov;
6aa8b732 2879 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2880 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2881 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2882 goto cmp;
dfb507c4
MG		 2883 case 0xa8 ... 0xa9: /* test ax, imm */
2884 goto test;
6aa8b732 2885 case 0xaa ... 0xab: /* stos */
e4e03ded 2886 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2887 break;
2888 case 0xac ... 0xad: /* lods */
a682e354 2889 goto mov;
6aa8b732
AK		 2890 case 0xae ... 0xaf: /* scas */
2891 DPRINTF("Urk! I don't handle SCAS.\n");
2892 goto cannot_emulate;
a5e2e82b 2893 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2894 goto mov;
018a98db
AK		 2895 case 0xc0 ... 0xc1:
2896 emulate_grp2(ctxt);
2897 break;
111de5d6 2898 case 0xc3: /* ret */
cf5de4f8 2899 c->dst.type = OP_REG;
111de5d6 2900 c->dst.ptr = &c->eip;
cf5de4f8 2901 c->dst.bytes = c->op_bytes;
111de5d6 2902 goto pop_instruction;
018a98db
AK		 2903 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2904 mov:
2905 c->dst.val = c->src.val;
2906 break;
a77ab5ea
AK		 2907 case 0xcb: /* ret far */
2908 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2909 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2910 goto done;
2911 break;
018a98db
AK		 2912 case 0xd0 ... 0xd1: /* Grp2 */
2913 c->src.val = 1;
2914 emulate_grp2(ctxt);
2915 break;
2916 case 0xd2 ... 0xd3: /* Grp2 */
2917 c->src.val = c->regs[VCPU_REGS_RCX];
2918 emulate_grp2(ctxt);
2919 break;
a6a3034c
MG		 2920 case 0xe4: /* inb */
2921 case 0xe5: /* in */
cf8f70bf 2922 goto do_io_in;
a6a3034c
MG		 2923 case 0xe6: /* outb */
2924 case 0xe7: /* out */
cf8f70bf 2925 goto do_io_out;
1a52e051 2926 case 0xe8: /* call (near) */ {
d53c4777 2927 long int rel = c->src.val;
e4e03ded 2928 c->src.val = (unsigned long) c->eip;
7a957275 2929 jmp_rel(c, rel);
79168fd1 2930 emulate_push(ctxt, ops);
8cdbd2c9 2931 break;
1a52e051
NK		 2932 }
2933 case 0xe9: /* jmp rel */
954cd36f 2934 goto jmp;
414e6277
GN		 2935 case 0xea: { /* jmp far */
2936 unsigned short sel;
ea79849d 2937 jump_far:
414e6277
GN		 2938 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2939
2940 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2941 goto done;
954cd36f 2942
414e6277
GN		 2943 c->eip = 0;
2944 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2945 break;
414e6277 2946 }
954cd36f
GT		 2947 case 0xeb:
2948 jmp: /* jmp rel short */
7a957275 2949 jmp_rel(c, c->src.val);
a01af5ec 2950 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2951 break;
a6a3034c
MG		 2952 case 0xec: /* in al,dx */
2953 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2954 c->src.val = c->regs[VCPU_REGS_RDX];
2955 do_io_in:
2956 c->dst.bytes = min(c->dst.bytes, 4u);
2957 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2958 emulate_gp(ctxt, 0);
cf8f70bf
GN		 2959 goto done;
2960 }
7b262e90
GN		 2961 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2962 &c->dst.val))
cf8f70bf
GN		 2963 goto done; /* IO is needed */
2964 break;
ce7a0ad3
WY		 2965 case 0xee: /* out dx,al */
2966 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 2967 c->src.val = c->regs[VCPU_REGS_RDX];
2968 do_io_out:
2969 c->dst.bytes = min(c->dst.bytes, 4u);
2970 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2971 emulate_gp(ctxt, 0);
f850e2e6
GN		 2972 goto done;
2973 }
cf8f70bf
GN		 2974 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2975 ctxt->vcpu);
2976 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2977 break;
111de5d6 2978 case 0xf4: /* hlt */
ad312c7c 2979 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2980 break;
111de5d6
AK		 2981 case 0xf5: /* cmc */
2982 /* complement carry flag from eflags reg */
2983 ctxt->eflags ^= EFLG_CF;
2984 c->dst.type = OP_NONE; /* Disable writeback. */
2985 break;
018a98db 2986 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2987 if (!emulate_grp3(ctxt, ops))
2988 goto cannot_emulate;
018a98db 2989 break;
111de5d6
AK		 2990 case 0xf8: /* clc */
2991 ctxt->eflags &= ~EFLG_CF;
2992 c->dst.type = OP_NONE; /* Disable writeback. */
2993 break;
2994 case 0xfa: /* cli */
07cbc6c1 2995 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 2996 emulate_gp(ctxt, 0);
07cbc6c1
WY		 2997 goto done;
2998 } else {
f850e2e6
GN		 2999 ctxt->eflags &= ~X86_EFLAGS_IF;
3000 c->dst.type = OP_NONE; /* Disable writeback. */
3001 }
111de5d6
AK		 3002 break;
3003 case 0xfb: /* sti */
07cbc6c1 3004 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3005 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3006 goto done;
3007 } else {
95cb2295 3008 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3009 ctxt->eflags |= X86_EFLAGS_IF;
3010 c->dst.type = OP_NONE; /* Disable writeback. */
3011 }
111de5d6 3012 break;
fb4616f4
MG		 3013 case 0xfc: /* cld */
3014 ctxt->eflags &= ~EFLG_DF;
3015 c->dst.type = OP_NONE; /* Disable writeback. */
3016 break;
3017 case 0xfd: /* std */
3018 ctxt->eflags |= EFLG_DF;
3019 c->dst.type = OP_NONE; /* Disable writeback. */
3020 break;
ea79849d
GN		 3021 case 0xfe: /* Grp4 */
3022 grp45:
018a98db 3023 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3024 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3025 goto done;
3026 break;
ea79849d
GN		 3027 case 0xff: /* Grp5 */
3028 if (c->modrm_reg == 5)
3029 goto jump_far;
3030 goto grp45;
6aa8b732 3031 }
018a98db
AK		 3032
3033writeback:
3034 rc = writeback(ctxt, ops);
1b30eaa8 3035 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3036 goto done;
3037
5cd21917
GN		 3038 /*
3039 * restore dst type in case the decoding will be reused
3040 * (happens for string instruction )
3041 */
3042 c->dst.type = saved_dst_type;
3043
a682e354 3044 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3045 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3046 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3047
3048 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3049 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3050 &c->dst);
d9271123 3051
5cd21917 3052 if (c->rep_prefix && (c->d & String)) {
7b262e90 3053 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3054 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3055 /*
3056 * Re-enter guest when pio read ahead buffer is empty or,
3057 * if it is not used, after each 1024 iteration.
3058 */
3059 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3060 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3061 ctxt->restart = false;
3062 }
9de41573
GN		 3063 /*
3064 * reset read cache here in case string instruction is restared
3065 * without decoding
3066 */
3067 ctxt->decode.mem_read.end = 0;
95c55886 3068 ctxt->eip = c->eip;
018a98db
AK		 3069
3070done:
cb404fe0 3071 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3072
3073twobyte_insn:
e4e03ded 3074 switch (c->b) {
6aa8b732 3075 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3076 switch (c->modrm_reg) {
6aa8b732
AK		 3077 u16 size;
3078 unsigned long address;
3079
aca7f966 3080 case 0: /* vmcall */
e4e03ded 3081 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3082 goto cannot_emulate;
3083
7aa81cc0 3084 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3085 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3086 goto done;
3087
33e3885d 3088 /* Let the processor re-execute the fixed hypercall */
063db061 3089 c->eip = ctxt->eip;
16286d08
AK		 3090 /* Disable writeback. */
3091 c->dst.type = OP_NONE;
aca7f966 3092 break;
6aa8b732 3093 case 2: /* lgdt */
e4e03ded
LV		 3094 rc = read_descriptor(ctxt, ops, c->src.ptr,
3095 &size, &address, c->op_bytes);
1b30eaa8 3096 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3097 goto done;
3098 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3099 /* Disable writeback. */
3100 c->dst.type = OP_NONE;
6aa8b732 3101 break;
aca7f966 3102 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3103 if (c->modrm_mod == 3) {
3104 switch (c->modrm_rm) {
3105 case 1:
3106 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3107 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3108 goto done;
3109 break;
3110 default:
3111 goto cannot_emulate;
3112 }
aca7f966 3113 } else {
e4e03ded 3114 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3115 &size, &address,
e4e03ded 3116 c->op_bytes);
1b30eaa8 3117 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3118 goto done;
3119 realmode_lidt(ctxt->vcpu, size, address);
3120 }
16286d08
AK		 3121 /* Disable writeback. */
3122 c->dst.type = OP_NONE;
6aa8b732
AK		 3123 break;
3124 case 4: /* smsw */
16286d08 3125 c->dst.bytes = 2;
52a46617 3126 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3127 break;
3128 case 6: /* lmsw */
93a152be
GN		 3129 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3130 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3131 c->dst.type = OP_NONE;
6aa8b732 3132 break;
6e1e5ffe 3133 case 5: /* not defined */
54b8486f 3134 emulate_ud(ctxt);
6e1e5ffe 3135 goto done;
6aa8b732 3136 case 7: /* invlpg*/
69f55cb1 3137 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3138 /* Disable writeback. */
3139 c->dst.type = OP_NONE;
6aa8b732
AK		 3140 break;
3141 default:
3142 goto cannot_emulate;
3143 }
3144 break;
e99f0507 3145 case 0x05: /* syscall */
3fb1b5db 3146 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3147 if (rc != X86EMUL_CONTINUE)
3148 goto done;
e66bb2cc
AP		 3149 else
3150 goto writeback;
e99f0507 3151 break;
018a98db
AK		 3152 case 0x06:
3153 emulate_clts(ctxt->vcpu);
3154 c->dst.type = OP_NONE;
3155 break;
018a98db 3156 case 0x09: /* wbinvd */
f5f48ee1
SY		 3157 kvm_emulate_wbinvd(ctxt->vcpu);
3158 c->dst.type = OP_NONE;
3159 break;
3160 case 0x08: /* invd */
018a98db
AK		 3161 case 0x0d: /* GrpP (prefetch) */
3162 case 0x18: /* Grp16 (prefetch/nop) */
3163 c->dst.type = OP_NONE;
3164 break;
3165 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3166 switch (c->modrm_reg) {
3167 case 1:
3168 case 5 ... 7:
3169 case 9 ... 15:
54b8486f 3170 emulate_ud(ctxt);
6aebfa6e
GN		 3171 goto done;
3172 }
52a46617 3173 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3174 c->dst.type = OP_NONE; /* no writeback */
3175 break;
6aa8b732 3176 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3177 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3178 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3179 emulate_ud(ctxt);
1e470be5
GN		 3180 goto done;
3181 }
35aa5375 3182 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3183 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3184 break;
018a98db 3185 case 0x22: /* mov reg, cr */
0f12244f 3186 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3187 emulate_gp(ctxt, 0);
0f12244f
GN		 3188 goto done;
3189 }
018a98db
AK		 3190 c->dst.type = OP_NONE;
3191 break;
6aa8b732 3192 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3193 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3194 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3195 emulate_ud(ctxt);
1e470be5
GN		 3196 goto done;
3197 }
35aa5375 3198
338dbc97
GN		 3199 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3200 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3201 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3202 /* #UD condition is already handled by the code above */
54b8486f 3203 emulate_gp(ctxt, 0);
338dbc97
GN		 3204 goto done;
3205 }
3206
a01af5ec 3207 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3208 break;
018a98db
AK		 3209 case 0x30:
3210 /* wrmsr */
3211 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3212 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3213 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3214 emulate_gp(ctxt, 0);
fd525365 3215 goto done;
018a98db
AK		 3216 }
3217 rc = X86EMUL_CONTINUE;
3218 c->dst.type = OP_NONE;
3219 break;
3220 case 0x32:
3221 /* rdmsr */
3fb1b5db 3222 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3223 emulate_gp(ctxt, 0);
fd525365 3224 goto done;
018a98db
AK		 3225 } else {
3226 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3227 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3228 }
3229 rc = X86EMUL_CONTINUE;
3230 c->dst.type = OP_NONE;
3231 break;
e99f0507 3232 case 0x34: /* sysenter */
3fb1b5db 3233 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3234 if (rc != X86EMUL_CONTINUE)
3235 goto done;
8c604352
AP		 3236 else
3237 goto writeback;
e99f0507
AP		 3238 break;
3239 case 0x35: /* sysexit */
3fb1b5db 3240 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3241 if (rc != X86EMUL_CONTINUE)
3242 goto done;
4668f050
AP		 3243 else
3244 goto writeback;
e99f0507 3245 break;
6aa8b732 3246 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3247 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3248 if (!test_cc(c->b, ctxt->eflags))
3249 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3250 break;
b2833e3c 3251 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3252 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3253 jmp_rel(c, c->src.val);
018a98db
AK		 3254 c->dst.type = OP_NONE;
3255 break;
0934ac9d 3256 case 0xa0: /* push fs */
79168fd1 3257 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3258 break;
3259 case 0xa1: /* pop fs */
3260 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3261 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3262 goto done;
3263 break;
7de75248
NK		 3264 case 0xa3:
3265 bt: /* bt */
e4f8e039 3266 c->dst.type = OP_NONE;
e4e03ded
LV		 3267 /* only subword offset */
3268 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3269 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3270 break;
9bf8ea42
GT		 3271 case 0xa4: /* shld imm8, r, r/m */
3272 case 0xa5: /* shld cl, r, r/m */
3273 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3274 break;
0934ac9d 3275 case 0xa8: /* push gs */
79168fd1 3276 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3277 break;
3278 case 0xa9: /* pop gs */
3279 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3280 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3281 goto done;
3282 break;
7de75248
NK		 3283 case 0xab:
3284 bts: /* bts */
e4e03ded
LV		 3285 /* only subword offset */
3286 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3287 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3288 break;
9bf8ea42
GT		 3289 case 0xac: /* shrd imm8, r, r/m */
3290 case 0xad: /* shrd cl, r, r/m */
3291 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3292 break;
2a7c5b8b
GC		 3293 case 0xae: /* clflush */
3294 break;
6aa8b732
AK		 3295 case 0xb0 ... 0xb1: /* cmpxchg */
3296 /*
3297 * Save real source value, then compare EAX against
3298 * destination.
3299 */
e4e03ded
LV		 3300 c->src.orig_val = c->src.val;
3301 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3302 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3303 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3304 /* Success: write back to memory. */
e4e03ded 3305 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3306 } else {
3307 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3308 c->dst.type = OP_REG;
3309 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3310 }
3311 break;
6aa8b732
AK		 3312 case 0xb3:
3313 btr: /* btr */
e4e03ded
LV		 3314 /* only subword offset */
3315 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3316 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3317 break;
6aa8b732 3318 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3319 c->dst.bytes = c->op_bytes;
3320 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3321 : (u16) c->src.val;
6aa8b732 3322 break;
6aa8b732 3323 case 0xba: /* Grp8 */
e4e03ded 3324 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3325 case 0:
3326 goto bt;
3327 case 1:
3328 goto bts;
3329 case 2:
3330 goto btr;
3331 case 3:
3332 goto btc;
3333 }
3334 break;
7de75248
NK		 3335 case 0xbb:
3336 btc: /* btc */
e4e03ded
LV		 3337 /* only subword offset */
3338 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3339 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3340 break;
6aa8b732 3341 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3342 c->dst.bytes = c->op_bytes;
3343 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3344 (s16) c->src.val;
6aa8b732 3345 break;
a012e65a 3346 case 0xc3: /* movnti */
e4e03ded
LV		 3347 c->dst.bytes = c->op_bytes;
3348 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3349 (u64) c->src.val;
a012e65a 3350 break;
6aa8b732 3351 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3352 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3353 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3354 goto done;
3355 break;
6aa8b732
AK		 3356 }
3357 goto writeback;
3358
3359cannot_emulate:
e4e03ded 3360 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3361 return -1;
3362}
Clone of davem's net-next-2.6 tree