[net-next-2.6.git] / arch / x86 / kernel / smp.c

/*
 *	Intel SMP support routines.
 *
 *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
 *	(c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
 *      (c) 2002,2003 Andi Kleen, SuSE Labs.
 *
 *	i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
 *
 *	This code is released under the GNU General Public License version 2 or
 *	later.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/gfp.h>

#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <asm/apic.h>
/*
 *	Some notes on x86 processor bugs affecting SMP operation:
 *
 *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
 *	The Linux implications for SMP are handled as follows:
 *
 *	Pentium III / [Xeon]
 *		None of the E1AP-E3AP errata are visible to the user.
 *
 *	E1AP.	see PII A1AP
 *	E2AP.	see PII A2AP
 *	E3AP.	see PII A3AP
 *
 *	Pentium II / [Xeon]
 *		None of the A1AP-A3AP errata are visible to the user.
 *
 *	A1AP.	see PPro 1AP
 *	A2AP.	see PPro 2AP
 *	A3AP.	see PPro 7AP
 *
 *	Pentium Pro
 *		None of 1AP-9AP errata are visible to the normal user,
 *	except occasional delivery of 'spurious interrupt' as trap #15.
 *	This is very rare and a non-problem.
 *
 *	1AP.	Linux maps APIC as non-cacheable
 *	2AP.	worked around in hardware
 *	3AP.	fixed in C0 and above steppings microcode update.
 *		Linux does not use excessive STARTUP_IPIs.
 *	4AP.	worked around in hardware
 *	5AP.	symmetric IO mode (normal Linux operation) not affected.
 *		'noapic' mode has vector 0xf filled out properly.
 *	6AP.	'noapic' mode might be affected - fixed in later steppings
 *	7AP.	We do not assume writes to the LVT deassering IRQs
 *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
 *	9AP.	We do not use mixed mode
 *
 *	Pentium
 *		There is a marginal case where REP MOVS on 100MHz SMP
 *	machines with B stepping processors can fail. XXX should provide
 *	an L1cache=Writethrough or L1cache=off option.
 *
 *		B stepping CPUs may hang. There are hardware work arounds
 *	for this. We warn about it in case your board doesn't have the work
 *	arounds. Basically that's so I can tell anyone with a B stepping
 *	CPU and SMP problems "tough".
 *
 *	Specific items [From Pentium Processor Specification Update]
 *
 *	1AP.	Linux doesn't use remote read
 *	2AP.	Linux doesn't trust APIC errors
 *	3AP.	We work around this
 *	4AP.	Linux never generated 3 interrupts of the same priority
 *		to cause a lost local interrupt.
 *	5AP.	Remote read is never used
 *	6AP.	not affected - worked around in hardware
 *	7AP.	not affected - worked around in hardware
 *	8AP.	worked around in hardware - we get explicit CS errors if not
 *	9AP.	only 'noapic' mode affected. Might generate spurious
 *		interrupts, we log only the first one and count the
 *		rest silently.
 *	10AP.	not affected - worked around in hardware
 *	11AP.	Linux reads the APIC between writes to avoid this, as per
 *		the documentation. Make sure you preserve this as it affects
 *		the C stepping chips too.
 *	12AP.	not affected - worked around in hardware
 *	13AP.	not affected - worked around in hardware
 *	14AP.	we always deassert INIT during bootup
 *	15AP.	not affected - worked around in hardware
 *	16AP.	not affected - worked around in hardware
 *	17AP.	not affected - worked around in hardware
 *	18AP.	not affected - worked around in hardware
 *	19AP.	not affected - worked around in BIOS
 *
 *	If this sounds worrying believe me these bugs are either ___RARE___,
 *	or are signal timing bugs worked around in hardware and there's
 *	about nothing of note with C stepping upwards.
 */

/*
 * this function sends a 'reschedule' IPI to another CPU.
 * it goes straight through and wastes no time serializing
 * anything. Worst case is that we lose a reschedule ...
 */
static void native_smp_send_reschedule(int cpu)
{
	if (unlikely(cpu_is_offline(cpu))) {
		WARN_ON(1);
		return;
	}
	apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
}

void native_send_call_func_single_ipi(int cpu)
{
	apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
}

void native_send_call_func_ipi(const struct cpumask *mask)
{
	cpumask_var_t allbutself;

	if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
		return;
	}

	cpumask_copy(allbutself, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), allbutself);

	if (cpumask_equal(mask, allbutself) &&
	    cpumask_equal(cpu_online_mask, cpu_callout_mask))
		apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
	else
		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);

	free_cpumask_var(allbutself);
}

/*
 * this function calls the 'stop' function on all other CPUs in the system.
 */

asmlinkage void smp_reboot_interrupt(void)
{
	ack_APIC_irq();
	irq_enter();
	stop_this_cpu(NULL);
	irq_exit();
}

static void native_smp_send_stop(void)
{
	unsigned long flags;
	unsigned long wait;

	if (reboot_force)
		return;

	/*
	 * Use an own vector here because smp_call_function
	 * does lots of things not suitable in a panic situation.
	 * On most systems we could also use an NMI here,
	 * but there are a few systems around where NMI
	 * is problematic so stay with an non NMI for now
	 * (this implies we cannot stop CPUs spinning with irq off
	 * currently)
	 */
	if (num_online_cpus() > 1) {
		apic->send_IPI_allbutself(REBOOT_VECTOR);

		/* Don't wait longer than a second */
		wait = USEC_PER_SEC;
		while (num_online_cpus() > 1 && wait--)
			udelay(1);
	}

	local_irq_save(flags);
	disable_local_APIC();
	local_irq_restore(flags);
}

/*
 * Reschedule call back. Nothing to do,
 * all the work is done automatically when
 * we return from the interrupt.
 */
void smp_reschedule_interrupt(struct pt_regs *regs)
{
	ack_APIC_irq();
	inc_irq_stat(irq_resched_count);
	/*
	 * KVM uses this interrupt to force a cpu out of guest mode
	 */
}

void smp_call_function_interrupt(struct pt_regs *regs)
{
	ack_APIC_irq();
	irq_enter();
	generic_smp_call_function_interrupt();
	inc_irq_stat(irq_call_count);
	irq_exit();
}

void smp_call_function_single_interrupt(struct pt_regs *regs)
{
	ack_APIC_irq();
	irq_enter();
	generic_smp_call_function_single_interrupt();
	inc_irq_stat(irq_call_count);
	irq_exit();
}

struct smp_ops smp_ops = {
	.smp_prepare_boot_cpu	= native_smp_prepare_boot_cpu,
	.smp_prepare_cpus	= native_smp_prepare_cpus,
	.smp_cpus_done		= native_smp_cpus_done,

	.smp_send_stop		= native_smp_send_stop,
	.smp_send_reschedule	= native_smp_send_reschedule,

	.cpu_up			= native_cpu_up,
	.cpu_die		= native_cpu_die,
	.cpu_disable		= native_cpu_disable,
	.play_dead		= native_play_dead,

	.send_call_func_ipi	= native_send_call_func_ipi,
	.send_call_func_single_ipi = native_send_call_func_single_ipi,
};
EXPORT_SYMBOL_GPL(smp_ops);
Commit	Line	Data
0941ecb5 GC	1	/*
	2	* Intel SMP support routines.
	3	*
87c6fe26	4	* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
8f47e163	5	* (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
0941ecb5 GC	6	* (c) 2002,2003 Andi Kleen, SuSE Labs.
	7	*
	8	* i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
	9	*
	10	* This code is released under the GNU General Public License version 2 or
	11	* later.
	12	*/
	13
f9e47a12 GC	14	#include <linux/init.h>
	15
	16	#include <linux/mm.h>
	17	#include <linux/delay.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/kernel_stat.h>
	20	#include <linux/mc146818rtc.h>
	21	#include <linux/cache.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/cpu.h>
5a0e3ad6	24	#include <linux/gfp.h>
f9e47a12 GC	25
	26	#include <asm/mtrr.h>
	27	#include <asm/tlbflush.h>
	28	#include <asm/mmu_context.h>
	29	#include <asm/proto.h>
7b6aa335	30	#include <asm/apic.h>
0941ecb5 GC	31	/*
	32	* Some notes on x86 processor bugs affecting SMP operation:
	33	*
	34	* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
	35	* The Linux implications for SMP are handled as follows:
	36	*
	37	* Pentium III / [Xeon]
	38	* None of the E1AP-E3AP errata are visible to the user.
	39	*
	40	* E1AP. see PII A1AP
	41	* E2AP. see PII A2AP
	42	* E3AP. see PII A3AP
	43	*
	44	* Pentium II / [Xeon]
	45	* None of the A1AP-A3AP errata are visible to the user.
	46	*
	47	* A1AP. see PPro 1AP
	48	* A2AP. see PPro 2AP
	49	* A3AP. see PPro 7AP
	50	*
	51	* Pentium Pro
	52	* None of 1AP-9AP errata are visible to the normal user,
	53	* except occasional delivery of 'spurious interrupt' as trap #15.
	54	* This is very rare and a non-problem.
	55	*
	56	* 1AP. Linux maps APIC as non-cacheable
	57	* 2AP. worked around in hardware
	58	* 3AP. fixed in C0 and above steppings microcode update.
	59	* Linux does not use excessive STARTUP_IPIs.
	60	* 4AP. worked around in hardware
	61	* 5AP. symmetric IO mode (normal Linux operation) not affected.
	62	* 'noapic' mode has vector 0xf filled out properly.
	63	* 6AP. 'noapic' mode might be affected - fixed in later steppings
	64	* 7AP. We do not assume writes to the LVT deassering IRQs
	65	* 8AP. We do not enable low power mode (deep sleep) during MP bootup
	66	* 9AP. We do not use mixed mode
	67	*
	68	* Pentium
	69	* There is a marginal case where REP MOVS on 100MHz SMP
	70	* machines with B stepping processors can fail. XXX should provide
	71	* an L1cache=Writethrough or L1cache=off option.
	72	*
	73	* B stepping CPUs may hang. There are hardware work arounds
	74	* for this. We warn about it in case your board doesn't have the work
	75	* arounds. Basically that's so I can tell anyone with a B stepping
	76	* CPU and SMP problems "tough".
	77	*
	78	* Specific items [From Pentium Processor Specification Update]
	79	*
	80	* 1AP. Linux doesn't use remote read
	81	* 2AP. Linux doesn't trust APIC errors
	82	* 3AP. We work around this
	83	* 4AP. Linux never generated 3 interrupts of the same priority
	84	* to cause a lost local interrupt.
	85	* 5AP. Remote read is never used
	86	* 6AP. not affected - worked around in hardware
	87	* 7AP. not affected - worked around in hardware
	88	* 8AP. worked around in hardware - we get explicit CS errors if not
	89	* 9AP. only 'noapic' mode affected. Might generate spurious
	90	* interrupts, we log only the first one and count the
	91	* rest silently.
	92	* 10AP. not affected - worked around in hardware
	93	* 11AP. Linux reads the APIC between writes to avoid this, as per
	94	* the documentation. Make sure you preserve this as it affects
95	* the C stepping chips too.
96	* 12AP. not affected - worked around in hardware
97	* 13AP. not affected - worked around in hardware
98	* 14AP. we always deassert INIT during bootup
99	* 15AP. not affected - worked around in hardware
100	* 16AP. not affected - worked around in hardware
101	* 17AP. not affected - worked around in hardware
102	* 18AP. not affected - worked around in hardware
103	* 19AP. not affected - worked around in BIOS
104	*
105	* If this sounds worrying believe me these bugs are either ___RARE___,
106	* or are signal timing bugs worked around in hardware and there's
107	* about nothing of note with C stepping upwards.
108	*/
f9e47a12 GC	109
	110	/*
	111	* this function sends a 'reschedule' IPI to another CPU.
	112	* it goes straight through and wastes no time serializing
	113	* anything. Worst case is that we lose a reschedule ...
	114	*/
	115	static void native_smp_send_reschedule(int cpu)
	116	{
f6940101 GS	117	if (unlikely(cpu_is_offline(cpu))) {
	118	WARN_ON(1);
	119	return;
	120	}
dac5f412	121	apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
f9e47a12 GC	122	}
f9e47a12 GC	123
3b16cf87	124	void native_send_call_func_single_ipi(int cpu)
f9e47a12	125	{
dac5f412	126	apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
f9e47a12 GC	127	}
f9e47a12 GC	128
bcda016e	129	void native_send_call_func_ipi(const struct cpumask *mask)
f9e47a12	130	{
c2d1cec1	131	cpumask_var_t allbutself;
f9e47a12	132
c2d1cec1	133	if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
dac5f412	134	apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
c2d1cec1 MT	135	return;
c2d1cec1 MT	136	}
f9e47a12	137
c2d1cec1 MT	138	cpumask_copy(allbutself, cpu_online_mask);
	139	cpumask_clear_cpu(smp_processor_id(), allbutself);
	140
	141	if (cpumask_equal(mask, allbutself) &&
	142	cpumask_equal(cpu_online_mask, cpu_callout_mask))
dac5f412	143	apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
f9e47a12	144	else
dac5f412	145	apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
c2d1cec1 MT	146
c2d1cec1 MT	147	free_cpumask_var(allbutself);
f9e47a12 GC	148	}
f9e47a12 GC	149
f9e47a12 GC	150	/*
	151	* this function calls the 'stop' function on all other CPUs in the system.
	152	*/
	153
4ef702c1 AK	154	asmlinkage void smp_reboot_interrupt(void)
	155	{
	156	ack_APIC_irq();
	157	irq_enter();
	158	stop_this_cpu(NULL);
	159	irq_exit();
	160	}
	161
f9e47a12 GC	162	static void native_smp_send_stop(void)
f9e47a12 GC	163	{
f9e47a12	164	unsigned long flags;
4ef702c1	165	unsigned long wait;
f9e47a12 GC	166
	167	if (reboot_force)
	168	return;
	169
4ef702c1 AK	170	/*
	171	* Use an own vector here because smp_call_function
	172	* does lots of things not suitable in a panic situation.
	173	* On most systems we could also use an NMI here,
	174	* but there are a few systems around where NMI
	175	* is problematic so stay with an non NMI for now
	176	* (this implies we cannot stop CPUs spinning with irq off
	177	* currently)
	178	*/
	179	if (num_online_cpus() > 1) {
	180	apic->send_IPI_allbutself(REBOOT_VECTOR);
	181
	182	/* Don't wait longer than a second */
	183	wait = USEC_PER_SEC;
	184	while (num_online_cpus() > 1 && wait--)
	185	udelay(1);
	186	}
	187
f9e47a12	188	local_irq_save(flags);
f9e47a12 GC	189	disable_local_APIC();
	190	local_irq_restore(flags);
	191	}
	192
	193	/*
	194	* Reschedule call back. Nothing to do,
	195	* all the work is done automatically when
	196	* we return from the interrupt.
	197	*/
	198	void smp_reschedule_interrupt(struct pt_regs *regs)
	199	{
	200	ack_APIC_irq();
915b0d01	201	inc_irq_stat(irq_resched_count);
32f88400 MT	202	/*
	203	* KVM uses this interrupt to force a cpu out of guest mode
	204	*/
f9e47a12 GC	205	}
	206
	207	void smp_call_function_interrupt(struct pt_regs *regs)
	208	{
f9e47a12	209	ack_APIC_irq();
f9e47a12	210	irq_enter();
3b16cf87	211	generic_smp_call_function_interrupt();
915b0d01	212	inc_irq_stat(irq_call_count);
f9e47a12	213	irq_exit();
3b16cf87	214	}
f9e47a12	215
5e374fb6	216	void smp_call_function_single_interrupt(struct pt_regs *regs)
3b16cf87 JA	217	{
	218	ack_APIC_irq();
	219	irq_enter();
	220	generic_smp_call_function_single_interrupt();
915b0d01	221	inc_irq_stat(irq_call_count);
3b16cf87	222	irq_exit();
f9e47a12 GC	223	}
	224
	225	struct smp_ops smp_ops = {
b9b34f24 CG	226	.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
	227	.smp_prepare_cpus = native_smp_prepare_cpus,
	228	.smp_cpus_done = native_smp_cpus_done,
f9e47a12	229
b9b34f24 CG	230	.smp_send_stop = native_smp_send_stop,
b9b34f24 CG	231	.smp_send_reschedule = native_smp_send_reschedule,
3b16cf87	232
b9b34f24 CG	233	.cpu_up = native_cpu_up,
	234	.cpu_die = native_cpu_die,
	235	.cpu_disable = native_cpu_disable,
	236	.play_dead = native_play_dead,
93be71b6	237
b9b34f24	238	.send_call_func_ipi = native_send_call_func_ipi,
3b16cf87	239	.send_call_func_single_ipi = native_send_call_func_single_ipi,
f9e47a12 GC	240	};
f9e47a12 GC	241	EXPORT_SYMBOL_GPL(smp_ops);