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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
f3294a33 | 28 | #include <linux/bootmem.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
1d16b53e | 39 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 40 | |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/smp.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/timer.h> | |
306e440d | 45 | #include <asm/i8259.h> |
3e4ff115 | 46 | #include <asm/nmi.h> |
2d3fcc1c | 47 | #include <asm/msidef.h> |
8b955b0d | 48 | #include <asm/hypertransport.h> |
a4dbc34d | 49 | #include <asm/setup.h> |
1da177e4 | 50 | |
497c9a19 | 51 | #include <mach_ipi.h> |
1da177e4 | 52 | #include <mach_apic.h> |
874c4fe3 | 53 | #include <mach_apicdef.h> |
1da177e4 | 54 | |
32f71aff MR |
55 | #define __apicdebuginit(type) static type __init |
56 | ||
1da177e4 LT |
57 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
58 | atomic_t irq_mis_count; | |
59 | ||
fcfd636a EB |
60 | /* Where if anywhere is the i8259 connect in external int mode */ |
61 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
62 | ||
1da177e4 | 63 | static DEFINE_SPINLOCK(ioapic_lock); |
497c9a19 | 64 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 65 | |
35542c5e | 66 | int timer_through_8259 __initdata; |
f9262c12 | 67 | |
1da177e4 LT |
68 | /* |
69 | * Is the SiS APIC rmw bug present ? | |
70 | * -1 = don't know, 0 = no, 1 = yes | |
71 | */ | |
72 | int sis_apic_bug = -1; | |
73 | ||
301e6190 | 74 | int first_free_entry; |
1da177e4 LT |
75 | /* |
76 | * # of IRQ routing registers | |
77 | */ | |
78 | int nr_ioapic_registers[MAX_IO_APICS]; | |
79 | ||
9f640ccb | 80 | /* I/O APIC entries */ |
ec2cd0a2 | 81 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
82 | int nr_ioapics; |
83 | ||
584f734d | 84 | /* MP IRQ source entries */ |
2fddb6e2 | 85 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
86 | |
87 | /* # of MP IRQ source entries */ | |
88 | int mp_irq_entries; | |
89 | ||
8732fc4b AS |
90 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
91 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
92 | #endif | |
93 | ||
94 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
95 | ||
1a3f239d | 96 | static int disable_timer_pin_1 __initdata; |
66759a01 | 97 | |
da51a821 | 98 | struct irq_cfg; |
0f978f45 | 99 | struct irq_pin_list; |
a1420f39 | 100 | struct irq_cfg { |
da51a821 YL |
101 | unsigned int irq; |
102 | struct irq_cfg *next; | |
0f978f45 | 103 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
104 | cpumask_t domain; |
105 | cpumask_t old_domain; | |
106 | unsigned move_cleanup_count; | |
a1420f39 | 107 | u8 vector; |
497c9a19 | 108 | u8 move_in_progress : 1; |
a1420f39 YL |
109 | }; |
110 | ||
111 | ||
112 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ | |
113 | static struct irq_cfg irq_cfg_legacy[] __initdata = { | |
497c9a19 YL |
114 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
115 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
116 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
117 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
118 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
119 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
120 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
121 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
122 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
123 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
124 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
125 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
126 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
127 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
128 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
129 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
130 | }; |
131 | ||
da51a821 YL |
132 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
133 | /* need to be biger than size of irq_cfg_legacy */ | |
134 | static int nr_irq_cfg = 32; | |
135 | ||
136 | static int __init parse_nr_irq_cfg(char *arg) | |
137 | { | |
138 | if (arg) { | |
139 | nr_irq_cfg = simple_strtoul(arg, NULL, 0); | |
140 | if (nr_irq_cfg < 32) | |
141 | nr_irq_cfg = 32; | |
142 | } | |
143 | return 0; | |
144 | } | |
145 | ||
146 | early_param("nr_irq_cfg", parse_nr_irq_cfg); | |
147 | ||
148 | static void init_one_irq_cfg(struct irq_cfg *cfg) | |
149 | { | |
150 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); | |
151 | } | |
152 | ||
153 | static struct irq_cfg *irq_cfgx; | |
154 | static struct irq_cfg *irq_cfgx_free; | |
a1420f39 YL |
155 | static void __init init_work(void *data) |
156 | { | |
da51a821 YL |
157 | struct dyn_array *da = data; |
158 | struct irq_cfg *cfg; | |
159 | int legacy_count; | |
160 | int i; | |
161 | ||
162 | cfg = *da->name; | |
a1420f39 | 163 | |
da51a821 | 164 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); |
a1420f39 | 165 | |
da51a821 YL |
166 | legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]); |
167 | for (i = legacy_count; i < *da->nr; i++) | |
168 | init_one_irq_cfg(&cfg[i]); | |
a1420f39 | 169 | |
da51a821 YL |
170 | for (i = 1; i < *da->nr; i++) |
171 | cfg[i-1].next = &cfg[i]; | |
a1420f39 | 172 | |
da51a821 YL |
173 | irq_cfgx_free = &irq_cfgx[legacy_count]; |
174 | irq_cfgx[legacy_count - 1].next = NULL; | |
a1420f39 YL |
175 | } |
176 | ||
da51a821 YL |
177 | #define for_each_irq_cfg(cfg) \ |
178 | for (cfg = irq_cfgx; cfg; cfg = cfg->next) | |
179 | ||
180 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work); | |
a1420f39 YL |
181 | |
182 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
183 | { | |
da51a821 YL |
184 | struct irq_cfg *cfg; |
185 | ||
186 | cfg = irq_cfgx; | |
187 | while (cfg) { | |
188 | if (cfg->irq == irq) | |
189 | return cfg; | |
190 | ||
191 | cfg = cfg->next; | |
192 | } | |
193 | ||
194 | return NULL; | |
195 | } | |
196 | ||
197 | static struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
198 | { | |
199 | struct irq_cfg *cfg, *cfg_pri; | |
200 | int i; | |
201 | int count = 0; | |
202 | ||
203 | cfg_pri = cfg = irq_cfgx; | |
204 | while (cfg) { | |
205 | if (cfg->irq == irq) | |
206 | return cfg; | |
207 | ||
208 | cfg_pri = cfg; | |
209 | cfg = cfg->next; | |
210 | count++; | |
211 | } | |
212 | ||
213 | if (!irq_cfgx_free) { | |
214 | unsigned long phys; | |
215 | unsigned long total_bytes; | |
216 | /* | |
217 | * we run out of pre-allocate ones, allocate more | |
218 | */ | |
219 | printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg); | |
220 | ||
221 | total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg; | |
222 | if (after_bootmem) | |
223 | cfg = kzalloc(total_bytes, GFP_ATOMIC); | |
224 | else | |
225 | cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0); | |
a1420f39 | 226 | |
da51a821 YL |
227 | if (!cfg) |
228 | panic("please boot with nr_irq_cfg= %d\n", count * 2); | |
229 | ||
230 | phys = __pa(cfg); | |
231 | printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes); | |
232 | ||
233 | for (i = 0; i < nr_irq_cfg; i++) | |
234 | init_one_irq_cfg(&cfg[i]); | |
235 | ||
236 | for (i = 1; i < nr_irq_cfg; i++) | |
237 | cfg[i-1].next = &cfg[i]; | |
238 | ||
239 | irq_cfgx_free = cfg; | |
240 | } | |
241 | ||
242 | cfg = irq_cfgx_free; | |
243 | irq_cfgx_free = irq_cfgx_free->next; | |
244 | cfg->next = NULL; | |
245 | if (cfg_pri) | |
246 | cfg_pri->next = cfg; | |
247 | else | |
248 | irq_cfgx = cfg; | |
249 | cfg->irq = irq; | |
250 | printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq); | |
251 | ||
252 | #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG | |
253 | { | |
254 | /* dump the results */ | |
255 | struct irq_cfg *cfg; | |
256 | unsigned long phys; | |
257 | unsigned long bytes = sizeof(struct irq_cfg); | |
258 | ||
259 | printk(KERN_DEBUG "=========================== %d\n", irq); | |
260 | printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq); | |
261 | for_each_irq_cfg(cfg) { | |
262 | phys = __pa(cfg); | |
263 | printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes); | |
264 | } | |
265 | printk(KERN_DEBUG "===========================\n"); | |
266 | } | |
267 | #endif | |
268 | return cfg; | |
a1420f39 YL |
269 | } |
270 | ||
497c9a19 | 271 | static int assign_irq_vector(int irq, cpumask_t mask); |
1da177e4 LT |
272 | /* |
273 | * Rough estimation of how many shared IRQs there are, can | |
274 | * be changed anytime. | |
275 | */ | |
301e6190 | 276 | int pin_map_size; |
0799e432 | 277 | |
1da177e4 LT |
278 | /* |
279 | * This is performance-critical, we want to do it O(1) | |
280 | * | |
281 | * the indexing order of this array favors 1:1 mappings | |
282 | * between pins and IRQs. | |
283 | */ | |
284 | ||
0f978f45 YL |
285 | struct irq_pin_list { |
286 | int apic, pin; | |
287 | struct irq_pin_list *next; | |
288 | }; | |
289 | ||
290 | static struct irq_pin_list *irq_2_pin_head; | |
291 | /* fill one page ? */ | |
292 | static int nr_irq_2_pin = 0x100; | |
293 | static struct irq_pin_list *irq_2_pin_ptr; | |
294 | static void __init irq_2_pin_init_work(void *data) | |
295 | { | |
296 | struct dyn_array *da = data; | |
297 | struct irq_pin_list *pin; | |
298 | int i; | |
299 | ||
300 | pin = *da->name; | |
301 | ||
302 | for (i = 1; i < *da->nr; i++) | |
303 | pin[i-1].next = &pin[i]; | |
304 | ||
305 | irq_2_pin_ptr = &pin[0]; | |
306 | } | |
307 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); | |
308 | ||
309 | static struct irq_pin_list *get_one_free_irq_2_pin(void) | |
310 | { | |
311 | struct irq_pin_list *pin; | |
312 | int i; | |
313 | ||
314 | pin = irq_2_pin_ptr; | |
315 | ||
316 | if (pin) { | |
317 | irq_2_pin_ptr = pin->next; | |
318 | pin->next = NULL; | |
319 | return pin; | |
320 | } | |
321 | ||
322 | /* | |
323 | * we run out of pre-allocate ones, allocate more | |
324 | */ | |
325 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); | |
326 | ||
327 | if (after_bootmem) | |
328 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, | |
329 | GFP_ATOMIC); | |
330 | else | |
331 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * | |
332 | nr_irq_2_pin, PAGE_SIZE, 0); | |
333 | ||
334 | if (!pin) | |
335 | panic("can not get more irq_2_pin\n"); | |
301e6190 | 336 | |
0f978f45 YL |
337 | for (i = 1; i < nr_irq_2_pin; i++) |
338 | pin[i-1].next = &pin[i]; | |
339 | ||
340 | irq_2_pin_ptr = pin->next; | |
341 | pin->next = NULL; | |
342 | ||
343 | return pin; | |
344 | } | |
1da177e4 | 345 | |
130fe05d LT |
346 | struct io_apic { |
347 | unsigned int index; | |
348 | unsigned int unused[3]; | |
349 | unsigned int data; | |
350 | }; | |
351 | ||
352 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
353 | { | |
354 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 355 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
356 | } |
357 | ||
358 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
359 | { | |
360 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
361 | writel(reg, &io_apic->index); | |
362 | return readl(&io_apic->data); | |
363 | } | |
364 | ||
365 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(reg, &io_apic->index); | |
369 | writel(value, &io_apic->data); | |
370 | } | |
371 | ||
372 | /* | |
373 | * Re-write a value: to be used for read-modify-write | |
374 | * cycles where the read already set up the index register. | |
375 | * | |
376 | * Older SiS APIC requires we rewrite the index register | |
377 | */ | |
378 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
379 | { | |
cb468984 | 380 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
381 | if (sis_apic_bug) |
382 | writel(reg, &io_apic->index); | |
383 | writel(value, &io_apic->data); | |
384 | } | |
385 | ||
cf4c6a2f AK |
386 | union entry_union { |
387 | struct { u32 w1, w2; }; | |
388 | struct IO_APIC_route_entry entry; | |
389 | }; | |
390 | ||
391 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
392 | { | |
393 | union entry_union eu; | |
394 | unsigned long flags; | |
395 | spin_lock_irqsave(&ioapic_lock, flags); | |
396 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
397 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
398 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
399 | return eu.entry; | |
400 | } | |
401 | ||
f9dadfa7 LT |
402 | /* |
403 | * When we write a new IO APIC routing entry, we need to write the high | |
404 | * word first! If the mask bit in the low word is clear, we will enable | |
405 | * the interrupt, and we need to make sure the entry is fully populated | |
406 | * before that happens. | |
407 | */ | |
d15512f4 AK |
408 | static void |
409 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 410 | { |
cf4c6a2f AK |
411 | union entry_union eu; |
412 | eu.entry = e; | |
f9dadfa7 LT |
413 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
414 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
415 | } |
416 | ||
417 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
418 | { | |
419 | unsigned long flags; | |
420 | spin_lock_irqsave(&ioapic_lock, flags); | |
421 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
422 | spin_unlock_irqrestore(&ioapic_lock, flags); |
423 | } | |
424 | ||
425 | /* | |
426 | * When we mask an IO APIC routing entry, we need to write the low | |
427 | * word first, in order to set the mask bit before we change the | |
428 | * high bits! | |
429 | */ | |
430 | static void ioapic_mask_entry(int apic, int pin) | |
431 | { | |
432 | unsigned long flags; | |
433 | union entry_union eu = { .entry.mask = 1 }; | |
434 | ||
cf4c6a2f AK |
435 | spin_lock_irqsave(&ioapic_lock, flags); |
436 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
437 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
438 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
439 | } | |
440 | ||
497c9a19 YL |
441 | #ifdef CONFIG_SMP |
442 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) | |
443 | { | |
444 | int apic, pin; | |
445 | struct irq_cfg *cfg; | |
446 | struct irq_pin_list *entry; | |
447 | ||
448 | cfg = irq_cfg(irq); | |
449 | entry = cfg->irq_2_pin; | |
450 | for (;;) { | |
451 | unsigned int reg; | |
452 | ||
453 | if (!entry) | |
454 | break; | |
455 | ||
456 | apic = entry->apic; | |
457 | pin = entry->pin; | |
458 | io_apic_write(apic, 0x11 + pin*2, dest); | |
459 | reg = io_apic_read(apic, 0x10 + pin*2); | |
460 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
461 | reg |= vector; | |
462 | io_apic_modify(apic, 0x10 + pin *2, reg); | |
463 | if (!entry->next) | |
464 | break; | |
465 | entry = entry->next; | |
466 | } | |
467 | } | |
468 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
469 | { | |
470 | struct irq_cfg *cfg; | |
471 | unsigned long flags; | |
472 | unsigned int dest; | |
473 | cpumask_t tmp; | |
474 | ||
475 | cfg = irq_cfg(irq); | |
476 | ||
477 | cpus_and(tmp, mask, cpu_online_map); | |
478 | if (cpus_empty(tmp)) | |
479 | return; | |
480 | ||
481 | if (assign_irq_vector(irq, mask)) | |
482 | return; | |
483 | ||
484 | cpus_and(tmp, cfg->domain, mask); | |
485 | ||
486 | dest = cpu_mask_to_apicid(tmp); | |
487 | /* | |
488 | * Only the high 8 bits are valid. | |
489 | */ | |
490 | dest = SET_APIC_LOGICAL_ID(dest); | |
491 | ||
492 | spin_lock_irqsave(&ioapic_lock, flags); | |
493 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
494 | irq_to_desc(irq)->affinity = mask; | |
495 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
496 | } | |
497 | ||
498 | #endif /* CONFIG_SMP */ | |
499 | ||
1da177e4 LT |
500 | /* |
501 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
502 | * shared ISA-space IRQs, so we have to support them. We are super | |
503 | * fast in the common case, and fast for shared ISA-space IRQs. | |
504 | */ | |
505 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
506 | { | |
0f978f45 YL |
507 | struct irq_cfg *cfg; |
508 | struct irq_pin_list *entry; | |
509 | ||
510 | /* first time to refer irq_cfg, so with new */ | |
511 | cfg = irq_cfg_alloc(irq); | |
512 | entry = cfg->irq_2_pin; | |
513 | if (!entry) { | |
514 | entry = get_one_free_irq_2_pin(); | |
515 | cfg->irq_2_pin = entry; | |
516 | entry->apic = apic; | |
517 | entry->pin = pin; | |
518 | printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); | |
519 | return; | |
520 | } | |
1da177e4 | 521 | |
0f978f45 YL |
522 | while (entry->next) { |
523 | /* not again, please */ | |
524 | if (entry->apic == apic && entry->pin == pin) | |
525 | return; | |
1da177e4 | 526 | |
0f978f45 | 527 | entry = entry->next; |
1da177e4 | 528 | } |
0f978f45 YL |
529 | |
530 | entry->next = get_one_free_irq_2_pin(); | |
531 | entry = entry->next; | |
1da177e4 LT |
532 | entry->apic = apic; |
533 | entry->pin = pin; | |
0f978f45 | 534 | printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); |
1da177e4 LT |
535 | } |
536 | ||
537 | /* | |
538 | * Reroute an IRQ to a different pin. | |
539 | */ | |
540 | static void __init replace_pin_at_irq(unsigned int irq, | |
541 | int oldapic, int oldpin, | |
542 | int newapic, int newpin) | |
543 | { | |
0f978f45 YL |
544 | struct irq_cfg *cfg = irq_cfg(irq); |
545 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
546 | int replaced = 0; | |
1da177e4 | 547 | |
0f978f45 | 548 | while (entry) { |
1da177e4 LT |
549 | if (entry->apic == oldapic && entry->pin == oldpin) { |
550 | entry->apic = newapic; | |
551 | entry->pin = newpin; | |
0f978f45 YL |
552 | replaced = 1; |
553 | /* every one is different, right? */ | |
1da177e4 | 554 | break; |
0f978f45 YL |
555 | } |
556 | entry = entry->next; | |
1da177e4 | 557 | } |
0f978f45 YL |
558 | |
559 | /* why? call replace before add? */ | |
560 | if (!replaced) | |
561 | add_pin_to_irq(irq, newapic, newpin); | |
1da177e4 LT |
562 | } |
563 | ||
36062448 | 564 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 | 565 | { |
0f978f45 YL |
566 | struct irq_cfg *cfg; |
567 | struct irq_pin_list *entry; | |
1da177e4 LT |
568 | unsigned int pin, reg; |
569 | ||
0f978f45 YL |
570 | cfg = irq_cfg(irq); |
571 | entry = cfg->irq_2_pin; | |
1da177e4 | 572 | for (;;) { |
0f978f45 | 573 | if (!entry) |
1da177e4 | 574 | break; |
0f978f45 | 575 | pin = entry->pin; |
1da177e4 LT |
576 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
577 | reg &= ~disable; | |
578 | reg |= enable; | |
579 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
580 | if (!entry->next) | |
581 | break; | |
0f978f45 | 582 | entry = entry->next; |
1da177e4 LT |
583 | } |
584 | } | |
585 | ||
586 | /* mask = 1 */ | |
36062448 | 587 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 588 | { |
46b3b4ef | 589 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
590 | } |
591 | ||
592 | /* mask = 0 */ | |
36062448 | 593 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 594 | { |
46b3b4ef | 595 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
596 | } |
597 | ||
598 | /* mask = 1, trigger = 0 */ | |
36062448 | 599 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 600 | { |
46b3b4ef CG |
601 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
602 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
603 | } |
604 | ||
605 | /* mask = 0, trigger = 1 */ | |
36062448 | 606 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 607 | { |
46b3b4ef CG |
608 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
609 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
610 | } |
611 | ||
36062448 | 612 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
613 | { |
614 | unsigned long flags; | |
615 | ||
616 | spin_lock_irqsave(&ioapic_lock, flags); | |
617 | __mask_IO_APIC_irq(irq); | |
618 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
619 | } | |
620 | ||
36062448 | 621 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
622 | { |
623 | unsigned long flags; | |
624 | ||
625 | spin_lock_irqsave(&ioapic_lock, flags); | |
626 | __unmask_IO_APIC_irq(irq); | |
627 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
628 | } | |
629 | ||
630 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
631 | { | |
632 | struct IO_APIC_route_entry entry; | |
36062448 | 633 | |
1da177e4 | 634 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 635 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
636 | if (entry.delivery_mode == dest_SMI) |
637 | return; | |
638 | ||
639 | /* | |
640 | * Disable it in the IO-APIC irq-routing table: | |
641 | */ | |
f9dadfa7 | 642 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
643 | } |
644 | ||
36062448 | 645 | static void clear_IO_APIC(void) |
1da177e4 LT |
646 | { |
647 | int apic, pin; | |
648 | ||
649 | for (apic = 0; apic < nr_ioapics; apic++) | |
650 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
651 | clear_IO_APIC_pin(apic, pin); | |
652 | } | |
653 | ||
1da177e4 | 654 | #ifndef CONFIG_SMP |
75604d7f | 655 | void send_IPI_self(int vector) |
1da177e4 LT |
656 | { |
657 | unsigned int cfg; | |
658 | ||
659 | /* | |
660 | * Wait for idle. | |
661 | */ | |
662 | apic_wait_icr_idle(); | |
663 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
664 | /* | |
665 | * Send the IPI. The write to APIC_ICR fires this off. | |
666 | */ | |
593f4a78 | 667 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
668 | } |
669 | #endif /* !CONFIG_SMP */ | |
670 | ||
671 | ||
672 | /* | |
673 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
674 | * specific CPU-side IRQs. | |
675 | */ | |
676 | ||
677 | #define MAX_PIRQS 8 | |
678 | static int pirq_entries [MAX_PIRQS]; | |
679 | static int pirqs_enabled; | |
680 | int skip_ioapic_setup; | |
681 | ||
1da177e4 LT |
682 | static int __init ioapic_pirq_setup(char *str) |
683 | { | |
684 | int i, max; | |
685 | int ints[MAX_PIRQS+1]; | |
686 | ||
687 | get_options(str, ARRAY_SIZE(ints), ints); | |
688 | ||
689 | for (i = 0; i < MAX_PIRQS; i++) | |
690 | pirq_entries[i] = -1; | |
691 | ||
692 | pirqs_enabled = 1; | |
693 | apic_printk(APIC_VERBOSE, KERN_INFO | |
694 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
695 | max = MAX_PIRQS; | |
696 | if (ints[0] < MAX_PIRQS) | |
697 | max = ints[0]; | |
698 | ||
699 | for (i = 0; i < max; i++) { | |
700 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
701 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
702 | /* | |
703 | * PIRQs are mapped upside down, usually. | |
704 | */ | |
705 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
706 | } | |
707 | return 1; | |
708 | } | |
709 | ||
710 | __setup("pirq=", ioapic_pirq_setup); | |
711 | ||
712 | /* | |
713 | * Find the IRQ entry number of a certain pin. | |
714 | */ | |
715 | static int find_irq_entry(int apic, int pin, int type) | |
716 | { | |
717 | int i; | |
718 | ||
719 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
720 | if (mp_irqs[i].mp_irqtype == type && |
721 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
722 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
723 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
724 | return i; |
725 | ||
726 | return -1; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Find the pin to which IRQ[irq] (ISA) is connected | |
731 | */ | |
fcfd636a | 732 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
733 | { |
734 | int i; | |
735 | ||
736 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 737 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 738 | |
d27e2b8e | 739 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
740 | (mp_irqs[i].mp_irqtype == type) && |
741 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 742 | |
2fddb6e2 | 743 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
744 | } |
745 | return -1; | |
746 | } | |
747 | ||
fcfd636a EB |
748 | static int __init find_isa_irq_apic(int irq, int type) |
749 | { | |
750 | int i; | |
751 | ||
752 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 753 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 754 | |
73b2961b | 755 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
756 | (mp_irqs[i].mp_irqtype == type) && |
757 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
758 | break; |
759 | } | |
760 | if (i < mp_irq_entries) { | |
761 | int apic; | |
36062448 | 762 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 763 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
764 | return apic; |
765 | } | |
766 | } | |
767 | ||
768 | return -1; | |
769 | } | |
770 | ||
1da177e4 LT |
771 | /* |
772 | * Find a specific PCI IRQ entry. | |
773 | * Not an __init, possibly needed by modules | |
774 | */ | |
775 | static int pin_2_irq(int idx, int apic, int pin); | |
776 | ||
777 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
778 | { | |
779 | int apic, i, best_guess = -1; | |
780 | ||
781 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
782 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 783 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
784 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
785 | return -1; | |
786 | } | |
787 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 788 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
789 | |
790 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
791 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
792 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
793 | break; |
794 | ||
47cab822 | 795 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 796 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 797 | (bus == lbus) && |
2fddb6e2 | 798 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 799 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
800 | |
801 | if (!(apic || IO_APIC_IRQ(irq))) | |
802 | continue; | |
803 | ||
2fddb6e2 | 804 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
805 | return irq; |
806 | /* | |
807 | * Use the first all-but-pin matching entry as a | |
808 | * best-guess fuzzy result for broken mptables. | |
809 | */ | |
810 | if (best_guess < 0) | |
811 | best_guess = irq; | |
812 | } | |
813 | } | |
814 | return best_guess; | |
815 | } | |
129f6946 | 816 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 817 | |
c0a282c2 | 818 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
819 | /* |
820 | * EISA Edge/Level control register, ELCR | |
821 | */ | |
822 | static int EISA_ELCR(unsigned int irq) | |
823 | { | |
824 | if (irq < 16) { | |
825 | unsigned int port = 0x4d0 + (irq >> 3); | |
826 | return (inb(port) >> (irq & 7)) & 1; | |
827 | } | |
828 | apic_printk(APIC_VERBOSE, KERN_INFO | |
829 | "Broken MPtable reports ISA irq %d\n", irq); | |
830 | return 0; | |
831 | } | |
c0a282c2 | 832 | #endif |
1da177e4 | 833 | |
6728801d AS |
834 | /* ISA interrupts are always polarity zero edge triggered, |
835 | * when listed as conforming in the MP table. */ | |
836 | ||
837 | #define default_ISA_trigger(idx) (0) | |
838 | #define default_ISA_polarity(idx) (0) | |
839 | ||
1da177e4 LT |
840 | /* EISA interrupts are always polarity zero and can be edge or level |
841 | * trigger depending on the ELCR value. If an interrupt is listed as | |
842 | * EISA conforming in the MP table, that means its trigger type must | |
843 | * be read in from the ELCR */ | |
844 | ||
2fddb6e2 | 845 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 846 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
847 | |
848 | /* PCI interrupts are always polarity one level triggered, | |
849 | * when listed as conforming in the MP table. */ | |
850 | ||
851 | #define default_PCI_trigger(idx) (1) | |
852 | #define default_PCI_polarity(idx) (1) | |
853 | ||
854 | /* MCA interrupts are always polarity zero level triggered, | |
855 | * when listed as conforming in the MP table. */ | |
856 | ||
857 | #define default_MCA_trigger(idx) (1) | |
6728801d | 858 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 859 | |
61fd47e0 | 860 | static int MPBIOS_polarity(int idx) |
1da177e4 | 861 | { |
2fddb6e2 | 862 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
863 | int polarity; |
864 | ||
865 | /* | |
866 | * Determine IRQ line polarity (high active or low active): | |
867 | */ | |
3de352bb | 868 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 869 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 870 | { |
36062448 PC |
871 | polarity = test_bit(bus, mp_bus_not_pci)? |
872 | default_ISA_polarity(idx): | |
873 | default_PCI_polarity(idx); | |
874 | break; | |
875 | } | |
876 | case 1: /* high active */ | |
877 | { | |
878 | polarity = 0; | |
879 | break; | |
880 | } | |
881 | case 2: /* reserved */ | |
882 | { | |
883 | printk(KERN_WARNING "broken BIOS!!\n"); | |
884 | polarity = 1; | |
885 | break; | |
886 | } | |
887 | case 3: /* low active */ | |
888 | { | |
889 | polarity = 1; | |
890 | break; | |
891 | } | |
892 | default: /* invalid */ | |
893 | { | |
894 | printk(KERN_WARNING "broken BIOS!!\n"); | |
895 | polarity = 1; | |
896 | break; | |
897 | } | |
1da177e4 LT |
898 | } |
899 | return polarity; | |
900 | } | |
901 | ||
902 | static int MPBIOS_trigger(int idx) | |
903 | { | |
2fddb6e2 | 904 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
905 | int trigger; |
906 | ||
907 | /* | |
908 | * Determine IRQ trigger mode (edge or level sensitive): | |
909 | */ | |
3de352bb | 910 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 911 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 912 | { |
36062448 PC |
913 | trigger = test_bit(bus, mp_bus_not_pci)? |
914 | default_ISA_trigger(idx): | |
915 | default_PCI_trigger(idx); | |
c0a282c2 | 916 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
917 | switch (mp_bus_id_to_type[bus]) { |
918 | case MP_BUS_ISA: /* ISA pin */ | |
919 | { | |
920 | /* set before the switch */ | |
1da177e4 LT |
921 | break; |
922 | } | |
36062448 | 923 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 924 | { |
36062448 | 925 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
926 | break; |
927 | } | |
36062448 | 928 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 929 | { |
36062448 | 930 | /* set before the switch */ |
1da177e4 LT |
931 | break; |
932 | } | |
36062448 | 933 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 934 | { |
36062448 | 935 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
936 | break; |
937 | } | |
36062448 | 938 | default: |
1da177e4 LT |
939 | { |
940 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 941 | trigger = 1; |
1da177e4 LT |
942 | break; |
943 | } | |
944 | } | |
36062448 PC |
945 | #endif |
946 | break; | |
947 | } | |
948 | case 1: /* edge */ | |
949 | { | |
950 | trigger = 0; | |
951 | break; | |
952 | } | |
953 | case 2: /* reserved */ | |
954 | { | |
955 | printk(KERN_WARNING "broken BIOS!!\n"); | |
956 | trigger = 1; | |
957 | break; | |
958 | } | |
959 | case 3: /* level */ | |
960 | { | |
961 | trigger = 1; | |
962 | break; | |
963 | } | |
964 | default: /* invalid */ | |
965 | { | |
966 | printk(KERN_WARNING "broken BIOS!!\n"); | |
967 | trigger = 0; | |
968 | break; | |
969 | } | |
970 | } | |
1da177e4 LT |
971 | return trigger; |
972 | } | |
973 | ||
974 | static inline int irq_polarity(int idx) | |
975 | { | |
976 | return MPBIOS_polarity(idx); | |
977 | } | |
978 | ||
979 | static inline int irq_trigger(int idx) | |
980 | { | |
981 | return MPBIOS_trigger(idx); | |
982 | } | |
983 | ||
984 | static int pin_2_irq(int idx, int apic, int pin) | |
985 | { | |
986 | int irq, i; | |
2fddb6e2 | 987 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
988 | |
989 | /* | |
990 | * Debugging check, we are in big trouble if this message pops up! | |
991 | */ | |
2fddb6e2 | 992 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
993 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
994 | ||
643befed | 995 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 996 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
997 | else { |
998 | /* | |
999 | * PCI IRQs are mapped in order | |
1000 | */ | |
1001 | i = irq = 0; | |
1002 | while (i < apic) | |
1003 | irq += nr_ioapic_registers[i++]; | |
1004 | irq += pin; | |
1da177e4 | 1005 | |
643befed AS |
1006 | /* |
1007 | * For MPS mode, so far only needed by ES7000 platform | |
1008 | */ | |
1009 | if (ioapic_renumber_irq) | |
1010 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | /* | |
1014 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1015 | */ | |
1016 | if ((pin >= 16) && (pin <= 23)) { | |
1017 | if (pirq_entries[pin-16] != -1) { | |
1018 | if (!pirq_entries[pin-16]) { | |
1019 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1020 | "disabling PIRQ%d\n", pin-16); | |
1021 | } else { | |
1022 | irq = pirq_entries[pin-16]; | |
1023 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1024 | "using PIRQ%d -> IRQ %d\n", | |
1025 | pin-16, irq); | |
1026 | } | |
1027 | } | |
1028 | } | |
1029 | return irq; | |
1030 | } | |
1031 | ||
1032 | static inline int IO_APIC_irq_trigger(int irq) | |
1033 | { | |
1034 | int apic, idx, pin; | |
1035 | ||
1036 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1037 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
1038 | idx = find_irq_entry(apic, pin, mp_INT); |
1039 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
1040 | return irq_trigger(idx); |
1041 | } | |
1042 | } | |
1043 | /* | |
1044 | * nonexistent IRQs are edge default | |
1045 | */ | |
1046 | return 0; | |
1047 | } | |
1048 | ||
497c9a19 YL |
1049 | void lock_vector_lock(void) |
1050 | { | |
1051 | /* Used to the online set of cpus does not change | |
1052 | * during assign_irq_vector. | |
1053 | */ | |
1054 | spin_lock(&vector_lock); | |
1055 | } | |
1da177e4 | 1056 | |
497c9a19 | 1057 | void unlock_vector_lock(void) |
1da177e4 | 1058 | { |
497c9a19 YL |
1059 | spin_unlock(&vector_lock); |
1060 | } | |
1da177e4 | 1061 | |
497c9a19 YL |
1062 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1063 | { | |
1064 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; | |
1065 | unsigned int old_vector; | |
1066 | int cpu; | |
1067 | struct irq_cfg *cfg; | |
ace80ab7 | 1068 | |
497c9a19 | 1069 | cfg = irq_cfg(irq); |
8339f000 | 1070 | |
497c9a19 YL |
1071 | /* Only try and allocate irqs on cpus that are present */ |
1072 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1073 | |
497c9a19 YL |
1074 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1075 | return -EBUSY; | |
0a1ad60d | 1076 | |
497c9a19 YL |
1077 | old_vector = cfg->vector; |
1078 | if (old_vector) { | |
1079 | cpumask_t tmp; | |
1080 | cpus_and(tmp, cfg->domain, mask); | |
1081 | if (!cpus_empty(tmp)) | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | for_each_cpu_mask_nr(cpu, mask) { | |
1086 | cpumask_t domain, new_mask; | |
1087 | int new_cpu; | |
1088 | int vector, offset; | |
1089 | ||
1090 | domain = vector_allocation_domain(cpu); | |
1091 | cpus_and(new_mask, domain, cpu_online_map); | |
1092 | ||
1093 | vector = current_vector; | |
1094 | offset = current_offset; | |
1095 | next: | |
1096 | vector += 8; | |
1097 | if (vector >= first_system_vector) { | |
1098 | /* If we run out of vectors on large boxen, must share them. */ | |
1099 | offset = (offset + 1) % 8; | |
1100 | vector = FIRST_DEVICE_VECTOR + offset; | |
1101 | } | |
1102 | if (unlikely(current_vector == vector)) | |
1103 | continue; | |
1104 | if (vector == SYSCALL_VECTOR) | |
1105 | goto next; | |
1106 | ||
1107 | for_each_cpu_mask_nr(new_cpu, new_mask) | |
1108 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1109 | goto next; | |
1110 | /* Found one! */ | |
1111 | current_vector = vector; | |
1112 | current_offset = offset; | |
1113 | if (old_vector) { | |
1114 | cfg->move_in_progress = 1; | |
1115 | cfg->old_domain = cfg->domain; | |
1116 | } | |
7a959cff YL |
1117 | printk(KERN_DEBUG "assign_irq_vector: irq %d vector %#x cpu ", irq, vector); |
1118 | for_each_cpu_mask_nr(new_cpu, new_mask) { | |
1119 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1120 | printk(KERN_CONT " %d ", new_cpu); | |
1121 | } | |
1122 | printk(KERN_CONT "\n"); | |
497c9a19 YL |
1123 | cfg->vector = vector; |
1124 | cfg->domain = domain; | |
1125 | return 0; | |
1126 | } | |
1127 | return -ENOSPC; | |
1128 | } | |
1129 | ||
1130 | static int assign_irq_vector(int irq, cpumask_t mask) | |
1131 | { | |
1132 | int err; | |
ace80ab7 | 1133 | unsigned long flags; |
ace80ab7 EB |
1134 | |
1135 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 1136 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1137 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1138 | |
497c9a19 YL |
1139 | return err; |
1140 | } | |
1141 | ||
1142 | static void __clear_irq_vector(int irq) | |
1143 | { | |
1144 | struct irq_cfg *cfg; | |
1145 | cpumask_t mask; | |
1146 | int cpu, vector; | |
1147 | ||
1148 | cfg = irq_cfg(irq); | |
1149 | BUG_ON(!cfg->vector); | |
1150 | ||
1151 | vector = cfg->vector; | |
1152 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1153 | for_each_cpu_mask_nr(cpu, mask) | |
1154 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1155 | ||
1156 | cfg->vector = 0; | |
1157 | cpus_clear(cfg->domain); | |
1158 | } | |
1159 | ||
1160 | void __setup_vector_irq(int cpu) | |
1161 | { | |
1162 | /* Initialize vector_irq on a new cpu */ | |
1163 | /* This function must be called with vector_lock held */ | |
1164 | int irq, vector; | |
1165 | struct irq_cfg *cfg; | |
1166 | ||
1167 | /* Mark the inuse vectors */ | |
1168 | for_each_irq_cfg(cfg) { | |
1169 | if (!cpu_isset(cpu, cfg->domain)) | |
1170 | continue; | |
1171 | vector = cfg->vector; | |
1172 | irq = cfg->irq; | |
1173 | per_cpu(vector_irq, cpu)[vector] = irq; | |
1174 | } | |
1175 | /* Mark the free vectors */ | |
1176 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1177 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1178 | if (irq < 0) | |
1179 | continue; | |
1180 | ||
1181 | cfg = irq_cfg(irq); | |
1182 | if (!cpu_isset(cpu, cfg->domain)) | |
1183 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1184 | } | |
1da177e4 | 1185 | } |
3fde6900 | 1186 | |
f5b9ed7a | 1187 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1188 | |
1189 | #define IOAPIC_AUTO -1 | |
1190 | #define IOAPIC_EDGE 0 | |
1191 | #define IOAPIC_LEVEL 1 | |
1192 | ||
497c9a19 | 1193 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1194 | { |
08678b08 YL |
1195 | struct irq_desc *desc; |
1196 | ||
199751d7 YL |
1197 | /* first time to use this irq_desc */ |
1198 | if (irq < 16) | |
1199 | desc = irq_to_desc(irq); | |
1200 | else | |
1201 | desc = irq_to_desc_alloc(irq); | |
1202 | ||
6ebcc00e | 1203 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d | 1204 | trigger == IOAPIC_LEVEL) { |
08678b08 | 1205 | desc->status |= IRQ_LEVEL; |
a460e745 IM |
1206 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1207 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d | 1208 | } else { |
08678b08 | 1209 | desc->status &= ~IRQ_LEVEL; |
a460e745 IM |
1210 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1211 | handle_edge_irq, "edge"); | |
cc75b92d | 1212 | } |
1da177e4 LT |
1213 | } |
1214 | ||
497c9a19 YL |
1215 | static int setup_ioapic_entry(int apic, int irq, |
1216 | struct IO_APIC_route_entry *entry, | |
1217 | unsigned int destination, int trigger, | |
1218 | int polarity, int vector) | |
1da177e4 | 1219 | { |
497c9a19 YL |
1220 | /* |
1221 | * add it to the IO-APIC irq-routing table: | |
1222 | */ | |
1223 | memset(entry,0,sizeof(*entry)); | |
1224 | ||
1225 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1226 | entry->dest_mode = INT_DEST_MODE; | |
d83e94ac | 1227 | entry->dest = destination; |
497c9a19 YL |
1228 | |
1229 | entry->mask = 0; /* enable IRQ */ | |
1230 | entry->trigger = trigger; | |
1231 | entry->polarity = polarity; | |
1232 | entry->vector = vector; | |
1233 | ||
1234 | /* Mask level triggered irqs. | |
1235 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1236 | */ | |
1237 | if (trigger) | |
1238 | entry->mask = 1; | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
1244 | int trigger, int polarity) | |
1245 | { | |
1246 | struct irq_cfg *cfg; | |
1da177e4 | 1247 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1248 | cpumask_t mask; |
1249 | ||
1250 | if (!IO_APIC_IRQ(irq)) | |
1251 | return; | |
1252 | ||
1253 | cfg = irq_cfg(irq); | |
1254 | ||
1255 | mask = TARGET_CPUS; | |
1256 | if (assign_irq_vector(irq, mask)) | |
1257 | return; | |
1258 | ||
1259 | cpus_and(mask, cfg->domain, mask); | |
1260 | ||
1261 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1262 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1263 | "IRQ %d Mode:%i Active:%i)\n", | |
1264 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1265 | irq, trigger, polarity); | |
1266 | ||
1267 | ||
1268 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1269 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1270 | cfg->vector)) { | |
1271 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1272 | mp_ioapics[apic].mp_apicid, pin); | |
1273 | __clear_irq_vector(irq); | |
1274 | return; | |
1275 | } | |
1276 | ||
1277 | ioapic_register_intr(irq, trigger); | |
1278 | if (irq < 16) | |
1279 | disable_8259A_irq(irq); | |
1280 | ||
1281 | ioapic_write_entry(apic, pin, entry); | |
1282 | } | |
1283 | ||
1284 | static void __init setup_IO_APIC_irqs(void) | |
1285 | { | |
1286 | int apic, pin, idx, irq, first_notcon = 1; | |
1da177e4 LT |
1287 | |
1288 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1289 | ||
1290 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1291 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1292 | ||
497c9a19 | 1293 | idx = find_irq_entry(apic,pin,mp_INT); |
1da177e4 LT |
1294 | if (idx == -1) { |
1295 | if (first_notcon) { | |
497c9a19 | 1296 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1297 | first_notcon = 0; |
1298 | } else | |
497c9a19 | 1299 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1300 | continue; |
1301 | } | |
20d225b9 YL |
1302 | if (!first_notcon) { |
1303 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1304 | first_notcon = 1; | |
1305 | } | |
1306 | ||
1da177e4 | 1307 | irq = pin_2_irq(idx, apic, pin); |
1da177e4 | 1308 | |
497c9a19 YL |
1309 | if (multi_timer_check(apic, irq)) |
1310 | continue; | |
1da177e4 | 1311 | |
497c9a19 | 1312 | add_pin_to_irq(irq, apic, pin); |
36062448 | 1313 | |
497c9a19 YL |
1314 | setup_IO_APIC_irq(apic, pin, irq, |
1315 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1316 | } |
1317 | } | |
1318 | ||
1319 | if (!first_notcon) | |
1320 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1321 | } | |
1322 | ||
1323 | /* | |
f7633ce5 | 1324 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1325 | */ |
f7633ce5 MR |
1326 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1327 | int vector) | |
1da177e4 LT |
1328 | { |
1329 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1330 | |
36062448 | 1331 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1332 | |
1333 | /* | |
1334 | * We use logical delivery to get the timer IRQ | |
1335 | * to the first CPU. | |
1336 | */ | |
1337 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1338 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1339 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1340 | entry.delivery_mode = INT_DELIVERY_MODE; |
1341 | entry.polarity = 0; | |
1342 | entry.trigger = 0; | |
1343 | entry.vector = vector; | |
1344 | ||
1345 | /* | |
1346 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1347 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1348 | */ |
497c9a19 | 1349 | ioapic_register_intr(0, IOAPIC_EDGE); |
1da177e4 LT |
1350 | |
1351 | /* | |
1352 | * Add it to the IO-APIC irq-routing table: | |
1353 | */ | |
cf4c6a2f | 1354 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1355 | } |
1356 | ||
32f71aff MR |
1357 | |
1358 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1359 | { |
1360 | int apic, i; | |
1361 | union IO_APIC_reg_00 reg_00; | |
1362 | union IO_APIC_reg_01 reg_01; | |
1363 | union IO_APIC_reg_02 reg_02; | |
1364 | union IO_APIC_reg_03 reg_03; | |
1365 | unsigned long flags; | |
0f978f45 | 1366 | struct irq_cfg *cfg; |
1da177e4 LT |
1367 | |
1368 | if (apic_verbosity == APIC_QUIET) | |
1369 | return; | |
1370 | ||
36062448 | 1371 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1372 | for (i = 0; i < nr_ioapics; i++) |
1373 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1374 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1375 | |
1376 | /* | |
1377 | * We are a bit conservative about what we expect. We have to | |
1378 | * know about every hardware change ASAP. | |
1379 | */ | |
1380 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1381 | ||
1382 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1383 | ||
1384 | spin_lock_irqsave(&ioapic_lock, flags); | |
1385 | reg_00.raw = io_apic_read(apic, 0); | |
1386 | reg_01.raw = io_apic_read(apic, 1); | |
1387 | if (reg_01.bits.version >= 0x10) | |
1388 | reg_02.raw = io_apic_read(apic, 2); | |
1389 | if (reg_01.bits.version >= 0x20) | |
1390 | reg_03.raw = io_apic_read(apic, 3); | |
1391 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1392 | ||
ec2cd0a2 | 1393 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1394 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1395 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1396 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1397 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1398 | |
1399 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1400 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1401 | |
1402 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1403 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1404 | |
1405 | /* | |
1406 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1407 | * but the value of reg_02 is read as the previous read register | |
1408 | * value, so ignore it if reg_02 == reg_01. | |
1409 | */ | |
1410 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1411 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1412 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1413 | } |
1414 | ||
1415 | /* | |
1416 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1417 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1418 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1419 | */ | |
1420 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1421 | reg_03.raw != reg_01.raw) { | |
1422 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1423 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1424 | } |
1425 | ||
1426 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1427 | ||
d83e94ac YL |
1428 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1429 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1430 | |
1431 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1432 | struct IO_APIC_route_entry entry; | |
1433 | ||
cf4c6a2f | 1434 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1435 | |
d83e94ac | 1436 | printk(KERN_DEBUG " %02x %02X ", i, entry.dest); |
1da177e4 LT |
1437 | |
1438 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1439 | entry.mask, | |
1440 | entry.trigger, | |
1441 | entry.irr, | |
1442 | entry.polarity, | |
1443 | entry.delivery_status, | |
1444 | entry.dest_mode, | |
1445 | entry.delivery_mode, | |
1446 | entry.vector | |
1447 | ); | |
1448 | } | |
1449 | } | |
1da177e4 | 1450 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0f978f45 YL |
1451 | for_each_irq_cfg(cfg) { |
1452 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
1453 | if (!entry) | |
1da177e4 | 1454 | continue; |
ace80ab7 | 1455 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1456 | for (;;) { |
1457 | printk("-> %d:%d", entry->apic, entry->pin); | |
1458 | if (!entry->next) | |
1459 | break; | |
0f978f45 | 1460 | entry = entry->next; |
1da177e4 LT |
1461 | } |
1462 | printk("\n"); | |
1463 | } | |
1464 | ||
1465 | printk(KERN_INFO ".................................... done.\n"); | |
1466 | ||
1467 | return; | |
1468 | } | |
1469 | ||
32f71aff | 1470 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1471 | { |
1472 | unsigned int v; | |
1473 | int i, j; | |
1474 | ||
1475 | if (apic_verbosity == APIC_QUIET) | |
1476 | return; | |
1477 | ||
1478 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1479 | for (i = 0; i < 8; i++) { | |
1480 | v = apic_read(base + i*0x10); | |
1481 | for (j = 0; j < 32; j++) { | |
1482 | if (v & (1<<j)) | |
1483 | printk("1"); | |
1484 | else | |
1485 | printk("0"); | |
1486 | } | |
1487 | printk("\n"); | |
1488 | } | |
1489 | } | |
1490 | ||
32f71aff | 1491 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1492 | { |
1493 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1494 | u64 icr; |
1da177e4 LT |
1495 | |
1496 | if (apic_verbosity == APIC_QUIET) | |
1497 | return; | |
1498 | ||
1499 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1500 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1501 | v = apic_read(APIC_ID); |
05f2d12c | 1502 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
4c9961d5 | 1503 | GET_APIC_ID(v)); |
1da177e4 LT |
1504 | v = apic_read(APIC_LVR); |
1505 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1506 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1507 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1508 | |
1509 | v = apic_read(APIC_TASKPRI); | |
1510 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1511 | ||
1512 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1513 | v = apic_read(APIC_ARBPRI); | |
1514 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1515 | v & APIC_ARBPRI_MASK); | |
1516 | v = apic_read(APIC_PROCPRI); | |
1517 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1518 | } | |
1519 | ||
1520 | v = apic_read(APIC_EOI); | |
1521 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1522 | v = apic_read(APIC_RRR); | |
1523 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1524 | v = apic_read(APIC_LDR); | |
1525 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1526 | v = apic_read(APIC_DFR); | |
1527 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1528 | v = apic_read(APIC_SPIV); | |
1529 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1530 | ||
1531 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1532 | print_APIC_bitfield(APIC_ISR); | |
1533 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1534 | print_APIC_bitfield(APIC_TMR); | |
1535 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1536 | print_APIC_bitfield(APIC_IRR); | |
1537 | ||
1538 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1539 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1540 | apic_write(APIC_ESR, 0); | |
1541 | v = apic_read(APIC_ESR); | |
1542 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1543 | } | |
1544 | ||
7ab6af7a HS |
1545 | icr = apic_icr_read(); |
1546 | printk(KERN_DEBUG "... APIC ICR: %08x\n", icr); | |
1547 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32); | |
1da177e4 LT |
1548 | |
1549 | v = apic_read(APIC_LVTT); | |
1550 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1551 | ||
1552 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1553 | v = apic_read(APIC_LVTPC); | |
1554 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1555 | } | |
1556 | v = apic_read(APIC_LVT0); | |
1557 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1558 | v = apic_read(APIC_LVT1); | |
1559 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1560 | ||
1561 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1562 | v = apic_read(APIC_LVTERR); | |
1563 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1564 | } | |
1565 | ||
1566 | v = apic_read(APIC_TMICT); | |
1567 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1568 | v = apic_read(APIC_TMCCT); | |
1569 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1570 | v = apic_read(APIC_TDCR); | |
1571 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1572 | printk("\n"); | |
1573 | } | |
1574 | ||
32f71aff | 1575 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1576 | { |
15c8b6c1 | 1577 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1578 | } |
1579 | ||
32f71aff | 1580 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1581 | { |
1da177e4 LT |
1582 | unsigned int v; |
1583 | unsigned long flags; | |
1584 | ||
1585 | if (apic_verbosity == APIC_QUIET) | |
1586 | return; | |
1587 | ||
1588 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1589 | ||
1590 | spin_lock_irqsave(&i8259A_lock, flags); | |
1591 | ||
1592 | v = inb(0xa1) << 8 | inb(0x21); | |
1593 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1594 | ||
1595 | v = inb(0xa0) << 8 | inb(0x20); | |
1596 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1597 | ||
36062448 PC |
1598 | outb(0x0b, 0xa0); |
1599 | outb(0x0b, 0x20); | |
1da177e4 | 1600 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1601 | outb(0x0a, 0xa0); |
1602 | outb(0x0a, 0x20); | |
1da177e4 LT |
1603 | |
1604 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1605 | ||
1606 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1607 | ||
1608 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1609 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1610 | } | |
1611 | ||
32f71aff MR |
1612 | __apicdebuginit(int) print_all_ICs(void) |
1613 | { | |
1614 | print_PIC(); | |
1615 | print_all_local_APICs(); | |
1616 | print_IO_APIC(); | |
1617 | ||
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | fs_initcall(print_all_ICs); | |
1622 | ||
1da177e4 LT |
1623 | |
1624 | static void __init enable_IO_APIC(void) | |
1625 | { | |
1626 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1627 | int i8259_apic, i8259_pin; |
1628 | int i, apic; | |
1da177e4 LT |
1629 | unsigned long flags; |
1630 | ||
1da177e4 LT |
1631 | if (!pirqs_enabled) |
1632 | for (i = 0; i < MAX_PIRQS; i++) | |
1633 | pirq_entries[i] = -1; | |
1634 | ||
1635 | /* | |
1636 | * The number of IO-APIC IRQ registers (== #pins): | |
1637 | */ | |
fcfd636a | 1638 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1639 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1640 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1641 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1642 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1643 | } | |
36062448 | 1644 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1645 | int pin; |
1646 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1647 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1648 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1649 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1650 | |
1651 | ||
1652 | /* If the interrupt line is enabled and in ExtInt mode | |
1653 | * I have found the pin where the i8259 is connected. | |
1654 | */ | |
1655 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1656 | ioapic_i8259.apic = apic; | |
1657 | ioapic_i8259.pin = pin; | |
1658 | goto found_i8259; | |
1659 | } | |
1660 | } | |
1661 | } | |
1662 | found_i8259: | |
1663 | /* Look to see what if the MP table has reported the ExtINT */ | |
1664 | /* If we could not find the appropriate pin by looking at the ioapic | |
1665 | * the i8259 probably is not connected the ioapic but give the | |
1666 | * mptable a chance anyway. | |
1667 | */ | |
1668 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1669 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1670 | /* Trust the MP table if nothing is setup in the hardware */ | |
1671 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1672 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1673 | ioapic_i8259.pin = i8259_pin; | |
1674 | ioapic_i8259.apic = i8259_apic; | |
1675 | } | |
1676 | /* Complain if the MP table and the hardware disagree */ | |
1677 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1678 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1679 | { | |
1680 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1681 | } |
1682 | ||
1683 | /* | |
1684 | * Do not trust the IO-APIC being empty at bootup | |
1685 | */ | |
1686 | clear_IO_APIC(); | |
1687 | } | |
1688 | ||
1689 | /* | |
1690 | * Not an __init, needed by the reboot code | |
1691 | */ | |
1692 | void disable_IO_APIC(void) | |
1693 | { | |
1694 | /* | |
1695 | * Clear the IO-APIC before rebooting: | |
1696 | */ | |
1697 | clear_IO_APIC(); | |
1698 | ||
650927ef | 1699 | /* |
0b968d23 | 1700 | * If the i8259 is routed through an IOAPIC |
650927ef | 1701 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1702 | * so legacy interrupts can be delivered. |
650927ef | 1703 | */ |
fcfd636a | 1704 | if (ioapic_i8259.pin != -1) { |
650927ef | 1705 | struct IO_APIC_route_entry entry; |
650927ef EB |
1706 | |
1707 | memset(&entry, 0, sizeof(entry)); | |
1708 | entry.mask = 0; /* Enabled */ | |
1709 | entry.trigger = 0; /* Edge */ | |
1710 | entry.irr = 0; | |
1711 | entry.polarity = 0; /* High */ | |
1712 | entry.delivery_status = 0; | |
1713 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1714 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1715 | entry.vector = 0; |
d83e94ac | 1716 | entry.dest = read_apic_id(); |
650927ef EB |
1717 | |
1718 | /* | |
1719 | * Add it to the IO-APIC irq-routing table: | |
1720 | */ | |
cf4c6a2f | 1721 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1722 | } |
fcfd636a | 1723 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1724 | } |
1725 | ||
1726 | /* | |
1727 | * function to set the IO-APIC physical IDs based on the | |
1728 | * values stored in the MPC table. | |
1729 | * | |
1730 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1731 | */ | |
1732 | ||
1da177e4 LT |
1733 | static void __init setup_ioapic_ids_from_mpc(void) |
1734 | { | |
1735 | union IO_APIC_reg_00 reg_00; | |
1736 | physid_mask_t phys_id_present_map; | |
1737 | int apic; | |
1738 | int i; | |
1739 | unsigned char old_id; | |
1740 | unsigned long flags; | |
1741 | ||
a4dbc34d | 1742 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1743 | return; |
d49c4288 | 1744 | |
ca05fea6 NP |
1745 | /* |
1746 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1747 | * no meaning without the serial APIC bus. | |
1748 | */ | |
7c5c1e42 SL |
1749 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1750 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1751 | return; |
1da177e4 LT |
1752 | /* |
1753 | * This is broken; anything with a real cpu count has to | |
1754 | * circumvent this idiocy regardless. | |
1755 | */ | |
1756 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1757 | ||
1758 | /* | |
1759 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1760 | */ | |
1761 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1762 | ||
1763 | /* Read the register 0 value */ | |
1764 | spin_lock_irqsave(&ioapic_lock, flags); | |
1765 | reg_00.raw = io_apic_read(apic, 0); | |
1766 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1767 | |
ec2cd0a2 | 1768 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1769 | |
ec2cd0a2 | 1770 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1771 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1772 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1773 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1774 | reg_00.bits.ID); | |
ec2cd0a2 | 1775 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1776 | } |
1777 | ||
1da177e4 LT |
1778 | /* |
1779 | * Sanity check, is the ID really free? Every APIC in a | |
1780 | * system must have a unique ID or we get lots of nice | |
1781 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1782 | */ | |
1783 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1784 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1785 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1786 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1787 | for (i = 0; i < get_physical_broadcast(); i++) |
1788 | if (!physid_isset(i, phys_id_present_map)) | |
1789 | break; | |
1790 | if (i >= get_physical_broadcast()) | |
1791 | panic("Max APIC ID exceeded!\n"); | |
1792 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1793 | i); | |
1794 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1795 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1796 | } else { |
1797 | physid_mask_t tmp; | |
ec2cd0a2 | 1798 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1799 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1800 | "phys_id_present_map\n", | |
ec2cd0a2 | 1801 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1802 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1803 | } | |
1804 | ||
1805 | ||
1806 | /* | |
1807 | * We need to adjust the IRQ routing table | |
1808 | * if the ID changed. | |
1809 | */ | |
ec2cd0a2 | 1810 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1811 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1812 | if (mp_irqs[i].mp_dstapic == old_id) |
1813 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1814 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1815 | |
1816 | /* | |
1817 | * Read the right value from the MPC table and | |
1818 | * write it into the ID register. | |
36062448 | 1819 | */ |
1da177e4 LT |
1820 | apic_printk(APIC_VERBOSE, KERN_INFO |
1821 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1822 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1823 | |
ec2cd0a2 | 1824 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1825 | spin_lock_irqsave(&ioapic_lock, flags); |
1826 | io_apic_write(apic, 0, reg_00.raw); | |
1827 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1828 | ||
1829 | /* | |
1830 | * Sanity check | |
1831 | */ | |
1832 | spin_lock_irqsave(&ioapic_lock, flags); | |
1833 | reg_00.raw = io_apic_read(apic, 0); | |
1834 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1835 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1836 | printk("could not set ID!\n"); |
1837 | else | |
1838 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1839 | } | |
1840 | } | |
1da177e4 | 1841 | |
7ce0bcfd | 1842 | int no_timer_check __initdata; |
8542b200 ZA |
1843 | |
1844 | static int __init notimercheck(char *s) | |
1845 | { | |
1846 | no_timer_check = 1; | |
1847 | return 1; | |
1848 | } | |
1849 | __setup("no_timer_check", notimercheck); | |
1850 | ||
1da177e4 LT |
1851 | /* |
1852 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1853 | * about the timer IRQ. We do the following to work around the situation: | |
1854 | * | |
1855 | * - timer IRQ defaults to IO-APIC IRQ | |
1856 | * - if this function detects that timer IRQs are defunct, then we fall | |
1857 | * back to ISA timer IRQs | |
1858 | */ | |
f0a7a5c9 | 1859 | static int __init timer_irq_works(void) |
1da177e4 LT |
1860 | { |
1861 | unsigned long t1 = jiffies; | |
4aae0702 | 1862 | unsigned long flags; |
1da177e4 | 1863 | |
8542b200 ZA |
1864 | if (no_timer_check) |
1865 | return 1; | |
1866 | ||
4aae0702 | 1867 | local_save_flags(flags); |
1da177e4 LT |
1868 | local_irq_enable(); |
1869 | /* Let ten ticks pass... */ | |
1870 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1871 | local_irq_restore(flags); |
1da177e4 LT |
1872 | |
1873 | /* | |
1874 | * Expect a few ticks at least, to be sure some possible | |
1875 | * glue logic does not lock up after one or two first | |
1876 | * ticks in a non-ExtINT mode. Also the local APIC | |
1877 | * might have cached one ExtINT interrupt. Finally, at | |
1878 | * least one tick may be lost due to delays. | |
1879 | */ | |
1d16b53e | 1880 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1881 | return 1; |
1882 | ||
1883 | return 0; | |
1884 | } | |
1885 | ||
1886 | /* | |
1887 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1888 | * number of pending IRQ events unhandled. These cases are very rare, | |
1889 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1890 | * better to do it this way as thus we do not have to be aware of | |
1891 | * 'pending' interrupts in the IRQ path, except at this point. | |
1892 | */ | |
1893 | /* | |
1894 | * Edge triggered needs to resend any interrupt | |
1895 | * that was delayed but this is now handled in the device | |
1896 | * independent code. | |
1897 | */ | |
1898 | ||
1899 | /* | |
f5b9ed7a IM |
1900 | * Startup quirk: |
1901 | * | |
1da177e4 LT |
1902 | * Starting up a edge-triggered IO-APIC interrupt is |
1903 | * nasty - we need to make sure that we get the edge. | |
1904 | * If it is already asserted for some reason, we need | |
1905 | * return 1 to indicate that is was pending. | |
1906 | * | |
1907 | * This is not complete - we should be able to fake | |
1908 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1909 | * |
1910 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1911 | */ |
f5b9ed7a | 1912 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1913 | { |
1914 | int was_pending = 0; | |
1915 | unsigned long flags; | |
1916 | ||
1917 | spin_lock_irqsave(&ioapic_lock, flags); | |
1918 | if (irq < 16) { | |
1919 | disable_8259A_irq(irq); | |
1920 | if (i8259A_irq_pending(irq)) | |
1921 | was_pending = 1; | |
1922 | } | |
1923 | __unmask_IO_APIC_irq(irq); | |
1924 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1925 | ||
1926 | return was_pending; | |
1927 | } | |
1928 | ||
497c9a19 | 1929 | static void irq_complete_move(unsigned int irq); |
f5b9ed7a | 1930 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1931 | { |
497c9a19 | 1932 | irq_complete_move(irq); |
ace80ab7 | 1933 | move_native_irq(irq); |
1da177e4 LT |
1934 | ack_APIC_irq(); |
1935 | } | |
1936 | ||
f5b9ed7a | 1937 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1938 | { |
1939 | unsigned long v; | |
1940 | int i; | |
1941 | ||
497c9a19 | 1942 | irq_complete_move(irq); |
ace80ab7 | 1943 | move_native_irq(irq); |
1da177e4 LT |
1944 | /* |
1945 | * It appears there is an erratum which affects at least version 0x11 | |
1946 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1947 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1948 | * erroneously delivered as edge-triggered one but the respective IRR | |
1949 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1950 | * message but it will never arrive and further interrupts are blocked | |
1951 | * from the source. The exact reason is so far unknown, but the | |
1952 | * phenomenon was observed when two consecutive interrupt requests | |
1953 | * from a given source get delivered to the same CPU and the source is | |
1954 | * temporarily disabled in between. | |
1955 | * | |
1956 | * A workaround is to simulate an EOI message manually. We achieve it | |
1957 | * by setting the trigger mode to edge and then to level when the edge | |
1958 | * trigger mode gets detected in the TMR of a local APIC for a | |
1959 | * level-triggered interrupt. We mask the source for the time of the | |
1960 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1961 | * The idea is from Manfred Spraul. --macro | |
1962 | */ | |
a1420f39 | 1963 | i = irq_cfg(irq)->vector; |
1da177e4 LT |
1964 | |
1965 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1966 | ||
1967 | ack_APIC_irq(); | |
1968 | ||
1969 | if (!(v & (1 << (i & 0x1f)))) { | |
1970 | atomic_inc(&irq_mis_count); | |
1971 | spin_lock(&ioapic_lock); | |
1972 | __mask_and_edge_IO_APIC_irq(irq); | |
1973 | __unmask_and_level_IO_APIC_irq(irq); | |
1974 | spin_unlock(&ioapic_lock); | |
1975 | } | |
1976 | } | |
1977 | ||
ace80ab7 | 1978 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1979 | { |
a1420f39 | 1980 | send_IPI_self(irq_cfg(irq)->vector); |
c0ad90a3 IM |
1981 | |
1982 | return 1; | |
1983 | } | |
1984 | ||
497c9a19 YL |
1985 | #ifdef CONFIG_SMP |
1986 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
1987 | { | |
1988 | unsigned vector, me; | |
1989 | ack_APIC_irq(); | |
1990 | irq_enter(); | |
1991 | ||
1992 | me = smp_processor_id(); | |
1993 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
1994 | unsigned int irq; | |
1995 | struct irq_desc *desc; | |
1996 | struct irq_cfg *cfg; | |
1997 | irq = __get_cpu_var(vector_irq)[vector]; | |
1998 | ||
1999 | desc = irq_to_desc(irq); | |
2000 | if (!desc) | |
2001 | continue; | |
2002 | ||
2003 | cfg = irq_cfg(irq); | |
2004 | spin_lock(&desc->lock); | |
2005 | if (!cfg->move_cleanup_count) | |
2006 | goto unlock; | |
2007 | ||
2008 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2009 | goto unlock; | |
2010 | ||
2011 | __get_cpu_var(vector_irq)[vector] = -1; | |
2012 | cfg->move_cleanup_count--; | |
2013 | unlock: | |
2014 | spin_unlock(&desc->lock); | |
2015 | } | |
2016 | ||
2017 | irq_exit(); | |
2018 | } | |
2019 | ||
2020 | static void irq_complete_move(unsigned int irq) | |
2021 | { | |
2022 | struct irq_cfg *cfg = irq_cfg(irq); | |
2023 | unsigned vector, me; | |
2024 | ||
2025 | if (likely(!cfg->move_in_progress)) | |
2026 | return; | |
2027 | ||
2028 | vector = ~get_irq_regs()->orig_ax; | |
2029 | me = smp_processor_id(); | |
2030 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2031 | cpumask_t cleanup_mask; | |
2032 | ||
2033 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2034 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2035 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2036 | cfg->move_in_progress = 0; | |
2037 | } | |
2038 | } | |
2039 | #else | |
2040 | static inline void irq_complete_move(unsigned int irq) {} | |
2041 | #endif | |
2042 | ||
f5b9ed7a IM |
2043 | static struct irq_chip ioapic_chip __read_mostly = { |
2044 | .name = "IO-APIC", | |
ace80ab7 EB |
2045 | .startup = startup_ioapic_irq, |
2046 | .mask = mask_IO_APIC_irq, | |
2047 | .unmask = unmask_IO_APIC_irq, | |
2048 | .ack = ack_ioapic_irq, | |
2049 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2050 | #ifdef CONFIG_SMP |
ace80ab7 | 2051 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2052 | #endif |
ace80ab7 | 2053 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2054 | }; |
2055 | ||
1da177e4 LT |
2056 | |
2057 | static inline void init_IO_APIC_traps(void) | |
2058 | { | |
2059 | int irq; | |
08678b08 | 2060 | struct irq_desc *desc; |
da51a821 | 2061 | struct irq_cfg *cfg; |
1da177e4 LT |
2062 | |
2063 | /* | |
2064 | * NOTE! The local APIC isn't very good at handling | |
2065 | * multiple interrupts at the same interrupt level. | |
2066 | * As the interrupt level is determined by taking the | |
2067 | * vector number and shifting that right by 4, we | |
2068 | * want to spread these out a bit so that they don't | |
2069 | * all fall in the same interrupt level. | |
2070 | * | |
2071 | * Also, we've got to be careful not to trash gate | |
2072 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2073 | */ | |
da51a821 YL |
2074 | for_each_irq_cfg(cfg) { |
2075 | irq = cfg->irq; | |
2076 | if (IO_APIC_IRQ(irq) && !cfg->vector) { | |
1da177e4 LT |
2077 | /* |
2078 | * Hmm.. We don't have an entry for this, | |
2079 | * so default to an old-fashioned 8259 | |
2080 | * interrupt if we can.. | |
2081 | */ | |
2082 | if (irq < 16) | |
2083 | make_8259A_irq(irq); | |
08678b08 YL |
2084 | else { |
2085 | desc = irq_to_desc(irq); | |
1da177e4 | 2086 | /* Strange. Oh, well.. */ |
08678b08 YL |
2087 | desc->chip = &no_irq_chip; |
2088 | } | |
1da177e4 LT |
2089 | } |
2090 | } | |
2091 | } | |
2092 | ||
f5b9ed7a IM |
2093 | /* |
2094 | * The local APIC irq-chip implementation: | |
2095 | */ | |
1da177e4 | 2096 | |
c88ac1df | 2097 | static void ack_lapic_irq(unsigned int irq) |
f5b9ed7a IM |
2098 | { |
2099 | ack_APIC_irq(); | |
1da177e4 LT |
2100 | } |
2101 | ||
36062448 | 2102 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2103 | { |
2104 | unsigned long v; | |
2105 | ||
2106 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2107 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2108 | } |
2109 | ||
36062448 | 2110 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2111 | { |
f5b9ed7a | 2112 | unsigned long v; |
1da177e4 | 2113 | |
f5b9ed7a | 2114 | v = apic_read(APIC_LVT0); |
593f4a78 | 2115 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2116 | } |
1da177e4 | 2117 | |
f5b9ed7a | 2118 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2119 | .name = "local-APIC", |
f5b9ed7a IM |
2120 | .mask = mask_lapic_irq, |
2121 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2122 | .ack = ack_lapic_irq, |
1da177e4 LT |
2123 | }; |
2124 | ||
497c9a19 | 2125 | static void lapic_register_intr(int irq) |
c88ac1df | 2126 | { |
08678b08 YL |
2127 | struct irq_desc *desc; |
2128 | ||
2129 | desc = irq_to_desc(irq); | |
2130 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2131 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2132 | "edge"); | |
c88ac1df MR |
2133 | } |
2134 | ||
e9427101 | 2135 | static void __init setup_nmi(void) |
1da177e4 LT |
2136 | { |
2137 | /* | |
36062448 | 2138 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2139 | * We put the 8259A master into AEOI mode and |
2140 | * unmask on all local APICs LVT0 as NMI. | |
2141 | * | |
2142 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2143 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2144 | * the NMI handler or the timer interrupt. | |
36062448 | 2145 | */ |
1da177e4 LT |
2146 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2147 | ||
e9427101 | 2148 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2149 | |
2150 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2151 | } | |
2152 | ||
2153 | /* | |
2154 | * This looks a bit hackish but it's about the only one way of sending | |
2155 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2156 | * not support the ExtINT mode, unfortunately. We need to send these | |
2157 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2158 | * 8259A interrupt line asserted until INTA. --macro | |
2159 | */ | |
28acf285 | 2160 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2161 | { |
fcfd636a | 2162 | int apic, pin, i; |
1da177e4 LT |
2163 | struct IO_APIC_route_entry entry0, entry1; |
2164 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2165 | |
fcfd636a | 2166 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2167 | if (pin == -1) { |
2168 | WARN_ON_ONCE(1); | |
2169 | return; | |
2170 | } | |
fcfd636a | 2171 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2172 | if (apic == -1) { |
2173 | WARN_ON_ONCE(1); | |
1da177e4 | 2174 | return; |
956fb531 | 2175 | } |
1da177e4 | 2176 | |
cf4c6a2f | 2177 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2178 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2179 | |
2180 | memset(&entry1, 0, sizeof(entry1)); | |
2181 | ||
2182 | entry1.dest_mode = 0; /* physical delivery */ | |
2183 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2184 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2185 | entry1.delivery_mode = dest_ExtINT; |
2186 | entry1.polarity = entry0.polarity; | |
2187 | entry1.trigger = 0; | |
2188 | entry1.vector = 0; | |
2189 | ||
cf4c6a2f | 2190 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2191 | |
2192 | save_control = CMOS_READ(RTC_CONTROL); | |
2193 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2194 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2195 | RTC_FREQ_SELECT); | |
2196 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2197 | ||
2198 | i = 100; | |
2199 | while (i-- > 0) { | |
2200 | mdelay(10); | |
2201 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2202 | i -= 10; | |
2203 | } | |
2204 | ||
2205 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2206 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2207 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2208 | |
cf4c6a2f | 2209 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2210 | } |
2211 | ||
2212 | /* | |
2213 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2214 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2215 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2216 | * fanatically on his truly buggy board. | |
2217 | */ | |
8542b200 | 2218 | static inline void __init check_timer(void) |
1da177e4 | 2219 | { |
497c9a19 | 2220 | struct irq_cfg *cfg = irq_cfg(0); |
fcfd636a | 2221 | int apic1, pin1, apic2, pin2; |
691874fa | 2222 | int no_pin1 = 0; |
6e908947 | 2223 | unsigned int ver; |
4aae0702 IM |
2224 | unsigned long flags; |
2225 | ||
2226 | local_irq_save(flags); | |
d4d25dec | 2227 | |
6e908947 IM |
2228 | ver = apic_read(APIC_LVR); |
2229 | ver = GET_APIC_VERSION(ver); | |
2230 | ||
1da177e4 LT |
2231 | /* |
2232 | * get/set the timer IRQ vector: | |
2233 | */ | |
2234 | disable_8259A_irq(0); | |
497c9a19 | 2235 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2236 | |
2237 | /* | |
d11d5794 MR |
2238 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2239 | * wire has to be disabled in the local APIC. Also | |
2240 | * timer interrupts need to be acknowledged manually in | |
2241 | * the 8259A for the i82489DX when using the NMI | |
2242 | * watchdog as that APIC treats NMIs as level-triggered. | |
2243 | * The AEOI mode will finish them in the 8259A | |
2244 | * automatically. | |
1da177e4 | 2245 | */ |
593f4a78 | 2246 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2247 | init_8259A(1); |
d11d5794 | 2248 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2249 | |
fcfd636a EB |
2250 | pin1 = find_isa_irq_pin(0, mp_INT); |
2251 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2252 | pin2 = ioapic_i8259.pin; | |
2253 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2254 | |
49a66a0b MR |
2255 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2256 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2257 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2258 | |
691874fa MR |
2259 | /* |
2260 | * Some BIOS writers are clueless and report the ExtINTA | |
2261 | * I/O APIC input from the cascaded 8259A as the timer | |
2262 | * interrupt input. So just in case, if only one pin | |
2263 | * was found above, try it both directly and through the | |
2264 | * 8259A. | |
2265 | */ | |
2266 | if (pin1 == -1) { | |
2267 | pin1 = pin2; | |
2268 | apic1 = apic2; | |
2269 | no_pin1 = 1; | |
2270 | } else if (pin2 == -1) { | |
2271 | pin2 = pin1; | |
2272 | apic2 = apic1; | |
2273 | } | |
2274 | ||
1da177e4 LT |
2275 | if (pin1 != -1) { |
2276 | /* | |
2277 | * Ok, does IRQ0 through the IOAPIC work? | |
2278 | */ | |
691874fa MR |
2279 | if (no_pin1) { |
2280 | add_pin_to_irq(0, apic1, pin1); | |
497c9a19 | 2281 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2282 | } |
1da177e4 LT |
2283 | unmask_IO_APIC_irq(0); |
2284 | if (timer_irq_works()) { | |
2285 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2286 | setup_nmi(); |
2287 | enable_8259A_irq(0); | |
1da177e4 | 2288 | } |
66759a01 CE |
2289 | if (disable_timer_pin_1 > 0) |
2290 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2291 | goto out; |
1da177e4 | 2292 | } |
fcfd636a | 2293 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2294 | if (!no_pin1) |
49a66a0b MR |
2295 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2296 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2297 | |
49a66a0b MR |
2298 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2299 | "(IRQ0) through the 8259A ...\n"); | |
2300 | apic_printk(APIC_QUIET, KERN_INFO | |
2301 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2302 | /* |
2303 | * legacy devices should be connected to IO APIC #0 | |
2304 | */ | |
691874fa | 2305 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
497c9a19 | 2306 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2307 | unmask_IO_APIC_irq(0); |
ecd29476 | 2308 | enable_8259A_irq(0); |
1da177e4 | 2309 | if (timer_irq_works()) { |
49a66a0b | 2310 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2311 | timer_through_8259 = 1; |
1da177e4 | 2312 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2313 | disable_8259A_irq(0); |
1da177e4 | 2314 | setup_nmi(); |
60134ebe | 2315 | enable_8259A_irq(0); |
1da177e4 | 2316 | } |
4aae0702 | 2317 | goto out; |
1da177e4 LT |
2318 | } |
2319 | /* | |
2320 | * Cleanup, just in case ... | |
2321 | */ | |
ecd29476 | 2322 | disable_8259A_irq(0); |
fcfd636a | 2323 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2324 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2325 | } |
1da177e4 LT |
2326 | |
2327 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2328 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2329 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2330 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2331 | } |
d11d5794 | 2332 | timer_ack = 0; |
1da177e4 | 2333 | |
49a66a0b MR |
2334 | apic_printk(APIC_QUIET, KERN_INFO |
2335 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2336 | |
497c9a19 YL |
2337 | lapic_register_intr(0); |
2338 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ | |
1da177e4 LT |
2339 | enable_8259A_irq(0); |
2340 | ||
2341 | if (timer_irq_works()) { | |
49a66a0b | 2342 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2343 | goto out; |
1da177e4 | 2344 | } |
e67465f1 | 2345 | disable_8259A_irq(0); |
497c9a19 | 2346 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2347 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2348 | |
49a66a0b MR |
2349 | apic_printk(APIC_QUIET, KERN_INFO |
2350 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2351 | |
1da177e4 LT |
2352 | init_8259A(0); |
2353 | make_8259A_irq(0); | |
593f4a78 | 2354 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2355 | |
2356 | unlock_ExtINT_logic(); | |
2357 | ||
2358 | if (timer_irq_works()) { | |
49a66a0b | 2359 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2360 | goto out; |
1da177e4 | 2361 | } |
49a66a0b | 2362 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2363 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2364 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2365 | out: |
2366 | local_irq_restore(flags); | |
1da177e4 LT |
2367 | } |
2368 | ||
2369 | /* | |
af174783 MR |
2370 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2371 | * to devices. However there may be an I/O APIC pin available for | |
2372 | * this interrupt regardless. The pin may be left unconnected, but | |
2373 | * typically it will be reused as an ExtINT cascade interrupt for | |
2374 | * the master 8259A. In the MPS case such a pin will normally be | |
2375 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2376 | * there is no provision for ExtINT interrupts, and in the absence | |
2377 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2378 | * interrupt, that is edge-triggered and unmasked by default. We | |
2379 | * used to do this, but it caused problems on some systems because | |
2380 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2381 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2382 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2383 | * the I/O APIC in all cases now. No actual device should request | |
2384 | * it anyway. --macro | |
1da177e4 LT |
2385 | */ |
2386 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2387 | ||
2388 | void __init setup_IO_APIC(void) | |
2389 | { | |
2390 | enable_IO_APIC(); | |
2391 | ||
af174783 | 2392 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
2393 | |
2394 | printk("ENABLING IO-APIC IRQs\n"); | |
2395 | ||
2396 | /* | |
2397 | * Set up IO-APIC IRQ routing. | |
2398 | */ | |
2399 | if (!acpi_ioapic) | |
2400 | setup_ioapic_ids_from_mpc(); | |
2401 | sync_Arb_IDs(); | |
2402 | setup_IO_APIC_irqs(); | |
2403 | init_IO_APIC_traps(); | |
1e4c85f9 | 2404 | check_timer(); |
1da177e4 LT |
2405 | } |
2406 | ||
2407 | /* | |
2408 | * Called after all the initialization is done. If we didnt find any | |
2409 | * APIC bugs then we can allow the modify fast path | |
2410 | */ | |
36062448 | 2411 | |
1da177e4 LT |
2412 | static int __init io_apic_bug_finalize(void) |
2413 | { | |
36062448 | 2414 | if (sis_apic_bug == -1) |
1da177e4 LT |
2415 | sis_apic_bug = 0; |
2416 | return 0; | |
2417 | } | |
2418 | ||
2419 | late_initcall(io_apic_bug_finalize); | |
2420 | ||
2421 | struct sysfs_ioapic_data { | |
2422 | struct sys_device dev; | |
2423 | struct IO_APIC_route_entry entry[0]; | |
2424 | }; | |
36062448 | 2425 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2426 | |
438510f6 | 2427 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2428 | { |
2429 | struct IO_APIC_route_entry *entry; | |
2430 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2431 | int i; |
36062448 | 2432 | |
1da177e4 LT |
2433 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2434 | entry = data->entry; | |
36062448 | 2435 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2436 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2437 | |
2438 | return 0; | |
2439 | } | |
2440 | ||
2441 | static int ioapic_resume(struct sys_device *dev) | |
2442 | { | |
2443 | struct IO_APIC_route_entry *entry; | |
2444 | struct sysfs_ioapic_data *data; | |
2445 | unsigned long flags; | |
2446 | union IO_APIC_reg_00 reg_00; | |
2447 | int i; | |
36062448 | 2448 | |
1da177e4 LT |
2449 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2450 | entry = data->entry; | |
2451 | ||
2452 | spin_lock_irqsave(&ioapic_lock, flags); | |
2453 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2454 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2455 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2456 | io_apic_write(dev->id, 0, reg_00.raw); |
2457 | } | |
1da177e4 | 2458 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2459 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2460 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2461 | |
2462 | return 0; | |
2463 | } | |
2464 | ||
2465 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2466 | .name = "ioapic", |
1da177e4 LT |
2467 | .suspend = ioapic_suspend, |
2468 | .resume = ioapic_resume, | |
2469 | }; | |
2470 | ||
2471 | static int __init ioapic_init_sysfs(void) | |
2472 | { | |
36062448 | 2473 | struct sys_device *dev; |
1da177e4 LT |
2474 | int i, size, error = 0; |
2475 | ||
2476 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2477 | if (error) | |
2478 | return error; | |
2479 | ||
36062448 PC |
2480 | for (i = 0; i < nr_ioapics; i++) { |
2481 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2482 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2483 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2484 | if (!mp_ioapic_data[i]) { |
2485 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2486 | continue; | |
2487 | } | |
1da177e4 | 2488 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2489 | dev->id = i; |
1da177e4 LT |
2490 | dev->cls = &ioapic_sysdev_class; |
2491 | error = sysdev_register(dev); | |
2492 | if (error) { | |
2493 | kfree(mp_ioapic_data[i]); | |
2494 | mp_ioapic_data[i] = NULL; | |
2495 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2496 | continue; | |
2497 | } | |
2498 | } | |
2499 | ||
2500 | return 0; | |
2501 | } | |
2502 | ||
2503 | device_initcall(ioapic_init_sysfs); | |
2504 | ||
3fc471ed | 2505 | /* |
95d77884 | 2506 | * Dynamic irq allocate and deallocation |
3fc471ed | 2507 | */ |
199751d7 | 2508 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 2509 | { |
ace80ab7 | 2510 | /* Allocate an unused irq */ |
497c9a19 | 2511 | unsigned int irq, new; |
3fc471ed | 2512 | unsigned long flags; |
da51a821 | 2513 | struct irq_cfg *cfg_new; |
3fc471ed | 2514 | |
497c9a19 | 2515 | #ifndef CONFIG_HAVE_SPARSE_IRQ |
199751d7 YL |
2516 | /* only can use bus/dev/fn.. when per_cpu vector is used */ |
2517 | irq_want = nr_irqs - 1; | |
497c9a19 | 2518 | #endif |
199751d7 YL |
2519 | |
2520 | irq = 0; | |
ace80ab7 | 2521 | spin_lock_irqsave(&vector_lock, flags); |
199751d7 | 2522 | for (new = (nr_irqs - 1); new > 0; new--) { |
ace80ab7 EB |
2523 | if (platform_legacy_irq(new)) |
2524 | continue; | |
da51a821 YL |
2525 | cfg_new = irq_cfg(new); |
2526 | if (cfg_new && cfg_new->vector != 0) | |
ace80ab7 | 2527 | continue; |
da51a821 YL |
2528 | if (!cfg_new) |
2529 | cfg_new = irq_cfg_alloc(new); | |
497c9a19 | 2530 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
ace80ab7 EB |
2531 | irq = new; |
2532 | break; | |
2533 | } | |
2534 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2535 | |
199751d7 | 2536 | if (irq > 0) { |
3fc471ed EB |
2537 | dynamic_irq_init(irq); |
2538 | } | |
2539 | return irq; | |
2540 | } | |
2541 | ||
199751d7 YL |
2542 | int create_irq(void) |
2543 | { | |
2544 | return create_irq_nr(nr_irqs - 1); | |
2545 | } | |
2546 | ||
3fc471ed EB |
2547 | void destroy_irq(unsigned int irq) |
2548 | { | |
2549 | unsigned long flags; | |
3fc471ed EB |
2550 | |
2551 | dynamic_irq_cleanup(irq); | |
2552 | ||
2553 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 2554 | __clear_irq_vector(irq); |
3fc471ed EB |
2555 | spin_unlock_irqrestore(&vector_lock, flags); |
2556 | } | |
3fc471ed | 2557 | |
2d3fcc1c | 2558 | /* |
27b46d76 | 2559 | * MSI message composition |
2d3fcc1c EB |
2560 | */ |
2561 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2562 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2563 | { |
497c9a19 YL |
2564 | struct irq_cfg *cfg; |
2565 | int err; | |
2d3fcc1c | 2566 | unsigned dest; |
497c9a19 | 2567 | cpumask_t tmp; |
2d3fcc1c | 2568 | |
497c9a19 YL |
2569 | tmp = TARGET_CPUS; |
2570 | err = assign_irq_vector(irq, tmp); | |
2571 | if (err) | |
2572 | return err; | |
2d3fcc1c | 2573 | |
497c9a19 YL |
2574 | cfg = irq_cfg(irq); |
2575 | cpus_and(tmp, cfg->domain, tmp); | |
2576 | dest = cpu_mask_to_apicid(tmp); | |
2577 | ||
2578 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2579 | msg->address_lo = | |
2580 | MSI_ADDR_BASE_LO | | |
2581 | ((INT_DEST_MODE == 0) ? | |
2582 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2583 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2584 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2585 | MSI_ADDR_REDIRECTION_CPU: | |
2586 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2587 | MSI_ADDR_DEST_ID(dest); | |
2588 | ||
2589 | msg->data = | |
2590 | MSI_DATA_TRIGGER_EDGE | | |
2591 | MSI_DATA_LEVEL_ASSERT | | |
2592 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2593 | MSI_DATA_DELIVERY_FIXED: | |
2594 | MSI_DATA_DELIVERY_LOWPRI) | | |
2595 | MSI_DATA_VECTOR(cfg->vector); | |
2596 | ||
2597 | return err; | |
2d3fcc1c EB |
2598 | } |
2599 | ||
3b7d1921 EB |
2600 | #ifdef CONFIG_SMP |
2601 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2602 | { |
497c9a19 | 2603 | struct irq_cfg *cfg; |
3b7d1921 EB |
2604 | struct msi_msg msg; |
2605 | unsigned int dest; | |
2606 | cpumask_t tmp; | |
3b7d1921 EB |
2607 | |
2608 | cpus_and(tmp, mask, cpu_online_map); | |
2609 | if (cpus_empty(tmp)) | |
497c9a19 | 2610 | return; |
2d3fcc1c | 2611 | |
497c9a19 | 2612 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 2613 | return; |
2d3fcc1c | 2614 | |
497c9a19 YL |
2615 | cfg = irq_cfg(irq); |
2616 | cpus_and(tmp, cfg->domain, mask); | |
2617 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 EB |
2618 | |
2619 | read_msi_msg(irq, &msg); | |
2620 | ||
2621 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 2622 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
2623 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
2624 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2625 | ||
2626 | write_msi_msg(irq, &msg); | |
199751d7 | 2627 | irq_to_desc(irq)->affinity = mask; |
2d3fcc1c | 2628 | } |
3b7d1921 | 2629 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2630 | |
3b7d1921 EB |
2631 | /* |
2632 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2633 | * which implement the MSI or MSI-X Capability Structure. | |
2634 | */ | |
2635 | static struct irq_chip msi_chip = { | |
2636 | .name = "PCI-MSI", | |
2637 | .unmask = unmask_msi_irq, | |
2638 | .mask = mask_msi_irq, | |
2639 | .ack = ack_ioapic_irq, | |
2640 | #ifdef CONFIG_SMP | |
2641 | .set_affinity = set_msi_irq_affinity, | |
2642 | #endif | |
2643 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2644 | }; |
2645 | ||
199751d7 YL |
2646 | static unsigned int build_irq_for_pci_dev(struct pci_dev *dev) |
2647 | { | |
2648 | unsigned int irq; | |
2649 | ||
2650 | irq = dev->bus->number; | |
2651 | irq <<= 8; | |
2652 | irq |= dev->devfn; | |
2653 | irq <<= 12; | |
2654 | ||
2655 | return irq; | |
2656 | } | |
2657 | ||
f7feaca7 | 2658 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2659 | { |
2660 | struct msi_msg msg; | |
f7feaca7 | 2661 | int irq, ret; |
199751d7 YL |
2662 | |
2663 | unsigned int irq_want; | |
2664 | ||
2665 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
2666 | ||
2667 | irq = create_irq_nr(irq_want); | |
2668 | ||
2669 | if (irq == 0) | |
2670 | return -1; | |
f7feaca7 | 2671 | |
3b7d1921 | 2672 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2673 | if (ret < 0) { |
2674 | destroy_irq(irq); | |
3b7d1921 | 2675 | return ret; |
f7feaca7 | 2676 | } |
3b7d1921 | 2677 | |
7fe3730d | 2678 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2679 | write_msi_msg(irq, &msg); |
2680 | ||
a460e745 IM |
2681 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2682 | "edge"); | |
3b7d1921 | 2683 | |
7fe3730d | 2684 | return 0; |
3b7d1921 EB |
2685 | } |
2686 | ||
2687 | void arch_teardown_msi_irq(unsigned int irq) | |
2688 | { | |
f7feaca7 | 2689 | destroy_irq(irq); |
3b7d1921 EB |
2690 | } |
2691 | ||
2d3fcc1c EB |
2692 | #endif /* CONFIG_PCI_MSI */ |
2693 | ||
8b955b0d EB |
2694 | /* |
2695 | * Hypertransport interrupt support | |
2696 | */ | |
2697 | #ifdef CONFIG_HT_IRQ | |
2698 | ||
2699 | #ifdef CONFIG_SMP | |
2700 | ||
497c9a19 | 2701 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 2702 | { |
ec68307c EB |
2703 | struct ht_irq_msg msg; |
2704 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2705 | |
497c9a19 | 2706 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 2707 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 2708 | |
497c9a19 | 2709 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 2710 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2711 | |
ec68307c | 2712 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2713 | } |
2714 | ||
2715 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2716 | { | |
497c9a19 | 2717 | struct irq_cfg *cfg; |
8b955b0d EB |
2718 | unsigned int dest; |
2719 | cpumask_t tmp; | |
2720 | ||
2721 | cpus_and(tmp, mask, cpu_online_map); | |
2722 | if (cpus_empty(tmp)) | |
497c9a19 | 2723 | return; |
8b955b0d | 2724 | |
497c9a19 YL |
2725 | if (assign_irq_vector(irq, mask)) |
2726 | return; | |
8b955b0d | 2727 | |
497c9a19 YL |
2728 | cfg = irq_cfg(irq); |
2729 | cpus_and(tmp, cfg->domain, mask); | |
2730 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 2731 | |
497c9a19 | 2732 | target_ht_irq(irq, dest, cfg->vector); |
199751d7 | 2733 | irq_to_desc(irq)->affinity = mask; |
8b955b0d EB |
2734 | } |
2735 | #endif | |
2736 | ||
c37e108d | 2737 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2738 | .name = "PCI-HT", |
2739 | .mask = mask_ht_irq, | |
2740 | .unmask = unmask_ht_irq, | |
2741 | .ack = ack_ioapic_irq, | |
2742 | #ifdef CONFIG_SMP | |
2743 | .set_affinity = set_ht_irq_affinity, | |
2744 | #endif | |
2745 | .retrigger = ioapic_retrigger_irq, | |
2746 | }; | |
2747 | ||
2748 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2749 | { | |
497c9a19 YL |
2750 | struct irq_cfg *cfg; |
2751 | int err; | |
2752 | cpumask_t tmp; | |
8b955b0d | 2753 | |
497c9a19 YL |
2754 | tmp = TARGET_CPUS; |
2755 | err = assign_irq_vector(irq, tmp); | |
2756 | if ( !err) { | |
ec68307c | 2757 | struct ht_irq_msg msg; |
8b955b0d | 2758 | unsigned dest; |
8b955b0d | 2759 | |
497c9a19 YL |
2760 | cfg = irq_cfg(irq); |
2761 | cpus_and(tmp, cfg->domain, tmp); | |
8b955b0d EB |
2762 | dest = cpu_mask_to_apicid(tmp); |
2763 | ||
ec68307c | 2764 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2765 | |
ec68307c EB |
2766 | msg.address_lo = |
2767 | HT_IRQ_LOW_BASE | | |
8b955b0d | 2768 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 2769 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
2770 | ((INT_DEST_MODE == 0) ? |
2771 | HT_IRQ_LOW_DM_PHYSICAL : | |
2772 | HT_IRQ_LOW_DM_LOGICAL) | | |
2773 | HT_IRQ_LOW_RQEOI_EDGE | | |
2774 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2775 | HT_IRQ_LOW_MT_FIXED : | |
2776 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2777 | HT_IRQ_LOW_IRQ_MASKED; | |
2778 | ||
ec68307c | 2779 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2780 | |
a460e745 IM |
2781 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2782 | handle_edge_irq, "edge"); | |
8b955b0d | 2783 | } |
497c9a19 | 2784 | return err; |
8b955b0d EB |
2785 | } |
2786 | #endif /* CONFIG_HT_IRQ */ | |
2787 | ||
1da177e4 | 2788 | /* -------------------------------------------------------------------------- |
36062448 | 2789 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2790 | -------------------------------------------------------------------------- */ |
2791 | ||
888ba6c6 | 2792 | #ifdef CONFIG_ACPI |
1da177e4 | 2793 | |
36062448 | 2794 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2795 | { |
2796 | union IO_APIC_reg_00 reg_00; | |
2797 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2798 | physid_mask_t tmp; | |
2799 | unsigned long flags; | |
2800 | int i = 0; | |
2801 | ||
2802 | /* | |
36062448 PC |
2803 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2804 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2805 | * supports up to 16 on one shared APIC bus. |
36062448 | 2806 | * |
1da177e4 LT |
2807 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2808 | * advantage of new APIC bus architecture. | |
2809 | */ | |
2810 | ||
2811 | if (physids_empty(apic_id_map)) | |
2812 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2813 | ||
2814 | spin_lock_irqsave(&ioapic_lock, flags); | |
2815 | reg_00.raw = io_apic_read(ioapic, 0); | |
2816 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2817 | ||
2818 | if (apic_id >= get_physical_broadcast()) { | |
2819 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2820 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2821 | apic_id = reg_00.bits.ID; | |
2822 | } | |
2823 | ||
2824 | /* | |
36062448 | 2825 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2826 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2827 | */ | |
2828 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2829 | ||
2830 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2831 | if (!check_apicid_used(apic_id_map, i)) | |
2832 | break; | |
2833 | } | |
2834 | ||
2835 | if (i == get_physical_broadcast()) | |
2836 | panic("Max apic_id exceeded!\n"); | |
2837 | ||
2838 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2839 | "trying %d\n", ioapic, apic_id, i); | |
2840 | ||
2841 | apic_id = i; | |
36062448 | 2842 | } |
1da177e4 LT |
2843 | |
2844 | tmp = apicid_to_cpu_present(apic_id); | |
2845 | physids_or(apic_id_map, apic_id_map, tmp); | |
2846 | ||
2847 | if (reg_00.bits.ID != apic_id) { | |
2848 | reg_00.bits.ID = apic_id; | |
2849 | ||
2850 | spin_lock_irqsave(&ioapic_lock, flags); | |
2851 | io_apic_write(ioapic, 0, reg_00.raw); | |
2852 | reg_00.raw = io_apic_read(ioapic, 0); | |
2853 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2854 | ||
2855 | /* Sanity check */ | |
6070f9ec AD |
2856 | if (reg_00.bits.ID != apic_id) { |
2857 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2858 | return -1; | |
2859 | } | |
1da177e4 LT |
2860 | } |
2861 | ||
2862 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2863 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2864 | ||
2865 | return apic_id; | |
2866 | } | |
2867 | ||
2868 | ||
36062448 | 2869 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2870 | { |
2871 | union IO_APIC_reg_01 reg_01; | |
2872 | unsigned long flags; | |
2873 | ||
2874 | spin_lock_irqsave(&ioapic_lock, flags); | |
2875 | reg_01.raw = io_apic_read(ioapic, 1); | |
2876 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2877 | ||
2878 | return reg_01.bits.version; | |
2879 | } | |
2880 | ||
2881 | ||
36062448 | 2882 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2883 | { |
2884 | union IO_APIC_reg_01 reg_01; | |
2885 | unsigned long flags; | |
2886 | ||
2887 | spin_lock_irqsave(&ioapic_lock, flags); | |
2888 | reg_01.raw = io_apic_read(ioapic, 1); | |
2889 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2890 | ||
2891 | return reg_01.bits.entries; | |
2892 | } | |
2893 | ||
2894 | ||
497c9a19 | 2895 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 2896 | { |
1da177e4 LT |
2897 | if (!IO_APIC_IRQ(irq)) { |
2898 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2899 | ioapic); | |
2900 | return -EINVAL; | |
2901 | } | |
2902 | ||
1da177e4 LT |
2903 | /* |
2904 | * IRQs < 16 are already in the irq_2_pin[] map | |
2905 | */ | |
2906 | if (irq >= 16) | |
2907 | add_pin_to_irq(irq, ioapic, pin); | |
2908 | ||
497c9a19 | 2909 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
2910 | |
2911 | return 0; | |
2912 | } | |
2913 | ||
61fd47e0 SL |
2914 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2915 | { | |
2916 | int i; | |
2917 | ||
2918 | if (skip_ioapic_setup) | |
2919 | return -1; | |
2920 | ||
2921 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2922 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2923 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2924 | break; |
2925 | if (i >= mp_irq_entries) | |
2926 | return -1; | |
2927 | ||
2928 | *trigger = irq_trigger(i); | |
2929 | *polarity = irq_polarity(i); | |
2930 | return 0; | |
2931 | } | |
2932 | ||
888ba6c6 | 2933 | #endif /* CONFIG_ACPI */ |
1a3f239d | 2934 | |
497c9a19 YL |
2935 | /* |
2936 | * This function currently is only a helper for the i386 smp boot process where | |
2937 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
2938 | * so mask in all cases should simply be TARGET_CPUS | |
2939 | */ | |
2940 | #ifdef CONFIG_SMP | |
2941 | void __init setup_ioapic_dest(void) | |
2942 | { | |
2943 | int pin, ioapic, irq, irq_entry; | |
2944 | struct irq_cfg *cfg; | |
2945 | struct irq_desc *desc; | |
2946 | ||
2947 | if (skip_ioapic_setup == 1) | |
2948 | return; | |
2949 | ||
2950 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
2951 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
2952 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
2953 | if (irq_entry == -1) | |
2954 | continue; | |
2955 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
2956 | ||
2957 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
2958 | * when you have too many devices, because at that time only boot | |
2959 | * cpu is online. | |
2960 | */ | |
2961 | cfg = irq_cfg(irq); | |
2962 | if (!cfg->vector) | |
2963 | setup_IO_APIC_irq(ioapic, pin, irq, | |
2964 | irq_trigger(irq_entry), | |
2965 | irq_polarity(irq_entry)); | |
2966 | else { | |
2967 | desc = irq_to_desc(irq); | |
2968 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
2969 | } | |
2970 | } | |
2971 | ||
2972 | } | |
2973 | } | |
2974 | #endif | |
2975 | ||
1a3f239d RR |
2976 | static int __init parse_disable_timer_pin_1(char *arg) |
2977 | { | |
2978 | disable_timer_pin_1 = 1; | |
2979 | return 0; | |
2980 | } | |
2981 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2982 | ||
2983 | static int __init parse_enable_timer_pin_1(char *arg) | |
2984 | { | |
2985 | disable_timer_pin_1 = -1; | |
2986 | return 0; | |
2987 | } | |
2988 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2989 | ||
2990 | static int __init parse_noapic(char *arg) | |
2991 | { | |
2992 | /* disable IO-APIC */ | |
2993 | disable_ioapic_setup(); | |
2994 | return 0; | |
2995 | } | |
2996 | early_param("noapic", parse_noapic); | |
f3294a33 YL |
2997 | |
2998 | void __init ioapic_init_mappings(void) | |
2999 | { | |
3000 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
3001 | int i; | |
3002 | ||
3003 | for (i = 0; i < nr_ioapics; i++) { | |
3004 | if (smp_found_config) { | |
3005 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
3006 | if (!ioapic_phys) { | |
3007 | printk(KERN_ERR | |
3008 | "WARNING: bogus zero IO-APIC " | |
3009 | "address found in MPTABLE, " | |
3010 | "disabling IO/APIC support!\n"); | |
3011 | smp_found_config = 0; | |
3012 | skip_ioapic_setup = 1; | |
3013 | goto fake_ioapic_page; | |
3014 | } | |
3015 | } else { | |
3016 | fake_ioapic_page: | |
3017 | ioapic_phys = (unsigned long) | |
3018 | alloc_bootmem_pages(PAGE_SIZE); | |
3019 | ioapic_phys = __pa(ioapic_phys); | |
3020 | } | |
3021 | set_fixmap_nocache(idx, ioapic_phys); | |
3022 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
3023 | __fix_to_virt(idx), ioapic_phys); | |
3024 | idx++; | |
3025 | } | |
3026 | } | |
3027 |