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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
1dcdd3d1 | 65 | #include <asm/genapic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
132 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
133 | { | |
134 | struct irq_pin_list *pin; | |
135 | int node; | |
136 | ||
137 | node = cpu_to_node(cpu); | |
138 | ||
139 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
140 | |
141 | return pin; | |
142 | } | |
143 | ||
a1420f39 | 144 | struct irq_cfg { |
0f978f45 | 145 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
146 | cpumask_var_t domain; |
147 | cpumask_var_t old_domain; | |
497c9a19 | 148 | unsigned move_cleanup_count; |
a1420f39 | 149 | u8 vector; |
497c9a19 | 150 | u8 move_in_progress : 1; |
48a1b10a YL |
151 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
152 | u8 move_desc_pending : 1; | |
153 | #endif | |
a1420f39 YL |
154 | }; |
155 | ||
a1420f39 | 156 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
157 | #ifdef CONFIG_SPARSE_IRQ |
158 | static struct irq_cfg irq_cfgx[] = { | |
159 | #else | |
d6c88a50 | 160 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 161 | #endif |
22f65d31 MT |
162 | [0] = { .vector = IRQ0_VECTOR, }, |
163 | [1] = { .vector = IRQ1_VECTOR, }, | |
164 | [2] = { .vector = IRQ2_VECTOR, }, | |
165 | [3] = { .vector = IRQ3_VECTOR, }, | |
166 | [4] = { .vector = IRQ4_VECTOR, }, | |
167 | [5] = { .vector = IRQ5_VECTOR, }, | |
168 | [6] = { .vector = IRQ6_VECTOR, }, | |
169 | [7] = { .vector = IRQ7_VECTOR, }, | |
170 | [8] = { .vector = IRQ8_VECTOR, }, | |
171 | [9] = { .vector = IRQ9_VECTOR, }, | |
172 | [10] = { .vector = IRQ10_VECTOR, }, | |
173 | [11] = { .vector = IRQ11_VECTOR, }, | |
174 | [12] = { .vector = IRQ12_VECTOR, }, | |
175 | [13] = { .vector = IRQ13_VECTOR, }, | |
176 | [14] = { .vector = IRQ14_VECTOR, }, | |
177 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
178 | }; |
179 | ||
13a0c3c2 | 180 | int __init arch_early_irq_init(void) |
8f09cd20 | 181 | { |
0b8f1efa YL |
182 | struct irq_cfg *cfg; |
183 | struct irq_desc *desc; | |
184 | int count; | |
185 | int i; | |
d6c88a50 | 186 | |
0b8f1efa YL |
187 | cfg = irq_cfgx; |
188 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 189 | |
0b8f1efa YL |
190 | for (i = 0; i < count; i++) { |
191 | desc = irq_to_desc(i); | |
192 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
193 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
194 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
195 | if (i < NR_IRQS_LEGACY) | |
196 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 197 | } |
13a0c3c2 YL |
198 | |
199 | return 0; | |
0b8f1efa | 200 | } |
8f09cd20 | 201 | |
0b8f1efa | 202 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 203 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 204 | { |
0b8f1efa YL |
205 | struct irq_cfg *cfg = NULL; |
206 | struct irq_desc *desc; | |
1da177e4 | 207 | |
0b8f1efa YL |
208 | desc = irq_to_desc(irq); |
209 | if (desc) | |
210 | cfg = desc->chip_data; | |
0f978f45 | 211 | |
0b8f1efa | 212 | return cfg; |
8f09cd20 | 213 | } |
d6c88a50 | 214 | |
0b8f1efa | 215 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
8f09cd20 | 216 | { |
0b8f1efa YL |
217 | struct irq_cfg *cfg; |
218 | int node; | |
219 | ||
220 | node = cpu_to_node(cpu); | |
0f978f45 | 221 | |
0b8f1efa | 222 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 223 | if (cfg) { |
80855f73 | 224 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
225 | kfree(cfg); |
226 | cfg = NULL; | |
80855f73 MT |
227 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
228 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
229 | free_cpumask_var(cfg->domain); |
230 | kfree(cfg); | |
231 | cfg = NULL; | |
232 | } else { | |
233 | cpumask_clear(cfg->domain); | |
234 | cpumask_clear(cfg->old_domain); | |
235 | } | |
236 | } | |
0f978f45 | 237 | |
0b8f1efa | 238 | return cfg; |
8f09cd20 YL |
239 | } |
240 | ||
13a0c3c2 | 241 | int arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 242 | { |
0b8f1efa | 243 | struct irq_cfg *cfg; |
d6c88a50 | 244 | |
0b8f1efa YL |
245 | cfg = desc->chip_data; |
246 | if (!cfg) { | |
247 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
248 | if (!desc->chip_data) { | |
249 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
250 | BUG_ON(1); | |
251 | } | |
252 | } | |
1da177e4 | 253 | |
13a0c3c2 | 254 | return 0; |
0b8f1efa | 255 | } |
0f978f45 | 256 | |
48a1b10a | 257 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
d6c88a50 | 258 | |
48a1b10a YL |
259 | static void |
260 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
0f978f45 | 261 | { |
48a1b10a YL |
262 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
263 | ||
264 | cfg->irq_2_pin = NULL; | |
265 | old_entry = old_cfg->irq_2_pin; | |
266 | if (!old_entry) | |
267 | return; | |
0f978f45 | 268 | |
48a1b10a YL |
269 | entry = get_one_free_irq_2_pin(cpu); |
270 | if (!entry) | |
271 | return; | |
0f978f45 | 272 | |
48a1b10a YL |
273 | entry->apic = old_entry->apic; |
274 | entry->pin = old_entry->pin; | |
275 | head = entry; | |
276 | tail = entry; | |
277 | old_entry = old_entry->next; | |
278 | while (old_entry) { | |
279 | entry = get_one_free_irq_2_pin(cpu); | |
280 | if (!entry) { | |
281 | entry = head; | |
282 | while (entry) { | |
283 | head = entry->next; | |
284 | kfree(entry); | |
285 | entry = head; | |
286 | } | |
287 | /* still use the old one */ | |
288 | return; | |
289 | } | |
290 | entry->apic = old_entry->apic; | |
291 | entry->pin = old_entry->pin; | |
292 | tail->next = entry; | |
293 | tail = entry; | |
294 | old_entry = old_entry->next; | |
295 | } | |
0f978f45 | 296 | |
48a1b10a YL |
297 | tail->next = NULL; |
298 | cfg->irq_2_pin = head; | |
0f978f45 | 299 | } |
0f978f45 | 300 | |
48a1b10a | 301 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 302 | { |
48a1b10a | 303 | struct irq_pin_list *entry, *next; |
0f978f45 | 304 | |
48a1b10a YL |
305 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
306 | return; | |
301e6190 | 307 | |
48a1b10a | 308 | entry = old_cfg->irq_2_pin; |
0f978f45 | 309 | |
48a1b10a YL |
310 | while (entry) { |
311 | next = entry->next; | |
312 | kfree(entry); | |
313 | entry = next; | |
314 | } | |
315 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 316 | } |
0f978f45 | 317 | |
48a1b10a YL |
318 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
319 | struct irq_desc *desc, int cpu) | |
0f978f45 | 320 | { |
48a1b10a YL |
321 | struct irq_cfg *cfg; |
322 | struct irq_cfg *old_cfg; | |
0f978f45 | 323 | |
48a1b10a | 324 | cfg = get_one_free_irq_cfg(cpu); |
301e6190 | 325 | |
48a1b10a YL |
326 | if (!cfg) |
327 | return; | |
328 | ||
329 | desc->chip_data = cfg; | |
330 | ||
331 | old_cfg = old_desc->chip_data; | |
332 | ||
333 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
334 | ||
335 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
0f978f45 | 336 | } |
1da177e4 | 337 | |
48a1b10a YL |
338 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
339 | { | |
340 | kfree(old_cfg); | |
341 | } | |
342 | ||
343 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
344 | { | |
345 | struct irq_cfg *old_cfg, *cfg; | |
346 | ||
347 | old_cfg = old_desc->chip_data; | |
348 | cfg = desc->chip_data; | |
349 | ||
350 | if (old_cfg == cfg) | |
351 | return; | |
352 | ||
353 | if (old_cfg) { | |
354 | free_irq_2_pin(old_cfg, cfg); | |
355 | free_irq_cfg(old_cfg); | |
356 | old_desc->chip_data = NULL; | |
357 | } | |
358 | } | |
359 | ||
d733e00d IM |
360 | static void |
361 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
48a1b10a YL |
362 | { |
363 | struct irq_cfg *cfg = desc->chip_data; | |
364 | ||
365 | if (!cfg->move_in_progress) { | |
366 | /* it means that domain is not changed */ | |
7f7ace0c | 367 | if (!cpumask_intersects(desc->affinity, mask)) |
48a1b10a YL |
368 | cfg->move_desc_pending = 1; |
369 | } | |
0f978f45 | 370 | } |
48a1b10a YL |
371 | #endif |
372 | ||
0b8f1efa YL |
373 | #else |
374 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
375 | { | |
376 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 377 | } |
1da177e4 | 378 | |
0b8f1efa YL |
379 | #endif |
380 | ||
48a1b10a | 381 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
382 | static inline void |
383 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 YL |
384 | { |
385 | } | |
48a1b10a | 386 | #endif |
1da177e4 | 387 | |
130fe05d LT |
388 | struct io_apic { |
389 | unsigned int index; | |
390 | unsigned int unused[3]; | |
391 | unsigned int data; | |
392 | }; | |
393 | ||
394 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
395 | { | |
396 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 397 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
398 | } |
399 | ||
400 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
401 | { | |
402 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
403 | writel(reg, &io_apic->index); | |
404 | return readl(&io_apic->data); | |
405 | } | |
406 | ||
407 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
408 | { | |
409 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
410 | writel(reg, &io_apic->index); | |
411 | writel(value, &io_apic->data); | |
412 | } | |
413 | ||
414 | /* | |
415 | * Re-write a value: to be used for read-modify-write | |
416 | * cycles where the read already set up the index register. | |
417 | * | |
418 | * Older SiS APIC requires we rewrite the index register | |
419 | */ | |
420 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
421 | { | |
54168ed7 | 422 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
423 | |
424 | if (sis_apic_bug) | |
425 | writel(reg, &io_apic->index); | |
130fe05d LT |
426 | writel(value, &io_apic->data); |
427 | } | |
428 | ||
3145e941 | 429 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
430 | { |
431 | struct irq_pin_list *entry; | |
432 | unsigned long flags; | |
047c8fdb YL |
433 | |
434 | spin_lock_irqsave(&ioapic_lock, flags); | |
435 | entry = cfg->irq_2_pin; | |
436 | for (;;) { | |
437 | unsigned int reg; | |
438 | int pin; | |
439 | ||
440 | if (!entry) | |
441 | break; | |
442 | pin = entry->pin; | |
443 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
444 | /* Is the remote IRR bit set? */ | |
445 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
446 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
447 | return true; | |
448 | } | |
449 | if (!entry->next) | |
450 | break; | |
451 | entry = entry->next; | |
452 | } | |
453 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
454 | ||
455 | return false; | |
456 | } | |
047c8fdb | 457 | |
cf4c6a2f AK |
458 | union entry_union { |
459 | struct { u32 w1, w2; }; | |
460 | struct IO_APIC_route_entry entry; | |
461 | }; | |
462 | ||
463 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
464 | { | |
465 | union entry_union eu; | |
466 | unsigned long flags; | |
467 | spin_lock_irqsave(&ioapic_lock, flags); | |
468 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
469 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
470 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
471 | return eu.entry; | |
472 | } | |
473 | ||
f9dadfa7 LT |
474 | /* |
475 | * When we write a new IO APIC routing entry, we need to write the high | |
476 | * word first! If the mask bit in the low word is clear, we will enable | |
477 | * the interrupt, and we need to make sure the entry is fully populated | |
478 | * before that happens. | |
479 | */ | |
d15512f4 AK |
480 | static void |
481 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 482 | { |
cf4c6a2f AK |
483 | union entry_union eu; |
484 | eu.entry = e; | |
f9dadfa7 LT |
485 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
486 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
487 | } |
488 | ||
489 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
490 | { | |
491 | unsigned long flags; | |
492 | spin_lock_irqsave(&ioapic_lock, flags); | |
493 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
494 | spin_unlock_irqrestore(&ioapic_lock, flags); |
495 | } | |
496 | ||
497 | /* | |
498 | * When we mask an IO APIC routing entry, we need to write the low | |
499 | * word first, in order to set the mask bit before we change the | |
500 | * high bits! | |
501 | */ | |
502 | static void ioapic_mask_entry(int apic, int pin) | |
503 | { | |
504 | unsigned long flags; | |
505 | union entry_union eu = { .entry.mask = 1 }; | |
506 | ||
cf4c6a2f AK |
507 | spin_lock_irqsave(&ioapic_lock, flags); |
508 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
509 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
510 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
511 | } | |
512 | ||
497c9a19 | 513 | #ifdef CONFIG_SMP |
22f65d31 MT |
514 | static void send_cleanup_vector(struct irq_cfg *cfg) |
515 | { | |
516 | cpumask_var_t cleanup_mask; | |
517 | ||
518 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
519 | unsigned int i; | |
520 | cfg->move_cleanup_count = 0; | |
521 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
522 | cfg->move_cleanup_count++; | |
523 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
dac5f412 | 524 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
525 | } else { |
526 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
527 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
dac5f412 | 528 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
529 | free_cpumask_var(cleanup_mask); |
530 | } | |
531 | cfg->move_in_progress = 0; | |
532 | } | |
533 | ||
3145e941 | 534 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
535 | { |
536 | int apic, pin; | |
497c9a19 | 537 | struct irq_pin_list *entry; |
3145e941 | 538 | u8 vector = cfg->vector; |
497c9a19 | 539 | |
497c9a19 YL |
540 | entry = cfg->irq_2_pin; |
541 | for (;;) { | |
542 | unsigned int reg; | |
543 | ||
544 | if (!entry) | |
545 | break; | |
546 | ||
547 | apic = entry->apic; | |
548 | pin = entry->pin; | |
54168ed7 IM |
549 | #ifdef CONFIG_INTR_REMAP |
550 | /* | |
551 | * With interrupt-remapping, destination information comes | |
552 | * from interrupt-remapping table entry. | |
553 | */ | |
554 | if (!irq_remapped(irq)) | |
555 | io_apic_write(apic, 0x11 + pin*2, dest); | |
556 | #else | |
497c9a19 | 557 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 558 | #endif |
497c9a19 YL |
559 | reg = io_apic_read(apic, 0x10 + pin*2); |
560 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
561 | reg |= vector; | |
54168ed7 | 562 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
563 | if (!entry->next) |
564 | break; | |
565 | entry = entry->next; | |
566 | } | |
567 | } | |
efa2559f | 568 | |
e7986739 MT |
569 | static int |
570 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 571 | |
22f65d31 | 572 | /* |
debccb3e IM |
573 | * Either sets desc->affinity to a valid value, and returns |
574 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
575 | * leaves desc->affinity untouched. | |
22f65d31 MT |
576 | */ |
577 | static unsigned int | |
578 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
579 | { |
580 | struct irq_cfg *cfg; | |
3145e941 | 581 | unsigned int irq; |
497c9a19 | 582 | |
0de26520 | 583 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 584 | return BAD_APICID; |
497c9a19 | 585 | |
3145e941 YL |
586 | irq = desc->irq; |
587 | cfg = desc->chip_data; | |
588 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 589 | return BAD_APICID; |
497c9a19 | 590 | |
7f7ace0c | 591 | cpumask_and(desc->affinity, cfg->domain, mask); |
3145e941 | 592 | set_extra_move_desc(desc, mask); |
debccb3e IM |
593 | |
594 | return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask); | |
22f65d31 | 595 | } |
3145e941 | 596 | |
22f65d31 MT |
597 | static void |
598 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
599 | { |
600 | struct irq_cfg *cfg; | |
601 | unsigned long flags; | |
602 | unsigned int dest; | |
22f65d31 | 603 | unsigned int irq; |
497c9a19 | 604 | |
22f65d31 MT |
605 | irq = desc->irq; |
606 | cfg = desc->chip_data; | |
497c9a19 | 607 | |
497c9a19 | 608 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
609 | dest = set_desc_affinity(desc, mask); |
610 | if (dest != BAD_APICID) { | |
611 | /* Only the high 8 bits are valid. */ | |
612 | dest = SET_APIC_LOGICAL_ID(dest); | |
613 | __target_IO_APIC_irq(irq, dest, cfg); | |
614 | } | |
497c9a19 YL |
615 | spin_unlock_irqrestore(&ioapic_lock, flags); |
616 | } | |
497c9a19 | 617 | |
22f65d31 MT |
618 | static void |
619 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
620 | { |
621 | struct irq_desc *desc; | |
497c9a19 | 622 | |
54168ed7 | 623 | desc = irq_to_desc(irq); |
3145e941 YL |
624 | |
625 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 626 | } |
497c9a19 YL |
627 | #endif /* CONFIG_SMP */ |
628 | ||
1da177e4 LT |
629 | /* |
630 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
631 | * shared ISA-space IRQs, so we have to support them. We are super | |
632 | * fast in the common case, and fast for shared ISA-space IRQs. | |
633 | */ | |
3145e941 | 634 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 635 | { |
0f978f45 YL |
636 | struct irq_pin_list *entry; |
637 | ||
0f978f45 YL |
638 | entry = cfg->irq_2_pin; |
639 | if (!entry) { | |
0b8f1efa YL |
640 | entry = get_one_free_irq_2_pin(cpu); |
641 | if (!entry) { | |
642 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
643 | apic, pin); | |
644 | return; | |
645 | } | |
0f978f45 YL |
646 | cfg->irq_2_pin = entry; |
647 | entry->apic = apic; | |
648 | entry->pin = pin; | |
0f978f45 YL |
649 | return; |
650 | } | |
1da177e4 | 651 | |
0f978f45 YL |
652 | while (entry->next) { |
653 | /* not again, please */ | |
654 | if (entry->apic == apic && entry->pin == pin) | |
655 | return; | |
1da177e4 | 656 | |
0f978f45 | 657 | entry = entry->next; |
1da177e4 | 658 | } |
0f978f45 | 659 | |
0b8f1efa | 660 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 661 | entry = entry->next; |
1da177e4 LT |
662 | entry->apic = apic; |
663 | entry->pin = pin; | |
664 | } | |
665 | ||
666 | /* | |
667 | * Reroute an IRQ to a different pin. | |
668 | */ | |
3145e941 | 669 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
670 | int oldapic, int oldpin, |
671 | int newapic, int newpin) | |
672 | { | |
0f978f45 YL |
673 | struct irq_pin_list *entry = cfg->irq_2_pin; |
674 | int replaced = 0; | |
1da177e4 | 675 | |
0f978f45 | 676 | while (entry) { |
1da177e4 LT |
677 | if (entry->apic == oldapic && entry->pin == oldpin) { |
678 | entry->apic = newapic; | |
679 | entry->pin = newpin; | |
0f978f45 YL |
680 | replaced = 1; |
681 | /* every one is different, right? */ | |
1da177e4 | 682 | break; |
0f978f45 YL |
683 | } |
684 | entry = entry->next; | |
1da177e4 | 685 | } |
0f978f45 YL |
686 | |
687 | /* why? call replace before add? */ | |
688 | if (!replaced) | |
3145e941 | 689 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
690 | } |
691 | ||
3145e941 | 692 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
693 | int mask_and, int mask_or, |
694 | void (*final)(struct irq_pin_list *entry)) | |
695 | { | |
696 | int pin; | |
87783be4 | 697 | struct irq_pin_list *entry; |
047c8fdb | 698 | |
87783be4 CG |
699 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
700 | unsigned int reg; | |
701 | pin = entry->pin; | |
702 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
703 | reg &= mask_and; | |
704 | reg |= mask_or; | |
705 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
706 | if (final) | |
707 | final(entry); | |
708 | } | |
709 | } | |
047c8fdb | 710 | |
3145e941 | 711 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 712 | { |
3145e941 | 713 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 714 | } |
047c8fdb | 715 | |
4e738e2f | 716 | #ifdef CONFIG_X86_64 |
7f3e632f | 717 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 718 | { |
87783be4 CG |
719 | /* |
720 | * Synchronize the IO-APIC and the CPU by doing | |
721 | * a dummy read from the IO-APIC | |
722 | */ | |
723 | struct io_apic __iomem *io_apic; | |
724 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 725 | readl(&io_apic->data); |
1da177e4 LT |
726 | } |
727 | ||
3145e941 | 728 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 729 | { |
3145e941 | 730 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
731 | } |
732 | #else /* CONFIG_X86_32 */ | |
3145e941 | 733 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 734 | { |
3145e941 | 735 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 736 | } |
1da177e4 | 737 | |
3145e941 | 738 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 739 | { |
3145e941 | 740 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
741 | IO_APIC_REDIR_MASKED, NULL); |
742 | } | |
1da177e4 | 743 | |
3145e941 | 744 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 745 | { |
3145e941 | 746 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
747 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
748 | } | |
749 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 750 | |
3145e941 | 751 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 752 | { |
3145e941 | 753 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
754 | unsigned long flags; |
755 | ||
3145e941 YL |
756 | BUG_ON(!cfg); |
757 | ||
1da177e4 | 758 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 759 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
760 | spin_unlock_irqrestore(&ioapic_lock, flags); |
761 | } | |
762 | ||
3145e941 | 763 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 764 | { |
3145e941 | 765 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
766 | unsigned long flags; |
767 | ||
768 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 769 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
770 | spin_unlock_irqrestore(&ioapic_lock, flags); |
771 | } | |
772 | ||
3145e941 YL |
773 | static void mask_IO_APIC_irq(unsigned int irq) |
774 | { | |
775 | struct irq_desc *desc = irq_to_desc(irq); | |
776 | ||
777 | mask_IO_APIC_irq_desc(desc); | |
778 | } | |
779 | static void unmask_IO_APIC_irq(unsigned int irq) | |
780 | { | |
781 | struct irq_desc *desc = irq_to_desc(irq); | |
782 | ||
783 | unmask_IO_APIC_irq_desc(desc); | |
784 | } | |
785 | ||
1da177e4 LT |
786 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
787 | { | |
788 | struct IO_APIC_route_entry entry; | |
36062448 | 789 | |
1da177e4 | 790 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 791 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
792 | if (entry.delivery_mode == dest_SMI) |
793 | return; | |
1da177e4 LT |
794 | /* |
795 | * Disable it in the IO-APIC irq-routing table: | |
796 | */ | |
f9dadfa7 | 797 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
798 | } |
799 | ||
54168ed7 | 800 | static void clear_IO_APIC (void) |
1da177e4 LT |
801 | { |
802 | int apic, pin; | |
803 | ||
804 | for (apic = 0; apic < nr_ioapics; apic++) | |
805 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
806 | clear_IO_APIC_pin(apic, pin); | |
807 | } | |
808 | ||
54168ed7 | 809 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
810 | /* |
811 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
812 | * specific CPU-side IRQs. | |
813 | */ | |
814 | ||
815 | #define MAX_PIRQS 8 | |
816 | static int pirq_entries [MAX_PIRQS]; | |
817 | static int pirqs_enabled; | |
1da177e4 | 818 | |
1da177e4 LT |
819 | static int __init ioapic_pirq_setup(char *str) |
820 | { | |
821 | int i, max; | |
822 | int ints[MAX_PIRQS+1]; | |
823 | ||
824 | get_options(str, ARRAY_SIZE(ints), ints); | |
825 | ||
826 | for (i = 0; i < MAX_PIRQS; i++) | |
827 | pirq_entries[i] = -1; | |
828 | ||
829 | pirqs_enabled = 1; | |
830 | apic_printk(APIC_VERBOSE, KERN_INFO | |
831 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
832 | max = MAX_PIRQS; | |
833 | if (ints[0] < MAX_PIRQS) | |
834 | max = ints[0]; | |
835 | ||
836 | for (i = 0; i < max; i++) { | |
837 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
838 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
839 | /* | |
840 | * PIRQs are mapped upside down, usually. | |
841 | */ | |
842 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
843 | } | |
844 | return 1; | |
845 | } | |
846 | ||
847 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
848 | #endif /* CONFIG_X86_32 */ |
849 | ||
850 | #ifdef CONFIG_INTR_REMAP | |
851 | /* I/O APIC RTE contents at the OS boot up */ | |
852 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
853 | ||
854 | /* | |
855 | * Saves and masks all the unmasked IO-APIC RTE's | |
856 | */ | |
857 | int save_mask_IO_APIC_setup(void) | |
858 | { | |
859 | union IO_APIC_reg_01 reg_01; | |
860 | unsigned long flags; | |
861 | int apic, pin; | |
862 | ||
863 | /* | |
864 | * The number of IO-APIC IRQ registers (== #pins): | |
865 | */ | |
866 | for (apic = 0; apic < nr_ioapics; apic++) { | |
867 | spin_lock_irqsave(&ioapic_lock, flags); | |
868 | reg_01.raw = io_apic_read(apic, 1); | |
869 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
870 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
871 | } | |
872 | ||
873 | for (apic = 0; apic < nr_ioapics; apic++) { | |
874 | early_ioapic_entries[apic] = | |
875 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
876 | nr_ioapic_registers[apic], GFP_KERNEL); | |
877 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 878 | goto nomem; |
54168ed7 IM |
879 | } |
880 | ||
881 | for (apic = 0; apic < nr_ioapics; apic++) | |
882 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
883 | struct IO_APIC_route_entry entry; | |
884 | ||
885 | entry = early_ioapic_entries[apic][pin] = | |
886 | ioapic_read_entry(apic, pin); | |
887 | if (!entry.mask) { | |
888 | entry.mask = 1; | |
889 | ioapic_write_entry(apic, pin, entry); | |
890 | } | |
891 | } | |
5ffa4eb2 | 892 | |
54168ed7 | 893 | return 0; |
5ffa4eb2 CG |
894 | |
895 | nomem: | |
c1370b49 CG |
896 | while (apic >= 0) |
897 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
898 | memset(early_ioapic_entries, 0, |
899 | ARRAY_SIZE(early_ioapic_entries)); | |
900 | ||
901 | return -ENOMEM; | |
54168ed7 IM |
902 | } |
903 | ||
904 | void restore_IO_APIC_setup(void) | |
905 | { | |
906 | int apic, pin; | |
907 | ||
5ffa4eb2 CG |
908 | for (apic = 0; apic < nr_ioapics; apic++) { |
909 | if (!early_ioapic_entries[apic]) | |
910 | break; | |
54168ed7 IM |
911 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
912 | ioapic_write_entry(apic, pin, | |
913 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
914 | kfree(early_ioapic_entries[apic]); |
915 | early_ioapic_entries[apic] = NULL; | |
916 | } | |
54168ed7 IM |
917 | } |
918 | ||
919 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
920 | { | |
921 | /* | |
922 | * for now plain restore of previous settings. | |
923 | * TBD: In the case of OS enabling interrupt-remapping, | |
924 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
925 | * table entries. for now, do a plain restore, and wait for | |
926 | * the setup_IO_APIC_irqs() to do proper initialization. | |
927 | */ | |
928 | restore_IO_APIC_setup(); | |
929 | } | |
930 | #endif | |
1da177e4 LT |
931 | |
932 | /* | |
933 | * Find the IRQ entry number of a certain pin. | |
934 | */ | |
935 | static int find_irq_entry(int apic, int pin, int type) | |
936 | { | |
937 | int i; | |
938 | ||
939 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
940 | if (mp_irqs[i].irqtype == type && |
941 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
942 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
943 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
944 | return i; |
945 | ||
946 | return -1; | |
947 | } | |
948 | ||
949 | /* | |
950 | * Find the pin to which IRQ[irq] (ISA) is connected | |
951 | */ | |
fcfd636a | 952 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
953 | { |
954 | int i; | |
955 | ||
956 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 957 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 958 | |
d27e2b8e | 959 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
960 | (mp_irqs[i].irqtype == type) && |
961 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 962 | |
c2c21745 | 963 | return mp_irqs[i].dstirq; |
1da177e4 LT |
964 | } |
965 | return -1; | |
966 | } | |
967 | ||
fcfd636a EB |
968 | static int __init find_isa_irq_apic(int irq, int type) |
969 | { | |
970 | int i; | |
971 | ||
972 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 973 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 974 | |
73b2961b | 975 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
976 | (mp_irqs[i].irqtype == type) && |
977 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
978 | break; |
979 | } | |
980 | if (i < mp_irq_entries) { | |
981 | int apic; | |
54168ed7 | 982 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 983 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
984 | return apic; |
985 | } | |
986 | } | |
987 | ||
988 | return -1; | |
989 | } | |
990 | ||
1da177e4 LT |
991 | /* |
992 | * Find a specific PCI IRQ entry. | |
993 | * Not an __init, possibly needed by modules | |
994 | */ | |
995 | static int pin_2_irq(int idx, int apic, int pin); | |
996 | ||
997 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
998 | { | |
999 | int apic, i, best_guess = -1; | |
1000 | ||
54168ed7 IM |
1001 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1002 | bus, slot, pin); | |
ce6444d3 | 1003 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1004 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1005 | return -1; |
1006 | } | |
1007 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1008 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
1009 | |
1010 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
1011 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
1012 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1013 | break; |
1014 | ||
47cab822 | 1015 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 1016 | !mp_irqs[i].irqtype && |
1da177e4 | 1017 | (bus == lbus) && |
c2c21745 JSR |
1018 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
1019 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
1020 | |
1021 | if (!(apic || IO_APIC_IRQ(irq))) | |
1022 | continue; | |
1023 | ||
c2c21745 | 1024 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
1025 | return irq; |
1026 | /* | |
1027 | * Use the first all-but-pin matching entry as a | |
1028 | * best-guess fuzzy result for broken mptables. | |
1029 | */ | |
1030 | if (best_guess < 0) | |
1031 | best_guess = irq; | |
1032 | } | |
1033 | } | |
1034 | return best_guess; | |
1035 | } | |
54168ed7 | 1036 | |
129f6946 | 1037 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1038 | |
c0a282c2 | 1039 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1040 | /* |
1041 | * EISA Edge/Level control register, ELCR | |
1042 | */ | |
1043 | static int EISA_ELCR(unsigned int irq) | |
1044 | { | |
99d093d1 | 1045 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1046 | unsigned int port = 0x4d0 + (irq >> 3); |
1047 | return (inb(port) >> (irq & 7)) & 1; | |
1048 | } | |
1049 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1050 | "Broken MPtable reports ISA irq %d\n", irq); | |
1051 | return 0; | |
1052 | } | |
54168ed7 | 1053 | |
c0a282c2 | 1054 | #endif |
1da177e4 | 1055 | |
6728801d AS |
1056 | /* ISA interrupts are always polarity zero edge triggered, |
1057 | * when listed as conforming in the MP table. */ | |
1058 | ||
1059 | #define default_ISA_trigger(idx) (0) | |
1060 | #define default_ISA_polarity(idx) (0) | |
1061 | ||
1da177e4 LT |
1062 | /* EISA interrupts are always polarity zero and can be edge or level |
1063 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1064 | * EISA conforming in the MP table, that means its trigger type must | |
1065 | * be read in from the ELCR */ | |
1066 | ||
c2c21745 | 1067 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 1068 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1069 | |
1070 | /* PCI interrupts are always polarity one level triggered, | |
1071 | * when listed as conforming in the MP table. */ | |
1072 | ||
1073 | #define default_PCI_trigger(idx) (1) | |
1074 | #define default_PCI_polarity(idx) (1) | |
1075 | ||
1076 | /* MCA interrupts are always polarity zero level triggered, | |
1077 | * when listed as conforming in the MP table. */ | |
1078 | ||
1079 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1080 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1081 | |
61fd47e0 | 1082 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1083 | { |
c2c21745 | 1084 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1085 | int polarity; |
1086 | ||
1087 | /* | |
1088 | * Determine IRQ line polarity (high active or low active): | |
1089 | */ | |
c2c21745 | 1090 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 1091 | { |
54168ed7 IM |
1092 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1093 | if (test_bit(bus, mp_bus_not_pci)) | |
1094 | polarity = default_ISA_polarity(idx); | |
1095 | else | |
1096 | polarity = default_PCI_polarity(idx); | |
1097 | break; | |
1098 | case 1: /* high active */ | |
1099 | { | |
1100 | polarity = 0; | |
1101 | break; | |
1102 | } | |
1103 | case 2: /* reserved */ | |
1104 | { | |
1105 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1106 | polarity = 1; | |
1107 | break; | |
1108 | } | |
1109 | case 3: /* low active */ | |
1110 | { | |
1111 | polarity = 1; | |
1112 | break; | |
1113 | } | |
1114 | default: /* invalid */ | |
1115 | { | |
1116 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1117 | polarity = 1; | |
1118 | break; | |
1119 | } | |
1da177e4 LT |
1120 | } |
1121 | return polarity; | |
1122 | } | |
1123 | ||
1124 | static int MPBIOS_trigger(int idx) | |
1125 | { | |
c2c21745 | 1126 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1127 | int trigger; |
1128 | ||
1129 | /* | |
1130 | * Determine IRQ trigger mode (edge or level sensitive): | |
1131 | */ | |
c2c21745 | 1132 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1133 | { |
54168ed7 IM |
1134 | case 0: /* conforms, ie. bus-type dependent */ |
1135 | if (test_bit(bus, mp_bus_not_pci)) | |
1136 | trigger = default_ISA_trigger(idx); | |
1137 | else | |
1138 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1139 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1140 | switch (mp_bus_id_to_type[bus]) { |
1141 | case MP_BUS_ISA: /* ISA pin */ | |
1142 | { | |
1143 | /* set before the switch */ | |
1144 | break; | |
1145 | } | |
1146 | case MP_BUS_EISA: /* EISA pin */ | |
1147 | { | |
1148 | trigger = default_EISA_trigger(idx); | |
1149 | break; | |
1150 | } | |
1151 | case MP_BUS_PCI: /* PCI pin */ | |
1152 | { | |
1153 | /* set before the switch */ | |
1154 | break; | |
1155 | } | |
1156 | case MP_BUS_MCA: /* MCA pin */ | |
1157 | { | |
1158 | trigger = default_MCA_trigger(idx); | |
1159 | break; | |
1160 | } | |
1161 | default: | |
1162 | { | |
1163 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1164 | trigger = 1; | |
1165 | break; | |
1166 | } | |
1167 | } | |
1168 | #endif | |
1da177e4 | 1169 | break; |
54168ed7 | 1170 | case 1: /* edge */ |
1da177e4 | 1171 | { |
54168ed7 | 1172 | trigger = 0; |
1da177e4 LT |
1173 | break; |
1174 | } | |
54168ed7 | 1175 | case 2: /* reserved */ |
1da177e4 | 1176 | { |
54168ed7 IM |
1177 | printk(KERN_WARNING "broken BIOS!!\n"); |
1178 | trigger = 1; | |
1da177e4 LT |
1179 | break; |
1180 | } | |
54168ed7 | 1181 | case 3: /* level */ |
1da177e4 | 1182 | { |
54168ed7 | 1183 | trigger = 1; |
1da177e4 LT |
1184 | break; |
1185 | } | |
54168ed7 | 1186 | default: /* invalid */ |
1da177e4 LT |
1187 | { |
1188 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1189 | trigger = 0; |
1da177e4 LT |
1190 | break; |
1191 | } | |
1192 | } | |
1193 | return trigger; | |
1194 | } | |
1195 | ||
1196 | static inline int irq_polarity(int idx) | |
1197 | { | |
1198 | return MPBIOS_polarity(idx); | |
1199 | } | |
1200 | ||
1201 | static inline int irq_trigger(int idx) | |
1202 | { | |
1203 | return MPBIOS_trigger(idx); | |
1204 | } | |
1205 | ||
efa2559f | 1206 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1207 | static int pin_2_irq(int idx, int apic, int pin) |
1208 | { | |
1209 | int irq, i; | |
c2c21745 | 1210 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1211 | |
1212 | /* | |
1213 | * Debugging check, we are in big trouble if this message pops up! | |
1214 | */ | |
c2c21745 | 1215 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1216 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1217 | ||
54168ed7 | 1218 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1219 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1220 | } else { |
643befed AS |
1221 | /* |
1222 | * PCI IRQs are mapped in order | |
1223 | */ | |
1224 | i = irq = 0; | |
1225 | while (i < apic) | |
1226 | irq += nr_ioapic_registers[i++]; | |
1227 | irq += pin; | |
d6c88a50 | 1228 | /* |
54168ed7 IM |
1229 | * For MPS mode, so far only needed by ES7000 platform |
1230 | */ | |
d6c88a50 TG |
1231 | if (ioapic_renumber_irq) |
1232 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1233 | } |
1234 | ||
54168ed7 | 1235 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1236 | /* |
1237 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1238 | */ | |
1239 | if ((pin >= 16) && (pin <= 23)) { | |
1240 | if (pirq_entries[pin-16] != -1) { | |
1241 | if (!pirq_entries[pin-16]) { | |
1242 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1243 | "disabling PIRQ%d\n", pin-16); | |
1244 | } else { | |
1245 | irq = pirq_entries[pin-16]; | |
1246 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1247 | "using PIRQ%d -> IRQ %d\n", | |
1248 | pin-16, irq); | |
1249 | } | |
1250 | } | |
1251 | } | |
54168ed7 IM |
1252 | #endif |
1253 | ||
1da177e4 LT |
1254 | return irq; |
1255 | } | |
1256 | ||
497c9a19 YL |
1257 | void lock_vector_lock(void) |
1258 | { | |
1259 | /* Used to the online set of cpus does not change | |
1260 | * during assign_irq_vector. | |
1261 | */ | |
1262 | spin_lock(&vector_lock); | |
1263 | } | |
1da177e4 | 1264 | |
497c9a19 | 1265 | void unlock_vector_lock(void) |
1da177e4 | 1266 | { |
497c9a19 YL |
1267 | spin_unlock(&vector_lock); |
1268 | } | |
1da177e4 | 1269 | |
e7986739 MT |
1270 | static int |
1271 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1272 | { |
047c8fdb YL |
1273 | /* |
1274 | * NOTE! The local APIC isn't very good at handling | |
1275 | * multiple interrupts at the same interrupt level. | |
1276 | * As the interrupt level is determined by taking the | |
1277 | * vector number and shifting that right by 4, we | |
1278 | * want to spread these out a bit so that they don't | |
1279 | * all fall in the same interrupt level. | |
1280 | * | |
1281 | * Also, we've got to be careful not to trash gate | |
1282 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1283 | */ | |
54168ed7 IM |
1284 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1285 | unsigned int old_vector; | |
22f65d31 MT |
1286 | int cpu, err; |
1287 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1288 | |
54168ed7 IM |
1289 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1290 | return -EBUSY; | |
0a1ad60d | 1291 | |
22f65d31 MT |
1292 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1293 | return -ENOMEM; | |
ace80ab7 | 1294 | |
54168ed7 IM |
1295 | old_vector = cfg->vector; |
1296 | if (old_vector) { | |
22f65d31 MT |
1297 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1298 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1299 | if (!cpumask_empty(tmp_mask)) { | |
1300 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1301 | return 0; |
22f65d31 | 1302 | } |
54168ed7 | 1303 | } |
497c9a19 | 1304 | |
e7986739 | 1305 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1306 | err = -ENOSPC; |
1307 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1308 | int new_cpu; |
1309 | int vector, offset; | |
497c9a19 | 1310 | |
e2d40b18 | 1311 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1312 | |
54168ed7 IM |
1313 | vector = current_vector; |
1314 | offset = current_offset; | |
497c9a19 | 1315 | next: |
54168ed7 IM |
1316 | vector += 8; |
1317 | if (vector >= first_system_vector) { | |
e7986739 | 1318 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1319 | offset = (offset + 1) % 8; |
1320 | vector = FIRST_DEVICE_VECTOR + offset; | |
1321 | } | |
1322 | if (unlikely(current_vector == vector)) | |
1323 | continue; | |
b77b881f YL |
1324 | |
1325 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1326 | goto next; |
b77b881f | 1327 | |
22f65d31 | 1328 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1329 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1330 | goto next; | |
1331 | /* Found one! */ | |
1332 | current_vector = vector; | |
1333 | current_offset = offset; | |
1334 | if (old_vector) { | |
1335 | cfg->move_in_progress = 1; | |
22f65d31 | 1336 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1337 | } |
22f65d31 | 1338 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1339 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1340 | cfg->vector = vector; | |
22f65d31 MT |
1341 | cpumask_copy(cfg->domain, tmp_mask); |
1342 | err = 0; | |
1343 | break; | |
54168ed7 | 1344 | } |
22f65d31 MT |
1345 | free_cpumask_var(tmp_mask); |
1346 | return err; | |
497c9a19 YL |
1347 | } |
1348 | ||
e7986739 MT |
1349 | static int |
1350 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1351 | { |
1352 | int err; | |
ace80ab7 | 1353 | unsigned long flags; |
ace80ab7 EB |
1354 | |
1355 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1356 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1357 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1358 | return err; |
1359 | } | |
1360 | ||
3145e941 | 1361 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1362 | { |
497c9a19 YL |
1363 | int cpu, vector; |
1364 | ||
497c9a19 YL |
1365 | BUG_ON(!cfg->vector); |
1366 | ||
1367 | vector = cfg->vector; | |
22f65d31 | 1368 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1369 | per_cpu(vector_irq, cpu)[vector] = -1; |
1370 | ||
1371 | cfg->vector = 0; | |
22f65d31 | 1372 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1373 | |
1374 | if (likely(!cfg->move_in_progress)) | |
1375 | return; | |
22f65d31 | 1376 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1377 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1378 | vector++) { | |
1379 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1380 | continue; | |
1381 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1382 | break; | |
1383 | } | |
1384 | } | |
1385 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1386 | } |
1387 | ||
1388 | void __setup_vector_irq(int cpu) | |
1389 | { | |
1390 | /* Initialize vector_irq on a new cpu */ | |
1391 | /* This function must be called with vector_lock held */ | |
1392 | int irq, vector; | |
1393 | struct irq_cfg *cfg; | |
0b8f1efa | 1394 | struct irq_desc *desc; |
497c9a19 YL |
1395 | |
1396 | /* Mark the inuse vectors */ | |
0b8f1efa | 1397 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1398 | cfg = desc->chip_data; |
22f65d31 | 1399 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1400 | continue; |
1401 | vector = cfg->vector; | |
497c9a19 YL |
1402 | per_cpu(vector_irq, cpu)[vector] = irq; |
1403 | } | |
1404 | /* Mark the free vectors */ | |
1405 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1406 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1407 | if (irq < 0) | |
1408 | continue; | |
1409 | ||
1410 | cfg = irq_cfg(irq); | |
22f65d31 | 1411 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1412 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1413 | } |
1da177e4 | 1414 | } |
3fde6900 | 1415 | |
f5b9ed7a | 1416 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1417 | #ifdef CONFIG_INTR_REMAP |
1418 | static struct irq_chip ir_ioapic_chip; | |
1419 | #endif | |
1da177e4 | 1420 | |
54168ed7 IM |
1421 | #define IOAPIC_AUTO -1 |
1422 | #define IOAPIC_EDGE 0 | |
1423 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1424 | |
047c8fdb | 1425 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1426 | static inline int IO_APIC_irq_trigger(int irq) |
1427 | { | |
d6c88a50 | 1428 | int apic, idx, pin; |
1d025192 | 1429 | |
d6c88a50 TG |
1430 | for (apic = 0; apic < nr_ioapics; apic++) { |
1431 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1432 | idx = find_irq_entry(apic, pin, mp_INT); | |
1433 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1434 | return irq_trigger(idx); | |
1435 | } | |
1436 | } | |
1437 | /* | |
54168ed7 IM |
1438 | * nonexistent IRQs are edge default |
1439 | */ | |
d6c88a50 | 1440 | return 0; |
1d025192 | 1441 | } |
047c8fdb YL |
1442 | #else |
1443 | static inline int IO_APIC_irq_trigger(int irq) | |
1444 | { | |
54168ed7 | 1445 | return 1; |
047c8fdb YL |
1446 | } |
1447 | #endif | |
1d025192 | 1448 | |
3145e941 | 1449 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1450 | { |
199751d7 | 1451 | |
6ebcc00e | 1452 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1453 | trigger == IOAPIC_LEVEL) |
08678b08 | 1454 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1455 | else |
1456 | desc->status &= ~IRQ_LEVEL; | |
1457 | ||
54168ed7 IM |
1458 | #ifdef CONFIG_INTR_REMAP |
1459 | if (irq_remapped(irq)) { | |
1460 | desc->status |= IRQ_MOVE_PCNTXT; | |
1461 | if (trigger) | |
1462 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1463 | handle_fasteoi_irq, | |
1464 | "fasteoi"); | |
1465 | else | |
1466 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1467 | handle_edge_irq, "edge"); | |
1468 | return; | |
1469 | } | |
1470 | #endif | |
047c8fdb YL |
1471 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1472 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1473 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1474 | handle_fasteoi_irq, |
1475 | "fasteoi"); | |
047c8fdb | 1476 | else |
a460e745 | 1477 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1478 | handle_edge_irq, "edge"); |
1da177e4 LT |
1479 | } |
1480 | ||
c8d46cf0 | 1481 | static int setup_ioapic_entry(int apic_id, int irq, |
497c9a19 YL |
1482 | struct IO_APIC_route_entry *entry, |
1483 | unsigned int destination, int trigger, | |
1484 | int polarity, int vector) | |
1da177e4 | 1485 | { |
497c9a19 YL |
1486 | /* |
1487 | * add it to the IO-APIC irq-routing table: | |
1488 | */ | |
1489 | memset(entry,0,sizeof(*entry)); | |
1490 | ||
54168ed7 IM |
1491 | #ifdef CONFIG_INTR_REMAP |
1492 | if (intr_remapping_enabled) { | |
c8d46cf0 | 1493 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1494 | struct irte irte; |
1495 | struct IR_IO_APIC_route_entry *ir_entry = | |
1496 | (struct IR_IO_APIC_route_entry *) entry; | |
1497 | int index; | |
1498 | ||
1499 | if (!iommu) | |
c8d46cf0 | 1500 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1501 | |
1502 | index = alloc_irte(iommu, irq, 1); | |
1503 | if (index < 0) | |
c8d46cf0 | 1504 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1505 | |
1506 | memset(&irte, 0, sizeof(irte)); | |
1507 | ||
1508 | irte.present = 1; | |
9b5bc8dc | 1509 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 1510 | irte.trigger_mode = trigger; |
9b5bc8dc | 1511 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1512 | irte.vector = vector; |
1513 | irte.dest_id = IRTE_DEST(destination); | |
1514 | ||
1515 | modify_irte(irq, &irte); | |
1516 | ||
1517 | ir_entry->index2 = (index >> 15) & 0x1; | |
1518 | ir_entry->zero = 0; | |
1519 | ir_entry->format = 1; | |
1520 | ir_entry->index = (index & 0x7fff); | |
1521 | } else | |
1522 | #endif | |
1523 | { | |
9b5bc8dc IM |
1524 | entry->delivery_mode = apic->irq_delivery_mode; |
1525 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 IM |
1526 | entry->dest = destination; |
1527 | } | |
497c9a19 | 1528 | |
54168ed7 | 1529 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1530 | entry->trigger = trigger; |
1531 | entry->polarity = polarity; | |
1532 | entry->vector = vector; | |
1533 | ||
1534 | /* Mask level triggered irqs. | |
1535 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1536 | */ | |
1537 | if (trigger) | |
1538 | entry->mask = 1; | |
497c9a19 YL |
1539 | return 0; |
1540 | } | |
1541 | ||
c8d46cf0 | 1542 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1543 | int trigger, int polarity) |
497c9a19 YL |
1544 | { |
1545 | struct irq_cfg *cfg; | |
1da177e4 | 1546 | struct IO_APIC_route_entry entry; |
22f65d31 | 1547 | unsigned int dest; |
497c9a19 YL |
1548 | |
1549 | if (!IO_APIC_IRQ(irq)) | |
1550 | return; | |
1551 | ||
3145e941 | 1552 | cfg = desc->chip_data; |
497c9a19 | 1553 | |
fe402e1f | 1554 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1555 | return; |
1556 | ||
debccb3e | 1557 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1558 | |
1559 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1560 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1561 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1562 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1563 | irq, trigger, polarity); |
1564 | ||
1565 | ||
c8d46cf0 | 1566 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
22f65d31 | 1567 | dest, trigger, polarity, cfg->vector)) { |
497c9a19 | 1568 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1569 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1570 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1571 | return; |
1572 | } | |
1573 | ||
3145e941 | 1574 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1575 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1576 | disable_8259A_irq(irq); |
1577 | ||
c8d46cf0 | 1578 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1579 | } |
1580 | ||
1581 | static void __init setup_IO_APIC_irqs(void) | |
1582 | { | |
c8d46cf0 | 1583 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1584 | int notcon = 0; |
0b8f1efa | 1585 | struct irq_desc *desc; |
3145e941 | 1586 | struct irq_cfg *cfg; |
0b8f1efa | 1587 | int cpu = boot_cpu_id; |
1da177e4 LT |
1588 | |
1589 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1590 | ||
c8d46cf0 IM |
1591 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1592 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1593 | |
c8d46cf0 | 1594 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1595 | if (idx == -1) { |
2a554fb1 | 1596 | if (!notcon) { |
3c2cbd24 | 1597 | notcon = 1; |
2a554fb1 CG |
1598 | apic_printk(APIC_VERBOSE, |
1599 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1600 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1601 | } else |
1602 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1603 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1604 | continue; |
1605 | } | |
56ffa1a0 CG |
1606 | if (notcon) { |
1607 | apic_printk(APIC_VERBOSE, | |
1608 | " (apicid-pin) not connected\n"); | |
1609 | notcon = 0; | |
1610 | } | |
3c2cbd24 | 1611 | |
c8d46cf0 | 1612 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa IM |
1613 | |
1614 | /* | |
1615 | * Skip the timer IRQ if there's a quirk handler | |
1616 | * installed and if it returns 1: | |
1617 | */ | |
1618 | if (apic->multi_timer_check && | |
1619 | apic->multi_timer_check(apic_id, irq)) | |
3c2cbd24 | 1620 | continue; |
33a201fa | 1621 | |
0b8f1efa YL |
1622 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1623 | if (!desc) { | |
1624 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1625 | continue; | |
1626 | } | |
3145e941 | 1627 | cfg = desc->chip_data; |
c8d46cf0 | 1628 | add_pin_to_irq_cpu(cfg, cpu, apic_id, pin); |
36062448 | 1629 | |
c8d46cf0 | 1630 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1631 | irq_trigger(idx), irq_polarity(idx)); |
1632 | } | |
1da177e4 LT |
1633 | } |
1634 | ||
3c2cbd24 CG |
1635 | if (notcon) |
1636 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1637 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1638 | } |
1639 | ||
1640 | /* | |
f7633ce5 | 1641 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1642 | */ |
c8d46cf0 | 1643 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1644 | int vector) |
1da177e4 LT |
1645 | { |
1646 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1647 | |
54168ed7 IM |
1648 | #ifdef CONFIG_INTR_REMAP |
1649 | if (intr_remapping_enabled) | |
1650 | return; | |
1651 | #endif | |
1652 | ||
36062448 | 1653 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1654 | |
1655 | /* | |
1656 | * We use logical delivery to get the timer IRQ | |
1657 | * to the first CPU. | |
1658 | */ | |
9b5bc8dc | 1659 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1660 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1661 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1662 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1663 | entry.polarity = 0; |
1664 | entry.trigger = 0; | |
1665 | entry.vector = vector; | |
1666 | ||
1667 | /* | |
1668 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1669 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1670 | */ |
54168ed7 | 1671 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1672 | |
1673 | /* | |
1674 | * Add it to the IO-APIC irq-routing table: | |
1675 | */ | |
c8d46cf0 | 1676 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1677 | } |
1678 | ||
32f71aff MR |
1679 | |
1680 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1681 | { |
1682 | int apic, i; | |
1683 | union IO_APIC_reg_00 reg_00; | |
1684 | union IO_APIC_reg_01 reg_01; | |
1685 | union IO_APIC_reg_02 reg_02; | |
1686 | union IO_APIC_reg_03 reg_03; | |
1687 | unsigned long flags; | |
0f978f45 | 1688 | struct irq_cfg *cfg; |
0b8f1efa | 1689 | struct irq_desc *desc; |
8f09cd20 | 1690 | unsigned int irq; |
1da177e4 LT |
1691 | |
1692 | if (apic_verbosity == APIC_QUIET) | |
1693 | return; | |
1694 | ||
36062448 | 1695 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1696 | for (i = 0; i < nr_ioapics; i++) |
1697 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1698 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1699 | |
1700 | /* | |
1701 | * We are a bit conservative about what we expect. We have to | |
1702 | * know about every hardware change ASAP. | |
1703 | */ | |
1704 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1705 | ||
1706 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1707 | ||
1708 | spin_lock_irqsave(&ioapic_lock, flags); | |
1709 | reg_00.raw = io_apic_read(apic, 0); | |
1710 | reg_01.raw = io_apic_read(apic, 1); | |
1711 | if (reg_01.bits.version >= 0x10) | |
1712 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1713 | if (reg_01.bits.version >= 0x20) |
1714 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1715 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1716 | ||
54168ed7 | 1717 | printk("\n"); |
b5ba7e6d | 1718 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1719 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1720 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1721 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1722 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1723 | |
54168ed7 | 1724 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1725 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1726 | |
1727 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1728 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1729 | |
1730 | /* | |
1731 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1732 | * but the value of reg_02 is read as the previous read register | |
1733 | * value, so ignore it if reg_02 == reg_01. | |
1734 | */ | |
1735 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1736 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1737 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1738 | } |
1739 | ||
1740 | /* | |
1741 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1742 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1743 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1744 | */ | |
1745 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1746 | reg_03.raw != reg_01.raw) { | |
1747 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1748 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1749 | } |
1750 | ||
1751 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1752 | ||
d83e94ac YL |
1753 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1754 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1755 | |
1756 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1757 | struct IO_APIC_route_entry entry; | |
1758 | ||
cf4c6a2f | 1759 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1760 | |
54168ed7 IM |
1761 | printk(KERN_DEBUG " %02x %03X ", |
1762 | i, | |
1763 | entry.dest | |
1764 | ); | |
1da177e4 LT |
1765 | |
1766 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1767 | entry.mask, | |
1768 | entry.trigger, | |
1769 | entry.irr, | |
1770 | entry.polarity, | |
1771 | entry.delivery_status, | |
1772 | entry.dest_mode, | |
1773 | entry.delivery_mode, | |
1774 | entry.vector | |
1775 | ); | |
1776 | } | |
1777 | } | |
1da177e4 | 1778 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1779 | for_each_irq_desc(irq, desc) { |
1780 | struct irq_pin_list *entry; | |
1781 | ||
0b8f1efa YL |
1782 | cfg = desc->chip_data; |
1783 | entry = cfg->irq_2_pin; | |
0f978f45 | 1784 | if (!entry) |
1da177e4 | 1785 | continue; |
8f09cd20 | 1786 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1787 | for (;;) { |
1788 | printk("-> %d:%d", entry->apic, entry->pin); | |
1789 | if (!entry->next) | |
1790 | break; | |
0f978f45 | 1791 | entry = entry->next; |
1da177e4 LT |
1792 | } |
1793 | printk("\n"); | |
1794 | } | |
1795 | ||
1796 | printk(KERN_INFO ".................................... done.\n"); | |
1797 | ||
1798 | return; | |
1799 | } | |
1800 | ||
32f71aff | 1801 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1802 | { |
1803 | unsigned int v; | |
1804 | int i, j; | |
1805 | ||
1806 | if (apic_verbosity == APIC_QUIET) | |
1807 | return; | |
1808 | ||
1809 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1810 | for (i = 0; i < 8; i++) { | |
1811 | v = apic_read(base + i*0x10); | |
1812 | for (j = 0; j < 32; j++) { | |
1813 | if (v & (1<<j)) | |
1814 | printk("1"); | |
1815 | else | |
1816 | printk("0"); | |
1817 | } | |
1818 | printk("\n"); | |
1819 | } | |
1820 | } | |
1821 | ||
32f71aff | 1822 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1823 | { |
1824 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1825 | u64 icr; |
1da177e4 LT |
1826 | |
1827 | if (apic_verbosity == APIC_QUIET) | |
1828 | return; | |
1829 | ||
1830 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1831 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1832 | v = apic_read(APIC_ID); |
54168ed7 | 1833 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1834 | v = apic_read(APIC_LVR); |
1835 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1836 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1837 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1838 | |
1839 | v = apic_read(APIC_TASKPRI); | |
1840 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1841 | ||
54168ed7 | 1842 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1843 | if (!APIC_XAPIC(ver)) { |
1844 | v = apic_read(APIC_ARBPRI); | |
1845 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1846 | v & APIC_ARBPRI_MASK); | |
1847 | } | |
1da177e4 LT |
1848 | v = apic_read(APIC_PROCPRI); |
1849 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1850 | } | |
1851 | ||
a11b5abe YL |
1852 | /* |
1853 | * Remote read supported only in the 82489DX and local APIC for | |
1854 | * Pentium processors. | |
1855 | */ | |
1856 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1857 | v = apic_read(APIC_RRR); | |
1858 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1859 | } | |
1860 | ||
1da177e4 LT |
1861 | v = apic_read(APIC_LDR); |
1862 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1863 | if (!x2apic_enabled()) { |
1864 | v = apic_read(APIC_DFR); | |
1865 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1866 | } | |
1da177e4 LT |
1867 | v = apic_read(APIC_SPIV); |
1868 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1869 | ||
1870 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1871 | print_APIC_bitfield(APIC_ISR); | |
1872 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1873 | print_APIC_bitfield(APIC_TMR); | |
1874 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1875 | print_APIC_bitfield(APIC_IRR); | |
1876 | ||
54168ed7 IM |
1877 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1878 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1879 | apic_write(APIC_ESR, 0); |
54168ed7 | 1880 | |
1da177e4 LT |
1881 | v = apic_read(APIC_ESR); |
1882 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1883 | } | |
1884 | ||
7ab6af7a | 1885 | icr = apic_icr_read(); |
0c425cec IM |
1886 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1887 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1888 | |
1889 | v = apic_read(APIC_LVTT); | |
1890 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1891 | ||
1892 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1893 | v = apic_read(APIC_LVTPC); | |
1894 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1895 | } | |
1896 | v = apic_read(APIC_LVT0); | |
1897 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1898 | v = apic_read(APIC_LVT1); | |
1899 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1900 | ||
1901 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1902 | v = apic_read(APIC_LVTERR); | |
1903 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1904 | } | |
1905 | ||
1906 | v = apic_read(APIC_TMICT); | |
1907 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1908 | v = apic_read(APIC_TMCCT); | |
1909 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1910 | v = apic_read(APIC_TDCR); | |
1911 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1912 | printk("\n"); | |
1913 | } | |
1914 | ||
32f71aff | 1915 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1916 | { |
ffd5aae7 YL |
1917 | int cpu; |
1918 | ||
1919 | preempt_disable(); | |
1920 | for_each_online_cpu(cpu) | |
1921 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1922 | preempt_enable(); | |
1da177e4 LT |
1923 | } |
1924 | ||
32f71aff | 1925 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1926 | { |
1da177e4 LT |
1927 | unsigned int v; |
1928 | unsigned long flags; | |
1929 | ||
1930 | if (apic_verbosity == APIC_QUIET) | |
1931 | return; | |
1932 | ||
1933 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1934 | ||
1935 | spin_lock_irqsave(&i8259A_lock, flags); | |
1936 | ||
1937 | v = inb(0xa1) << 8 | inb(0x21); | |
1938 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1939 | ||
1940 | v = inb(0xa0) << 8 | inb(0x20); | |
1941 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1942 | ||
54168ed7 IM |
1943 | outb(0x0b,0xa0); |
1944 | outb(0x0b,0x20); | |
1da177e4 | 1945 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1946 | outb(0x0a,0xa0); |
1947 | outb(0x0a,0x20); | |
1da177e4 LT |
1948 | |
1949 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1950 | ||
1951 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1952 | ||
1953 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1954 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1955 | } | |
1956 | ||
32f71aff MR |
1957 | __apicdebuginit(int) print_all_ICs(void) |
1958 | { | |
1959 | print_PIC(); | |
1960 | print_all_local_APICs(); | |
1961 | print_IO_APIC(); | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | fs_initcall(print_all_ICs); | |
1967 | ||
1da177e4 | 1968 | |
efa2559f YL |
1969 | /* Where if anywhere is the i8259 connect in external int mode */ |
1970 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1971 | ||
54168ed7 | 1972 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1973 | { |
1974 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1975 | int i8259_apic, i8259_pin; |
54168ed7 | 1976 | int apic; |
1da177e4 LT |
1977 | unsigned long flags; |
1978 | ||
54168ed7 IM |
1979 | #ifdef CONFIG_X86_32 |
1980 | int i; | |
1da177e4 LT |
1981 | if (!pirqs_enabled) |
1982 | for (i = 0; i < MAX_PIRQS; i++) | |
1983 | pirq_entries[i] = -1; | |
54168ed7 | 1984 | #endif |
1da177e4 LT |
1985 | |
1986 | /* | |
1987 | * The number of IO-APIC IRQ registers (== #pins): | |
1988 | */ | |
fcfd636a | 1989 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1990 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1991 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1992 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1993 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1994 | } | |
54168ed7 | 1995 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1996 | int pin; |
1997 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1998 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1999 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2000 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2001 | |
fcfd636a EB |
2002 | /* If the interrupt line is enabled and in ExtInt mode |
2003 | * I have found the pin where the i8259 is connected. | |
2004 | */ | |
2005 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2006 | ioapic_i8259.apic = apic; | |
2007 | ioapic_i8259.pin = pin; | |
2008 | goto found_i8259; | |
2009 | } | |
2010 | } | |
2011 | } | |
2012 | found_i8259: | |
2013 | /* Look to see what if the MP table has reported the ExtINT */ | |
2014 | /* If we could not find the appropriate pin by looking at the ioapic | |
2015 | * the i8259 probably is not connected the ioapic but give the | |
2016 | * mptable a chance anyway. | |
2017 | */ | |
2018 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2019 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2020 | /* Trust the MP table if nothing is setup in the hardware */ | |
2021 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2022 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2023 | ioapic_i8259.pin = i8259_pin; | |
2024 | ioapic_i8259.apic = i8259_apic; | |
2025 | } | |
2026 | /* Complain if the MP table and the hardware disagree */ | |
2027 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2028 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2029 | { | |
2030 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2031 | } |
2032 | ||
2033 | /* | |
2034 | * Do not trust the IO-APIC being empty at bootup | |
2035 | */ | |
2036 | clear_IO_APIC(); | |
2037 | } | |
2038 | ||
2039 | /* | |
2040 | * Not an __init, needed by the reboot code | |
2041 | */ | |
2042 | void disable_IO_APIC(void) | |
2043 | { | |
2044 | /* | |
2045 | * Clear the IO-APIC before rebooting: | |
2046 | */ | |
2047 | clear_IO_APIC(); | |
2048 | ||
650927ef | 2049 | /* |
0b968d23 | 2050 | * If the i8259 is routed through an IOAPIC |
650927ef | 2051 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2052 | * so legacy interrupts can be delivered. |
650927ef | 2053 | */ |
fcfd636a | 2054 | if (ioapic_i8259.pin != -1) { |
650927ef | 2055 | struct IO_APIC_route_entry entry; |
650927ef EB |
2056 | |
2057 | memset(&entry, 0, sizeof(entry)); | |
2058 | entry.mask = 0; /* Enabled */ | |
2059 | entry.trigger = 0; /* Edge */ | |
2060 | entry.irr = 0; | |
2061 | entry.polarity = 0; /* High */ | |
2062 | entry.delivery_status = 0; | |
2063 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2064 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2065 | entry.vector = 0; |
54168ed7 | 2066 | entry.dest = read_apic_id(); |
650927ef EB |
2067 | |
2068 | /* | |
2069 | * Add it to the IO-APIC irq-routing table: | |
2070 | */ | |
cf4c6a2f | 2071 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2072 | } |
54168ed7 | 2073 | |
fcfd636a | 2074 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2075 | } |
2076 | ||
54168ed7 | 2077 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2078 | /* |
2079 | * function to set the IO-APIC physical IDs based on the | |
2080 | * values stored in the MPC table. | |
2081 | * | |
2082 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2083 | */ | |
2084 | ||
1da177e4 LT |
2085 | static void __init setup_ioapic_ids_from_mpc(void) |
2086 | { | |
2087 | union IO_APIC_reg_00 reg_00; | |
2088 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2089 | int apic_id; |
1da177e4 LT |
2090 | int i; |
2091 | unsigned char old_id; | |
2092 | unsigned long flags; | |
2093 | ||
a4dbc34d | 2094 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2095 | return; |
d49c4288 | 2096 | |
ca05fea6 NP |
2097 | /* |
2098 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2099 | * no meaning without the serial APIC bus. | |
2100 | */ | |
7c5c1e42 SL |
2101 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2102 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2103 | return; |
1da177e4 LT |
2104 | /* |
2105 | * This is broken; anything with a real cpu count has to | |
2106 | * circumvent this idiocy regardless. | |
2107 | */ | |
d190cb87 | 2108 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2109 | |
2110 | /* | |
2111 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2112 | */ | |
c8d46cf0 | 2113 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2114 | |
2115 | /* Read the register 0 value */ | |
2116 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2117 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2118 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2119 | |
c8d46cf0 | 2120 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2121 | |
c8d46cf0 | 2122 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2123 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2124 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2125 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2126 | reg_00.bits.ID); | |
c8d46cf0 | 2127 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2128 | } |
2129 | ||
1da177e4 LT |
2130 | /* |
2131 | * Sanity check, is the ID really free? Every APIC in a | |
2132 | * system must have a unique ID or we get lots of nice | |
2133 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2134 | */ | |
d1d7cae8 | 2135 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2136 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2137 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2138 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2139 | for (i = 0; i < get_physical_broadcast(); i++) |
2140 | if (!physid_isset(i, phys_id_present_map)) | |
2141 | break; | |
2142 | if (i >= get_physical_broadcast()) | |
2143 | panic("Max APIC ID exceeded!\n"); | |
2144 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2145 | i); | |
2146 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2147 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2148 | } else { |
2149 | physid_mask_t tmp; | |
8058714a | 2150 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2151 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2152 | "phys_id_present_map\n", | |
c8d46cf0 | 2153 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2154 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2155 | } | |
2156 | ||
2157 | ||
2158 | /* | |
2159 | * We need to adjust the IRQ routing table | |
2160 | * if the ID changed. | |
2161 | */ | |
c8d46cf0 | 2162 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2163 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2164 | if (mp_irqs[i].dstapic == old_id) |
2165 | mp_irqs[i].dstapic | |
c8d46cf0 | 2166 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2167 | |
2168 | /* | |
2169 | * Read the right value from the MPC table and | |
2170 | * write it into the ID register. | |
36062448 | 2171 | */ |
1da177e4 LT |
2172 | apic_printk(APIC_VERBOSE, KERN_INFO |
2173 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2174 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2175 | |
c8d46cf0 | 2176 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2177 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2178 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2179 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2180 | |
2181 | /* | |
2182 | * Sanity check | |
2183 | */ | |
2184 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2185 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2186 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2187 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2188 | printk("could not set ID!\n"); |
2189 | else | |
2190 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2191 | } | |
2192 | } | |
54168ed7 | 2193 | #endif |
1da177e4 | 2194 | |
7ce0bcfd | 2195 | int no_timer_check __initdata; |
8542b200 ZA |
2196 | |
2197 | static int __init notimercheck(char *s) | |
2198 | { | |
2199 | no_timer_check = 1; | |
2200 | return 1; | |
2201 | } | |
2202 | __setup("no_timer_check", notimercheck); | |
2203 | ||
1da177e4 LT |
2204 | /* |
2205 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2206 | * about the timer IRQ. We do the following to work around the situation: | |
2207 | * | |
2208 | * - timer IRQ defaults to IO-APIC IRQ | |
2209 | * - if this function detects that timer IRQs are defunct, then we fall | |
2210 | * back to ISA timer IRQs | |
2211 | */ | |
f0a7a5c9 | 2212 | static int __init timer_irq_works(void) |
1da177e4 LT |
2213 | { |
2214 | unsigned long t1 = jiffies; | |
4aae0702 | 2215 | unsigned long flags; |
1da177e4 | 2216 | |
8542b200 ZA |
2217 | if (no_timer_check) |
2218 | return 1; | |
2219 | ||
4aae0702 | 2220 | local_save_flags(flags); |
1da177e4 LT |
2221 | local_irq_enable(); |
2222 | /* Let ten ticks pass... */ | |
2223 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2224 | local_irq_restore(flags); |
1da177e4 LT |
2225 | |
2226 | /* | |
2227 | * Expect a few ticks at least, to be sure some possible | |
2228 | * glue logic does not lock up after one or two first | |
2229 | * ticks in a non-ExtINT mode. Also the local APIC | |
2230 | * might have cached one ExtINT interrupt. Finally, at | |
2231 | * least one tick may be lost due to delays. | |
2232 | */ | |
54168ed7 IM |
2233 | |
2234 | /* jiffies wrap? */ | |
1d16b53e | 2235 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2236 | return 1; |
1da177e4 LT |
2237 | return 0; |
2238 | } | |
2239 | ||
2240 | /* | |
2241 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2242 | * number of pending IRQ events unhandled. These cases are very rare, | |
2243 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2244 | * better to do it this way as thus we do not have to be aware of | |
2245 | * 'pending' interrupts in the IRQ path, except at this point. | |
2246 | */ | |
2247 | /* | |
2248 | * Edge triggered needs to resend any interrupt | |
2249 | * that was delayed but this is now handled in the device | |
2250 | * independent code. | |
2251 | */ | |
2252 | ||
2253 | /* | |
2254 | * Starting up a edge-triggered IO-APIC interrupt is | |
2255 | * nasty - we need to make sure that we get the edge. | |
2256 | * If it is already asserted for some reason, we need | |
2257 | * return 1 to indicate that is was pending. | |
2258 | * | |
2259 | * This is not complete - we should be able to fake | |
2260 | * an edge even if it isn't on the 8259A... | |
2261 | */ | |
54168ed7 | 2262 | |
f5b9ed7a | 2263 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2264 | { |
2265 | int was_pending = 0; | |
2266 | unsigned long flags; | |
0b8f1efa | 2267 | struct irq_cfg *cfg; |
1da177e4 LT |
2268 | |
2269 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2270 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2271 | disable_8259A_irq(irq); |
2272 | if (i8259A_irq_pending(irq)) | |
2273 | was_pending = 1; | |
2274 | } | |
0b8f1efa | 2275 | cfg = irq_cfg(irq); |
3145e941 | 2276 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2277 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2278 | ||
2279 | return was_pending; | |
2280 | } | |
2281 | ||
54168ed7 | 2282 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2283 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2284 | { |
54168ed7 IM |
2285 | |
2286 | struct irq_cfg *cfg = irq_cfg(irq); | |
2287 | unsigned long flags; | |
2288 | ||
2289 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2290 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2291 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2292 | |
2293 | return 1; | |
2294 | } | |
54168ed7 IM |
2295 | #else |
2296 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2297 | { |
dac5f412 | 2298 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2299 | |
d6c88a50 | 2300 | return 1; |
54168ed7 IM |
2301 | } |
2302 | #endif | |
497c9a19 | 2303 | |
54168ed7 IM |
2304 | /* |
2305 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2306 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2307 | * handled with the level-triggered descriptor, but that one has slightly | |
2308 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2309 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2310 | * races. | |
2311 | */ | |
497c9a19 | 2312 | |
54168ed7 | 2313 | #ifdef CONFIG_SMP |
497c9a19 | 2314 | |
54168ed7 IM |
2315 | #ifdef CONFIG_INTR_REMAP |
2316 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2317 | |
54168ed7 | 2318 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2319 | |
54168ed7 IM |
2320 | /* |
2321 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2322 | * | |
2323 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2324 | * and cpu destination) of IRTE and flush the hardware cache. | |
2325 | * | |
2326 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2327 | * vector information, along with modifying IRTE with vector and destination. | |
2328 | * So irq migration for level triggered is little bit more complex compared to | |
2329 | * edge triggered migration. But the good news is, we use the same algorithm | |
2330 | * for level triggered migration as we have today, only difference being, | |
2331 | * we now initiate the irq migration from process context instead of the | |
2332 | * interrupt context. | |
2333 | * | |
2334 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2335 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2336 | * as simple as edge triggered migration and we can do the irq migration | |
2337 | * with a simple atomic update to IO-APIC RTE. | |
2338 | */ | |
e7986739 MT |
2339 | static void |
2340 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2341 | { |
54168ed7 | 2342 | struct irq_cfg *cfg; |
54168ed7 IM |
2343 | struct irte irte; |
2344 | int modify_ioapic_rte; | |
2345 | unsigned int dest; | |
2346 | unsigned long flags; | |
3145e941 | 2347 | unsigned int irq; |
497c9a19 | 2348 | |
22f65d31 | 2349 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2350 | return; |
2351 | ||
3145e941 | 2352 | irq = desc->irq; |
54168ed7 IM |
2353 | if (get_irte(irq, &irte)) |
2354 | return; | |
497c9a19 | 2355 | |
3145e941 YL |
2356 | cfg = desc->chip_data; |
2357 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2358 | return; |
2359 | ||
3145e941 YL |
2360 | set_extra_move_desc(desc, mask); |
2361 | ||
debccb3e | 2362 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2363 | |
54168ed7 IM |
2364 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2365 | if (modify_ioapic_rte) { | |
2366 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2367 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2368 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2369 | } | |
2370 | ||
2371 | irte.vector = cfg->vector; | |
2372 | irte.dest_id = IRTE_DEST(dest); | |
2373 | ||
2374 | /* | |
2375 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2376 | */ | |
2377 | modify_irte(irq, &irte); | |
2378 | ||
22f65d31 MT |
2379 | if (cfg->move_in_progress) |
2380 | send_cleanup_vector(cfg); | |
54168ed7 | 2381 | |
7f7ace0c | 2382 | cpumask_copy(desc->affinity, mask); |
54168ed7 IM |
2383 | } |
2384 | ||
3145e941 | 2385 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2386 | { |
2387 | int ret = -1; | |
3145e941 | 2388 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2389 | |
3145e941 | 2390 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2391 | |
3145e941 | 2392 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2393 | /* |
d6c88a50 | 2394 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2395 | * vector information in the IO-APIC RTE and that will confuse |
2396 | * the EOI broadcast performed by cpu. | |
2397 | * So, delay the irq migration to the next instance. | |
2398 | */ | |
2399 | schedule_delayed_work(&ir_migration_work, 1); | |
2400 | goto unmask; | |
2401 | } | |
2402 | ||
2403 | /* everthing is clear. we have right of way */ | |
7f7ace0c | 2404 | migrate_ioapic_irq_desc(desc, desc->pending_mask); |
54168ed7 IM |
2405 | |
2406 | ret = 0; | |
2407 | desc->status &= ~IRQ_MOVE_PENDING; | |
7f7ace0c | 2408 | cpumask_clear(desc->pending_mask); |
54168ed7 IM |
2409 | |
2410 | unmask: | |
3145e941 YL |
2411 | unmask_IO_APIC_irq_desc(desc); |
2412 | ||
54168ed7 IM |
2413 | return ret; |
2414 | } | |
2415 | ||
2416 | static void ir_irq_migration(struct work_struct *work) | |
2417 | { | |
2418 | unsigned int irq; | |
2419 | struct irq_desc *desc; | |
2420 | ||
2421 | for_each_irq_desc(irq, desc) { | |
2422 | if (desc->status & IRQ_MOVE_PENDING) { | |
2423 | unsigned long flags; | |
2424 | ||
2425 | spin_lock_irqsave(&desc->lock, flags); | |
2426 | if (!desc->chip->set_affinity || | |
2427 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2428 | desc->status &= ~IRQ_MOVE_PENDING; | |
2429 | spin_unlock_irqrestore(&desc->lock, flags); | |
2430 | continue; | |
2431 | } | |
2432 | ||
7f7ace0c | 2433 | desc->chip->set_affinity(irq, desc->pending_mask); |
54168ed7 IM |
2434 | spin_unlock_irqrestore(&desc->lock, flags); |
2435 | } | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | /* | |
2440 | * Migrates the IRQ destination in the process context. | |
2441 | */ | |
968ea6d8 RR |
2442 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2443 | const struct cpumask *mask) | |
54168ed7 | 2444 | { |
54168ed7 IM |
2445 | if (desc->status & IRQ_LEVEL) { |
2446 | desc->status |= IRQ_MOVE_PENDING; | |
7f7ace0c | 2447 | cpumask_copy(desc->pending_mask, mask); |
3145e941 | 2448 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2449 | return; |
2450 | } | |
2451 | ||
3145e941 YL |
2452 | migrate_ioapic_irq_desc(desc, mask); |
2453 | } | |
968ea6d8 RR |
2454 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2455 | const struct cpumask *mask) | |
3145e941 YL |
2456 | { |
2457 | struct irq_desc *desc = irq_to_desc(irq); | |
2458 | ||
2459 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2460 | } |
2461 | #endif | |
2462 | ||
2463 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2464 | { | |
2465 | unsigned vector, me; | |
8f2466f4 | 2466 | |
54168ed7 | 2467 | ack_APIC_irq(); |
54168ed7 | 2468 | exit_idle(); |
54168ed7 IM |
2469 | irq_enter(); |
2470 | ||
2471 | me = smp_processor_id(); | |
2472 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2473 | unsigned int irq; | |
2474 | struct irq_desc *desc; | |
2475 | struct irq_cfg *cfg; | |
2476 | irq = __get_cpu_var(vector_irq)[vector]; | |
2477 | ||
0b8f1efa YL |
2478 | if (irq == -1) |
2479 | continue; | |
2480 | ||
54168ed7 IM |
2481 | desc = irq_to_desc(irq); |
2482 | if (!desc) | |
2483 | continue; | |
2484 | ||
2485 | cfg = irq_cfg(irq); | |
2486 | spin_lock(&desc->lock); | |
2487 | if (!cfg->move_cleanup_count) | |
2488 | goto unlock; | |
2489 | ||
22f65d31 | 2490 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2491 | goto unlock; |
2492 | ||
2493 | __get_cpu_var(vector_irq)[vector] = -1; | |
2494 | cfg->move_cleanup_count--; | |
2495 | unlock: | |
2496 | spin_unlock(&desc->lock); | |
2497 | } | |
2498 | ||
2499 | irq_exit(); | |
2500 | } | |
2501 | ||
3145e941 | 2502 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2503 | { |
3145e941 YL |
2504 | struct irq_desc *desc = *descp; |
2505 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2506 | unsigned vector, me; |
2507 | ||
48a1b10a YL |
2508 | if (likely(!cfg->move_in_progress)) { |
2509 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2510 | if (likely(!cfg->move_desc_pending)) | |
2511 | return; | |
2512 | ||
b9098957 | 2513 | /* domain has not changed, but affinity did */ |
48a1b10a | 2514 | me = smp_processor_id(); |
7f7ace0c | 2515 | if (cpumask_test_cpu(me, desc->affinity)) { |
48a1b10a YL |
2516 | *descp = desc = move_irq_desc(desc, me); |
2517 | /* get the new one */ | |
2518 | cfg = desc->chip_data; | |
2519 | cfg->move_desc_pending = 0; | |
2520 | } | |
2521 | #endif | |
54168ed7 | 2522 | return; |
48a1b10a | 2523 | } |
54168ed7 IM |
2524 | |
2525 | vector = ~get_irq_regs()->orig_ax; | |
2526 | me = smp_processor_id(); | |
10b888d6 YL |
2527 | |
2528 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) { | |
48a1b10a YL |
2529 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2530 | *descp = desc = move_irq_desc(desc, me); | |
2531 | /* get the new one */ | |
2532 | cfg = desc->chip_data; | |
2533 | #endif | |
22f65d31 | 2534 | send_cleanup_vector(cfg); |
10b888d6 | 2535 | } |
497c9a19 YL |
2536 | } |
2537 | #else | |
3145e941 | 2538 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2539 | #endif |
3145e941 | 2540 | |
54168ed7 IM |
2541 | #ifdef CONFIG_INTR_REMAP |
2542 | static void ack_x2apic_level(unsigned int irq) | |
2543 | { | |
2544 | ack_x2APIC_irq(); | |
2545 | } | |
2546 | ||
2547 | static void ack_x2apic_edge(unsigned int irq) | |
2548 | { | |
2549 | ack_x2APIC_irq(); | |
2550 | } | |
3145e941 | 2551 | |
54168ed7 | 2552 | #endif |
497c9a19 | 2553 | |
1d025192 YL |
2554 | static void ack_apic_edge(unsigned int irq) |
2555 | { | |
3145e941 YL |
2556 | struct irq_desc *desc = irq_to_desc(irq); |
2557 | ||
2558 | irq_complete_move(&desc); | |
1d025192 YL |
2559 | move_native_irq(irq); |
2560 | ack_APIC_irq(); | |
2561 | } | |
2562 | ||
3eb2cce8 | 2563 | atomic_t irq_mis_count; |
3eb2cce8 | 2564 | |
047c8fdb YL |
2565 | static void ack_apic_level(unsigned int irq) |
2566 | { | |
3145e941 YL |
2567 | struct irq_desc *desc = irq_to_desc(irq); |
2568 | ||
3eb2cce8 YL |
2569 | #ifdef CONFIG_X86_32 |
2570 | unsigned long v; | |
2571 | int i; | |
2572 | #endif | |
3145e941 | 2573 | struct irq_cfg *cfg; |
54168ed7 | 2574 | int do_unmask_irq = 0; |
047c8fdb | 2575 | |
3145e941 | 2576 | irq_complete_move(&desc); |
047c8fdb | 2577 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2578 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2579 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2580 | do_unmask_irq = 1; |
3145e941 | 2581 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2582 | } |
047c8fdb YL |
2583 | #endif |
2584 | ||
3eb2cce8 YL |
2585 | #ifdef CONFIG_X86_32 |
2586 | /* | |
2587 | * It appears there is an erratum which affects at least version 0x11 | |
2588 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2589 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2590 | * erroneously delivered as edge-triggered one but the respective IRR | |
2591 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2592 | * message but it will never arrive and further interrupts are blocked | |
2593 | * from the source. The exact reason is so far unknown, but the | |
2594 | * phenomenon was observed when two consecutive interrupt requests | |
2595 | * from a given source get delivered to the same CPU and the source is | |
2596 | * temporarily disabled in between. | |
2597 | * | |
2598 | * A workaround is to simulate an EOI message manually. We achieve it | |
2599 | * by setting the trigger mode to edge and then to level when the edge | |
2600 | * trigger mode gets detected in the TMR of a local APIC for a | |
2601 | * level-triggered interrupt. We mask the source for the time of the | |
2602 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2603 | * The idea is from Manfred Spraul. --macro | |
2604 | */ | |
3145e941 YL |
2605 | cfg = desc->chip_data; |
2606 | i = cfg->vector; | |
3eb2cce8 YL |
2607 | |
2608 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2609 | #endif | |
2610 | ||
54168ed7 IM |
2611 | /* |
2612 | * We must acknowledge the irq before we move it or the acknowledge will | |
2613 | * not propagate properly. | |
2614 | */ | |
2615 | ack_APIC_irq(); | |
2616 | ||
2617 | /* Now we can move and renable the irq */ | |
2618 | if (unlikely(do_unmask_irq)) { | |
2619 | /* Only migrate the irq if the ack has been received. | |
2620 | * | |
2621 | * On rare occasions the broadcast level triggered ack gets | |
2622 | * delayed going to ioapics, and if we reprogram the | |
2623 | * vector while Remote IRR is still set the irq will never | |
2624 | * fire again. | |
2625 | * | |
2626 | * To prevent this scenario we read the Remote IRR bit | |
2627 | * of the ioapic. This has two effects. | |
2628 | * - On any sane system the read of the ioapic will | |
2629 | * flush writes (and acks) going to the ioapic from | |
2630 | * this cpu. | |
2631 | * - We get to see if the ACK has actually been delivered. | |
2632 | * | |
2633 | * Based on failed experiments of reprogramming the | |
2634 | * ioapic entry from outside of irq context starting | |
2635 | * with masking the ioapic entry and then polling until | |
2636 | * Remote IRR was clear before reprogramming the | |
2637 | * ioapic I don't trust the Remote IRR bit to be | |
2638 | * completey accurate. | |
2639 | * | |
2640 | * However there appears to be no other way to plug | |
2641 | * this race, so if the Remote IRR bit is not | |
2642 | * accurate and is causing problems then it is a hardware bug | |
2643 | * and you can go talk to the chipset vendor about it. | |
2644 | */ | |
3145e941 YL |
2645 | cfg = desc->chip_data; |
2646 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2647 | move_masked_irq(irq); |
3145e941 | 2648 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2649 | } |
1d025192 | 2650 | |
3eb2cce8 | 2651 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2652 | if (!(v & (1 << (i & 0x1f)))) { |
2653 | atomic_inc(&irq_mis_count); | |
2654 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2655 | __mask_and_edge_IO_APIC_irq(cfg); |
2656 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2657 | spin_unlock(&ioapic_lock); |
2658 | } | |
047c8fdb | 2659 | #endif |
3eb2cce8 | 2660 | } |
1d025192 | 2661 | |
f5b9ed7a | 2662 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2663 | .name = "IO-APIC", |
2664 | .startup = startup_ioapic_irq, | |
2665 | .mask = mask_IO_APIC_irq, | |
2666 | .unmask = unmask_IO_APIC_irq, | |
2667 | .ack = ack_apic_edge, | |
2668 | .eoi = ack_apic_level, | |
54d5d424 | 2669 | #ifdef CONFIG_SMP |
d6c88a50 | 2670 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2671 | #endif |
ace80ab7 | 2672 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2673 | }; |
2674 | ||
54168ed7 IM |
2675 | #ifdef CONFIG_INTR_REMAP |
2676 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2677 | .name = "IR-IO-APIC", |
2678 | .startup = startup_ioapic_irq, | |
2679 | .mask = mask_IO_APIC_irq, | |
2680 | .unmask = unmask_IO_APIC_irq, | |
2681 | .ack = ack_x2apic_edge, | |
2682 | .eoi = ack_x2apic_level, | |
54168ed7 | 2683 | #ifdef CONFIG_SMP |
d6c88a50 | 2684 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2685 | #endif |
2686 | .retrigger = ioapic_retrigger_irq, | |
2687 | }; | |
2688 | #endif | |
1da177e4 LT |
2689 | |
2690 | static inline void init_IO_APIC_traps(void) | |
2691 | { | |
2692 | int irq; | |
08678b08 | 2693 | struct irq_desc *desc; |
da51a821 | 2694 | struct irq_cfg *cfg; |
1da177e4 LT |
2695 | |
2696 | /* | |
2697 | * NOTE! The local APIC isn't very good at handling | |
2698 | * multiple interrupts at the same interrupt level. | |
2699 | * As the interrupt level is determined by taking the | |
2700 | * vector number and shifting that right by 4, we | |
2701 | * want to spread these out a bit so that they don't | |
2702 | * all fall in the same interrupt level. | |
2703 | * | |
2704 | * Also, we've got to be careful not to trash gate | |
2705 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2706 | */ | |
0b8f1efa | 2707 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2708 | cfg = desc->chip_data; |
2709 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2710 | /* |
2711 | * Hmm.. We don't have an entry for this, | |
2712 | * so default to an old-fashioned 8259 | |
2713 | * interrupt if we can.. | |
2714 | */ | |
99d093d1 | 2715 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2716 | make_8259A_irq(irq); |
0b8f1efa | 2717 | else |
1da177e4 | 2718 | /* Strange. Oh, well.. */ |
08678b08 | 2719 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2720 | } |
2721 | } | |
2722 | } | |
2723 | ||
f5b9ed7a IM |
2724 | /* |
2725 | * The local APIC irq-chip implementation: | |
2726 | */ | |
1da177e4 | 2727 | |
36062448 | 2728 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2729 | { |
2730 | unsigned long v; | |
2731 | ||
2732 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2733 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2734 | } |
2735 | ||
36062448 | 2736 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2737 | { |
f5b9ed7a | 2738 | unsigned long v; |
1da177e4 | 2739 | |
f5b9ed7a | 2740 | v = apic_read(APIC_LVT0); |
593f4a78 | 2741 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2742 | } |
1da177e4 | 2743 | |
3145e941 | 2744 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2745 | { |
2746 | ack_APIC_irq(); | |
2747 | } | |
2748 | ||
f5b9ed7a | 2749 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2750 | .name = "local-APIC", |
f5b9ed7a IM |
2751 | .mask = mask_lapic_irq, |
2752 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2753 | .ack = ack_lapic_irq, |
1da177e4 LT |
2754 | }; |
2755 | ||
3145e941 | 2756 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2757 | { |
08678b08 | 2758 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2759 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2760 | "edge"); | |
c88ac1df MR |
2761 | } |
2762 | ||
e9427101 | 2763 | static void __init setup_nmi(void) |
1da177e4 LT |
2764 | { |
2765 | /* | |
36062448 | 2766 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2767 | * We put the 8259A master into AEOI mode and |
2768 | * unmask on all local APICs LVT0 as NMI. | |
2769 | * | |
2770 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2771 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2772 | * the NMI handler or the timer interrupt. | |
36062448 | 2773 | */ |
1da177e4 LT |
2774 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2775 | ||
e9427101 | 2776 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2777 | |
2778 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2779 | } | |
2780 | ||
2781 | /* | |
2782 | * This looks a bit hackish but it's about the only one way of sending | |
2783 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2784 | * not support the ExtINT mode, unfortunately. We need to send these | |
2785 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2786 | * 8259A interrupt line asserted until INTA. --macro | |
2787 | */ | |
28acf285 | 2788 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2789 | { |
fcfd636a | 2790 | int apic, pin, i; |
1da177e4 LT |
2791 | struct IO_APIC_route_entry entry0, entry1; |
2792 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2793 | |
fcfd636a | 2794 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2795 | if (pin == -1) { |
2796 | WARN_ON_ONCE(1); | |
2797 | return; | |
2798 | } | |
fcfd636a | 2799 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2800 | if (apic == -1) { |
2801 | WARN_ON_ONCE(1); | |
1da177e4 | 2802 | return; |
956fb531 | 2803 | } |
1da177e4 | 2804 | |
cf4c6a2f | 2805 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2806 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2807 | |
2808 | memset(&entry1, 0, sizeof(entry1)); | |
2809 | ||
2810 | entry1.dest_mode = 0; /* physical delivery */ | |
2811 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2812 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2813 | entry1.delivery_mode = dest_ExtINT; |
2814 | entry1.polarity = entry0.polarity; | |
2815 | entry1.trigger = 0; | |
2816 | entry1.vector = 0; | |
2817 | ||
cf4c6a2f | 2818 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2819 | |
2820 | save_control = CMOS_READ(RTC_CONTROL); | |
2821 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2822 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2823 | RTC_FREQ_SELECT); | |
2824 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2825 | ||
2826 | i = 100; | |
2827 | while (i-- > 0) { | |
2828 | mdelay(10); | |
2829 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2830 | i -= 10; | |
2831 | } | |
2832 | ||
2833 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2834 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2835 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2836 | |
cf4c6a2f | 2837 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2838 | } |
2839 | ||
efa2559f | 2840 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2841 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2842 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2843 | { |
2844 | disable_timer_pin_1 = 1; | |
2845 | return 0; | |
2846 | } | |
54168ed7 | 2847 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2848 | |
2849 | int timer_through_8259 __initdata; | |
2850 | ||
1da177e4 LT |
2851 | /* |
2852 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2853 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2854 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2855 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2856 | * |
2857 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2858 | */ |
8542b200 | 2859 | static inline void __init check_timer(void) |
1da177e4 | 2860 | { |
3145e941 YL |
2861 | struct irq_desc *desc = irq_to_desc(0); |
2862 | struct irq_cfg *cfg = desc->chip_data; | |
2863 | int cpu = boot_cpu_id; | |
fcfd636a | 2864 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2865 | unsigned long flags; |
047c8fdb | 2866 | int no_pin1 = 0; |
4aae0702 IM |
2867 | |
2868 | local_irq_save(flags); | |
d4d25dec | 2869 | |
1da177e4 LT |
2870 | /* |
2871 | * get/set the timer IRQ vector: | |
2872 | */ | |
2873 | disable_8259A_irq(0); | |
fe402e1f | 2874 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2875 | |
2876 | /* | |
d11d5794 MR |
2877 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2878 | * wire has to be disabled in the local APIC. Also | |
2879 | * timer interrupts need to be acknowledged manually in | |
2880 | * the 8259A for the i82489DX when using the NMI | |
2881 | * watchdog as that APIC treats NMIs as level-triggered. | |
2882 | * The AEOI mode will finish them in the 8259A | |
2883 | * automatically. | |
1da177e4 | 2884 | */ |
593f4a78 | 2885 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2886 | init_8259A(1); |
54168ed7 | 2887 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2888 | { |
2889 | unsigned int ver; | |
2890 | ||
2891 | ver = apic_read(APIC_LVR); | |
2892 | ver = GET_APIC_VERSION(ver); | |
2893 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2894 | } | |
54168ed7 | 2895 | #endif |
1da177e4 | 2896 | |
fcfd636a EB |
2897 | pin1 = find_isa_irq_pin(0, mp_INT); |
2898 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2899 | pin2 = ioapic_i8259.pin; | |
2900 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2901 | |
49a66a0b MR |
2902 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2903 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2904 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2905 | |
691874fa MR |
2906 | /* |
2907 | * Some BIOS writers are clueless and report the ExtINTA | |
2908 | * I/O APIC input from the cascaded 8259A as the timer | |
2909 | * interrupt input. So just in case, if only one pin | |
2910 | * was found above, try it both directly and through the | |
2911 | * 8259A. | |
2912 | */ | |
2913 | if (pin1 == -1) { | |
54168ed7 IM |
2914 | #ifdef CONFIG_INTR_REMAP |
2915 | if (intr_remapping_enabled) | |
2916 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2917 | #endif | |
691874fa MR |
2918 | pin1 = pin2; |
2919 | apic1 = apic2; | |
2920 | no_pin1 = 1; | |
2921 | } else if (pin2 == -1) { | |
2922 | pin2 = pin1; | |
2923 | apic2 = apic1; | |
2924 | } | |
2925 | ||
1da177e4 LT |
2926 | if (pin1 != -1) { |
2927 | /* | |
2928 | * Ok, does IRQ0 through the IOAPIC work? | |
2929 | */ | |
691874fa | 2930 | if (no_pin1) { |
3145e941 | 2931 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2932 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2933 | } else { |
2934 | /* for edge trigger, setup_IO_APIC_irq already | |
2935 | * leave it unmasked. | |
2936 | * so only need to unmask if it is level-trigger | |
2937 | * do we really have level trigger timer? | |
2938 | */ | |
2939 | int idx; | |
2940 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2941 | if (idx != -1 && irq_trigger(idx)) | |
2942 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2943 | } |
1da177e4 LT |
2944 | if (timer_irq_works()) { |
2945 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2946 | setup_nmi(); |
2947 | enable_8259A_irq(0); | |
1da177e4 | 2948 | } |
66759a01 CE |
2949 | if (disable_timer_pin_1 > 0) |
2950 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2951 | goto out; |
1da177e4 | 2952 | } |
54168ed7 IM |
2953 | #ifdef CONFIG_INTR_REMAP |
2954 | if (intr_remapping_enabled) | |
2955 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2956 | #endif | |
f72dccac | 2957 | local_irq_disable(); |
fcfd636a | 2958 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2959 | if (!no_pin1) |
49a66a0b MR |
2960 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2961 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2962 | |
49a66a0b MR |
2963 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2964 | "(IRQ0) through the 8259A ...\n"); | |
2965 | apic_printk(APIC_QUIET, KERN_INFO | |
2966 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2967 | /* |
2968 | * legacy devices should be connected to IO APIC #0 | |
2969 | */ | |
3145e941 | 2970 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2971 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2972 | enable_8259A_irq(0); |
1da177e4 | 2973 | if (timer_irq_works()) { |
49a66a0b | 2974 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2975 | timer_through_8259 = 1; |
1da177e4 | 2976 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2977 | disable_8259A_irq(0); |
1da177e4 | 2978 | setup_nmi(); |
60134ebe | 2979 | enable_8259A_irq(0); |
1da177e4 | 2980 | } |
4aae0702 | 2981 | goto out; |
1da177e4 LT |
2982 | } |
2983 | /* | |
2984 | * Cleanup, just in case ... | |
2985 | */ | |
f72dccac | 2986 | local_irq_disable(); |
ecd29476 | 2987 | disable_8259A_irq(0); |
fcfd636a | 2988 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2989 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2990 | } |
1da177e4 LT |
2991 | |
2992 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2993 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2994 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2995 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2996 | } |
54168ed7 | 2997 | #ifdef CONFIG_X86_32 |
d11d5794 | 2998 | timer_ack = 0; |
54168ed7 | 2999 | #endif |
1da177e4 | 3000 | |
49a66a0b MR |
3001 | apic_printk(APIC_QUIET, KERN_INFO |
3002 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3003 | |
3145e941 | 3004 | lapic_register_intr(0, desc); |
497c9a19 | 3005 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3006 | enable_8259A_irq(0); |
3007 | ||
3008 | if (timer_irq_works()) { | |
49a66a0b | 3009 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3010 | goto out; |
1da177e4 | 3011 | } |
f72dccac | 3012 | local_irq_disable(); |
e67465f1 | 3013 | disable_8259A_irq(0); |
497c9a19 | 3014 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3015 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3016 | |
49a66a0b MR |
3017 | apic_printk(APIC_QUIET, KERN_INFO |
3018 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3019 | |
1da177e4 LT |
3020 | init_8259A(0); |
3021 | make_8259A_irq(0); | |
593f4a78 | 3022 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3023 | |
3024 | unlock_ExtINT_logic(); | |
3025 | ||
3026 | if (timer_irq_works()) { | |
49a66a0b | 3027 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3028 | goto out; |
1da177e4 | 3029 | } |
f72dccac | 3030 | local_irq_disable(); |
49a66a0b | 3031 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3032 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3033 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3034 | out: |
3035 | local_irq_restore(flags); | |
1da177e4 LT |
3036 | } |
3037 | ||
3038 | /* | |
af174783 MR |
3039 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3040 | * to devices. However there may be an I/O APIC pin available for | |
3041 | * this interrupt regardless. The pin may be left unconnected, but | |
3042 | * typically it will be reused as an ExtINT cascade interrupt for | |
3043 | * the master 8259A. In the MPS case such a pin will normally be | |
3044 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3045 | * there is no provision for ExtINT interrupts, and in the absence | |
3046 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3047 | * interrupt, that is edge-triggered and unmasked by default. We | |
3048 | * used to do this, but it caused problems on some systems because | |
3049 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3050 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3051 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3052 | * the I/O APIC in all cases now. No actual device should request | |
3053 | * it anyway. --macro | |
1da177e4 LT |
3054 | */ |
3055 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3056 | ||
3057 | void __init setup_IO_APIC(void) | |
3058 | { | |
54168ed7 IM |
3059 | |
3060 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3061 | enable_IO_APIC(); |
54168ed7 IM |
3062 | #else |
3063 | /* | |
3064 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3065 | */ | |
3066 | #endif | |
1da177e4 | 3067 | |
af174783 | 3068 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3069 | |
54168ed7 | 3070 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3071 | /* |
54168ed7 IM |
3072 | * Set up IO-APIC IRQ routing. |
3073 | */ | |
3074 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3075 | if (!acpi_ioapic) |
3076 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3077 | #endif |
1da177e4 LT |
3078 | sync_Arb_IDs(); |
3079 | setup_IO_APIC_irqs(); | |
3080 | init_IO_APIC_traps(); | |
1e4c85f9 | 3081 | check_timer(); |
1da177e4 LT |
3082 | } |
3083 | ||
3084 | /* | |
54168ed7 IM |
3085 | * Called after all the initialization is done. If we didnt find any |
3086 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3087 | */ |
36062448 | 3088 | |
1da177e4 LT |
3089 | static int __init io_apic_bug_finalize(void) |
3090 | { | |
d6c88a50 TG |
3091 | if (sis_apic_bug == -1) |
3092 | sis_apic_bug = 0; | |
3093 | return 0; | |
1da177e4 LT |
3094 | } |
3095 | ||
3096 | late_initcall(io_apic_bug_finalize); | |
3097 | ||
3098 | struct sysfs_ioapic_data { | |
3099 | struct sys_device dev; | |
3100 | struct IO_APIC_route_entry entry[0]; | |
3101 | }; | |
54168ed7 | 3102 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3103 | |
438510f6 | 3104 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3105 | { |
3106 | struct IO_APIC_route_entry *entry; | |
3107 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3108 | int i; |
36062448 | 3109 | |
1da177e4 LT |
3110 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3111 | entry = data->entry; | |
54168ed7 IM |
3112 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3113 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3114 | |
3115 | return 0; | |
3116 | } | |
3117 | ||
3118 | static int ioapic_resume(struct sys_device *dev) | |
3119 | { | |
3120 | struct IO_APIC_route_entry *entry; | |
3121 | struct sysfs_ioapic_data *data; | |
3122 | unsigned long flags; | |
3123 | union IO_APIC_reg_00 reg_00; | |
3124 | int i; | |
36062448 | 3125 | |
1da177e4 LT |
3126 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3127 | entry = data->entry; | |
3128 | ||
3129 | spin_lock_irqsave(&ioapic_lock, flags); | |
3130 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3131 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3132 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3133 | io_apic_write(dev->id, 0, reg_00.raw); |
3134 | } | |
1da177e4 | 3135 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3136 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3137 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3138 | |
3139 | return 0; | |
3140 | } | |
3141 | ||
3142 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3143 | .name = "ioapic", |
1da177e4 LT |
3144 | .suspend = ioapic_suspend, |
3145 | .resume = ioapic_resume, | |
3146 | }; | |
3147 | ||
3148 | static int __init ioapic_init_sysfs(void) | |
3149 | { | |
54168ed7 IM |
3150 | struct sys_device * dev; |
3151 | int i, size, error; | |
1da177e4 LT |
3152 | |
3153 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3154 | if (error) | |
3155 | return error; | |
3156 | ||
54168ed7 | 3157 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3158 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3159 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3160 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3161 | if (!mp_ioapic_data[i]) { |
3162 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3163 | continue; | |
3164 | } | |
1da177e4 | 3165 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3166 | dev->id = i; |
1da177e4 LT |
3167 | dev->cls = &ioapic_sysdev_class; |
3168 | error = sysdev_register(dev); | |
3169 | if (error) { | |
3170 | kfree(mp_ioapic_data[i]); | |
3171 | mp_ioapic_data[i] = NULL; | |
3172 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3173 | continue; | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | return 0; | |
3178 | } | |
3179 | ||
3180 | device_initcall(ioapic_init_sysfs); | |
3181 | ||
abcaa2b8 | 3182 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3183 | /* |
95d77884 | 3184 | * Dynamic irq allocate and deallocation |
3fc471ed | 3185 | */ |
199751d7 | 3186 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3187 | { |
ace80ab7 | 3188 | /* Allocate an unused irq */ |
54168ed7 IM |
3189 | unsigned int irq; |
3190 | unsigned int new; | |
3fc471ed | 3191 | unsigned long flags; |
0b8f1efa YL |
3192 | struct irq_cfg *cfg_new = NULL; |
3193 | int cpu = boot_cpu_id; | |
3194 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3195 | |
3196 | irq = 0; | |
abcaa2b8 YL |
3197 | if (irq_want < nr_irqs_gsi) |
3198 | irq_want = nr_irqs_gsi; | |
3199 | ||
ace80ab7 | 3200 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3201 | for (new = irq_want; new < nr_irqs; new++) { |
0b8f1efa YL |
3202 | desc_new = irq_to_desc_alloc_cpu(new, cpu); |
3203 | if (!desc_new) { | |
3204 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3205 | continue; |
0b8f1efa YL |
3206 | } |
3207 | cfg_new = desc_new->chip_data; | |
3208 | ||
3209 | if (cfg_new->vector != 0) | |
ace80ab7 | 3210 | continue; |
fe402e1f | 3211 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3212 | irq = new; |
3213 | break; | |
3214 | } | |
3215 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3216 | |
199751d7 | 3217 | if (irq > 0) { |
3fc471ed | 3218 | dynamic_irq_init(irq); |
0b8f1efa YL |
3219 | /* restore it, in case dynamic_irq_init clear it */ |
3220 | if (desc_new) | |
3221 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3222 | } |
3223 | return irq; | |
3224 | } | |
3225 | ||
199751d7 YL |
3226 | int create_irq(void) |
3227 | { | |
be5d5350 | 3228 | unsigned int irq_want; |
54168ed7 IM |
3229 | int irq; |
3230 | ||
be5d5350 YL |
3231 | irq_want = nr_irqs_gsi; |
3232 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3233 | |
3234 | if (irq == 0) | |
3235 | irq = -1; | |
3236 | ||
3237 | return irq; | |
199751d7 YL |
3238 | } |
3239 | ||
3fc471ed EB |
3240 | void destroy_irq(unsigned int irq) |
3241 | { | |
3242 | unsigned long flags; | |
0b8f1efa YL |
3243 | struct irq_cfg *cfg; |
3244 | struct irq_desc *desc; | |
3fc471ed | 3245 | |
0b8f1efa YL |
3246 | /* store it, in case dynamic_irq_cleanup clear it */ |
3247 | desc = irq_to_desc(irq); | |
3248 | cfg = desc->chip_data; | |
3fc471ed | 3249 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3250 | /* connect back irq_cfg */ |
3251 | if (desc) | |
3252 | desc->chip_data = cfg; | |
3fc471ed | 3253 | |
54168ed7 IM |
3254 | #ifdef CONFIG_INTR_REMAP |
3255 | free_irte(irq); | |
3256 | #endif | |
3fc471ed | 3257 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3258 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3259 | spin_unlock_irqrestore(&vector_lock, flags); |
3260 | } | |
3fc471ed | 3261 | |
2d3fcc1c | 3262 | /* |
27b46d76 | 3263 | * MSI message composition |
2d3fcc1c EB |
3264 | */ |
3265 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3266 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3267 | { |
497c9a19 YL |
3268 | struct irq_cfg *cfg; |
3269 | int err; | |
2d3fcc1c EB |
3270 | unsigned dest; |
3271 | ||
f1182638 JB |
3272 | if (disable_apic) |
3273 | return -ENXIO; | |
3274 | ||
3145e941 | 3275 | cfg = irq_cfg(irq); |
fe402e1f | 3276 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3277 | if (err) |
3278 | return err; | |
2d3fcc1c | 3279 | |
debccb3e | 3280 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3281 | |
54168ed7 IM |
3282 | #ifdef CONFIG_INTR_REMAP |
3283 | if (irq_remapped(irq)) { | |
3284 | struct irte irte; | |
3285 | int ir_index; | |
3286 | u16 sub_handle; | |
3287 | ||
3288 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3289 | BUG_ON(ir_index == -1); | |
3290 | ||
3291 | memset (&irte, 0, sizeof(irte)); | |
3292 | ||
3293 | irte.present = 1; | |
9b5bc8dc | 3294 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3295 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3296 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3297 | irte.vector = cfg->vector; |
3298 | irte.dest_id = IRTE_DEST(dest); | |
3299 | ||
3300 | modify_irte(irq, &irte); | |
3301 | ||
3302 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3303 | msg->data = sub_handle; | |
3304 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3305 | MSI_ADDR_IR_SHV | | |
3306 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3307 | MSI_ADDR_IR_INDEX2(ir_index); | |
3308 | } else | |
3309 | #endif | |
3310 | { | |
3311 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3312 | msg->address_lo = | |
3313 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3314 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3315 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3316 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3317 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3318 | MSI_ADDR_REDIRECTION_CPU: |
3319 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3320 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3321 | |
54168ed7 IM |
3322 | msg->data = |
3323 | MSI_DATA_TRIGGER_EDGE | | |
3324 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3325 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3326 | MSI_DATA_DELIVERY_FIXED: |
3327 | MSI_DATA_DELIVERY_LOWPRI) | | |
3328 | MSI_DATA_VECTOR(cfg->vector); | |
3329 | } | |
497c9a19 | 3330 | return err; |
2d3fcc1c EB |
3331 | } |
3332 | ||
3b7d1921 | 3333 | #ifdef CONFIG_SMP |
0de26520 | 3334 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3335 | { |
3145e941 | 3336 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3337 | struct irq_cfg *cfg; |
3b7d1921 EB |
3338 | struct msi_msg msg; |
3339 | unsigned int dest; | |
3b7d1921 | 3340 | |
22f65d31 MT |
3341 | dest = set_desc_affinity(desc, mask); |
3342 | if (dest == BAD_APICID) | |
497c9a19 | 3343 | return; |
2d3fcc1c | 3344 | |
3145e941 | 3345 | cfg = desc->chip_data; |
2d3fcc1c | 3346 | |
3145e941 | 3347 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3348 | |
3349 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3350 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3351 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3352 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3353 | ||
3145e941 | 3354 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3355 | } |
54168ed7 IM |
3356 | #ifdef CONFIG_INTR_REMAP |
3357 | /* | |
3358 | * Migrate the MSI irq to another cpumask. This migration is | |
3359 | * done in the process context using interrupt-remapping hardware. | |
3360 | */ | |
e7986739 MT |
3361 | static void |
3362 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3363 | { |
3145e941 | 3364 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3365 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3366 | unsigned int dest; |
54168ed7 | 3367 | struct irte irte; |
54168ed7 IM |
3368 | |
3369 | if (get_irte(irq, &irte)) | |
3370 | return; | |
3371 | ||
22f65d31 MT |
3372 | dest = set_desc_affinity(desc, mask); |
3373 | if (dest == BAD_APICID) | |
54168ed7 IM |
3374 | return; |
3375 | ||
54168ed7 IM |
3376 | irte.vector = cfg->vector; |
3377 | irte.dest_id = IRTE_DEST(dest); | |
3378 | ||
3379 | /* | |
3380 | * atomically update the IRTE with the new destination and vector. | |
3381 | */ | |
3382 | modify_irte(irq, &irte); | |
3383 | ||
3384 | /* | |
3385 | * After this point, all the interrupts will start arriving | |
3386 | * at the new destination. So, time to cleanup the previous | |
3387 | * vector allocation. | |
3388 | */ | |
22f65d31 MT |
3389 | if (cfg->move_in_progress) |
3390 | send_cleanup_vector(cfg); | |
54168ed7 | 3391 | } |
3145e941 | 3392 | |
54168ed7 | 3393 | #endif |
3b7d1921 | 3394 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3395 | |
3b7d1921 EB |
3396 | /* |
3397 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3398 | * which implement the MSI or MSI-X Capability Structure. | |
3399 | */ | |
3400 | static struct irq_chip msi_chip = { | |
3401 | .name = "PCI-MSI", | |
3402 | .unmask = unmask_msi_irq, | |
3403 | .mask = mask_msi_irq, | |
1d025192 | 3404 | .ack = ack_apic_edge, |
3b7d1921 EB |
3405 | #ifdef CONFIG_SMP |
3406 | .set_affinity = set_msi_irq_affinity, | |
3407 | #endif | |
3408 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3409 | }; |
3410 | ||
54168ed7 IM |
3411 | #ifdef CONFIG_INTR_REMAP |
3412 | static struct irq_chip msi_ir_chip = { | |
3413 | .name = "IR-PCI-MSI", | |
3414 | .unmask = unmask_msi_irq, | |
3415 | .mask = mask_msi_irq, | |
3416 | .ack = ack_x2apic_edge, | |
3417 | #ifdef CONFIG_SMP | |
3418 | .set_affinity = ir_set_msi_irq_affinity, | |
3419 | #endif | |
3420 | .retrigger = ioapic_retrigger_irq, | |
3421 | }; | |
3422 | ||
3423 | /* | |
3424 | * Map the PCI dev to the corresponding remapping hardware unit | |
3425 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3426 | * in it. | |
3427 | */ | |
3428 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3429 | { | |
3430 | struct intel_iommu *iommu; | |
3431 | int index; | |
3432 | ||
3433 | iommu = map_dev_to_ir(dev); | |
3434 | if (!iommu) { | |
3435 | printk(KERN_ERR | |
3436 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3437 | return -ENOENT; | |
3438 | } | |
3439 | ||
3440 | index = alloc_irte(iommu, irq, nvec); | |
3441 | if (index < 0) { | |
3442 | printk(KERN_ERR | |
3443 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3444 | pci_name(dev)); |
54168ed7 IM |
3445 | return -ENOSPC; |
3446 | } | |
3447 | return index; | |
3448 | } | |
3449 | #endif | |
1d025192 | 3450 | |
3145e941 | 3451 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3452 | { |
3453 | int ret; | |
3454 | struct msi_msg msg; | |
3455 | ||
3456 | ret = msi_compose_msg(dev, irq, &msg); | |
3457 | if (ret < 0) | |
3458 | return ret; | |
3459 | ||
3145e941 | 3460 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3461 | write_msi_msg(irq, &msg); |
3462 | ||
54168ed7 IM |
3463 | #ifdef CONFIG_INTR_REMAP |
3464 | if (irq_remapped(irq)) { | |
3465 | struct irq_desc *desc = irq_to_desc(irq); | |
3466 | /* | |
3467 | * irq migration in process context | |
3468 | */ | |
3469 | desc->status |= IRQ_MOVE_PCNTXT; | |
3470 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3471 | } else | |
3472 | #endif | |
3473 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3474 | |
c81bba49 YL |
3475 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3476 | ||
1d025192 YL |
3477 | return 0; |
3478 | } | |
3479 | ||
047c8fdb YL |
3480 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3481 | { | |
54168ed7 IM |
3482 | unsigned int irq; |
3483 | int ret, sub_handle; | |
0b8f1efa | 3484 | struct msi_desc *msidesc; |
54168ed7 IM |
3485 | unsigned int irq_want; |
3486 | ||
3487 | #ifdef CONFIG_INTR_REMAP | |
3488 | struct intel_iommu *iommu = 0; | |
3489 | int index = 0; | |
3490 | #endif | |
3491 | ||
be5d5350 | 3492 | irq_want = nr_irqs_gsi; |
54168ed7 | 3493 | sub_handle = 0; |
0b8f1efa YL |
3494 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3495 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3496 | if (irq == 0) |
3497 | return -1; | |
f1ee5548 | 3498 | irq_want = irq + 1; |
54168ed7 IM |
3499 | #ifdef CONFIG_INTR_REMAP |
3500 | if (!intr_remapping_enabled) | |
3501 | goto no_ir; | |
3502 | ||
3503 | if (!sub_handle) { | |
3504 | /* | |
3505 | * allocate the consecutive block of IRTE's | |
3506 | * for 'nvec' | |
3507 | */ | |
3508 | index = msi_alloc_irte(dev, irq, nvec); | |
3509 | if (index < 0) { | |
3510 | ret = index; | |
3511 | goto error; | |
3512 | } | |
3513 | } else { | |
3514 | iommu = map_dev_to_ir(dev); | |
3515 | if (!iommu) { | |
3516 | ret = -ENOENT; | |
3517 | goto error; | |
3518 | } | |
3519 | /* | |
3520 | * setup the mapping between the irq and the IRTE | |
3521 | * base index, the sub_handle pointing to the | |
3522 | * appropriate interrupt remap table entry. | |
3523 | */ | |
3524 | set_irte_irq(irq, iommu, index, sub_handle); | |
3525 | } | |
3526 | no_ir: | |
3527 | #endif | |
0b8f1efa | 3528 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3529 | if (ret < 0) |
3530 | goto error; | |
3531 | sub_handle++; | |
3532 | } | |
3533 | return 0; | |
047c8fdb YL |
3534 | |
3535 | error: | |
54168ed7 IM |
3536 | destroy_irq(irq); |
3537 | return ret; | |
047c8fdb YL |
3538 | } |
3539 | ||
3b7d1921 EB |
3540 | void arch_teardown_msi_irq(unsigned int irq) |
3541 | { | |
f7feaca7 | 3542 | destroy_irq(irq); |
3b7d1921 EB |
3543 | } |
3544 | ||
54168ed7 IM |
3545 | #ifdef CONFIG_DMAR |
3546 | #ifdef CONFIG_SMP | |
22f65d31 | 3547 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3548 | { |
3145e941 | 3549 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3550 | struct irq_cfg *cfg; |
3551 | struct msi_msg msg; | |
3552 | unsigned int dest; | |
54168ed7 | 3553 | |
22f65d31 MT |
3554 | dest = set_desc_affinity(desc, mask); |
3555 | if (dest == BAD_APICID) | |
54168ed7 IM |
3556 | return; |
3557 | ||
3145e941 | 3558 | cfg = desc->chip_data; |
54168ed7 IM |
3559 | |
3560 | dmar_msi_read(irq, &msg); | |
3561 | ||
3562 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3563 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3564 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3565 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3566 | ||
3567 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3568 | } |
3145e941 | 3569 | |
54168ed7 IM |
3570 | #endif /* CONFIG_SMP */ |
3571 | ||
3572 | struct irq_chip dmar_msi_type = { | |
3573 | .name = "DMAR_MSI", | |
3574 | .unmask = dmar_msi_unmask, | |
3575 | .mask = dmar_msi_mask, | |
3576 | .ack = ack_apic_edge, | |
3577 | #ifdef CONFIG_SMP | |
3578 | .set_affinity = dmar_msi_set_affinity, | |
3579 | #endif | |
3580 | .retrigger = ioapic_retrigger_irq, | |
3581 | }; | |
3582 | ||
3583 | int arch_setup_dmar_msi(unsigned int irq) | |
3584 | { | |
3585 | int ret; | |
3586 | struct msi_msg msg; | |
2d3fcc1c | 3587 | |
54168ed7 IM |
3588 | ret = msi_compose_msg(NULL, irq, &msg); |
3589 | if (ret < 0) | |
3590 | return ret; | |
3591 | dmar_msi_write(irq, &msg); | |
3592 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3593 | "edge"); | |
3594 | return 0; | |
3595 | } | |
3596 | #endif | |
3597 | ||
58ac1e76 | 3598 | #ifdef CONFIG_HPET_TIMER |
3599 | ||
3600 | #ifdef CONFIG_SMP | |
22f65d31 | 3601 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3602 | { |
3145e941 | 3603 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3604 | struct irq_cfg *cfg; |
58ac1e76 | 3605 | struct msi_msg msg; |
3606 | unsigned int dest; | |
58ac1e76 | 3607 | |
22f65d31 MT |
3608 | dest = set_desc_affinity(desc, mask); |
3609 | if (dest == BAD_APICID) | |
58ac1e76 | 3610 | return; |
3611 | ||
3145e941 | 3612 | cfg = desc->chip_data; |
58ac1e76 | 3613 | |
3614 | hpet_msi_read(irq, &msg); | |
3615 | ||
3616 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3617 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3618 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3619 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3620 | ||
3621 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3622 | } |
3145e941 | 3623 | |
58ac1e76 | 3624 | #endif /* CONFIG_SMP */ |
3625 | ||
3626 | struct irq_chip hpet_msi_type = { | |
3627 | .name = "HPET_MSI", | |
3628 | .unmask = hpet_msi_unmask, | |
3629 | .mask = hpet_msi_mask, | |
3630 | .ack = ack_apic_edge, | |
3631 | #ifdef CONFIG_SMP | |
3632 | .set_affinity = hpet_msi_set_affinity, | |
3633 | #endif | |
3634 | .retrigger = ioapic_retrigger_irq, | |
3635 | }; | |
3636 | ||
3637 | int arch_setup_hpet_msi(unsigned int irq) | |
3638 | { | |
3639 | int ret; | |
3640 | struct msi_msg msg; | |
3641 | ||
3642 | ret = msi_compose_msg(NULL, irq, &msg); | |
3643 | if (ret < 0) | |
3644 | return ret; | |
3645 | ||
3646 | hpet_msi_write(irq, &msg); | |
3647 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3648 | "edge"); | |
c81bba49 | 3649 | |
58ac1e76 | 3650 | return 0; |
3651 | } | |
3652 | #endif | |
3653 | ||
54168ed7 | 3654 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3655 | /* |
3656 | * Hypertransport interrupt support | |
3657 | */ | |
3658 | #ifdef CONFIG_HT_IRQ | |
3659 | ||
3660 | #ifdef CONFIG_SMP | |
3661 | ||
497c9a19 | 3662 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3663 | { |
ec68307c EB |
3664 | struct ht_irq_msg msg; |
3665 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3666 | |
497c9a19 | 3667 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3668 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3669 | |
497c9a19 | 3670 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3671 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3672 | |
ec68307c | 3673 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3674 | } |
3675 | ||
22f65d31 | 3676 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3677 | { |
3145e941 | 3678 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3679 | struct irq_cfg *cfg; |
8b955b0d | 3680 | unsigned int dest; |
8b955b0d | 3681 | |
22f65d31 MT |
3682 | dest = set_desc_affinity(desc, mask); |
3683 | if (dest == BAD_APICID) | |
497c9a19 | 3684 | return; |
8b955b0d | 3685 | |
3145e941 | 3686 | cfg = desc->chip_data; |
8b955b0d | 3687 | |
497c9a19 | 3688 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3689 | } |
3145e941 | 3690 | |
8b955b0d EB |
3691 | #endif |
3692 | ||
c37e108d | 3693 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3694 | .name = "PCI-HT", |
3695 | .mask = mask_ht_irq, | |
3696 | .unmask = unmask_ht_irq, | |
1d025192 | 3697 | .ack = ack_apic_edge, |
8b955b0d EB |
3698 | #ifdef CONFIG_SMP |
3699 | .set_affinity = set_ht_irq_affinity, | |
3700 | #endif | |
3701 | .retrigger = ioapic_retrigger_irq, | |
3702 | }; | |
3703 | ||
3704 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3705 | { | |
497c9a19 YL |
3706 | struct irq_cfg *cfg; |
3707 | int err; | |
8b955b0d | 3708 | |
f1182638 JB |
3709 | if (disable_apic) |
3710 | return -ENXIO; | |
3711 | ||
3145e941 | 3712 | cfg = irq_cfg(irq); |
fe402e1f | 3713 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3714 | if (!err) { |
ec68307c | 3715 | struct ht_irq_msg msg; |
8b955b0d | 3716 | unsigned dest; |
8b955b0d | 3717 | |
debccb3e IM |
3718 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3719 | apic->target_cpus()); | |
8b955b0d | 3720 | |
ec68307c | 3721 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3722 | |
ec68307c EB |
3723 | msg.address_lo = |
3724 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3725 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3726 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3727 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3728 | HT_IRQ_LOW_DM_PHYSICAL : |
3729 | HT_IRQ_LOW_DM_LOGICAL) | | |
3730 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3731 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3732 | HT_IRQ_LOW_MT_FIXED : |
3733 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3734 | HT_IRQ_LOW_IRQ_MASKED; | |
3735 | ||
ec68307c | 3736 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3737 | |
a460e745 IM |
3738 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3739 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3740 | |
3741 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3742 | } |
497c9a19 | 3743 | return err; |
8b955b0d EB |
3744 | } |
3745 | #endif /* CONFIG_HT_IRQ */ | |
3746 | ||
03b48632 | 3747 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3748 | /* |
3749 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3750 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3751 | */ | |
3752 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3753 | unsigned long mmr_offset) | |
3754 | { | |
22f65d31 | 3755 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3756 | struct irq_cfg *cfg; |
3757 | int mmr_pnode; | |
3758 | unsigned long mmr_value; | |
3759 | struct uv_IO_APIC_route_entry *entry; | |
3760 | unsigned long flags; | |
3761 | int err; | |
3762 | ||
3145e941 YL |
3763 | cfg = irq_cfg(irq); |
3764 | ||
e7986739 | 3765 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3766 | if (err != 0) |
3767 | return err; | |
3768 | ||
3769 | spin_lock_irqsave(&vector_lock, flags); | |
3770 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3771 | irq_name); | |
3772 | spin_unlock_irqrestore(&vector_lock, flags); | |
3773 | ||
4173a0e7 DN |
3774 | mmr_value = 0; |
3775 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3776 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3777 | ||
3778 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3779 | entry->delivery_mode = apic->irq_delivery_mode; |
3780 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3781 | entry->polarity = 0; |
3782 | entry->trigger = 0; | |
3783 | entry->mask = 0; | |
debccb3e | 3784 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3785 | |
3786 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3787 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3788 | ||
3789 | return irq; | |
3790 | } | |
3791 | ||
3792 | /* | |
3793 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3794 | * longer allowed to be sent. | |
3795 | */ | |
3796 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3797 | { | |
3798 | unsigned long mmr_value; | |
3799 | struct uv_IO_APIC_route_entry *entry; | |
3800 | int mmr_pnode; | |
3801 | ||
3802 | mmr_value = 0; | |
3803 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3804 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3805 | ||
3806 | entry->mask = 1; | |
3807 | ||
3808 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3809 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3810 | } | |
3811 | #endif /* CONFIG_X86_64 */ | |
3812 | ||
9d6a4d08 YL |
3813 | int __init io_apic_get_redir_entries (int ioapic) |
3814 | { | |
3815 | union IO_APIC_reg_01 reg_01; | |
3816 | unsigned long flags; | |
3817 | ||
3818 | spin_lock_irqsave(&ioapic_lock, flags); | |
3819 | reg_01.raw = io_apic_read(ioapic, 1); | |
3820 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3821 | ||
3822 | return reg_01.bits.entries; | |
3823 | } | |
3824 | ||
be5d5350 | 3825 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3826 | { |
be5d5350 YL |
3827 | int idx; |
3828 | int nr = 0; | |
3829 | ||
3830 | for (idx = 0; idx < nr_ioapics; idx++) | |
3831 | nr += io_apic_get_redir_entries(idx) + 1; | |
3832 | ||
3833 | if (nr > nr_irqs_gsi) | |
3834 | nr_irqs_gsi = nr; | |
9d6a4d08 YL |
3835 | } |
3836 | ||
4a046d17 YL |
3837 | #ifdef CONFIG_SPARSE_IRQ |
3838 | int __init arch_probe_nr_irqs(void) | |
3839 | { | |
3840 | int nr; | |
3841 | ||
f1ee5548 YL |
3842 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3843 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3844 | |
f1ee5548 YL |
3845 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3846 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3847 | /* | |
3848 | * for MSI and HT dyn irq | |
3849 | */ | |
3850 | nr += nr_irqs_gsi * 16; | |
3851 | #endif | |
3852 | if (nr < nr_irqs) | |
4a046d17 YL |
3853 | nr_irqs = nr; |
3854 | ||
3855 | return 0; | |
3856 | } | |
3857 | #endif | |
3858 | ||
1da177e4 | 3859 | /* -------------------------------------------------------------------------- |
54168ed7 | 3860 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3861 | -------------------------------------------------------------------------- */ |
3862 | ||
888ba6c6 | 3863 | #ifdef CONFIG_ACPI |
1da177e4 | 3864 | |
54168ed7 | 3865 | #ifdef CONFIG_X86_32 |
36062448 | 3866 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3867 | { |
3868 | union IO_APIC_reg_00 reg_00; | |
3869 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3870 | physid_mask_t tmp; | |
3871 | unsigned long flags; | |
3872 | int i = 0; | |
3873 | ||
3874 | /* | |
36062448 PC |
3875 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3876 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3877 | * supports up to 16 on one shared APIC bus. |
36062448 | 3878 | * |
1da177e4 LT |
3879 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3880 | * advantage of new APIC bus architecture. | |
3881 | */ | |
3882 | ||
3883 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3884 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3885 | |
3886 | spin_lock_irqsave(&ioapic_lock, flags); | |
3887 | reg_00.raw = io_apic_read(ioapic, 0); | |
3888 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3889 | ||
3890 | if (apic_id >= get_physical_broadcast()) { | |
3891 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3892 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3893 | apic_id = reg_00.bits.ID; | |
3894 | } | |
3895 | ||
3896 | /* | |
36062448 | 3897 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3898 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3899 | */ | |
d1d7cae8 | 3900 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3901 | |
3902 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3903 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3904 | break; |
3905 | } | |
3906 | ||
3907 | if (i == get_physical_broadcast()) | |
3908 | panic("Max apic_id exceeded!\n"); | |
3909 | ||
3910 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3911 | "trying %d\n", ioapic, apic_id, i); | |
3912 | ||
3913 | apic_id = i; | |
36062448 | 3914 | } |
1da177e4 | 3915 | |
8058714a | 3916 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3917 | physids_or(apic_id_map, apic_id_map, tmp); |
3918 | ||
3919 | if (reg_00.bits.ID != apic_id) { | |
3920 | reg_00.bits.ID = apic_id; | |
3921 | ||
3922 | spin_lock_irqsave(&ioapic_lock, flags); | |
3923 | io_apic_write(ioapic, 0, reg_00.raw); | |
3924 | reg_00.raw = io_apic_read(ioapic, 0); | |
3925 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3926 | ||
3927 | /* Sanity check */ | |
6070f9ec AD |
3928 | if (reg_00.bits.ID != apic_id) { |
3929 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3930 | return -1; | |
3931 | } | |
1da177e4 LT |
3932 | } |
3933 | ||
3934 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3935 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3936 | ||
3937 | return apic_id; | |
3938 | } | |
3939 | ||
36062448 | 3940 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3941 | { |
3942 | union IO_APIC_reg_01 reg_01; | |
3943 | unsigned long flags; | |
3944 | ||
3945 | spin_lock_irqsave(&ioapic_lock, flags); | |
3946 | reg_01.raw = io_apic_read(ioapic, 1); | |
3947 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3948 | ||
3949 | return reg_01.bits.version; | |
3950 | } | |
54168ed7 | 3951 | #endif |
1da177e4 | 3952 | |
54168ed7 | 3953 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3954 | { |
0b8f1efa YL |
3955 | struct irq_desc *desc; |
3956 | struct irq_cfg *cfg; | |
3957 | int cpu = boot_cpu_id; | |
3958 | ||
1da177e4 | 3959 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3960 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3961 | ioapic); |
3962 | return -EINVAL; | |
3963 | } | |
3964 | ||
0b8f1efa YL |
3965 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3966 | if (!desc) { | |
3967 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3968 | return 0; | |
3969 | } | |
3970 | ||
1da177e4 LT |
3971 | /* |
3972 | * IRQs < 16 are already in the irq_2_pin[] map | |
3973 | */ | |
99d093d1 | 3974 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3975 | cfg = desc->chip_data; |
3145e941 | 3976 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3977 | } |
1da177e4 | 3978 | |
3145e941 | 3979 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3980 | |
3981 | return 0; | |
3982 | } | |
3983 | ||
54168ed7 | 3984 | |
61fd47e0 SL |
3985 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3986 | { | |
3987 | int i; | |
3988 | ||
3989 | if (skip_ioapic_setup) | |
3990 | return -1; | |
3991 | ||
3992 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
3993 | if (mp_irqs[i].irqtype == mp_INT && |
3994 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
3995 | break; |
3996 | if (i >= mp_irq_entries) | |
3997 | return -1; | |
3998 | ||
3999 | *trigger = irq_trigger(i); | |
4000 | *polarity = irq_polarity(i); | |
4001 | return 0; | |
4002 | } | |
4003 | ||
888ba6c6 | 4004 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4005 | |
497c9a19 YL |
4006 | /* |
4007 | * This function currently is only a helper for the i386 smp boot process where | |
4008 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4009 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4010 | */ |
4011 | #ifdef CONFIG_SMP | |
4012 | void __init setup_ioapic_dest(void) | |
4013 | { | |
4014 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4015 | struct irq_desc *desc; |
497c9a19 | 4016 | struct irq_cfg *cfg; |
22f65d31 | 4017 | const struct cpumask *mask; |
497c9a19 YL |
4018 | |
4019 | if (skip_ioapic_setup == 1) | |
4020 | return; | |
4021 | ||
4022 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4023 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4024 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4025 | if (irq_entry == -1) | |
4026 | continue; | |
4027 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4028 | ||
4029 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4030 | * when you have too many devices, because at that time only boot | |
4031 | * cpu is online. | |
4032 | */ | |
0b8f1efa YL |
4033 | desc = irq_to_desc(irq); |
4034 | cfg = desc->chip_data; | |
6c2e9403 | 4035 | if (!cfg->vector) { |
3145e941 | 4036 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4037 | irq_trigger(irq_entry), |
4038 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4039 | continue; |
4040 | ||
4041 | } | |
4042 | ||
4043 | /* | |
4044 | * Honour affinities which have been set in early boot | |
4045 | */ | |
6c2e9403 TG |
4046 | if (desc->status & |
4047 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4048 | mask = desc->affinity; |
6c2e9403 | 4049 | else |
fe402e1f | 4050 | mask = apic->target_cpus(); |
6c2e9403 | 4051 | |
54168ed7 | 4052 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4053 | if (intr_remapping_enabled) |
3145e941 | 4054 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4055 | else |
6c2e9403 | 4056 | #endif |
3145e941 | 4057 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4058 | } |
4059 | ||
4060 | } | |
4061 | } | |
4062 | #endif | |
4063 | ||
54168ed7 IM |
4064 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4065 | ||
4066 | static struct resource *ioapic_resources; | |
4067 | ||
4068 | static struct resource * __init ioapic_setup_resources(void) | |
4069 | { | |
4070 | unsigned long n; | |
4071 | struct resource *res; | |
4072 | char *mem; | |
4073 | int i; | |
4074 | ||
4075 | if (nr_ioapics <= 0) | |
4076 | return NULL; | |
4077 | ||
4078 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4079 | n *= nr_ioapics; | |
4080 | ||
4081 | mem = alloc_bootmem(n); | |
4082 | res = (void *)mem; | |
4083 | ||
4084 | if (mem != NULL) { | |
4085 | mem += sizeof(struct resource) * nr_ioapics; | |
4086 | ||
4087 | for (i = 0; i < nr_ioapics; i++) { | |
4088 | res[i].name = mem; | |
4089 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4090 | sprintf(mem, "IOAPIC %u", i); | |
4091 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4092 | } | |
4093 | } | |
4094 | ||
4095 | ioapic_resources = res; | |
4096 | ||
4097 | return res; | |
4098 | } | |
54168ed7 | 4099 | |
f3294a33 YL |
4100 | void __init ioapic_init_mappings(void) |
4101 | { | |
4102 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4103 | struct resource *ioapic_res; |
d6c88a50 | 4104 | int i; |
f3294a33 | 4105 | |
54168ed7 | 4106 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4107 | for (i = 0; i < nr_ioapics; i++) { |
4108 | if (smp_found_config) { | |
b5ba7e6d | 4109 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4110 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4111 | if (!ioapic_phys) { |
4112 | printk(KERN_ERR | |
4113 | "WARNING: bogus zero IO-APIC " | |
4114 | "address found in MPTABLE, " | |
4115 | "disabling IO/APIC support!\n"); | |
4116 | smp_found_config = 0; | |
4117 | skip_ioapic_setup = 1; | |
4118 | goto fake_ioapic_page; | |
4119 | } | |
54168ed7 | 4120 | #endif |
f3294a33 | 4121 | } else { |
54168ed7 | 4122 | #ifdef CONFIG_X86_32 |
f3294a33 | 4123 | fake_ioapic_page: |
54168ed7 | 4124 | #endif |
f3294a33 | 4125 | ioapic_phys = (unsigned long) |
54168ed7 | 4126 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4127 | ioapic_phys = __pa(ioapic_phys); |
4128 | } | |
4129 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4130 | apic_printk(APIC_VERBOSE, |
4131 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4132 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4133 | idx++; |
54168ed7 | 4134 | |
54168ed7 IM |
4135 | if (ioapic_res != NULL) { |
4136 | ioapic_res->start = ioapic_phys; | |
4137 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4138 | ioapic_res++; | |
4139 | } | |
f3294a33 YL |
4140 | } |
4141 | } | |
4142 | ||
54168ed7 IM |
4143 | static int __init ioapic_insert_resources(void) |
4144 | { | |
4145 | int i; | |
4146 | struct resource *r = ioapic_resources; | |
4147 | ||
4148 | if (!r) { | |
4149 | printk(KERN_ERR | |
4150 | "IO APIC resources could be not be allocated.\n"); | |
4151 | return -1; | |
4152 | } | |
4153 | ||
4154 | for (i = 0; i < nr_ioapics; i++) { | |
4155 | insert_resource(&iomem_resource, r); | |
4156 | r++; | |
4157 | } | |
4158 | ||
4159 | return 0; | |
4160 | } | |
4161 | ||
4162 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4163 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4164 | late_initcall(ioapic_insert_resources); |