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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
54d5d424 | 44 | |
d4057bdb | 45 | #include <asm/idle.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/smp.h> | |
48 | #include <asm/desc.h> | |
d4057bdb YL |
49 | #include <asm/proto.h> |
50 | #include <asm/acpi.h> | |
51 | #include <asm/dma.h> | |
1da177e4 | 52 | #include <asm/timer.h> |
306e440d | 53 | #include <asm/i8259.h> |
3e4ff115 | 54 | #include <asm/nmi.h> |
2d3fcc1c | 55 | #include <asm/msidef.h> |
8b955b0d | 56 | #include <asm/hypertransport.h> |
a4dbc34d | 57 | #include <asm/setup.h> |
d4057bdb | 58 | #include <asm/irq_remapping.h> |
1da177e4 | 59 | |
497c9a19 | 60 | #include <mach_ipi.h> |
1da177e4 | 61 | #include <mach_apic.h> |
874c4fe3 | 62 | #include <mach_apicdef.h> |
1da177e4 | 63 | |
32f71aff MR |
64 | #define __apicdebuginit(type) static type __init |
65 | ||
1da177e4 | 66 | /* |
54168ed7 IM |
67 | * Is the SiS APIC rmw bug present ? |
68 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
69 | */ |
70 | int sis_apic_bug = -1; | |
71 | ||
efa2559f YL |
72 | static DEFINE_SPINLOCK(ioapic_lock); |
73 | static DEFINE_SPINLOCK(vector_lock); | |
74 | ||
1da177e4 LT |
75 | /* |
76 | * # of IRQ routing registers | |
77 | */ | |
78 | int nr_ioapic_registers[MAX_IO_APICS]; | |
79 | ||
9f640ccb | 80 | /* I/O APIC entries */ |
ec2cd0a2 | 81 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
82 | int nr_ioapics; |
83 | ||
584f734d | 84 | /* MP IRQ source entries */ |
2fddb6e2 | 85 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
86 | |
87 | /* # of MP IRQ source entries */ | |
88 | int mp_irq_entries; | |
89 | ||
8732fc4b AS |
90 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
91 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
92 | #endif | |
93 | ||
94 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
95 | ||
efa2559f YL |
96 | int skip_ioapic_setup; |
97 | ||
54168ed7 | 98 | static int __init parse_noapic(char *str) |
efa2559f YL |
99 | { |
100 | /* disable IO-APIC */ | |
101 | disable_ioapic_setup(); | |
102 | return 0; | |
103 | } | |
104 | early_param("noapic", parse_noapic); | |
66759a01 | 105 | |
da51a821 | 106 | struct irq_cfg; |
0f978f45 | 107 | struct irq_pin_list; |
a1420f39 | 108 | struct irq_cfg { |
da51a821 | 109 | unsigned int irq; |
8f09cd20 | 110 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
da51a821 | 111 | struct irq_cfg *next; |
8f09cd20 | 112 | #endif |
0f978f45 | 113 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
114 | cpumask_t domain; |
115 | cpumask_t old_domain; | |
116 | unsigned move_cleanup_count; | |
a1420f39 | 117 | u8 vector; |
497c9a19 | 118 | u8 move_in_progress : 1; |
a1420f39 YL |
119 | }; |
120 | ||
a1420f39 YL |
121 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
122 | static struct irq_cfg irq_cfg_legacy[] __initdata = { | |
497c9a19 YL |
123 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
124 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
125 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
126 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
127 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
128 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
129 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
130 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
131 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
132 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
133 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
134 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
135 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
136 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
137 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
138 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
139 | }; |
140 | ||
da51a821 | 141 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
da51a821 YL |
142 | |
143 | static void init_one_irq_cfg(struct irq_cfg *cfg) | |
144 | { | |
145 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); | |
146 | } | |
147 | ||
148 | static struct irq_cfg *irq_cfgx; | |
e89eb438 | 149 | |
ac54a6c9 | 150 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
e89eb438 YL |
151 | /* |
152 | * Protect the irq_cfgx_free freelist: | |
153 | */ | |
154 | static DEFINE_SPINLOCK(irq_cfg_lock); | |
155 | ||
da51a821 | 156 | static struct irq_cfg *irq_cfgx_free; |
8f09cd20 | 157 | #endif |
ac54a6c9 | 158 | |
a1420f39 YL |
159 | static void __init init_work(void *data) |
160 | { | |
da51a821 YL |
161 | struct dyn_array *da = data; |
162 | struct irq_cfg *cfg; | |
163 | int legacy_count; | |
164 | int i; | |
165 | ||
166 | cfg = *da->name; | |
a1420f39 | 167 | |
da51a821 | 168 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); |
a1420f39 | 169 | |
676f4a92 | 170 | legacy_count = ARRAY_SIZE(irq_cfg_legacy); |
da51a821 YL |
171 | for (i = legacy_count; i < *da->nr; i++) |
172 | init_one_irq_cfg(&cfg[i]); | |
a1420f39 | 173 | |
8f09cd20 | 174 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
da51a821 YL |
175 | for (i = 1; i < *da->nr; i++) |
176 | cfg[i-1].next = &cfg[i]; | |
a1420f39 | 177 | |
da51a821 YL |
178 | irq_cfgx_free = &irq_cfgx[legacy_count]; |
179 | irq_cfgx[legacy_count - 1].next = NULL; | |
8f09cd20 YL |
180 | #endif |
181 | } | |
182 | ||
183 | #ifdef CONFIG_HAVE_SPARSE_IRQ | |
184 | /* need to be biger than size of irq_cfg_legacy */ | |
185 | static int nr_irq_cfg = 32; | |
186 | ||
187 | static int __init parse_nr_irq_cfg(char *arg) | |
188 | { | |
189 | if (arg) { | |
190 | nr_irq_cfg = simple_strtoul(arg, NULL, 0); | |
191 | if (nr_irq_cfg < 32) | |
192 | nr_irq_cfg = 32; | |
193 | } | |
194 | return 0; | |
a1420f39 YL |
195 | } |
196 | ||
8f09cd20 YL |
197 | early_param("nr_irq_cfg", parse_nr_irq_cfg); |
198 | ||
199 | #define for_each_irq_cfg(irqX, cfg) \ | |
200 | for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U) | |
201 | ||
da51a821 YL |
202 | |
203 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work); | |
a1420f39 YL |
204 | |
205 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
206 | { | |
da51a821 YL |
207 | struct irq_cfg *cfg; |
208 | ||
209 | cfg = irq_cfgx; | |
210 | while (cfg) { | |
211 | if (cfg->irq == irq) | |
212 | return cfg; | |
213 | ||
214 | cfg = cfg->next; | |
215 | } | |
216 | ||
217 | return NULL; | |
218 | } | |
219 | ||
220 | static struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
221 | { | |
222 | struct irq_cfg *cfg, *cfg_pri; | |
e89eb438 | 223 | unsigned long flags; |
da51a821 | 224 | int count = 0; |
e89eb438 | 225 | int i; |
da51a821 YL |
226 | |
227 | cfg_pri = cfg = irq_cfgx; | |
228 | while (cfg) { | |
229 | if (cfg->irq == irq) | |
230 | return cfg; | |
231 | ||
232 | cfg_pri = cfg; | |
233 | cfg = cfg->next; | |
234 | count++; | |
235 | } | |
236 | ||
e89eb438 | 237 | spin_lock_irqsave(&irq_cfg_lock, flags); |
da51a821 YL |
238 | if (!irq_cfgx_free) { |
239 | unsigned long phys; | |
240 | unsigned long total_bytes; | |
241 | /* | |
242 | * we run out of pre-allocate ones, allocate more | |
243 | */ | |
244 | printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg); | |
245 | ||
246 | total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg; | |
247 | if (after_bootmem) | |
248 | cfg = kzalloc(total_bytes, GFP_ATOMIC); | |
249 | else | |
250 | cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0); | |
a1420f39 | 251 | |
da51a821 YL |
252 | if (!cfg) |
253 | panic("please boot with nr_irq_cfg= %d\n", count * 2); | |
254 | ||
255 | phys = __pa(cfg); | |
256 | printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes); | |
257 | ||
258 | for (i = 0; i < nr_irq_cfg; i++) | |
259 | init_one_irq_cfg(&cfg[i]); | |
260 | ||
261 | for (i = 1; i < nr_irq_cfg; i++) | |
262 | cfg[i-1].next = &cfg[i]; | |
263 | ||
264 | irq_cfgx_free = cfg; | |
265 | } | |
266 | ||
267 | cfg = irq_cfgx_free; | |
268 | irq_cfgx_free = irq_cfgx_free->next; | |
269 | cfg->next = NULL; | |
270 | if (cfg_pri) | |
271 | cfg_pri->next = cfg; | |
272 | else | |
273 | irq_cfgx = cfg; | |
274 | cfg->irq = irq; | |
e89eb438 YL |
275 | |
276 | spin_unlock_irqrestore(&irq_cfg_lock, flags); | |
277 | ||
da51a821 | 278 | printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq); |
da51a821 YL |
279 | #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG |
280 | { | |
281 | /* dump the results */ | |
282 | struct irq_cfg *cfg; | |
283 | unsigned long phys; | |
284 | unsigned long bytes = sizeof(struct irq_cfg); | |
285 | ||
286 | printk(KERN_DEBUG "=========================== %d\n", irq); | |
287 | printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq); | |
288 | for_each_irq_cfg(cfg) { | |
289 | phys = __pa(cfg); | |
290 | printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes); | |
291 | } | |
292 | printk(KERN_DEBUG "===========================\n"); | |
293 | } | |
294 | #endif | |
295 | return cfg; | |
a1420f39 | 296 | } |
8f09cd20 YL |
297 | #else |
298 | ||
299 | #define for_each_irq_cfg(irq, cfg) \ | |
300 | for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq]) | |
301 | ||
302 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work); | |
a1420f39 | 303 | |
8f09cd20 YL |
304 | struct irq_cfg *irq_cfg(unsigned int irq) |
305 | { | |
306 | if (irq < nr_irqs) | |
307 | return &irq_cfgx[irq]; | |
308 | ||
309 | return NULL; | |
310 | } | |
311 | struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
312 | { | |
313 | return irq_cfg(irq); | |
314 | } | |
315 | ||
316 | #endif | |
1da177e4 LT |
317 | /* |
318 | * This is performance-critical, we want to do it O(1) | |
319 | * | |
320 | * the indexing order of this array favors 1:1 mappings | |
321 | * between pins and IRQs. | |
322 | */ | |
323 | ||
0f978f45 YL |
324 | struct irq_pin_list { |
325 | int apic, pin; | |
326 | struct irq_pin_list *next; | |
327 | }; | |
328 | ||
329 | static struct irq_pin_list *irq_2_pin_head; | |
330 | /* fill one page ? */ | |
331 | static int nr_irq_2_pin = 0x100; | |
332 | static struct irq_pin_list *irq_2_pin_ptr; | |
333 | static void __init irq_2_pin_init_work(void *data) | |
334 | { | |
335 | struct dyn_array *da = data; | |
336 | struct irq_pin_list *pin; | |
337 | int i; | |
338 | ||
339 | pin = *da->name; | |
340 | ||
341 | for (i = 1; i < *da->nr; i++) | |
342 | pin[i-1].next = &pin[i]; | |
343 | ||
344 | irq_2_pin_ptr = &pin[0]; | |
345 | } | |
346 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); | |
347 | ||
348 | static struct irq_pin_list *get_one_free_irq_2_pin(void) | |
349 | { | |
350 | struct irq_pin_list *pin; | |
351 | int i; | |
352 | ||
353 | pin = irq_2_pin_ptr; | |
354 | ||
355 | if (pin) { | |
356 | irq_2_pin_ptr = pin->next; | |
357 | pin->next = NULL; | |
358 | return pin; | |
359 | } | |
360 | ||
361 | /* | |
362 | * we run out of pre-allocate ones, allocate more | |
363 | */ | |
364 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); | |
365 | ||
366 | if (after_bootmem) | |
367 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, | |
368 | GFP_ATOMIC); | |
369 | else | |
370 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * | |
371 | nr_irq_2_pin, PAGE_SIZE, 0); | |
372 | ||
373 | if (!pin) | |
374 | panic("can not get more irq_2_pin\n"); | |
301e6190 | 375 | |
0f978f45 YL |
376 | for (i = 1; i < nr_irq_2_pin; i++) |
377 | pin[i-1].next = &pin[i]; | |
378 | ||
379 | irq_2_pin_ptr = pin->next; | |
380 | pin->next = NULL; | |
381 | ||
382 | return pin; | |
383 | } | |
1da177e4 | 384 | |
130fe05d LT |
385 | struct io_apic { |
386 | unsigned int index; | |
387 | unsigned int unused[3]; | |
388 | unsigned int data; | |
389 | }; | |
390 | ||
391 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
392 | { | |
393 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 394 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
395 | } |
396 | ||
397 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
398 | { | |
399 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
400 | writel(reg, &io_apic->index); | |
401 | return readl(&io_apic->data); | |
402 | } | |
403 | ||
404 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
405 | { | |
406 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
407 | writel(reg, &io_apic->index); | |
408 | writel(value, &io_apic->data); | |
409 | } | |
410 | ||
411 | /* | |
412 | * Re-write a value: to be used for read-modify-write | |
413 | * cycles where the read already set up the index register. | |
414 | * | |
415 | * Older SiS APIC requires we rewrite the index register | |
416 | */ | |
417 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
418 | { | |
54168ed7 IM |
419 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
420 | if (sis_apic_bug) | |
421 | writel(reg, &io_apic->index); | |
130fe05d LT |
422 | writel(value, &io_apic->data); |
423 | } | |
424 | ||
047c8fdb YL |
425 | static bool io_apic_level_ack_pending(unsigned int irq) |
426 | { | |
427 | struct irq_pin_list *entry; | |
428 | unsigned long flags; | |
429 | struct irq_cfg *cfg = irq_cfg(irq); | |
430 | ||
431 | spin_lock_irqsave(&ioapic_lock, flags); | |
432 | entry = cfg->irq_2_pin; | |
433 | for (;;) { | |
434 | unsigned int reg; | |
435 | int pin; | |
436 | ||
437 | if (!entry) | |
438 | break; | |
439 | pin = entry->pin; | |
440 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
441 | /* Is the remote IRR bit set? */ | |
442 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
443 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
444 | return true; | |
445 | } | |
446 | if (!entry->next) | |
447 | break; | |
448 | entry = entry->next; | |
449 | } | |
450 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
451 | ||
452 | return false; | |
453 | } | |
047c8fdb | 454 | |
cf4c6a2f AK |
455 | union entry_union { |
456 | struct { u32 w1, w2; }; | |
457 | struct IO_APIC_route_entry entry; | |
458 | }; | |
459 | ||
460 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
461 | { | |
462 | union entry_union eu; | |
463 | unsigned long flags; | |
464 | spin_lock_irqsave(&ioapic_lock, flags); | |
465 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
466 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
467 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
468 | return eu.entry; | |
469 | } | |
470 | ||
f9dadfa7 LT |
471 | /* |
472 | * When we write a new IO APIC routing entry, we need to write the high | |
473 | * word first! If the mask bit in the low word is clear, we will enable | |
474 | * the interrupt, and we need to make sure the entry is fully populated | |
475 | * before that happens. | |
476 | */ | |
d15512f4 AK |
477 | static void |
478 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 479 | { |
cf4c6a2f AK |
480 | union entry_union eu; |
481 | eu.entry = e; | |
f9dadfa7 LT |
482 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
483 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
484 | } |
485 | ||
486 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
487 | { | |
488 | unsigned long flags; | |
489 | spin_lock_irqsave(&ioapic_lock, flags); | |
490 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
491 | spin_unlock_irqrestore(&ioapic_lock, flags); |
492 | } | |
493 | ||
494 | /* | |
495 | * When we mask an IO APIC routing entry, we need to write the low | |
496 | * word first, in order to set the mask bit before we change the | |
497 | * high bits! | |
498 | */ | |
499 | static void ioapic_mask_entry(int apic, int pin) | |
500 | { | |
501 | unsigned long flags; | |
502 | union entry_union eu = { .entry.mask = 1 }; | |
503 | ||
cf4c6a2f AK |
504 | spin_lock_irqsave(&ioapic_lock, flags); |
505 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
506 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
507 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
508 | } | |
509 | ||
497c9a19 YL |
510 | #ifdef CONFIG_SMP |
511 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) | |
512 | { | |
513 | int apic, pin; | |
514 | struct irq_cfg *cfg; | |
515 | struct irq_pin_list *entry; | |
516 | ||
517 | cfg = irq_cfg(irq); | |
518 | entry = cfg->irq_2_pin; | |
519 | for (;;) { | |
520 | unsigned int reg; | |
521 | ||
522 | if (!entry) | |
523 | break; | |
524 | ||
525 | apic = entry->apic; | |
526 | pin = entry->pin; | |
54168ed7 IM |
527 | #ifdef CONFIG_INTR_REMAP |
528 | /* | |
529 | * With interrupt-remapping, destination information comes | |
530 | * from interrupt-remapping table entry. | |
531 | */ | |
532 | if (!irq_remapped(irq)) | |
533 | io_apic_write(apic, 0x11 + pin*2, dest); | |
534 | #else | |
497c9a19 | 535 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 536 | #endif |
497c9a19 YL |
537 | reg = io_apic_read(apic, 0x10 + pin*2); |
538 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
539 | reg |= vector; | |
54168ed7 | 540 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
541 | if (!entry->next) |
542 | break; | |
543 | entry = entry->next; | |
544 | } | |
545 | } | |
efa2559f YL |
546 | |
547 | static int assign_irq_vector(int irq, cpumask_t mask); | |
548 | ||
497c9a19 YL |
549 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
550 | { | |
551 | struct irq_cfg *cfg; | |
552 | unsigned long flags; | |
553 | unsigned int dest; | |
554 | cpumask_t tmp; | |
54168ed7 | 555 | struct irq_desc *desc; |
497c9a19 | 556 | |
497c9a19 YL |
557 | cpus_and(tmp, mask, cpu_online_map); |
558 | if (cpus_empty(tmp)) | |
559 | return; | |
560 | ||
047c8fdb | 561 | cfg = irq_cfg(irq); |
497c9a19 YL |
562 | if (assign_irq_vector(irq, mask)) |
563 | return; | |
564 | ||
565 | cpus_and(tmp, cfg->domain, mask); | |
497c9a19 YL |
566 | dest = cpu_mask_to_apicid(tmp); |
567 | /* | |
568 | * Only the high 8 bits are valid. | |
569 | */ | |
570 | dest = SET_APIC_LOGICAL_ID(dest); | |
571 | ||
54168ed7 | 572 | desc = irq_to_desc(irq); |
497c9a19 YL |
573 | spin_lock_irqsave(&ioapic_lock, flags); |
574 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
54168ed7 | 575 | desc->affinity = mask; |
497c9a19 YL |
576 | spin_unlock_irqrestore(&ioapic_lock, flags); |
577 | } | |
497c9a19 YL |
578 | #endif /* CONFIG_SMP */ |
579 | ||
1da177e4 LT |
580 | /* |
581 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
582 | * shared ISA-space IRQs, so we have to support them. We are super | |
583 | * fast in the common case, and fast for shared ISA-space IRQs. | |
584 | */ | |
585 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
586 | { | |
0f978f45 YL |
587 | struct irq_cfg *cfg; |
588 | struct irq_pin_list *entry; | |
589 | ||
590 | /* first time to refer irq_cfg, so with new */ | |
591 | cfg = irq_cfg_alloc(irq); | |
592 | entry = cfg->irq_2_pin; | |
593 | if (!entry) { | |
594 | entry = get_one_free_irq_2_pin(); | |
595 | cfg->irq_2_pin = entry; | |
596 | entry->apic = apic; | |
597 | entry->pin = pin; | |
598 | printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); | |
599 | return; | |
600 | } | |
1da177e4 | 601 | |
0f978f45 YL |
602 | while (entry->next) { |
603 | /* not again, please */ | |
604 | if (entry->apic == apic && entry->pin == pin) | |
605 | return; | |
1da177e4 | 606 | |
0f978f45 | 607 | entry = entry->next; |
1da177e4 | 608 | } |
0f978f45 YL |
609 | |
610 | entry->next = get_one_free_irq_2_pin(); | |
611 | entry = entry->next; | |
1da177e4 LT |
612 | entry->apic = apic; |
613 | entry->pin = pin; | |
0f978f45 | 614 | printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); |
1da177e4 LT |
615 | } |
616 | ||
617 | /* | |
618 | * Reroute an IRQ to a different pin. | |
619 | */ | |
620 | static void __init replace_pin_at_irq(unsigned int irq, | |
621 | int oldapic, int oldpin, | |
622 | int newapic, int newpin) | |
623 | { | |
0f978f45 YL |
624 | struct irq_cfg *cfg = irq_cfg(irq); |
625 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
626 | int replaced = 0; | |
1da177e4 | 627 | |
0f978f45 | 628 | while (entry) { |
1da177e4 LT |
629 | if (entry->apic == oldapic && entry->pin == oldpin) { |
630 | entry->apic = newapic; | |
631 | entry->pin = newpin; | |
0f978f45 YL |
632 | replaced = 1; |
633 | /* every one is different, right? */ | |
1da177e4 | 634 | break; |
0f978f45 YL |
635 | } |
636 | entry = entry->next; | |
1da177e4 | 637 | } |
0f978f45 YL |
638 | |
639 | /* why? call replace before add? */ | |
640 | if (!replaced) | |
641 | add_pin_to_irq(irq, newapic, newpin); | |
1da177e4 LT |
642 | } |
643 | ||
4e738e2f | 644 | #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \ |
047c8fdb YL |
645 | \ |
646 | { \ | |
647 | int pin; \ | |
648 | struct irq_cfg *cfg; \ | |
649 | struct irq_pin_list *entry; \ | |
650 | \ | |
651 | cfg = irq_cfg(irq); \ | |
652 | entry = cfg->irq_2_pin; \ | |
653 | for (;;) { \ | |
654 | unsigned int reg; \ | |
655 | if (!entry) \ | |
656 | break; \ | |
657 | pin = entry->pin; \ | |
658 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
4e738e2f YL |
659 | reg ACTION_DISABLE; \ |
660 | reg ACTION_ENABLE; \ | |
047c8fdb YL |
661 | io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \ |
662 | FINAL; \ | |
663 | if (!entry->next) \ | |
664 | break; \ | |
665 | entry = entry->next; \ | |
666 | } \ | |
667 | } | |
668 | ||
4e738e2f | 669 | #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \ |
047c8fdb YL |
670 | \ |
671 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
4e738e2f | 672 | __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) |
047c8fdb YL |
673 | |
674 | /* mask = 0 */ | |
4e738e2f | 675 | DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, ) |
047c8fdb | 676 | |
4e738e2f YL |
677 | #ifdef CONFIG_X86_64 |
678 | /* | |
679 | * Synchronize the IO-APIC and the CPU by doing | |
680 | * a dummy read from the IO-APIC | |
681 | */ | |
682 | static inline void io_apic_sync(unsigned int apic) | |
1da177e4 | 683 | { |
4e738e2f YL |
684 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
685 | readl(&io_apic->data); | |
1da177e4 LT |
686 | } |
687 | ||
688 | /* mask = 1 */ | |
4e738e2f | 689 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic)) |
1da177e4 | 690 | |
4e738e2f YL |
691 | #else |
692 | ||
693 | /* mask = 1 */ | |
694 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, ) | |
1da177e4 LT |
695 | |
696 | /* mask = 1, trigger = 0 */ | |
4e738e2f | 697 | DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, ) |
1da177e4 LT |
698 | |
699 | /* mask = 0, trigger = 1 */ | |
4e738e2f | 700 | DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, ) |
1da177e4 | 701 | |
047c8fdb YL |
702 | #endif |
703 | ||
54168ed7 | 704 | static void mask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
705 | { |
706 | unsigned long flags; | |
707 | ||
708 | spin_lock_irqsave(&ioapic_lock, flags); | |
709 | __mask_IO_APIC_irq(irq); | |
710 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
711 | } | |
712 | ||
54168ed7 | 713 | static void unmask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
714 | { |
715 | unsigned long flags; | |
716 | ||
717 | spin_lock_irqsave(&ioapic_lock, flags); | |
718 | __unmask_IO_APIC_irq(irq); | |
719 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
720 | } | |
721 | ||
722 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
723 | { | |
724 | struct IO_APIC_route_entry entry; | |
36062448 | 725 | |
1da177e4 | 726 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 727 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
728 | if (entry.delivery_mode == dest_SMI) |
729 | return; | |
1da177e4 LT |
730 | /* |
731 | * Disable it in the IO-APIC irq-routing table: | |
732 | */ | |
f9dadfa7 | 733 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
734 | } |
735 | ||
54168ed7 | 736 | static void clear_IO_APIC (void) |
1da177e4 LT |
737 | { |
738 | int apic, pin; | |
739 | ||
740 | for (apic = 0; apic < nr_ioapics; apic++) | |
741 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
742 | clear_IO_APIC_pin(apic, pin); | |
743 | } | |
744 | ||
54168ed7 | 745 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 746 | void send_IPI_self(int vector) |
1da177e4 LT |
747 | { |
748 | unsigned int cfg; | |
749 | ||
750 | /* | |
751 | * Wait for idle. | |
752 | */ | |
753 | apic_wait_icr_idle(); | |
754 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
755 | /* | |
756 | * Send the IPI. The write to APIC_ICR fires this off. | |
757 | */ | |
593f4a78 | 758 | apic_write(APIC_ICR, cfg); |
1da177e4 | 759 | } |
54168ed7 | 760 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 761 | |
54168ed7 | 762 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
763 | /* |
764 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
765 | * specific CPU-side IRQs. | |
766 | */ | |
767 | ||
768 | #define MAX_PIRQS 8 | |
769 | static int pirq_entries [MAX_PIRQS]; | |
770 | static int pirqs_enabled; | |
1da177e4 | 771 | |
1da177e4 LT |
772 | static int __init ioapic_pirq_setup(char *str) |
773 | { | |
774 | int i, max; | |
775 | int ints[MAX_PIRQS+1]; | |
776 | ||
777 | get_options(str, ARRAY_SIZE(ints), ints); | |
778 | ||
779 | for (i = 0; i < MAX_PIRQS; i++) | |
780 | pirq_entries[i] = -1; | |
781 | ||
782 | pirqs_enabled = 1; | |
783 | apic_printk(APIC_VERBOSE, KERN_INFO | |
784 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
785 | max = MAX_PIRQS; | |
786 | if (ints[0] < MAX_PIRQS) | |
787 | max = ints[0]; | |
788 | ||
789 | for (i = 0; i < max; i++) { | |
790 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
791 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
792 | /* | |
793 | * PIRQs are mapped upside down, usually. | |
794 | */ | |
795 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
796 | } | |
797 | return 1; | |
798 | } | |
799 | ||
800 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
801 | #endif /* CONFIG_X86_32 */ |
802 | ||
803 | #ifdef CONFIG_INTR_REMAP | |
804 | /* I/O APIC RTE contents at the OS boot up */ | |
805 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
806 | ||
807 | /* | |
808 | * Saves and masks all the unmasked IO-APIC RTE's | |
809 | */ | |
810 | int save_mask_IO_APIC_setup(void) | |
811 | { | |
812 | union IO_APIC_reg_01 reg_01; | |
813 | unsigned long flags; | |
814 | int apic, pin; | |
815 | ||
816 | /* | |
817 | * The number of IO-APIC IRQ registers (== #pins): | |
818 | */ | |
819 | for (apic = 0; apic < nr_ioapics; apic++) { | |
820 | spin_lock_irqsave(&ioapic_lock, flags); | |
821 | reg_01.raw = io_apic_read(apic, 1); | |
822 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
823 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
824 | } | |
825 | ||
826 | for (apic = 0; apic < nr_ioapics; apic++) { | |
827 | early_ioapic_entries[apic] = | |
828 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
829 | nr_ioapic_registers[apic], GFP_KERNEL); | |
830 | if (!early_ioapic_entries[apic]) | |
831 | return -ENOMEM; | |
832 | } | |
833 | ||
834 | for (apic = 0; apic < nr_ioapics; apic++) | |
835 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
836 | struct IO_APIC_route_entry entry; | |
837 | ||
838 | entry = early_ioapic_entries[apic][pin] = | |
839 | ioapic_read_entry(apic, pin); | |
840 | if (!entry.mask) { | |
841 | entry.mask = 1; | |
842 | ioapic_write_entry(apic, pin, entry); | |
843 | } | |
844 | } | |
845 | return 0; | |
846 | } | |
847 | ||
848 | void restore_IO_APIC_setup(void) | |
849 | { | |
850 | int apic, pin; | |
851 | ||
852 | for (apic = 0; apic < nr_ioapics; apic++) | |
853 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
854 | ioapic_write_entry(apic, pin, | |
855 | early_ioapic_entries[apic][pin]); | |
856 | } | |
857 | ||
858 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
859 | { | |
860 | /* | |
861 | * for now plain restore of previous settings. | |
862 | * TBD: In the case of OS enabling interrupt-remapping, | |
863 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
864 | * table entries. for now, do a plain restore, and wait for | |
865 | * the setup_IO_APIC_irqs() to do proper initialization. | |
866 | */ | |
867 | restore_IO_APIC_setup(); | |
868 | } | |
869 | #endif | |
1da177e4 LT |
870 | |
871 | /* | |
872 | * Find the IRQ entry number of a certain pin. | |
873 | */ | |
874 | static int find_irq_entry(int apic, int pin, int type) | |
875 | { | |
876 | int i; | |
877 | ||
878 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
879 | if (mp_irqs[i].mp_irqtype == type && |
880 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
881 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
882 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
883 | return i; |
884 | ||
885 | return -1; | |
886 | } | |
887 | ||
888 | /* | |
889 | * Find the pin to which IRQ[irq] (ISA) is connected | |
890 | */ | |
fcfd636a | 891 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
892 | { |
893 | int i; | |
894 | ||
895 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 896 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 897 | |
d27e2b8e | 898 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
899 | (mp_irqs[i].mp_irqtype == type) && |
900 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 901 | |
2fddb6e2 | 902 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
903 | } |
904 | return -1; | |
905 | } | |
906 | ||
fcfd636a EB |
907 | static int __init find_isa_irq_apic(int irq, int type) |
908 | { | |
909 | int i; | |
910 | ||
911 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 912 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 913 | |
73b2961b | 914 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
915 | (mp_irqs[i].mp_irqtype == type) && |
916 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
917 | break; |
918 | } | |
919 | if (i < mp_irq_entries) { | |
920 | int apic; | |
54168ed7 | 921 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 922 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
923 | return apic; |
924 | } | |
925 | } | |
926 | ||
927 | return -1; | |
928 | } | |
929 | ||
1da177e4 LT |
930 | /* |
931 | * Find a specific PCI IRQ entry. | |
932 | * Not an __init, possibly needed by modules | |
933 | */ | |
934 | static int pin_2_irq(int idx, int apic, int pin); | |
935 | ||
936 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
937 | { | |
938 | int apic, i, best_guess = -1; | |
939 | ||
54168ed7 IM |
940 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
941 | bus, slot, pin); | |
ce6444d3 | 942 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 943 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
944 | return -1; |
945 | } | |
946 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 947 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
948 | |
949 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
950 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
951 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
952 | break; |
953 | ||
47cab822 | 954 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 955 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 956 | (bus == lbus) && |
2fddb6e2 | 957 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 958 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
959 | |
960 | if (!(apic || IO_APIC_IRQ(irq))) | |
961 | continue; | |
962 | ||
2fddb6e2 | 963 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
964 | return irq; |
965 | /* | |
966 | * Use the first all-but-pin matching entry as a | |
967 | * best-guess fuzzy result for broken mptables. | |
968 | */ | |
969 | if (best_guess < 0) | |
970 | best_guess = irq; | |
971 | } | |
972 | } | |
973 | return best_guess; | |
974 | } | |
54168ed7 | 975 | |
129f6946 | 976 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 977 | |
c0a282c2 | 978 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
979 | /* |
980 | * EISA Edge/Level control register, ELCR | |
981 | */ | |
982 | static int EISA_ELCR(unsigned int irq) | |
983 | { | |
984 | if (irq < 16) { | |
985 | unsigned int port = 0x4d0 + (irq >> 3); | |
986 | return (inb(port) >> (irq & 7)) & 1; | |
987 | } | |
988 | apic_printk(APIC_VERBOSE, KERN_INFO | |
989 | "Broken MPtable reports ISA irq %d\n", irq); | |
990 | return 0; | |
991 | } | |
54168ed7 | 992 | |
c0a282c2 | 993 | #endif |
1da177e4 | 994 | |
6728801d AS |
995 | /* ISA interrupts are always polarity zero edge triggered, |
996 | * when listed as conforming in the MP table. */ | |
997 | ||
998 | #define default_ISA_trigger(idx) (0) | |
999 | #define default_ISA_polarity(idx) (0) | |
1000 | ||
1da177e4 LT |
1001 | /* EISA interrupts are always polarity zero and can be edge or level |
1002 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1003 | * EISA conforming in the MP table, that means its trigger type must | |
1004 | * be read in from the ELCR */ | |
1005 | ||
2fddb6e2 | 1006 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 1007 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1008 | |
1009 | /* PCI interrupts are always polarity one level triggered, | |
1010 | * when listed as conforming in the MP table. */ | |
1011 | ||
1012 | #define default_PCI_trigger(idx) (1) | |
1013 | #define default_PCI_polarity(idx) (1) | |
1014 | ||
1015 | /* MCA interrupts are always polarity zero level triggered, | |
1016 | * when listed as conforming in the MP table. */ | |
1017 | ||
1018 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1019 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1020 | |
61fd47e0 | 1021 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1022 | { |
2fddb6e2 | 1023 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1024 | int polarity; |
1025 | ||
1026 | /* | |
1027 | * Determine IRQ line polarity (high active or low active): | |
1028 | */ | |
54168ed7 | 1029 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 1030 | { |
54168ed7 IM |
1031 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1032 | if (test_bit(bus, mp_bus_not_pci)) | |
1033 | polarity = default_ISA_polarity(idx); | |
1034 | else | |
1035 | polarity = default_PCI_polarity(idx); | |
1036 | break; | |
1037 | case 1: /* high active */ | |
1038 | { | |
1039 | polarity = 0; | |
1040 | break; | |
1041 | } | |
1042 | case 2: /* reserved */ | |
1043 | { | |
1044 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1045 | polarity = 1; | |
1046 | break; | |
1047 | } | |
1048 | case 3: /* low active */ | |
1049 | { | |
1050 | polarity = 1; | |
1051 | break; | |
1052 | } | |
1053 | default: /* invalid */ | |
1054 | { | |
1055 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1056 | polarity = 1; | |
1057 | break; | |
1058 | } | |
1da177e4 LT |
1059 | } |
1060 | return polarity; | |
1061 | } | |
1062 | ||
1063 | static int MPBIOS_trigger(int idx) | |
1064 | { | |
2fddb6e2 | 1065 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1066 | int trigger; |
1067 | ||
1068 | /* | |
1069 | * Determine IRQ trigger mode (edge or level sensitive): | |
1070 | */ | |
54168ed7 | 1071 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1072 | { |
54168ed7 IM |
1073 | case 0: /* conforms, ie. bus-type dependent */ |
1074 | if (test_bit(bus, mp_bus_not_pci)) | |
1075 | trigger = default_ISA_trigger(idx); | |
1076 | else | |
1077 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1078 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1079 | switch (mp_bus_id_to_type[bus]) { |
1080 | case MP_BUS_ISA: /* ISA pin */ | |
1081 | { | |
1082 | /* set before the switch */ | |
1083 | break; | |
1084 | } | |
1085 | case MP_BUS_EISA: /* EISA pin */ | |
1086 | { | |
1087 | trigger = default_EISA_trigger(idx); | |
1088 | break; | |
1089 | } | |
1090 | case MP_BUS_PCI: /* PCI pin */ | |
1091 | { | |
1092 | /* set before the switch */ | |
1093 | break; | |
1094 | } | |
1095 | case MP_BUS_MCA: /* MCA pin */ | |
1096 | { | |
1097 | trigger = default_MCA_trigger(idx); | |
1098 | break; | |
1099 | } | |
1100 | default: | |
1101 | { | |
1102 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1103 | trigger = 1; | |
1104 | break; | |
1105 | } | |
1106 | } | |
1107 | #endif | |
1da177e4 | 1108 | break; |
54168ed7 | 1109 | case 1: /* edge */ |
1da177e4 | 1110 | { |
54168ed7 | 1111 | trigger = 0; |
1da177e4 LT |
1112 | break; |
1113 | } | |
54168ed7 | 1114 | case 2: /* reserved */ |
1da177e4 | 1115 | { |
54168ed7 IM |
1116 | printk(KERN_WARNING "broken BIOS!!\n"); |
1117 | trigger = 1; | |
1da177e4 LT |
1118 | break; |
1119 | } | |
54168ed7 | 1120 | case 3: /* level */ |
1da177e4 | 1121 | { |
54168ed7 | 1122 | trigger = 1; |
1da177e4 LT |
1123 | break; |
1124 | } | |
54168ed7 | 1125 | default: /* invalid */ |
1da177e4 LT |
1126 | { |
1127 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1128 | trigger = 0; |
1da177e4 LT |
1129 | break; |
1130 | } | |
1131 | } | |
1132 | return trigger; | |
1133 | } | |
1134 | ||
1135 | static inline int irq_polarity(int idx) | |
1136 | { | |
1137 | return MPBIOS_polarity(idx); | |
1138 | } | |
1139 | ||
1140 | static inline int irq_trigger(int idx) | |
1141 | { | |
1142 | return MPBIOS_trigger(idx); | |
1143 | } | |
1144 | ||
efa2559f | 1145 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1146 | static int pin_2_irq(int idx, int apic, int pin) |
1147 | { | |
1148 | int irq, i; | |
2fddb6e2 | 1149 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1150 | |
1151 | /* | |
1152 | * Debugging check, we are in big trouble if this message pops up! | |
1153 | */ | |
2fddb6e2 | 1154 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1155 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1156 | ||
54168ed7 | 1157 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1158 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1159 | } else { |
643befed AS |
1160 | /* |
1161 | * PCI IRQs are mapped in order | |
1162 | */ | |
1163 | i = irq = 0; | |
1164 | while (i < apic) | |
1165 | irq += nr_ioapic_registers[i++]; | |
1166 | irq += pin; | |
54168ed7 IM |
1167 | /* |
1168 | * For MPS mode, so far only needed by ES7000 platform | |
1169 | */ | |
1170 | if (ioapic_renumber_irq) | |
1171 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1172 | } |
1173 | ||
54168ed7 | 1174 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1175 | /* |
1176 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1177 | */ | |
1178 | if ((pin >= 16) && (pin <= 23)) { | |
1179 | if (pirq_entries[pin-16] != -1) { | |
1180 | if (!pirq_entries[pin-16]) { | |
1181 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1182 | "disabling PIRQ%d\n", pin-16); | |
1183 | } else { | |
1184 | irq = pirq_entries[pin-16]; | |
1185 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1186 | "using PIRQ%d -> IRQ %d\n", | |
1187 | pin-16, irq); | |
1188 | } | |
1189 | } | |
1190 | } | |
54168ed7 IM |
1191 | #endif |
1192 | ||
1da177e4 LT |
1193 | return irq; |
1194 | } | |
1195 | ||
497c9a19 YL |
1196 | void lock_vector_lock(void) |
1197 | { | |
1198 | /* Used to the online set of cpus does not change | |
1199 | * during assign_irq_vector. | |
1200 | */ | |
1201 | spin_lock(&vector_lock); | |
1202 | } | |
1da177e4 | 1203 | |
497c9a19 | 1204 | void unlock_vector_lock(void) |
1da177e4 | 1205 | { |
497c9a19 YL |
1206 | spin_unlock(&vector_lock); |
1207 | } | |
1da177e4 | 1208 | |
497c9a19 YL |
1209 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1210 | { | |
047c8fdb YL |
1211 | /* |
1212 | * NOTE! The local APIC isn't very good at handling | |
1213 | * multiple interrupts at the same interrupt level. | |
1214 | * As the interrupt level is determined by taking the | |
1215 | * vector number and shifting that right by 4, we | |
1216 | * want to spread these out a bit so that they don't | |
1217 | * all fall in the same interrupt level. | |
1218 | * | |
1219 | * Also, we've got to be careful not to trash gate | |
1220 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1221 | */ | |
54168ed7 IM |
1222 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1223 | unsigned int old_vector; | |
1224 | int cpu; | |
1225 | struct irq_cfg *cfg; | |
ace80ab7 | 1226 | |
54168ed7 | 1227 | cfg = irq_cfg(irq); |
8339f000 | 1228 | |
54168ed7 IM |
1229 | /* Only try and allocate irqs on cpus that are present */ |
1230 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1231 | |
54168ed7 IM |
1232 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1233 | return -EBUSY; | |
0a1ad60d | 1234 | |
54168ed7 IM |
1235 | old_vector = cfg->vector; |
1236 | if (old_vector) { | |
1237 | cpumask_t tmp; | |
1238 | cpus_and(tmp, cfg->domain, mask); | |
1239 | if (!cpus_empty(tmp)) | |
1240 | return 0; | |
1241 | } | |
497c9a19 | 1242 | |
54168ed7 IM |
1243 | for_each_cpu_mask_nr(cpu, mask) { |
1244 | cpumask_t domain, new_mask; | |
1245 | int new_cpu; | |
1246 | int vector, offset; | |
497c9a19 | 1247 | |
54168ed7 IM |
1248 | domain = vector_allocation_domain(cpu); |
1249 | cpus_and(new_mask, domain, cpu_online_map); | |
497c9a19 | 1250 | |
54168ed7 IM |
1251 | vector = current_vector; |
1252 | offset = current_offset; | |
497c9a19 | 1253 | next: |
54168ed7 IM |
1254 | vector += 8; |
1255 | if (vector >= first_system_vector) { | |
1256 | /* If we run out of vectors on large boxen, must share them. */ | |
1257 | offset = (offset + 1) % 8; | |
1258 | vector = FIRST_DEVICE_VECTOR + offset; | |
1259 | } | |
1260 | if (unlikely(current_vector == vector)) | |
1261 | continue; | |
047c8fdb | 1262 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1263 | if (vector == IA32_SYSCALL_VECTOR) |
1264 | goto next; | |
047c8fdb | 1265 | #else |
54168ed7 IM |
1266 | if (vector == SYSCALL_VECTOR) |
1267 | goto next; | |
047c8fdb | 1268 | #endif |
54168ed7 IM |
1269 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1270 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1271 | goto next; | |
1272 | /* Found one! */ | |
1273 | current_vector = vector; | |
1274 | current_offset = offset; | |
1275 | if (old_vector) { | |
1276 | cfg->move_in_progress = 1; | |
1277 | cfg->old_domain = cfg->domain; | |
7a959cff | 1278 | } |
54168ed7 IM |
1279 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1280 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1281 | cfg->vector = vector; | |
1282 | cfg->domain = domain; | |
1283 | return 0; | |
1284 | } | |
1285 | return -ENOSPC; | |
497c9a19 YL |
1286 | } |
1287 | ||
1288 | static int assign_irq_vector(int irq, cpumask_t mask) | |
1289 | { | |
1290 | int err; | |
ace80ab7 | 1291 | unsigned long flags; |
ace80ab7 EB |
1292 | |
1293 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 1294 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1295 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1296 | return err; |
1297 | } | |
1298 | ||
1299 | static void __clear_irq_vector(int irq) | |
1300 | { | |
1301 | struct irq_cfg *cfg; | |
1302 | cpumask_t mask; | |
1303 | int cpu, vector; | |
1304 | ||
1305 | cfg = irq_cfg(irq); | |
1306 | BUG_ON(!cfg->vector); | |
1307 | ||
1308 | vector = cfg->vector; | |
1309 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1310 | for_each_cpu_mask_nr(cpu, mask) | |
1311 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1312 | ||
1313 | cfg->vector = 0; | |
1314 | cpus_clear(cfg->domain); | |
1315 | } | |
1316 | ||
1317 | void __setup_vector_irq(int cpu) | |
1318 | { | |
1319 | /* Initialize vector_irq on a new cpu */ | |
1320 | /* This function must be called with vector_lock held */ | |
1321 | int irq, vector; | |
1322 | struct irq_cfg *cfg; | |
1323 | ||
1324 | /* Mark the inuse vectors */ | |
8f09cd20 | 1325 | for_each_irq_cfg(irq, cfg) { |
497c9a19 YL |
1326 | if (!cpu_isset(cpu, cfg->domain)) |
1327 | continue; | |
1328 | vector = cfg->vector; | |
497c9a19 YL |
1329 | per_cpu(vector_irq, cpu)[vector] = irq; |
1330 | } | |
1331 | /* Mark the free vectors */ | |
1332 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1333 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1334 | if (irq < 0) | |
1335 | continue; | |
1336 | ||
1337 | cfg = irq_cfg(irq); | |
1338 | if (!cpu_isset(cpu, cfg->domain)) | |
1339 | per_cpu(vector_irq, cpu)[vector] = -1; | |
54168ed7 | 1340 | } |
1da177e4 | 1341 | } |
3fde6900 | 1342 | |
f5b9ed7a | 1343 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1344 | #ifdef CONFIG_INTR_REMAP |
1345 | static struct irq_chip ir_ioapic_chip; | |
1346 | #endif | |
1da177e4 | 1347 | |
54168ed7 IM |
1348 | #define IOAPIC_AUTO -1 |
1349 | #define IOAPIC_EDGE 0 | |
1350 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1351 | |
047c8fdb | 1352 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1353 | static inline int IO_APIC_irq_trigger(int irq) |
1354 | { | |
54168ed7 | 1355 | int apic, idx, pin; |
1d025192 | 1356 | |
54168ed7 IM |
1357 | for (apic = 0; apic < nr_ioapics; apic++) { |
1358 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1359 | idx = find_irq_entry(apic, pin, mp_INT); | |
1360 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1361 | return irq_trigger(idx); | |
1362 | } | |
1363 | } | |
1364 | /* | |
1365 | * nonexistent IRQs are edge default | |
1366 | */ | |
1367 | return 0; | |
1d025192 | 1368 | } |
047c8fdb YL |
1369 | #else |
1370 | static inline int IO_APIC_irq_trigger(int irq) | |
1371 | { | |
54168ed7 | 1372 | return 1; |
047c8fdb YL |
1373 | } |
1374 | #endif | |
1d025192 | 1375 | |
497c9a19 | 1376 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1377 | { |
08678b08 YL |
1378 | struct irq_desc *desc; |
1379 | ||
199751d7 YL |
1380 | /* first time to use this irq_desc */ |
1381 | if (irq < 16) | |
1382 | desc = irq_to_desc(irq); | |
1383 | else | |
1384 | desc = irq_to_desc_alloc(irq); | |
1385 | ||
6ebcc00e | 1386 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1387 | trigger == IOAPIC_LEVEL) |
08678b08 | 1388 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1389 | else |
1390 | desc->status &= ~IRQ_LEVEL; | |
1391 | ||
54168ed7 IM |
1392 | #ifdef CONFIG_INTR_REMAP |
1393 | if (irq_remapped(irq)) { | |
1394 | desc->status |= IRQ_MOVE_PCNTXT; | |
1395 | if (trigger) | |
1396 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1397 | handle_fasteoi_irq, | |
1398 | "fasteoi"); | |
1399 | else | |
1400 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1401 | handle_edge_irq, "edge"); | |
1402 | return; | |
1403 | } | |
1404 | #endif | |
047c8fdb YL |
1405 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1406 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1407 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1408 | handle_fasteoi_irq, |
1409 | "fasteoi"); | |
047c8fdb | 1410 | else |
a460e745 | 1411 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1412 | handle_edge_irq, "edge"); |
1da177e4 LT |
1413 | } |
1414 | ||
497c9a19 YL |
1415 | static int setup_ioapic_entry(int apic, int irq, |
1416 | struct IO_APIC_route_entry *entry, | |
1417 | unsigned int destination, int trigger, | |
1418 | int polarity, int vector) | |
1da177e4 | 1419 | { |
497c9a19 YL |
1420 | /* |
1421 | * add it to the IO-APIC irq-routing table: | |
1422 | */ | |
1423 | memset(entry,0,sizeof(*entry)); | |
1424 | ||
54168ed7 IM |
1425 | #ifdef CONFIG_INTR_REMAP |
1426 | if (intr_remapping_enabled) { | |
1427 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1428 | struct irte irte; | |
1429 | struct IR_IO_APIC_route_entry *ir_entry = | |
1430 | (struct IR_IO_APIC_route_entry *) entry; | |
1431 | int index; | |
1432 | ||
1433 | if (!iommu) | |
1434 | panic("No mapping iommu for ioapic %d\n", apic); | |
1435 | ||
1436 | index = alloc_irte(iommu, irq, 1); | |
1437 | if (index < 0) | |
1438 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1439 | ||
1440 | memset(&irte, 0, sizeof(irte)); | |
1441 | ||
1442 | irte.present = 1; | |
1443 | irte.dst_mode = INT_DEST_MODE; | |
1444 | irte.trigger_mode = trigger; | |
1445 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1446 | irte.vector = vector; | |
1447 | irte.dest_id = IRTE_DEST(destination); | |
1448 | ||
1449 | modify_irte(irq, &irte); | |
1450 | ||
1451 | ir_entry->index2 = (index >> 15) & 0x1; | |
1452 | ir_entry->zero = 0; | |
1453 | ir_entry->format = 1; | |
1454 | ir_entry->index = (index & 0x7fff); | |
1455 | } else | |
1456 | #endif | |
1457 | { | |
1458 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1459 | entry->dest_mode = INT_DEST_MODE; | |
1460 | entry->dest = destination; | |
1461 | } | |
497c9a19 | 1462 | |
54168ed7 | 1463 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1464 | entry->trigger = trigger; |
1465 | entry->polarity = polarity; | |
1466 | entry->vector = vector; | |
1467 | ||
1468 | /* Mask level triggered irqs. | |
1469 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1470 | */ | |
1471 | if (trigger) | |
1472 | entry->mask = 1; | |
497c9a19 YL |
1473 | return 0; |
1474 | } | |
1475 | ||
1476 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
54168ed7 | 1477 | int trigger, int polarity) |
497c9a19 YL |
1478 | { |
1479 | struct irq_cfg *cfg; | |
1da177e4 | 1480 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1481 | cpumask_t mask; |
1482 | ||
1483 | if (!IO_APIC_IRQ(irq)) | |
1484 | return; | |
1485 | ||
1486 | cfg = irq_cfg(irq); | |
1487 | ||
1488 | mask = TARGET_CPUS; | |
1489 | if (assign_irq_vector(irq, mask)) | |
1490 | return; | |
1491 | ||
1492 | cpus_and(mask, cfg->domain, mask); | |
1493 | ||
1494 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1495 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1496 | "IRQ %d Mode:%i Active:%i)\n", | |
1497 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1498 | irq, trigger, polarity); | |
1499 | ||
1500 | ||
1501 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1502 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1503 | cfg->vector)) { | |
1504 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1505 | mp_ioapics[apic].mp_apicid, pin); | |
1506 | __clear_irq_vector(irq); | |
1507 | return; | |
1508 | } | |
1509 | ||
1510 | ioapic_register_intr(irq, trigger); | |
1511 | if (irq < 16) | |
1512 | disable_8259A_irq(irq); | |
1513 | ||
1514 | ioapic_write_entry(apic, pin, entry); | |
1515 | } | |
1516 | ||
1517 | static void __init setup_IO_APIC_irqs(void) | |
1518 | { | |
1519 | int apic, pin, idx, irq, first_notcon = 1; | |
1da177e4 LT |
1520 | |
1521 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1522 | ||
1523 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1524 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1525 | ||
497c9a19 | 1526 | idx = find_irq_entry(apic,pin,mp_INT); |
1da177e4 LT |
1527 | if (idx == -1) { |
1528 | if (first_notcon) { | |
497c9a19 | 1529 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1530 | first_notcon = 0; |
1531 | } else | |
497c9a19 | 1532 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1533 | continue; |
1534 | } | |
20d225b9 YL |
1535 | if (!first_notcon) { |
1536 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1537 | first_notcon = 1; | |
1538 | } | |
1539 | ||
1da177e4 | 1540 | irq = pin_2_irq(idx, apic, pin); |
54168ed7 | 1541 | #ifdef CONFIG_X86_32 |
497c9a19 YL |
1542 | if (multi_timer_check(apic, irq)) |
1543 | continue; | |
54168ed7 | 1544 | #endif |
497c9a19 | 1545 | add_pin_to_irq(irq, apic, pin); |
36062448 | 1546 | |
497c9a19 YL |
1547 | setup_IO_APIC_irq(apic, pin, irq, |
1548 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1549 | } |
1550 | } | |
1551 | ||
1552 | if (!first_notcon) | |
1553 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1554 | } | |
1555 | ||
1556 | /* | |
f7633ce5 | 1557 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1558 | */ |
f7633ce5 MR |
1559 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1560 | int vector) | |
1da177e4 LT |
1561 | { |
1562 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1563 | |
54168ed7 IM |
1564 | #ifdef CONFIG_INTR_REMAP |
1565 | if (intr_remapping_enabled) | |
1566 | return; | |
1567 | #endif | |
1568 | ||
36062448 | 1569 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1570 | |
1571 | /* | |
1572 | * We use logical delivery to get the timer IRQ | |
1573 | * to the first CPU. | |
1574 | */ | |
1575 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1576 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1577 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1578 | entry.delivery_mode = INT_DELIVERY_MODE; |
1579 | entry.polarity = 0; | |
1580 | entry.trigger = 0; | |
1581 | entry.vector = vector; | |
1582 | ||
1583 | /* | |
1584 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1585 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1586 | */ |
54168ed7 | 1587 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1588 | |
1589 | /* | |
1590 | * Add it to the IO-APIC irq-routing table: | |
1591 | */ | |
cf4c6a2f | 1592 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1593 | } |
1594 | ||
32f71aff MR |
1595 | |
1596 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1597 | { |
1598 | int apic, i; | |
1599 | union IO_APIC_reg_00 reg_00; | |
1600 | union IO_APIC_reg_01 reg_01; | |
1601 | union IO_APIC_reg_02 reg_02; | |
1602 | union IO_APIC_reg_03 reg_03; | |
1603 | unsigned long flags; | |
0f978f45 | 1604 | struct irq_cfg *cfg; |
8f09cd20 | 1605 | unsigned int irq; |
1da177e4 LT |
1606 | |
1607 | if (apic_verbosity == APIC_QUIET) | |
1608 | return; | |
1609 | ||
36062448 | 1610 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1611 | for (i = 0; i < nr_ioapics; i++) |
1612 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1613 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1614 | |
1615 | /* | |
1616 | * We are a bit conservative about what we expect. We have to | |
1617 | * know about every hardware change ASAP. | |
1618 | */ | |
1619 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1620 | ||
1621 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1622 | ||
1623 | spin_lock_irqsave(&ioapic_lock, flags); | |
1624 | reg_00.raw = io_apic_read(apic, 0); | |
1625 | reg_01.raw = io_apic_read(apic, 1); | |
1626 | if (reg_01.bits.version >= 0x10) | |
1627 | reg_02.raw = io_apic_read(apic, 2); | |
54168ed7 IM |
1628 | if (reg_01.bits.version >= 0x20) |
1629 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1630 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1631 | ||
54168ed7 | 1632 | printk("\n"); |
ec2cd0a2 | 1633 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1634 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1635 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1636 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1637 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1638 | |
54168ed7 | 1639 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1640 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1641 | |
1642 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1643 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1644 | |
1645 | /* | |
1646 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1647 | * but the value of reg_02 is read as the previous read register | |
1648 | * value, so ignore it if reg_02 == reg_01. | |
1649 | */ | |
1650 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1651 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1652 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1653 | } |
1654 | ||
1655 | /* | |
1656 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1657 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1658 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1659 | */ | |
1660 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1661 | reg_03.raw != reg_01.raw) { | |
1662 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1663 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1664 | } |
1665 | ||
1666 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1667 | ||
d83e94ac YL |
1668 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1669 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1670 | |
1671 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1672 | struct IO_APIC_route_entry entry; | |
1673 | ||
cf4c6a2f | 1674 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1675 | |
54168ed7 IM |
1676 | printk(KERN_DEBUG " %02x %03X ", |
1677 | i, | |
1678 | entry.dest | |
1679 | ); | |
1da177e4 LT |
1680 | |
1681 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1682 | entry.mask, | |
1683 | entry.trigger, | |
1684 | entry.irr, | |
1685 | entry.polarity, | |
1686 | entry.delivery_status, | |
1687 | entry.dest_mode, | |
1688 | entry.delivery_mode, | |
1689 | entry.vector | |
1690 | ); | |
1691 | } | |
1692 | } | |
1da177e4 | 1693 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
8f09cd20 | 1694 | for_each_irq_cfg(irq, cfg) { |
0f978f45 YL |
1695 | struct irq_pin_list *entry = cfg->irq_2_pin; |
1696 | if (!entry) | |
1da177e4 | 1697 | continue; |
8f09cd20 | 1698 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1699 | for (;;) { |
1700 | printk("-> %d:%d", entry->apic, entry->pin); | |
1701 | if (!entry->next) | |
1702 | break; | |
0f978f45 | 1703 | entry = entry->next; |
1da177e4 LT |
1704 | } |
1705 | printk("\n"); | |
1706 | } | |
1707 | ||
1708 | printk(KERN_INFO ".................................... done.\n"); | |
1709 | ||
1710 | return; | |
1711 | } | |
1712 | ||
32f71aff | 1713 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1714 | { |
1715 | unsigned int v; | |
1716 | int i, j; | |
1717 | ||
1718 | if (apic_verbosity == APIC_QUIET) | |
1719 | return; | |
1720 | ||
1721 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1722 | for (i = 0; i < 8; i++) { | |
1723 | v = apic_read(base + i*0x10); | |
1724 | for (j = 0; j < 32; j++) { | |
1725 | if (v & (1<<j)) | |
1726 | printk("1"); | |
1727 | else | |
1728 | printk("0"); | |
1729 | } | |
1730 | printk("\n"); | |
1731 | } | |
1732 | } | |
1733 | ||
32f71aff | 1734 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1735 | { |
1736 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1737 | u64 icr; |
1da177e4 LT |
1738 | |
1739 | if (apic_verbosity == APIC_QUIET) | |
1740 | return; | |
1741 | ||
1742 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1743 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1744 | v = apic_read(APIC_ID); |
54168ed7 | 1745 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1746 | v = apic_read(APIC_LVR); |
1747 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1748 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1749 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1750 | |
1751 | v = apic_read(APIC_TASKPRI); | |
1752 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1753 | ||
54168ed7 | 1754 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1755 | if (!APIC_XAPIC(ver)) { |
1756 | v = apic_read(APIC_ARBPRI); | |
1757 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1758 | v & APIC_ARBPRI_MASK); | |
1759 | } | |
1da177e4 LT |
1760 | v = apic_read(APIC_PROCPRI); |
1761 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1762 | } | |
1763 | ||
a11b5abe YL |
1764 | /* |
1765 | * Remote read supported only in the 82489DX and local APIC for | |
1766 | * Pentium processors. | |
1767 | */ | |
1768 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1769 | v = apic_read(APIC_RRR); | |
1770 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1771 | } | |
1772 | ||
1da177e4 LT |
1773 | v = apic_read(APIC_LDR); |
1774 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1775 | if (!x2apic_enabled()) { |
1776 | v = apic_read(APIC_DFR); | |
1777 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1778 | } | |
1da177e4 LT |
1779 | v = apic_read(APIC_SPIV); |
1780 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1781 | ||
1782 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1783 | print_APIC_bitfield(APIC_ISR); | |
1784 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1785 | print_APIC_bitfield(APIC_TMR); | |
1786 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1787 | print_APIC_bitfield(APIC_IRR); | |
1788 | ||
54168ed7 IM |
1789 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1790 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1791 | apic_write(APIC_ESR, 0); |
54168ed7 | 1792 | |
1da177e4 LT |
1793 | v = apic_read(APIC_ESR); |
1794 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1795 | } | |
1796 | ||
7ab6af7a | 1797 | icr = apic_icr_read(); |
0c425cec IM |
1798 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1799 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1800 | |
1801 | v = apic_read(APIC_LVTT); | |
1802 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1803 | ||
1804 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1805 | v = apic_read(APIC_LVTPC); | |
1806 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1807 | } | |
1808 | v = apic_read(APIC_LVT0); | |
1809 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1810 | v = apic_read(APIC_LVT1); | |
1811 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1812 | ||
1813 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1814 | v = apic_read(APIC_LVTERR); | |
1815 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1816 | } | |
1817 | ||
1818 | v = apic_read(APIC_TMICT); | |
1819 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1820 | v = apic_read(APIC_TMCCT); | |
1821 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1822 | v = apic_read(APIC_TDCR); | |
1823 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1824 | printk("\n"); | |
1825 | } | |
1826 | ||
32f71aff | 1827 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1828 | { |
ffd5aae7 YL |
1829 | int cpu; |
1830 | ||
1831 | preempt_disable(); | |
1832 | for_each_online_cpu(cpu) | |
1833 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1834 | preempt_enable(); | |
1da177e4 LT |
1835 | } |
1836 | ||
32f71aff | 1837 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1838 | { |
1da177e4 LT |
1839 | unsigned int v; |
1840 | unsigned long flags; | |
1841 | ||
1842 | if (apic_verbosity == APIC_QUIET) | |
1843 | return; | |
1844 | ||
1845 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1846 | ||
1847 | spin_lock_irqsave(&i8259A_lock, flags); | |
1848 | ||
1849 | v = inb(0xa1) << 8 | inb(0x21); | |
1850 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1851 | ||
1852 | v = inb(0xa0) << 8 | inb(0x20); | |
1853 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1854 | ||
54168ed7 IM |
1855 | outb(0x0b,0xa0); |
1856 | outb(0x0b,0x20); | |
1da177e4 | 1857 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1858 | outb(0x0a,0xa0); |
1859 | outb(0x0a,0x20); | |
1da177e4 LT |
1860 | |
1861 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1862 | ||
1863 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1864 | ||
1865 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1866 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1867 | } | |
1868 | ||
32f71aff MR |
1869 | __apicdebuginit(int) print_all_ICs(void) |
1870 | { | |
1871 | print_PIC(); | |
1872 | print_all_local_APICs(); | |
1873 | print_IO_APIC(); | |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | fs_initcall(print_all_ICs); | |
1879 | ||
1da177e4 | 1880 | |
efa2559f YL |
1881 | /* Where if anywhere is the i8259 connect in external int mode */ |
1882 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1883 | ||
54168ed7 | 1884 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1885 | { |
1886 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1887 | int i8259_apic, i8259_pin; |
54168ed7 | 1888 | int apic; |
1da177e4 LT |
1889 | unsigned long flags; |
1890 | ||
54168ed7 IM |
1891 | #ifdef CONFIG_X86_32 |
1892 | int i; | |
1da177e4 LT |
1893 | if (!pirqs_enabled) |
1894 | for (i = 0; i < MAX_PIRQS; i++) | |
1895 | pirq_entries[i] = -1; | |
54168ed7 | 1896 | #endif |
1da177e4 LT |
1897 | |
1898 | /* | |
1899 | * The number of IO-APIC IRQ registers (== #pins): | |
1900 | */ | |
fcfd636a | 1901 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1902 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1903 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1904 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1905 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1906 | } | |
54168ed7 | 1907 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1908 | int pin; |
1909 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1910 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1911 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1912 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1913 | |
fcfd636a EB |
1914 | /* If the interrupt line is enabled and in ExtInt mode |
1915 | * I have found the pin where the i8259 is connected. | |
1916 | */ | |
1917 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1918 | ioapic_i8259.apic = apic; | |
1919 | ioapic_i8259.pin = pin; | |
1920 | goto found_i8259; | |
1921 | } | |
1922 | } | |
1923 | } | |
1924 | found_i8259: | |
1925 | /* Look to see what if the MP table has reported the ExtINT */ | |
1926 | /* If we could not find the appropriate pin by looking at the ioapic | |
1927 | * the i8259 probably is not connected the ioapic but give the | |
1928 | * mptable a chance anyway. | |
1929 | */ | |
1930 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1931 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1932 | /* Trust the MP table if nothing is setup in the hardware */ | |
1933 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1934 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1935 | ioapic_i8259.pin = i8259_pin; | |
1936 | ioapic_i8259.apic = i8259_apic; | |
1937 | } | |
1938 | /* Complain if the MP table and the hardware disagree */ | |
1939 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1940 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1941 | { | |
1942 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1943 | } |
1944 | ||
1945 | /* | |
1946 | * Do not trust the IO-APIC being empty at bootup | |
1947 | */ | |
1948 | clear_IO_APIC(); | |
1949 | } | |
1950 | ||
1951 | /* | |
1952 | * Not an __init, needed by the reboot code | |
1953 | */ | |
1954 | void disable_IO_APIC(void) | |
1955 | { | |
1956 | /* | |
1957 | * Clear the IO-APIC before rebooting: | |
1958 | */ | |
1959 | clear_IO_APIC(); | |
1960 | ||
650927ef | 1961 | /* |
0b968d23 | 1962 | * If the i8259 is routed through an IOAPIC |
650927ef | 1963 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1964 | * so legacy interrupts can be delivered. |
650927ef | 1965 | */ |
fcfd636a | 1966 | if (ioapic_i8259.pin != -1) { |
650927ef | 1967 | struct IO_APIC_route_entry entry; |
650927ef EB |
1968 | |
1969 | memset(&entry, 0, sizeof(entry)); | |
1970 | entry.mask = 0; /* Enabled */ | |
1971 | entry.trigger = 0; /* Edge */ | |
1972 | entry.irr = 0; | |
1973 | entry.polarity = 0; /* High */ | |
1974 | entry.delivery_status = 0; | |
1975 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1976 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1977 | entry.vector = 0; |
54168ed7 | 1978 | entry.dest = read_apic_id(); |
650927ef EB |
1979 | |
1980 | /* | |
1981 | * Add it to the IO-APIC irq-routing table: | |
1982 | */ | |
cf4c6a2f | 1983 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1984 | } |
54168ed7 | 1985 | |
fcfd636a | 1986 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1987 | } |
1988 | ||
54168ed7 | 1989 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1990 | /* |
1991 | * function to set the IO-APIC physical IDs based on the | |
1992 | * values stored in the MPC table. | |
1993 | * | |
1994 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1995 | */ | |
1996 | ||
1da177e4 LT |
1997 | static void __init setup_ioapic_ids_from_mpc(void) |
1998 | { | |
1999 | union IO_APIC_reg_00 reg_00; | |
2000 | physid_mask_t phys_id_present_map; | |
2001 | int apic; | |
2002 | int i; | |
2003 | unsigned char old_id; | |
2004 | unsigned long flags; | |
2005 | ||
a4dbc34d | 2006 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2007 | return; |
d49c4288 | 2008 | |
ca05fea6 NP |
2009 | /* |
2010 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2011 | * no meaning without the serial APIC bus. | |
2012 | */ | |
7c5c1e42 SL |
2013 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2014 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2015 | return; |
1da177e4 LT |
2016 | /* |
2017 | * This is broken; anything with a real cpu count has to | |
2018 | * circumvent this idiocy regardless. | |
2019 | */ | |
2020 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2021 | ||
2022 | /* | |
2023 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2024 | */ | |
2025 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2026 | ||
2027 | /* Read the register 0 value */ | |
2028 | spin_lock_irqsave(&ioapic_lock, flags); | |
2029 | reg_00.raw = io_apic_read(apic, 0); | |
2030 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 2031 | |
ec2cd0a2 | 2032 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2033 | |
ec2cd0a2 | 2034 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 2035 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 2036 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2037 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2038 | reg_00.bits.ID); | |
ec2cd0a2 | 2039 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
2040 | } |
2041 | ||
1da177e4 LT |
2042 | /* |
2043 | * Sanity check, is the ID really free? Every APIC in a | |
2044 | * system must have a unique ID or we get lots of nice | |
2045 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2046 | */ | |
2047 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 2048 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2049 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2050 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2051 | for (i = 0; i < get_physical_broadcast(); i++) |
2052 | if (!physid_isset(i, phys_id_present_map)) | |
2053 | break; | |
2054 | if (i >= get_physical_broadcast()) | |
2055 | panic("Max APIC ID exceeded!\n"); | |
2056 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2057 | i); | |
2058 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2059 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2060 | } else { |
2061 | physid_mask_t tmp; | |
ec2cd0a2 | 2062 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2063 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2064 | "phys_id_present_map\n", | |
ec2cd0a2 | 2065 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2066 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2067 | } | |
2068 | ||
2069 | ||
2070 | /* | |
2071 | * We need to adjust the IRQ routing table | |
2072 | * if the ID changed. | |
2073 | */ | |
ec2cd0a2 | 2074 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2075 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2076 | if (mp_irqs[i].mp_dstapic == old_id) |
2077 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2078 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2079 | |
2080 | /* | |
2081 | * Read the right value from the MPC table and | |
2082 | * write it into the ID register. | |
36062448 | 2083 | */ |
1da177e4 LT |
2084 | apic_printk(APIC_VERBOSE, KERN_INFO |
2085 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2086 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2087 | |
ec2cd0a2 | 2088 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2089 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
2090 | io_apic_write(apic, 0, reg_00.raw); |
2091 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
2092 | |
2093 | /* | |
2094 | * Sanity check | |
2095 | */ | |
2096 | spin_lock_irqsave(&ioapic_lock, flags); | |
2097 | reg_00.raw = io_apic_read(apic, 0); | |
2098 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2099 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2100 | printk("could not set ID!\n"); |
2101 | else | |
2102 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2103 | } | |
2104 | } | |
54168ed7 | 2105 | #endif |
1da177e4 | 2106 | |
7ce0bcfd | 2107 | int no_timer_check __initdata; |
8542b200 ZA |
2108 | |
2109 | static int __init notimercheck(char *s) | |
2110 | { | |
2111 | no_timer_check = 1; | |
2112 | return 1; | |
2113 | } | |
2114 | __setup("no_timer_check", notimercheck); | |
2115 | ||
1da177e4 LT |
2116 | /* |
2117 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2118 | * about the timer IRQ. We do the following to work around the situation: | |
2119 | * | |
2120 | * - timer IRQ defaults to IO-APIC IRQ | |
2121 | * - if this function detects that timer IRQs are defunct, then we fall | |
2122 | * back to ISA timer IRQs | |
2123 | */ | |
f0a7a5c9 | 2124 | static int __init timer_irq_works(void) |
1da177e4 LT |
2125 | { |
2126 | unsigned long t1 = jiffies; | |
4aae0702 | 2127 | unsigned long flags; |
1da177e4 | 2128 | |
8542b200 ZA |
2129 | if (no_timer_check) |
2130 | return 1; | |
2131 | ||
4aae0702 | 2132 | local_save_flags(flags); |
1da177e4 LT |
2133 | local_irq_enable(); |
2134 | /* Let ten ticks pass... */ | |
2135 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2136 | local_irq_restore(flags); |
1da177e4 LT |
2137 | |
2138 | /* | |
2139 | * Expect a few ticks at least, to be sure some possible | |
2140 | * glue logic does not lock up after one or two first | |
2141 | * ticks in a non-ExtINT mode. Also the local APIC | |
2142 | * might have cached one ExtINT interrupt. Finally, at | |
2143 | * least one tick may be lost due to delays. | |
2144 | */ | |
54168ed7 IM |
2145 | |
2146 | /* jiffies wrap? */ | |
1d16b53e | 2147 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2148 | return 1; |
1da177e4 LT |
2149 | return 0; |
2150 | } | |
2151 | ||
2152 | /* | |
2153 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2154 | * number of pending IRQ events unhandled. These cases are very rare, | |
2155 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2156 | * better to do it this way as thus we do not have to be aware of | |
2157 | * 'pending' interrupts in the IRQ path, except at this point. | |
2158 | */ | |
2159 | /* | |
2160 | * Edge triggered needs to resend any interrupt | |
2161 | * that was delayed but this is now handled in the device | |
2162 | * independent code. | |
2163 | */ | |
2164 | ||
2165 | /* | |
2166 | * Starting up a edge-triggered IO-APIC interrupt is | |
2167 | * nasty - we need to make sure that we get the edge. | |
2168 | * If it is already asserted for some reason, we need | |
2169 | * return 1 to indicate that is was pending. | |
2170 | * | |
2171 | * This is not complete - we should be able to fake | |
2172 | * an edge even if it isn't on the 8259A... | |
2173 | */ | |
54168ed7 | 2174 | |
f5b9ed7a | 2175 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2176 | { |
2177 | int was_pending = 0; | |
2178 | unsigned long flags; | |
2179 | ||
2180 | spin_lock_irqsave(&ioapic_lock, flags); | |
2181 | if (irq < 16) { | |
2182 | disable_8259A_irq(irq); | |
2183 | if (i8259A_irq_pending(irq)) | |
2184 | was_pending = 1; | |
2185 | } | |
2186 | __unmask_IO_APIC_irq(irq); | |
2187 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2188 | ||
2189 | return was_pending; | |
2190 | } | |
2191 | ||
54168ed7 | 2192 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2193 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2194 | { |
54168ed7 IM |
2195 | |
2196 | struct irq_cfg *cfg = irq_cfg(irq); | |
2197 | unsigned long flags; | |
2198 | ||
2199 | spin_lock_irqsave(&vector_lock, flags); | |
2200 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); | |
2201 | spin_unlock_irqrestore(&vector_lock, flags); | |
c0ad90a3 IM |
2202 | |
2203 | return 1; | |
2204 | } | |
54168ed7 IM |
2205 | #else |
2206 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2207 | { |
54168ed7 | 2208 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2209 | |
54168ed7 IM |
2210 | return 1; |
2211 | } | |
2212 | #endif | |
497c9a19 | 2213 | |
54168ed7 IM |
2214 | /* |
2215 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2216 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2217 | * handled with the level-triggered descriptor, but that one has slightly | |
2218 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2219 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2220 | * races. | |
2221 | */ | |
497c9a19 | 2222 | |
54168ed7 | 2223 | #ifdef CONFIG_SMP |
497c9a19 | 2224 | |
54168ed7 IM |
2225 | #ifdef CONFIG_INTR_REMAP |
2226 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2227 | |
54168ed7 | 2228 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2229 | |
54168ed7 IM |
2230 | /* |
2231 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2232 | * | |
2233 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2234 | * and cpu destination) of IRTE and flush the hardware cache. | |
2235 | * | |
2236 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2237 | * vector information, along with modifying IRTE with vector and destination. | |
2238 | * So irq migration for level triggered is little bit more complex compared to | |
2239 | * edge triggered migration. But the good news is, we use the same algorithm | |
2240 | * for level triggered migration as we have today, only difference being, | |
2241 | * we now initiate the irq migration from process context instead of the | |
2242 | * interrupt context. | |
2243 | * | |
2244 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2245 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2246 | * as simple as edge triggered migration and we can do the irq migration | |
2247 | * with a simple atomic update to IO-APIC RTE. | |
2248 | */ | |
2249 | static void migrate_ioapic_irq(int irq, cpumask_t mask) | |
497c9a19 | 2250 | { |
54168ed7 IM |
2251 | struct irq_cfg *cfg; |
2252 | struct irq_desc *desc; | |
2253 | cpumask_t tmp, cleanup_mask; | |
2254 | struct irte irte; | |
2255 | int modify_ioapic_rte; | |
2256 | unsigned int dest; | |
2257 | unsigned long flags; | |
497c9a19 | 2258 | |
54168ed7 IM |
2259 | cpus_and(tmp, mask, cpu_online_map); |
2260 | if (cpus_empty(tmp)) | |
497c9a19 YL |
2261 | return; |
2262 | ||
54168ed7 IM |
2263 | if (get_irte(irq, &irte)) |
2264 | return; | |
497c9a19 | 2265 | |
54168ed7 IM |
2266 | if (assign_irq_vector(irq, mask)) |
2267 | return; | |
2268 | ||
2269 | cfg = irq_cfg(irq); | |
2270 | cpus_and(tmp, cfg->domain, mask); | |
2271 | dest = cpu_mask_to_apicid(tmp); | |
2272 | ||
2273 | desc = irq_to_desc(irq); | |
2274 | modify_ioapic_rte = desc->status & IRQ_LEVEL; | |
2275 | if (modify_ioapic_rte) { | |
2276 | spin_lock_irqsave(&ioapic_lock, flags); | |
2277 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
2278 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2279 | } | |
2280 | ||
2281 | irte.vector = cfg->vector; | |
2282 | irte.dest_id = IRTE_DEST(dest); | |
2283 | ||
2284 | /* | |
2285 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2286 | */ | |
2287 | modify_irte(irq, &irte); | |
2288 | ||
2289 | if (cfg->move_in_progress) { | |
2290 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2291 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2292 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2293 | cfg->move_in_progress = 0; | |
2294 | } | |
2295 | ||
2296 | desc->affinity = mask; | |
2297 | } | |
2298 | ||
2299 | static int migrate_irq_remapped_level(int irq) | |
2300 | { | |
2301 | int ret = -1; | |
2302 | struct irq_desc *desc = irq_to_desc(irq); | |
2303 | ||
2304 | mask_IO_APIC_irq(irq); | |
2305 | ||
2306 | if (io_apic_level_ack_pending(irq)) { | |
2307 | /* | |
2308 | * Interrupt in progress. Migrating irq now will change the | |
2309 | * vector information in the IO-APIC RTE and that will confuse | |
2310 | * the EOI broadcast performed by cpu. | |
2311 | * So, delay the irq migration to the next instance. | |
2312 | */ | |
2313 | schedule_delayed_work(&ir_migration_work, 1); | |
2314 | goto unmask; | |
2315 | } | |
2316 | ||
2317 | /* everthing is clear. we have right of way */ | |
2318 | migrate_ioapic_irq(irq, desc->pending_mask); | |
2319 | ||
2320 | ret = 0; | |
2321 | desc->status &= ~IRQ_MOVE_PENDING; | |
2322 | cpus_clear(desc->pending_mask); | |
2323 | ||
2324 | unmask: | |
2325 | unmask_IO_APIC_irq(irq); | |
2326 | return ret; | |
2327 | } | |
2328 | ||
2329 | static void ir_irq_migration(struct work_struct *work) | |
2330 | { | |
2331 | unsigned int irq; | |
2332 | struct irq_desc *desc; | |
2333 | ||
2334 | for_each_irq_desc(irq, desc) { | |
2335 | if (desc->status & IRQ_MOVE_PENDING) { | |
2336 | unsigned long flags; | |
2337 | ||
2338 | spin_lock_irqsave(&desc->lock, flags); | |
2339 | if (!desc->chip->set_affinity || | |
2340 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2341 | desc->status &= ~IRQ_MOVE_PENDING; | |
2342 | spin_unlock_irqrestore(&desc->lock, flags); | |
2343 | continue; | |
2344 | } | |
2345 | ||
2346 | desc->chip->set_affinity(irq, desc->pending_mask); | |
2347 | spin_unlock_irqrestore(&desc->lock, flags); | |
2348 | } | |
2349 | } | |
2350 | } | |
2351 | ||
2352 | /* | |
2353 | * Migrates the IRQ destination in the process context. | |
2354 | */ | |
2355 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
2356 | { | |
2357 | struct irq_desc *desc = irq_to_desc(irq); | |
2358 | ||
2359 | if (desc->status & IRQ_LEVEL) { | |
2360 | desc->status |= IRQ_MOVE_PENDING; | |
2361 | desc->pending_mask = mask; | |
2362 | migrate_irq_remapped_level(irq); | |
2363 | return; | |
2364 | } | |
2365 | ||
2366 | migrate_ioapic_irq(irq, mask); | |
2367 | } | |
2368 | #endif | |
2369 | ||
2370 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2371 | { | |
2372 | unsigned vector, me; | |
2373 | ack_APIC_irq(); | |
2374 | #ifdef CONFIG_X86_64 | |
2375 | exit_idle(); | |
2376 | #endif | |
2377 | irq_enter(); | |
2378 | ||
2379 | me = smp_processor_id(); | |
2380 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2381 | unsigned int irq; | |
2382 | struct irq_desc *desc; | |
2383 | struct irq_cfg *cfg; | |
2384 | irq = __get_cpu_var(vector_irq)[vector]; | |
2385 | ||
2386 | desc = irq_to_desc(irq); | |
2387 | if (!desc) | |
2388 | continue; | |
2389 | ||
2390 | cfg = irq_cfg(irq); | |
2391 | spin_lock(&desc->lock); | |
2392 | if (!cfg->move_cleanup_count) | |
2393 | goto unlock; | |
2394 | ||
2395 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2396 | goto unlock; | |
2397 | ||
2398 | __get_cpu_var(vector_irq)[vector] = -1; | |
2399 | cfg->move_cleanup_count--; | |
2400 | unlock: | |
2401 | spin_unlock(&desc->lock); | |
2402 | } | |
2403 | ||
2404 | irq_exit(); | |
2405 | } | |
2406 | ||
2407 | static void irq_complete_move(unsigned int irq) | |
2408 | { | |
2409 | struct irq_cfg *cfg = irq_cfg(irq); | |
2410 | unsigned vector, me; | |
2411 | ||
2412 | if (likely(!cfg->move_in_progress)) | |
2413 | return; | |
2414 | ||
2415 | vector = ~get_irq_regs()->orig_ax; | |
2416 | me = smp_processor_id(); | |
2417 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2418 | cpumask_t cleanup_mask; | |
2419 | ||
2420 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2421 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2422 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
497c9a19 YL |
2423 | cfg->move_in_progress = 0; |
2424 | } | |
2425 | } | |
2426 | #else | |
2427 | static inline void irq_complete_move(unsigned int irq) {} | |
2428 | #endif | |
54168ed7 IM |
2429 | #ifdef CONFIG_INTR_REMAP |
2430 | static void ack_x2apic_level(unsigned int irq) | |
2431 | { | |
2432 | ack_x2APIC_irq(); | |
2433 | } | |
2434 | ||
2435 | static void ack_x2apic_edge(unsigned int irq) | |
2436 | { | |
2437 | ack_x2APIC_irq(); | |
2438 | } | |
2439 | #endif | |
497c9a19 | 2440 | |
1d025192 YL |
2441 | static void ack_apic_edge(unsigned int irq) |
2442 | { | |
2443 | irq_complete_move(irq); | |
2444 | move_native_irq(irq); | |
2445 | ack_APIC_irq(); | |
2446 | } | |
2447 | ||
3eb2cce8 YL |
2448 | #ifdef CONFIG_X86_32 |
2449 | atomic_t irq_mis_count; | |
2450 | #endif | |
2451 | ||
047c8fdb YL |
2452 | static void ack_apic_level(unsigned int irq) |
2453 | { | |
3eb2cce8 YL |
2454 | #ifdef CONFIG_X86_32 |
2455 | unsigned long v; | |
2456 | int i; | |
2457 | #endif | |
54168ed7 | 2458 | int do_unmask_irq = 0; |
047c8fdb | 2459 | |
54168ed7 | 2460 | irq_complete_move(irq); |
047c8fdb | 2461 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 IM |
2462 | /* If we are moving the irq we need to mask it */ |
2463 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { | |
2464 | do_unmask_irq = 1; | |
2465 | mask_IO_APIC_irq(irq); | |
2466 | } | |
047c8fdb YL |
2467 | #endif |
2468 | ||
3eb2cce8 YL |
2469 | #ifdef CONFIG_X86_32 |
2470 | /* | |
2471 | * It appears there is an erratum which affects at least version 0x11 | |
2472 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2473 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2474 | * erroneously delivered as edge-triggered one but the respective IRR | |
2475 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2476 | * message but it will never arrive and further interrupts are blocked | |
2477 | * from the source. The exact reason is so far unknown, but the | |
2478 | * phenomenon was observed when two consecutive interrupt requests | |
2479 | * from a given source get delivered to the same CPU and the source is | |
2480 | * temporarily disabled in between. | |
2481 | * | |
2482 | * A workaround is to simulate an EOI message manually. We achieve it | |
2483 | * by setting the trigger mode to edge and then to level when the edge | |
2484 | * trigger mode gets detected in the TMR of a local APIC for a | |
2485 | * level-triggered interrupt. We mask the source for the time of the | |
2486 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2487 | * The idea is from Manfred Spraul. --macro | |
2488 | */ | |
2489 | i = irq_cfg(irq)->vector; | |
2490 | ||
2491 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2492 | #endif | |
2493 | ||
54168ed7 IM |
2494 | /* |
2495 | * We must acknowledge the irq before we move it or the acknowledge will | |
2496 | * not propagate properly. | |
2497 | */ | |
2498 | ack_APIC_irq(); | |
2499 | ||
2500 | /* Now we can move and renable the irq */ | |
2501 | if (unlikely(do_unmask_irq)) { | |
2502 | /* Only migrate the irq if the ack has been received. | |
2503 | * | |
2504 | * On rare occasions the broadcast level triggered ack gets | |
2505 | * delayed going to ioapics, and if we reprogram the | |
2506 | * vector while Remote IRR is still set the irq will never | |
2507 | * fire again. | |
2508 | * | |
2509 | * To prevent this scenario we read the Remote IRR bit | |
2510 | * of the ioapic. This has two effects. | |
2511 | * - On any sane system the read of the ioapic will | |
2512 | * flush writes (and acks) going to the ioapic from | |
2513 | * this cpu. | |
2514 | * - We get to see if the ACK has actually been delivered. | |
2515 | * | |
2516 | * Based on failed experiments of reprogramming the | |
2517 | * ioapic entry from outside of irq context starting | |
2518 | * with masking the ioapic entry and then polling until | |
2519 | * Remote IRR was clear before reprogramming the | |
2520 | * ioapic I don't trust the Remote IRR bit to be | |
2521 | * completey accurate. | |
2522 | * | |
2523 | * However there appears to be no other way to plug | |
2524 | * this race, so if the Remote IRR bit is not | |
2525 | * accurate and is causing problems then it is a hardware bug | |
2526 | * and you can go talk to the chipset vendor about it. | |
2527 | */ | |
2528 | if (!io_apic_level_ack_pending(irq)) | |
2529 | move_masked_irq(irq); | |
2530 | unmask_IO_APIC_irq(irq); | |
2531 | } | |
1d025192 | 2532 | |
3eb2cce8 | 2533 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2534 | if (!(v & (1 << (i & 0x1f)))) { |
2535 | atomic_inc(&irq_mis_count); | |
2536 | spin_lock(&ioapic_lock); | |
2537 | __mask_and_edge_IO_APIC_irq(irq); | |
2538 | __unmask_and_level_IO_APIC_irq(irq); | |
2539 | spin_unlock(&ioapic_lock); | |
2540 | } | |
047c8fdb | 2541 | #endif |
3eb2cce8 | 2542 | } |
1d025192 | 2543 | |
f5b9ed7a IM |
2544 | static struct irq_chip ioapic_chip __read_mostly = { |
2545 | .name = "IO-APIC", | |
ace80ab7 EB |
2546 | .startup = startup_ioapic_irq, |
2547 | .mask = mask_IO_APIC_irq, | |
2548 | .unmask = unmask_IO_APIC_irq, | |
1d025192 YL |
2549 | .ack = ack_apic_edge, |
2550 | .eoi = ack_apic_level, | |
54d5d424 | 2551 | #ifdef CONFIG_SMP |
ace80ab7 | 2552 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2553 | #endif |
ace80ab7 | 2554 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2555 | }; |
2556 | ||
54168ed7 IM |
2557 | #ifdef CONFIG_INTR_REMAP |
2558 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
2559 | .name = "IR-IO-APIC", | |
2560 | .startup = startup_ioapic_irq, | |
2561 | .mask = mask_IO_APIC_irq, | |
2562 | .unmask = unmask_IO_APIC_irq, | |
2563 | .ack = ack_x2apic_edge, | |
2564 | .eoi = ack_x2apic_level, | |
2565 | #ifdef CONFIG_SMP | |
2566 | .set_affinity = set_ir_ioapic_affinity_irq, | |
2567 | #endif | |
2568 | .retrigger = ioapic_retrigger_irq, | |
2569 | }; | |
2570 | #endif | |
1da177e4 LT |
2571 | |
2572 | static inline void init_IO_APIC_traps(void) | |
2573 | { | |
2574 | int irq; | |
08678b08 | 2575 | struct irq_desc *desc; |
da51a821 | 2576 | struct irq_cfg *cfg; |
1da177e4 LT |
2577 | |
2578 | /* | |
2579 | * NOTE! The local APIC isn't very good at handling | |
2580 | * multiple interrupts at the same interrupt level. | |
2581 | * As the interrupt level is determined by taking the | |
2582 | * vector number and shifting that right by 4, we | |
2583 | * want to spread these out a bit so that they don't | |
2584 | * all fall in the same interrupt level. | |
2585 | * | |
2586 | * Also, we've got to be careful not to trash gate | |
2587 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2588 | */ | |
8f09cd20 | 2589 | for_each_irq_cfg(irq, cfg) { |
da51a821 | 2590 | if (IO_APIC_IRQ(irq) && !cfg->vector) { |
1da177e4 LT |
2591 | /* |
2592 | * Hmm.. We don't have an entry for this, | |
2593 | * so default to an old-fashioned 8259 | |
2594 | * interrupt if we can.. | |
2595 | */ | |
2596 | if (irq < 16) | |
2597 | make_8259A_irq(irq); | |
08678b08 YL |
2598 | else { |
2599 | desc = irq_to_desc(irq); | |
1da177e4 | 2600 | /* Strange. Oh, well.. */ |
08678b08 YL |
2601 | desc->chip = &no_irq_chip; |
2602 | } | |
1da177e4 LT |
2603 | } |
2604 | } | |
2605 | } | |
2606 | ||
f5b9ed7a IM |
2607 | /* |
2608 | * The local APIC irq-chip implementation: | |
2609 | */ | |
1da177e4 | 2610 | |
36062448 | 2611 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2612 | { |
2613 | unsigned long v; | |
2614 | ||
2615 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2616 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2617 | } |
2618 | ||
36062448 | 2619 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2620 | { |
f5b9ed7a | 2621 | unsigned long v; |
1da177e4 | 2622 | |
f5b9ed7a | 2623 | v = apic_read(APIC_LVT0); |
593f4a78 | 2624 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2625 | } |
1da177e4 | 2626 | |
54168ed7 | 2627 | static void ack_lapic_irq (unsigned int irq) |
1d025192 YL |
2628 | { |
2629 | ack_APIC_irq(); | |
2630 | } | |
2631 | ||
f5b9ed7a | 2632 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2633 | .name = "local-APIC", |
f5b9ed7a IM |
2634 | .mask = mask_lapic_irq, |
2635 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2636 | .ack = ack_lapic_irq, |
1da177e4 LT |
2637 | }; |
2638 | ||
497c9a19 | 2639 | static void lapic_register_intr(int irq) |
c88ac1df | 2640 | { |
08678b08 YL |
2641 | struct irq_desc *desc; |
2642 | ||
2643 | desc = irq_to_desc(irq); | |
2644 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2645 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2646 | "edge"); | |
c88ac1df MR |
2647 | } |
2648 | ||
e9427101 | 2649 | static void __init setup_nmi(void) |
1da177e4 LT |
2650 | { |
2651 | /* | |
36062448 | 2652 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2653 | * We put the 8259A master into AEOI mode and |
2654 | * unmask on all local APICs LVT0 as NMI. | |
2655 | * | |
2656 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2657 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2658 | * the NMI handler or the timer interrupt. | |
36062448 | 2659 | */ |
1da177e4 LT |
2660 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2661 | ||
e9427101 | 2662 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2663 | |
2664 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2665 | } | |
2666 | ||
2667 | /* | |
2668 | * This looks a bit hackish but it's about the only one way of sending | |
2669 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2670 | * not support the ExtINT mode, unfortunately. We need to send these | |
2671 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2672 | * 8259A interrupt line asserted until INTA. --macro | |
2673 | */ | |
28acf285 | 2674 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2675 | { |
fcfd636a | 2676 | int apic, pin, i; |
1da177e4 LT |
2677 | struct IO_APIC_route_entry entry0, entry1; |
2678 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2679 | |
fcfd636a | 2680 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2681 | if (pin == -1) { |
2682 | WARN_ON_ONCE(1); | |
2683 | return; | |
2684 | } | |
fcfd636a | 2685 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2686 | if (apic == -1) { |
2687 | WARN_ON_ONCE(1); | |
1da177e4 | 2688 | return; |
956fb531 | 2689 | } |
1da177e4 | 2690 | |
cf4c6a2f | 2691 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2692 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2693 | |
2694 | memset(&entry1, 0, sizeof(entry1)); | |
2695 | ||
2696 | entry1.dest_mode = 0; /* physical delivery */ | |
2697 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2698 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2699 | entry1.delivery_mode = dest_ExtINT; |
2700 | entry1.polarity = entry0.polarity; | |
2701 | entry1.trigger = 0; | |
2702 | entry1.vector = 0; | |
2703 | ||
cf4c6a2f | 2704 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2705 | |
2706 | save_control = CMOS_READ(RTC_CONTROL); | |
2707 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2708 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2709 | RTC_FREQ_SELECT); | |
2710 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2711 | ||
2712 | i = 100; | |
2713 | while (i-- > 0) { | |
2714 | mdelay(10); | |
2715 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2716 | i -= 10; | |
2717 | } | |
2718 | ||
2719 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2720 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2721 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2722 | |
cf4c6a2f | 2723 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2724 | } |
2725 | ||
efa2559f | 2726 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2727 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2728 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2729 | { |
2730 | disable_timer_pin_1 = 1; | |
2731 | return 0; | |
2732 | } | |
54168ed7 | 2733 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2734 | |
2735 | int timer_through_8259 __initdata; | |
2736 | ||
1da177e4 LT |
2737 | /* |
2738 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2739 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2740 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2741 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2742 | * |
2743 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2744 | */ |
8542b200 | 2745 | static inline void __init check_timer(void) |
1da177e4 | 2746 | { |
497c9a19 | 2747 | struct irq_cfg *cfg = irq_cfg(0); |
fcfd636a | 2748 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2749 | unsigned long flags; |
047c8fdb YL |
2750 | unsigned int ver; |
2751 | int no_pin1 = 0; | |
4aae0702 IM |
2752 | |
2753 | local_irq_save(flags); | |
d4d25dec | 2754 | |
54168ed7 IM |
2755 | ver = apic_read(APIC_LVR); |
2756 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2757 | |
1da177e4 LT |
2758 | /* |
2759 | * get/set the timer IRQ vector: | |
2760 | */ | |
2761 | disable_8259A_irq(0); | |
497c9a19 | 2762 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2763 | |
2764 | /* | |
d11d5794 MR |
2765 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2766 | * wire has to be disabled in the local APIC. Also | |
2767 | * timer interrupts need to be acknowledged manually in | |
2768 | * the 8259A for the i82489DX when using the NMI | |
2769 | * watchdog as that APIC treats NMIs as level-triggered. | |
2770 | * The AEOI mode will finish them in the 8259A | |
2771 | * automatically. | |
1da177e4 | 2772 | */ |
593f4a78 | 2773 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2774 | init_8259A(1); |
54168ed7 | 2775 | #ifdef CONFIG_X86_32 |
d11d5794 | 2776 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2777 | #endif |
1da177e4 | 2778 | |
fcfd636a EB |
2779 | pin1 = find_isa_irq_pin(0, mp_INT); |
2780 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2781 | pin2 = ioapic_i8259.pin; | |
2782 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2783 | |
49a66a0b MR |
2784 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2785 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2786 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2787 | |
691874fa MR |
2788 | /* |
2789 | * Some BIOS writers are clueless and report the ExtINTA | |
2790 | * I/O APIC input from the cascaded 8259A as the timer | |
2791 | * interrupt input. So just in case, if only one pin | |
2792 | * was found above, try it both directly and through the | |
2793 | * 8259A. | |
2794 | */ | |
2795 | if (pin1 == -1) { | |
54168ed7 IM |
2796 | #ifdef CONFIG_INTR_REMAP |
2797 | if (intr_remapping_enabled) | |
2798 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2799 | #endif | |
691874fa MR |
2800 | pin1 = pin2; |
2801 | apic1 = apic2; | |
2802 | no_pin1 = 1; | |
2803 | } else if (pin2 == -1) { | |
2804 | pin2 = pin1; | |
2805 | apic2 = apic1; | |
2806 | } | |
2807 | ||
1da177e4 LT |
2808 | if (pin1 != -1) { |
2809 | /* | |
2810 | * Ok, does IRQ0 through the IOAPIC work? | |
2811 | */ | |
691874fa MR |
2812 | if (no_pin1) { |
2813 | add_pin_to_irq(0, apic1, pin1); | |
497c9a19 | 2814 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2815 | } |
1da177e4 LT |
2816 | unmask_IO_APIC_irq(0); |
2817 | if (timer_irq_works()) { | |
2818 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2819 | setup_nmi(); |
2820 | enable_8259A_irq(0); | |
1da177e4 | 2821 | } |
66759a01 CE |
2822 | if (disable_timer_pin_1 > 0) |
2823 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2824 | goto out; |
1da177e4 | 2825 | } |
54168ed7 IM |
2826 | #ifdef CONFIG_INTR_REMAP |
2827 | if (intr_remapping_enabled) | |
2828 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2829 | #endif | |
fcfd636a | 2830 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2831 | if (!no_pin1) |
49a66a0b MR |
2832 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2833 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2834 | |
49a66a0b MR |
2835 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2836 | "(IRQ0) through the 8259A ...\n"); | |
2837 | apic_printk(APIC_QUIET, KERN_INFO | |
2838 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2839 | /* |
2840 | * legacy devices should be connected to IO APIC #0 | |
2841 | */ | |
691874fa | 2842 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
497c9a19 | 2843 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2844 | unmask_IO_APIC_irq(0); |
ecd29476 | 2845 | enable_8259A_irq(0); |
1da177e4 | 2846 | if (timer_irq_works()) { |
49a66a0b | 2847 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2848 | timer_through_8259 = 1; |
1da177e4 | 2849 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2850 | disable_8259A_irq(0); |
1da177e4 | 2851 | setup_nmi(); |
60134ebe | 2852 | enable_8259A_irq(0); |
1da177e4 | 2853 | } |
4aae0702 | 2854 | goto out; |
1da177e4 LT |
2855 | } |
2856 | /* | |
2857 | * Cleanup, just in case ... | |
2858 | */ | |
ecd29476 | 2859 | disable_8259A_irq(0); |
fcfd636a | 2860 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2861 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2862 | } |
1da177e4 LT |
2863 | |
2864 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2865 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2866 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2867 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2868 | } |
54168ed7 | 2869 | #ifdef CONFIG_X86_32 |
d11d5794 | 2870 | timer_ack = 0; |
54168ed7 | 2871 | #endif |
1da177e4 | 2872 | |
49a66a0b MR |
2873 | apic_printk(APIC_QUIET, KERN_INFO |
2874 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2875 | |
497c9a19 YL |
2876 | lapic_register_intr(0); |
2877 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ | |
1da177e4 LT |
2878 | enable_8259A_irq(0); |
2879 | ||
2880 | if (timer_irq_works()) { | |
49a66a0b | 2881 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2882 | goto out; |
1da177e4 | 2883 | } |
e67465f1 | 2884 | disable_8259A_irq(0); |
497c9a19 | 2885 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2886 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2887 | |
49a66a0b MR |
2888 | apic_printk(APIC_QUIET, KERN_INFO |
2889 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2890 | |
1da177e4 LT |
2891 | init_8259A(0); |
2892 | make_8259A_irq(0); | |
593f4a78 | 2893 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2894 | |
2895 | unlock_ExtINT_logic(); | |
2896 | ||
2897 | if (timer_irq_works()) { | |
49a66a0b | 2898 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2899 | goto out; |
1da177e4 | 2900 | } |
49a66a0b | 2901 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2902 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2903 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2904 | out: |
2905 | local_irq_restore(flags); | |
1da177e4 LT |
2906 | } |
2907 | ||
2908 | /* | |
af174783 MR |
2909 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2910 | * to devices. However there may be an I/O APIC pin available for | |
2911 | * this interrupt regardless. The pin may be left unconnected, but | |
2912 | * typically it will be reused as an ExtINT cascade interrupt for | |
2913 | * the master 8259A. In the MPS case such a pin will normally be | |
2914 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2915 | * there is no provision for ExtINT interrupts, and in the absence | |
2916 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2917 | * interrupt, that is edge-triggered and unmasked by default. We | |
2918 | * used to do this, but it caused problems on some systems because | |
2919 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2920 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2921 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2922 | * the I/O APIC in all cases now. No actual device should request | |
2923 | * it anyway. --macro | |
1da177e4 LT |
2924 | */ |
2925 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2926 | ||
2927 | void __init setup_IO_APIC(void) | |
2928 | { | |
54168ed7 IM |
2929 | |
2930 | #ifdef CONFIG_X86_32 | |
1da177e4 | 2931 | enable_IO_APIC(); |
54168ed7 IM |
2932 | #else |
2933 | /* | |
2934 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2935 | */ | |
2936 | #endif | |
1da177e4 | 2937 | |
af174783 | 2938 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 2939 | |
54168ed7 IM |
2940 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
2941 | /* | |
2942 | * Set up IO-APIC IRQ routing. | |
2943 | */ | |
2944 | #ifdef CONFIG_X86_32 | |
2945 | if (!acpi_ioapic) | |
2946 | setup_ioapic_ids_from_mpc(); | |
2947 | #endif | |
1da177e4 LT |
2948 | sync_Arb_IDs(); |
2949 | setup_IO_APIC_irqs(); | |
2950 | init_IO_APIC_traps(); | |
1e4c85f9 | 2951 | check_timer(); |
1da177e4 LT |
2952 | } |
2953 | ||
2954 | /* | |
54168ed7 IM |
2955 | * Called after all the initialization is done. If we didnt find any |
2956 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2957 | */ |
36062448 | 2958 | |
1da177e4 LT |
2959 | static int __init io_apic_bug_finalize(void) |
2960 | { | |
54168ed7 IM |
2961 | if (sis_apic_bug == -1) |
2962 | sis_apic_bug = 0; | |
2963 | return 0; | |
1da177e4 LT |
2964 | } |
2965 | ||
2966 | late_initcall(io_apic_bug_finalize); | |
2967 | ||
2968 | struct sysfs_ioapic_data { | |
2969 | struct sys_device dev; | |
2970 | struct IO_APIC_route_entry entry[0]; | |
2971 | }; | |
54168ed7 | 2972 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2973 | |
438510f6 | 2974 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2975 | { |
2976 | struct IO_APIC_route_entry *entry; | |
2977 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2978 | int i; |
36062448 | 2979 | |
1da177e4 LT |
2980 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2981 | entry = data->entry; | |
54168ed7 IM |
2982 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2983 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2984 | |
2985 | return 0; | |
2986 | } | |
2987 | ||
2988 | static int ioapic_resume(struct sys_device *dev) | |
2989 | { | |
2990 | struct IO_APIC_route_entry *entry; | |
2991 | struct sysfs_ioapic_data *data; | |
2992 | unsigned long flags; | |
2993 | union IO_APIC_reg_00 reg_00; | |
2994 | int i; | |
36062448 | 2995 | |
1da177e4 LT |
2996 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2997 | entry = data->entry; | |
2998 | ||
2999 | spin_lock_irqsave(&ioapic_lock, flags); | |
3000 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
3001 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
3002 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
3003 | io_apic_write(dev->id, 0, reg_00.raw); |
3004 | } | |
1da177e4 | 3005 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3006 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3007 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3008 | |
3009 | return 0; | |
3010 | } | |
3011 | ||
3012 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3013 | .name = "ioapic", |
1da177e4 LT |
3014 | .suspend = ioapic_suspend, |
3015 | .resume = ioapic_resume, | |
3016 | }; | |
3017 | ||
3018 | static int __init ioapic_init_sysfs(void) | |
3019 | { | |
54168ed7 IM |
3020 | struct sys_device * dev; |
3021 | int i, size, error; | |
1da177e4 LT |
3022 | |
3023 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3024 | if (error) | |
3025 | return error; | |
3026 | ||
54168ed7 | 3027 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3028 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3029 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3030 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3031 | if (!mp_ioapic_data[i]) { |
3032 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3033 | continue; | |
3034 | } | |
1da177e4 | 3035 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3036 | dev->id = i; |
1da177e4 LT |
3037 | dev->cls = &ioapic_sysdev_class; |
3038 | error = sysdev_register(dev); | |
3039 | if (error) { | |
3040 | kfree(mp_ioapic_data[i]); | |
3041 | mp_ioapic_data[i] = NULL; | |
3042 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3043 | continue; | |
3044 | } | |
3045 | } | |
3046 | ||
3047 | return 0; | |
3048 | } | |
3049 | ||
3050 | device_initcall(ioapic_init_sysfs); | |
3051 | ||
3fc471ed | 3052 | /* |
95d77884 | 3053 | * Dynamic irq allocate and deallocation |
3fc471ed | 3054 | */ |
199751d7 | 3055 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3056 | { |
ace80ab7 | 3057 | /* Allocate an unused irq */ |
54168ed7 IM |
3058 | unsigned int irq; |
3059 | unsigned int new; | |
3fc471ed | 3060 | unsigned long flags; |
da51a821 | 3061 | struct irq_cfg *cfg_new; |
3fc471ed | 3062 | |
497c9a19 | 3063 | #ifndef CONFIG_HAVE_SPARSE_IRQ |
199751d7 | 3064 | irq_want = nr_irqs - 1; |
497c9a19 | 3065 | #endif |
199751d7 YL |
3066 | |
3067 | irq = 0; | |
ace80ab7 | 3068 | spin_lock_irqsave(&vector_lock, flags); |
54168ed7 | 3069 | for (new = irq_want; new > 0; new--) { |
ace80ab7 EB |
3070 | if (platform_legacy_irq(new)) |
3071 | continue; | |
da51a821 YL |
3072 | cfg_new = irq_cfg(new); |
3073 | if (cfg_new && cfg_new->vector != 0) | |
ace80ab7 | 3074 | continue; |
047c8fdb | 3075 | /* check if need to create one */ |
da51a821 YL |
3076 | if (!cfg_new) |
3077 | cfg_new = irq_cfg_alloc(new); | |
497c9a19 | 3078 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3079 | irq = new; |
3080 | break; | |
3081 | } | |
3082 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3083 | |
199751d7 | 3084 | if (irq > 0) { |
3fc471ed EB |
3085 | dynamic_irq_init(irq); |
3086 | } | |
3087 | return irq; | |
3088 | } | |
3089 | ||
199751d7 YL |
3090 | int create_irq(void) |
3091 | { | |
54168ed7 IM |
3092 | int irq; |
3093 | ||
3094 | irq = create_irq_nr(nr_irqs - 1); | |
3095 | ||
3096 | if (irq == 0) | |
3097 | irq = -1; | |
3098 | ||
3099 | return irq; | |
199751d7 YL |
3100 | } |
3101 | ||
3fc471ed EB |
3102 | void destroy_irq(unsigned int irq) |
3103 | { | |
3104 | unsigned long flags; | |
3fc471ed EB |
3105 | |
3106 | dynamic_irq_cleanup(irq); | |
3107 | ||
54168ed7 IM |
3108 | #ifdef CONFIG_INTR_REMAP |
3109 | free_irte(irq); | |
3110 | #endif | |
3fc471ed | 3111 | spin_lock_irqsave(&vector_lock, flags); |
497c9a19 | 3112 | __clear_irq_vector(irq); |
3fc471ed EB |
3113 | spin_unlock_irqrestore(&vector_lock, flags); |
3114 | } | |
3fc471ed | 3115 | |
2d3fcc1c | 3116 | /* |
27b46d76 | 3117 | * MSI message composition |
2d3fcc1c EB |
3118 | */ |
3119 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3120 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3121 | { |
497c9a19 YL |
3122 | struct irq_cfg *cfg; |
3123 | int err; | |
2d3fcc1c | 3124 | unsigned dest; |
497c9a19 | 3125 | cpumask_t tmp; |
2d3fcc1c | 3126 | |
497c9a19 YL |
3127 | tmp = TARGET_CPUS; |
3128 | err = assign_irq_vector(irq, tmp); | |
3129 | if (err) | |
3130 | return err; | |
2d3fcc1c | 3131 | |
497c9a19 YL |
3132 | cfg = irq_cfg(irq); |
3133 | cpus_and(tmp, cfg->domain, tmp); | |
3134 | dest = cpu_mask_to_apicid(tmp); | |
3135 | ||
54168ed7 IM |
3136 | #ifdef CONFIG_INTR_REMAP |
3137 | if (irq_remapped(irq)) { | |
3138 | struct irte irte; | |
3139 | int ir_index; | |
3140 | u16 sub_handle; | |
3141 | ||
3142 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3143 | BUG_ON(ir_index == -1); | |
3144 | ||
3145 | memset (&irte, 0, sizeof(irte)); | |
3146 | ||
3147 | irte.present = 1; | |
3148 | irte.dst_mode = INT_DEST_MODE; | |
3149 | irte.trigger_mode = 0; /* edge */ | |
3150 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3151 | irte.vector = cfg->vector; | |
3152 | irte.dest_id = IRTE_DEST(dest); | |
3153 | ||
3154 | modify_irte(irq, &irte); | |
3155 | ||
3156 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3157 | msg->data = sub_handle; | |
3158 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3159 | MSI_ADDR_IR_SHV | | |
3160 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3161 | MSI_ADDR_IR_INDEX2(ir_index); | |
3162 | } else | |
3163 | #endif | |
3164 | { | |
3165 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3166 | msg->address_lo = | |
3167 | MSI_ADDR_BASE_LO | | |
3168 | ((INT_DEST_MODE == 0) ? | |
3169 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3170 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3171 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3172 | MSI_ADDR_REDIRECTION_CPU: | |
3173 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3174 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3175 | |
54168ed7 IM |
3176 | msg->data = |
3177 | MSI_DATA_TRIGGER_EDGE | | |
3178 | MSI_DATA_LEVEL_ASSERT | | |
3179 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3180 | MSI_DATA_DELIVERY_FIXED: | |
3181 | MSI_DATA_DELIVERY_LOWPRI) | | |
3182 | MSI_DATA_VECTOR(cfg->vector); | |
3183 | } | |
497c9a19 | 3184 | return err; |
2d3fcc1c EB |
3185 | } |
3186 | ||
3b7d1921 EB |
3187 | #ifdef CONFIG_SMP |
3188 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 3189 | { |
497c9a19 | 3190 | struct irq_cfg *cfg; |
3b7d1921 EB |
3191 | struct msi_msg msg; |
3192 | unsigned int dest; | |
3193 | cpumask_t tmp; | |
54168ed7 | 3194 | struct irq_desc *desc; |
3b7d1921 EB |
3195 | |
3196 | cpus_and(tmp, mask, cpu_online_map); | |
3197 | if (cpus_empty(tmp)) | |
497c9a19 | 3198 | return; |
2d3fcc1c | 3199 | |
497c9a19 | 3200 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 3201 | return; |
2d3fcc1c | 3202 | |
497c9a19 YL |
3203 | cfg = irq_cfg(irq); |
3204 | cpus_and(tmp, cfg->domain, mask); | |
3205 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 EB |
3206 | |
3207 | read_msi_msg(irq, &msg); | |
3208 | ||
3209 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3210 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3211 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3212 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3213 | ||
3214 | write_msi_msg(irq, &msg); | |
54168ed7 IM |
3215 | desc = irq_to_desc(irq); |
3216 | desc->affinity = mask; | |
2d3fcc1c | 3217 | } |
54168ed7 IM |
3218 | |
3219 | #ifdef CONFIG_INTR_REMAP | |
3220 | /* | |
3221 | * Migrate the MSI irq to another cpumask. This migration is | |
3222 | * done in the process context using interrupt-remapping hardware. | |
3223 | */ | |
3224 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
3225 | { | |
3226 | struct irq_cfg *cfg; | |
3227 | unsigned int dest; | |
3228 | cpumask_t tmp, cleanup_mask; | |
3229 | struct irte irte; | |
3230 | struct irq_desc *desc; | |
3231 | ||
3232 | cpus_and(tmp, mask, cpu_online_map); | |
3233 | if (cpus_empty(tmp)) | |
3234 | return; | |
3235 | ||
3236 | if (get_irte(irq, &irte)) | |
3237 | return; | |
3238 | ||
3239 | if (assign_irq_vector(irq, mask)) | |
3240 | return; | |
3241 | ||
3242 | cfg = irq_cfg(irq); | |
3243 | cpus_and(tmp, cfg->domain, mask); | |
3244 | dest = cpu_mask_to_apicid(tmp); | |
3245 | ||
3246 | irte.vector = cfg->vector; | |
3247 | irte.dest_id = IRTE_DEST(dest); | |
3248 | ||
3249 | /* | |
3250 | * atomically update the IRTE with the new destination and vector. | |
3251 | */ | |
3252 | modify_irte(irq, &irte); | |
3253 | ||
3254 | /* | |
3255 | * After this point, all the interrupts will start arriving | |
3256 | * at the new destination. So, time to cleanup the previous | |
3257 | * vector allocation. | |
3258 | */ | |
3259 | if (cfg->move_in_progress) { | |
3260 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
3261 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
3262 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
3263 | cfg->move_in_progress = 0; | |
3264 | } | |
3265 | ||
3266 | desc = irq_to_desc(irq); | |
3267 | desc->affinity = mask; | |
3268 | } | |
3269 | #endif | |
3b7d1921 | 3270 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3271 | |
3b7d1921 EB |
3272 | /* |
3273 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3274 | * which implement the MSI or MSI-X Capability Structure. | |
3275 | */ | |
3276 | static struct irq_chip msi_chip = { | |
3277 | .name = "PCI-MSI", | |
3278 | .unmask = unmask_msi_irq, | |
3279 | .mask = mask_msi_irq, | |
1d025192 | 3280 | .ack = ack_apic_edge, |
3b7d1921 EB |
3281 | #ifdef CONFIG_SMP |
3282 | .set_affinity = set_msi_irq_affinity, | |
3283 | #endif | |
3284 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3285 | }; |
3286 | ||
54168ed7 IM |
3287 | #ifdef CONFIG_INTR_REMAP |
3288 | static struct irq_chip msi_ir_chip = { | |
3289 | .name = "IR-PCI-MSI", | |
3290 | .unmask = unmask_msi_irq, | |
3291 | .mask = mask_msi_irq, | |
3292 | .ack = ack_x2apic_edge, | |
3293 | #ifdef CONFIG_SMP | |
3294 | .set_affinity = ir_set_msi_irq_affinity, | |
3295 | #endif | |
3296 | .retrigger = ioapic_retrigger_irq, | |
3297 | }; | |
3298 | ||
3299 | /* | |
3300 | * Map the PCI dev to the corresponding remapping hardware unit | |
3301 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3302 | * in it. | |
3303 | */ | |
3304 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3305 | { | |
3306 | struct intel_iommu *iommu; | |
3307 | int index; | |
3308 | ||
3309 | iommu = map_dev_to_ir(dev); | |
3310 | if (!iommu) { | |
3311 | printk(KERN_ERR | |
3312 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3313 | return -ENOENT; | |
3314 | } | |
3315 | ||
3316 | index = alloc_irte(iommu, irq, nvec); | |
3317 | if (index < 0) { | |
3318 | printk(KERN_ERR | |
3319 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
3320 | pci_name(dev)); | |
3321 | return -ENOSPC; | |
3322 | } | |
3323 | return index; | |
3324 | } | |
3325 | #endif | |
1d025192 YL |
3326 | |
3327 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) | |
3328 | { | |
3329 | int ret; | |
3330 | struct msi_msg msg; | |
3331 | ||
3332 | ret = msi_compose_msg(dev, irq, &msg); | |
3333 | if (ret < 0) | |
3334 | return ret; | |
3335 | ||
3336 | set_irq_msi(irq, desc); | |
3337 | write_msi_msg(irq, &msg); | |
3338 | ||
54168ed7 IM |
3339 | #ifdef CONFIG_INTR_REMAP |
3340 | if (irq_remapped(irq)) { | |
3341 | struct irq_desc *desc = irq_to_desc(irq); | |
3342 | /* | |
3343 | * irq migration in process context | |
3344 | */ | |
3345 | desc->status |= IRQ_MOVE_PCNTXT; | |
3346 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3347 | } else | |
3348 | #endif | |
3349 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 YL |
3350 | |
3351 | return 0; | |
3352 | } | |
3353 | ||
199751d7 YL |
3354 | static unsigned int build_irq_for_pci_dev(struct pci_dev *dev) |
3355 | { | |
3356 | unsigned int irq; | |
3357 | ||
3358 | irq = dev->bus->number; | |
3359 | irq <<= 8; | |
3360 | irq |= dev->devfn; | |
3361 | irq <<= 12; | |
3362 | ||
3363 | return irq; | |
3364 | } | |
3365 | ||
f7feaca7 | 3366 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 | 3367 | { |
54168ed7 IM |
3368 | unsigned int irq; |
3369 | int ret; | |
199751d7 YL |
3370 | unsigned int irq_want; |
3371 | ||
3372 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3373 | ||
3374 | irq = create_irq_nr(irq_want); | |
199751d7 YL |
3375 | if (irq == 0) |
3376 | return -1; | |
f7feaca7 | 3377 | |
54168ed7 IM |
3378 | #ifdef CONFIG_INTR_REMAP |
3379 | if (!intr_remapping_enabled) | |
3380 | goto no_ir; | |
3381 | ||
3382 | ret = msi_alloc_irte(dev, irq, 1); | |
3383 | if (ret < 0) | |
3384 | goto error; | |
3385 | no_ir: | |
3386 | #endif | |
1d025192 | 3387 | ret = setup_msi_irq(dev, desc, irq); |
f7feaca7 EB |
3388 | if (ret < 0) { |
3389 | destroy_irq(irq); | |
3b7d1921 | 3390 | return ret; |
54168ed7 | 3391 | } |
7fe3730d | 3392 | return 0; |
54168ed7 IM |
3393 | |
3394 | #ifdef CONFIG_INTR_REMAP | |
3395 | error: | |
3396 | destroy_irq(irq); | |
3397 | return ret; | |
3398 | #endif | |
3b7d1921 EB |
3399 | } |
3400 | ||
047c8fdb YL |
3401 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3402 | { | |
54168ed7 IM |
3403 | unsigned int irq; |
3404 | int ret, sub_handle; | |
3405 | struct msi_desc *desc; | |
3406 | unsigned int irq_want; | |
3407 | ||
3408 | #ifdef CONFIG_INTR_REMAP | |
3409 | struct intel_iommu *iommu = 0; | |
3410 | int index = 0; | |
3411 | #endif | |
3412 | ||
3413 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3414 | sub_handle = 0; | |
3415 | list_for_each_entry(desc, &dev->msi_list, list) { | |
3416 | irq = create_irq_nr(irq_want--); | |
3417 | if (irq == 0) | |
3418 | return -1; | |
3419 | #ifdef CONFIG_INTR_REMAP | |
3420 | if (!intr_remapping_enabled) | |
3421 | goto no_ir; | |
3422 | ||
3423 | if (!sub_handle) { | |
3424 | /* | |
3425 | * allocate the consecutive block of IRTE's | |
3426 | * for 'nvec' | |
3427 | */ | |
3428 | index = msi_alloc_irte(dev, irq, nvec); | |
3429 | if (index < 0) { | |
3430 | ret = index; | |
3431 | goto error; | |
3432 | } | |
3433 | } else { | |
3434 | iommu = map_dev_to_ir(dev); | |
3435 | if (!iommu) { | |
3436 | ret = -ENOENT; | |
3437 | goto error; | |
3438 | } | |
3439 | /* | |
3440 | * setup the mapping between the irq and the IRTE | |
3441 | * base index, the sub_handle pointing to the | |
3442 | * appropriate interrupt remap table entry. | |
3443 | */ | |
3444 | set_irte_irq(irq, iommu, index, sub_handle); | |
3445 | } | |
3446 | no_ir: | |
3447 | #endif | |
3448 | ret = setup_msi_irq(dev, desc, irq); | |
3449 | if (ret < 0) | |
3450 | goto error; | |
3451 | sub_handle++; | |
3452 | } | |
3453 | return 0; | |
047c8fdb YL |
3454 | |
3455 | error: | |
54168ed7 IM |
3456 | destroy_irq(irq); |
3457 | return ret; | |
047c8fdb YL |
3458 | } |
3459 | ||
3b7d1921 EB |
3460 | void arch_teardown_msi_irq(unsigned int irq) |
3461 | { | |
f7feaca7 | 3462 | destroy_irq(irq); |
3b7d1921 EB |
3463 | } |
3464 | ||
54168ed7 IM |
3465 | #ifdef CONFIG_DMAR |
3466 | #ifdef CONFIG_SMP | |
3467 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3468 | { | |
3469 | struct irq_cfg *cfg; | |
3470 | struct msi_msg msg; | |
3471 | unsigned int dest; | |
3472 | cpumask_t tmp; | |
3473 | struct irq_desc *desc; | |
3474 | ||
3475 | cpus_and(tmp, mask, cpu_online_map); | |
3476 | if (cpus_empty(tmp)) | |
3477 | return; | |
3478 | ||
3479 | if (assign_irq_vector(irq, mask)) | |
3480 | return; | |
3481 | ||
3482 | cfg = irq_cfg(irq); | |
3483 | cpus_and(tmp, cfg->domain, mask); | |
3484 | dest = cpu_mask_to_apicid(tmp); | |
3485 | ||
3486 | dmar_msi_read(irq, &msg); | |
3487 | ||
3488 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3489 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3490 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3491 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3492 | ||
3493 | dmar_msi_write(irq, &msg); | |
3494 | desc = irq_to_desc(irq); | |
3495 | desc->affinity = mask; | |
3496 | } | |
3497 | #endif /* CONFIG_SMP */ | |
3498 | ||
3499 | struct irq_chip dmar_msi_type = { | |
3500 | .name = "DMAR_MSI", | |
3501 | .unmask = dmar_msi_unmask, | |
3502 | .mask = dmar_msi_mask, | |
3503 | .ack = ack_apic_edge, | |
3504 | #ifdef CONFIG_SMP | |
3505 | .set_affinity = dmar_msi_set_affinity, | |
3506 | #endif | |
3507 | .retrigger = ioapic_retrigger_irq, | |
3508 | }; | |
3509 | ||
3510 | int arch_setup_dmar_msi(unsigned int irq) | |
3511 | { | |
3512 | int ret; | |
3513 | struct msi_msg msg; | |
2d3fcc1c | 3514 | |
54168ed7 IM |
3515 | ret = msi_compose_msg(NULL, irq, &msg); |
3516 | if (ret < 0) | |
3517 | return ret; | |
3518 | dmar_msi_write(irq, &msg); | |
3519 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3520 | "edge"); | |
3521 | return 0; | |
3522 | } | |
3523 | #endif | |
3524 | ||
3525 | #endif /* CONFIG_PCI_MSI */ | |
8b955b0d EB |
3526 | /* |
3527 | * Hypertransport interrupt support | |
3528 | */ | |
3529 | #ifdef CONFIG_HT_IRQ | |
3530 | ||
3531 | #ifdef CONFIG_SMP | |
3532 | ||
497c9a19 | 3533 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3534 | { |
ec68307c EB |
3535 | struct ht_irq_msg msg; |
3536 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3537 | |
497c9a19 | 3538 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3539 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3540 | |
497c9a19 | 3541 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3542 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3543 | |
ec68307c | 3544 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3545 | } |
3546 | ||
3547 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
3548 | { | |
497c9a19 | 3549 | struct irq_cfg *cfg; |
8b955b0d EB |
3550 | unsigned int dest; |
3551 | cpumask_t tmp; | |
54168ed7 | 3552 | struct irq_desc *desc; |
8b955b0d EB |
3553 | |
3554 | cpus_and(tmp, mask, cpu_online_map); | |
3555 | if (cpus_empty(tmp)) | |
497c9a19 | 3556 | return; |
8b955b0d | 3557 | |
497c9a19 YL |
3558 | if (assign_irq_vector(irq, mask)) |
3559 | return; | |
8b955b0d | 3560 | |
497c9a19 YL |
3561 | cfg = irq_cfg(irq); |
3562 | cpus_and(tmp, cfg->domain, mask); | |
3563 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 3564 | |
497c9a19 | 3565 | target_ht_irq(irq, dest, cfg->vector); |
54168ed7 IM |
3566 | desc = irq_to_desc(irq); |
3567 | desc->affinity = mask; | |
8b955b0d EB |
3568 | } |
3569 | #endif | |
3570 | ||
c37e108d | 3571 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3572 | .name = "PCI-HT", |
3573 | .mask = mask_ht_irq, | |
3574 | .unmask = unmask_ht_irq, | |
1d025192 | 3575 | .ack = ack_apic_edge, |
8b955b0d EB |
3576 | #ifdef CONFIG_SMP |
3577 | .set_affinity = set_ht_irq_affinity, | |
3578 | #endif | |
3579 | .retrigger = ioapic_retrigger_irq, | |
3580 | }; | |
3581 | ||
3582 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3583 | { | |
497c9a19 YL |
3584 | struct irq_cfg *cfg; |
3585 | int err; | |
3586 | cpumask_t tmp; | |
8b955b0d | 3587 | |
497c9a19 YL |
3588 | tmp = TARGET_CPUS; |
3589 | err = assign_irq_vector(irq, tmp); | |
54168ed7 | 3590 | if (!err) { |
ec68307c | 3591 | struct ht_irq_msg msg; |
8b955b0d | 3592 | unsigned dest; |
8b955b0d | 3593 | |
497c9a19 YL |
3594 | cfg = irq_cfg(irq); |
3595 | cpus_and(tmp, cfg->domain, tmp); | |
8b955b0d EB |
3596 | dest = cpu_mask_to_apicid(tmp); |
3597 | ||
ec68307c | 3598 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3599 | |
ec68307c EB |
3600 | msg.address_lo = |
3601 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3602 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3603 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3604 | ((INT_DEST_MODE == 0) ? |
3605 | HT_IRQ_LOW_DM_PHYSICAL : | |
3606 | HT_IRQ_LOW_DM_LOGICAL) | | |
3607 | HT_IRQ_LOW_RQEOI_EDGE | | |
3608 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3609 | HT_IRQ_LOW_MT_FIXED : | |
3610 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3611 | HT_IRQ_LOW_IRQ_MASKED; | |
3612 | ||
ec68307c | 3613 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3614 | |
a460e745 IM |
3615 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3616 | handle_edge_irq, "edge"); | |
8b955b0d | 3617 | } |
497c9a19 | 3618 | return err; |
8b955b0d EB |
3619 | } |
3620 | #endif /* CONFIG_HT_IRQ */ | |
3621 | ||
9d6a4d08 YL |
3622 | int __init io_apic_get_redir_entries (int ioapic) |
3623 | { | |
3624 | union IO_APIC_reg_01 reg_01; | |
3625 | unsigned long flags; | |
3626 | ||
3627 | spin_lock_irqsave(&ioapic_lock, flags); | |
3628 | reg_01.raw = io_apic_read(ioapic, 1); | |
3629 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3630 | ||
3631 | return reg_01.bits.entries; | |
3632 | } | |
3633 | ||
3634 | int __init probe_nr_irqs(void) | |
3635 | { | |
3636 | int idx; | |
3637 | int nr = 0; | |
052c0bff YL |
3638 | #ifndef CONFIG_XEN |
3639 | int nr_min = 32; | |
3640 | #else | |
3641 | int nr_min = NR_IRQS; | |
3642 | #endif | |
9d6a4d08 YL |
3643 | |
3644 | for (idx = 0; idx < nr_ioapics; idx++) | |
052c0bff | 3645 | nr += io_apic_get_redir_entries(idx) + 1; |
9d6a4d08 YL |
3646 | |
3647 | /* double it for hotplug and msi and nmi */ | |
3648 | nr <<= 1; | |
3649 | ||
3650 | /* something wrong ? */ | |
052c0bff YL |
3651 | if (nr < nr_min) |
3652 | nr = nr_min; | |
9d6a4d08 YL |
3653 | |
3654 | return nr; | |
3655 | } | |
3656 | ||
1da177e4 | 3657 | /* -------------------------------------------------------------------------- |
54168ed7 | 3658 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3659 | -------------------------------------------------------------------------- */ |
3660 | ||
888ba6c6 | 3661 | #ifdef CONFIG_ACPI |
1da177e4 | 3662 | |
54168ed7 | 3663 | #ifdef CONFIG_X86_32 |
36062448 | 3664 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3665 | { |
3666 | union IO_APIC_reg_00 reg_00; | |
3667 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3668 | physid_mask_t tmp; | |
3669 | unsigned long flags; | |
3670 | int i = 0; | |
3671 | ||
3672 | /* | |
36062448 PC |
3673 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3674 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3675 | * supports up to 16 on one shared APIC bus. |
36062448 | 3676 | * |
1da177e4 LT |
3677 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3678 | * advantage of new APIC bus architecture. | |
3679 | */ | |
3680 | ||
3681 | if (physids_empty(apic_id_map)) | |
3682 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3683 | ||
3684 | spin_lock_irqsave(&ioapic_lock, flags); | |
3685 | reg_00.raw = io_apic_read(ioapic, 0); | |
3686 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3687 | ||
3688 | if (apic_id >= get_physical_broadcast()) { | |
3689 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3690 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3691 | apic_id = reg_00.bits.ID; | |
3692 | } | |
3693 | ||
3694 | /* | |
36062448 | 3695 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3696 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3697 | */ | |
3698 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3699 | ||
3700 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3701 | if (!check_apicid_used(apic_id_map, i)) | |
3702 | break; | |
3703 | } | |
3704 | ||
3705 | if (i == get_physical_broadcast()) | |
3706 | panic("Max apic_id exceeded!\n"); | |
3707 | ||
3708 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3709 | "trying %d\n", ioapic, apic_id, i); | |
3710 | ||
3711 | apic_id = i; | |
36062448 | 3712 | } |
1da177e4 LT |
3713 | |
3714 | tmp = apicid_to_cpu_present(apic_id); | |
3715 | physids_or(apic_id_map, apic_id_map, tmp); | |
3716 | ||
3717 | if (reg_00.bits.ID != apic_id) { | |
3718 | reg_00.bits.ID = apic_id; | |
3719 | ||
3720 | spin_lock_irqsave(&ioapic_lock, flags); | |
3721 | io_apic_write(ioapic, 0, reg_00.raw); | |
3722 | reg_00.raw = io_apic_read(ioapic, 0); | |
3723 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3724 | ||
3725 | /* Sanity check */ | |
6070f9ec AD |
3726 | if (reg_00.bits.ID != apic_id) { |
3727 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3728 | return -1; | |
3729 | } | |
1da177e4 LT |
3730 | } |
3731 | ||
3732 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3733 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3734 | ||
3735 | return apic_id; | |
3736 | } | |
3737 | ||
36062448 | 3738 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3739 | { |
3740 | union IO_APIC_reg_01 reg_01; | |
3741 | unsigned long flags; | |
3742 | ||
3743 | spin_lock_irqsave(&ioapic_lock, flags); | |
3744 | reg_01.raw = io_apic_read(ioapic, 1); | |
3745 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3746 | ||
3747 | return reg_01.bits.version; | |
3748 | } | |
54168ed7 | 3749 | #endif |
1da177e4 | 3750 | |
54168ed7 | 3751 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3752 | { |
1da177e4 | 3753 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3754 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3755 | ioapic); |
3756 | return -EINVAL; | |
3757 | } | |
3758 | ||
1da177e4 LT |
3759 | /* |
3760 | * IRQs < 16 are already in the irq_2_pin[] map | |
3761 | */ | |
3762 | if (irq >= 16) | |
3763 | add_pin_to_irq(irq, ioapic, pin); | |
3764 | ||
497c9a19 | 3765 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
3766 | |
3767 | return 0; | |
3768 | } | |
3769 | ||
54168ed7 | 3770 | |
61fd47e0 SL |
3771 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3772 | { | |
3773 | int i; | |
3774 | ||
3775 | if (skip_ioapic_setup) | |
3776 | return -1; | |
3777 | ||
3778 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3779 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3780 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
3781 | break; |
3782 | if (i >= mp_irq_entries) | |
3783 | return -1; | |
3784 | ||
3785 | *trigger = irq_trigger(i); | |
3786 | *polarity = irq_polarity(i); | |
3787 | return 0; | |
3788 | } | |
3789 | ||
888ba6c6 | 3790 | #endif /* CONFIG_ACPI */ |
1a3f239d | 3791 | |
497c9a19 YL |
3792 | /* |
3793 | * This function currently is only a helper for the i386 smp boot process where | |
3794 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3795 | * so mask in all cases should simply be TARGET_CPUS | |
3796 | */ | |
3797 | #ifdef CONFIG_SMP | |
3798 | void __init setup_ioapic_dest(void) | |
3799 | { | |
3800 | int pin, ioapic, irq, irq_entry; | |
3801 | struct irq_cfg *cfg; | |
497c9a19 YL |
3802 | |
3803 | if (skip_ioapic_setup == 1) | |
3804 | return; | |
3805 | ||
3806 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
3807 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
3808 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3809 | if (irq_entry == -1) | |
3810 | continue; | |
3811 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
3812 | ||
3813 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
3814 | * when you have too many devices, because at that time only boot | |
3815 | * cpu is online. | |
3816 | */ | |
3817 | cfg = irq_cfg(irq); | |
3818 | if (!cfg->vector) | |
3819 | setup_IO_APIC_irq(ioapic, pin, irq, | |
3820 | irq_trigger(irq_entry), | |
3821 | irq_polarity(irq_entry)); | |
54168ed7 IM |
3822 | #ifdef CONFIG_INTR_REMAP |
3823 | else if (intr_remapping_enabled) | |
3824 | set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); | |
3825 | #endif | |
3826 | else | |
497c9a19 | 3827 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
497c9a19 YL |
3828 | } |
3829 | ||
3830 | } | |
3831 | } | |
3832 | #endif | |
3833 | ||
54168ed7 IM |
3834 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3835 | ||
3836 | static struct resource *ioapic_resources; | |
3837 | ||
3838 | static struct resource * __init ioapic_setup_resources(void) | |
3839 | { | |
3840 | unsigned long n; | |
3841 | struct resource *res; | |
3842 | char *mem; | |
3843 | int i; | |
3844 | ||
3845 | if (nr_ioapics <= 0) | |
3846 | return NULL; | |
3847 | ||
3848 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3849 | n *= nr_ioapics; | |
3850 | ||
3851 | mem = alloc_bootmem(n); | |
3852 | res = (void *)mem; | |
3853 | ||
3854 | if (mem != NULL) { | |
3855 | mem += sizeof(struct resource) * nr_ioapics; | |
3856 | ||
3857 | for (i = 0; i < nr_ioapics; i++) { | |
3858 | res[i].name = mem; | |
3859 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
3860 | sprintf(mem, "IOAPIC %u", i); | |
3861 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
3862 | } | |
3863 | } | |
3864 | ||
3865 | ioapic_resources = res; | |
3866 | ||
3867 | return res; | |
3868 | } | |
54168ed7 | 3869 | |
f3294a33 YL |
3870 | void __init ioapic_init_mappings(void) |
3871 | { | |
3872 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
3873 | int i; | |
54168ed7 | 3874 | struct resource *ioapic_res; |
f3294a33 | 3875 | |
54168ed7 | 3876 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
3877 | for (i = 0; i < nr_ioapics; i++) { |
3878 | if (smp_found_config) { | |
3879 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 IM |
3880 | #ifdef CONFIG_X86_32 |
3881 | if (!ioapic_phys) { | |
3882 | printk(KERN_ERR | |
3883 | "WARNING: bogus zero IO-APIC " | |
3884 | "address found in MPTABLE, " | |
3885 | "disabling IO/APIC support!\n"); | |
3886 | smp_found_config = 0; | |
3887 | skip_ioapic_setup = 1; | |
3888 | goto fake_ioapic_page; | |
3889 | } | |
3890 | #endif | |
f3294a33 | 3891 | } else { |
54168ed7 | 3892 | #ifdef CONFIG_X86_32 |
f3294a33 | 3893 | fake_ioapic_page: |
54168ed7 | 3894 | #endif |
f3294a33 | 3895 | ioapic_phys = (unsigned long) |
54168ed7 | 3896 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3897 | ioapic_phys = __pa(ioapic_phys); |
3898 | } | |
3899 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
3900 | apic_printk(APIC_VERBOSE, |
3901 | "mapped IOAPIC to %08lx (%08lx)\n", | |
3902 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 3903 | idx++; |
54168ed7 | 3904 | |
54168ed7 IM |
3905 | if (ioapic_res != NULL) { |
3906 | ioapic_res->start = ioapic_phys; | |
3907 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
3908 | ioapic_res++; | |
3909 | } | |
f3294a33 YL |
3910 | } |
3911 | } | |
3912 | ||
54168ed7 IM |
3913 | static int __init ioapic_insert_resources(void) |
3914 | { | |
3915 | int i; | |
3916 | struct resource *r = ioapic_resources; | |
3917 | ||
3918 | if (!r) { | |
3919 | printk(KERN_ERR | |
3920 | "IO APIC resources could be not be allocated.\n"); | |
3921 | return -1; | |
3922 | } | |
3923 | ||
3924 | for (i = 0; i < nr_ioapics; i++) { | |
3925 | insert_resource(&iomem_resource, r); | |
3926 | r++; | |
3927 | } | |
3928 | ||
3929 | return 0; | |
3930 | } | |
3931 | ||
3932 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
3933 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
3934 | late_initcall(ioapic_insert_resources); |