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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
1da177e4 | 16 | #include <asm/uaccess.h> |
f668964e IM |
17 | #include <asm/ptrace.h> |
18 | #include <asm/i387.h> | |
19 | #include <asm/user.h> | |
1da177e4 | 20 | |
44210111 | 21 | #ifdef CONFIG_X86_64 |
f668964e IM |
22 | # include <asm/sigcontext32.h> |
23 | # include <asm/user32.h> | |
44210111 | 24 | #else |
ab513701 SS |
25 | # define save_i387_xstate_ia32 save_i387_xstate |
26 | # define restore_i387_xstate_ia32 restore_i387_xstate | |
f668964e | 27 | # define _fpstate_ia32 _fpstate |
ab513701 | 28 | # define _xstate_ia32 _xstate |
3c1c7f10 | 29 | # define sig_xstate_ia32_size sig_xstate_size |
c37b5efe | 30 | # define fx_sw_reserved_ia32 fx_sw_reserved |
f668964e IM |
31 | # define user_i387_ia32_struct user_i387_struct |
32 | # define user32_fxsr_struct user_fxsr_struct | |
44210111 RM |
33 | #endif |
34 | ||
1da177e4 | 35 | #ifdef CONFIG_MATH_EMULATION |
f668964e | 36 | # define HAVE_HWFP (boot_cpu_data.hard_math) |
1da177e4 | 37 | #else |
f668964e | 38 | # define HAVE_HWFP 1 |
1da177e4 LT |
39 | #endif |
40 | ||
f668964e | 41 | static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 42 | unsigned int xstate_size; |
f45755b8 | 43 | EXPORT_SYMBOL_GPL(xstate_size); |
3c1c7f10 | 44 | unsigned int sig_xstate_ia32_size = sizeof(struct _fpstate_ia32); |
61c4628b | 45 | static struct i387_fxsave_struct fx_scratch __cpuinitdata; |
1da177e4 | 46 | |
61c4628b | 47 | void __cpuinit mxcsr_feature_mask_init(void) |
1da177e4 LT |
48 | { |
49 | unsigned long mask = 0; | |
f668964e | 50 | |
1da177e4 LT |
51 | clts(); |
52 | if (cpu_has_fxsr) { | |
61c4628b SS |
53 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
54 | asm volatile("fxsave %0" : : "m" (fx_scratch)); | |
55 | mask = fx_scratch.mxcsr_mask; | |
3b095a04 CG |
56 | if (mask == 0) |
57 | mask = 0x0000ffbf; | |
58 | } | |
1da177e4 LT |
59 | mxcsr_feature_mask &= mask; |
60 | stts(); | |
61 | } | |
62 | ||
0e49bf66 | 63 | static void __cpuinit init_thread_xstate(void) |
61c4628b | 64 | { |
0e49bf66 RR |
65 | /* |
66 | * Note that xstate_size might be overwriten later during | |
67 | * xsave_init(). | |
68 | */ | |
69 | ||
e8a496ac SS |
70 | if (!HAVE_HWFP) { |
71 | xstate_size = sizeof(struct i387_soft_struct); | |
72 | return; | |
73 | } | |
74 | ||
61c4628b SS |
75 | if (cpu_has_fxsr) |
76 | xstate_size = sizeof(struct i387_fxsave_struct); | |
77 | #ifdef CONFIG_X86_32 | |
78 | else | |
79 | xstate_size = sizeof(struct i387_fsave_struct); | |
80 | #endif | |
61c4628b SS |
81 | } |
82 | ||
44210111 RM |
83 | #ifdef CONFIG_X86_64 |
84 | /* | |
85 | * Called at bootup to set up the initial FPU state that is later cloned | |
86 | * into all processes. | |
87 | */ | |
0e49bf66 | 88 | |
44210111 RM |
89 | void __cpuinit fpu_init(void) |
90 | { | |
91 | unsigned long oldcr0 = read_cr0(); | |
f668964e | 92 | |
44210111 RM |
93 | set_in_cr4(X86_CR4_OSFXSR); |
94 | set_in_cr4(X86_CR4_OSXMMEXCPT); | |
95 | ||
f668964e | 96 | write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */ |
44210111 | 97 | |
dc1e35c6 SS |
98 | if (!smp_processor_id()) |
99 | init_thread_xstate(); | |
dc1e35c6 | 100 | |
44210111 RM |
101 | mxcsr_feature_mask_init(); |
102 | /* clean state in init */ | |
c9ad4882 | 103 | current_thread_info()->status = 0; |
44210111 RM |
104 | clear_used_math(); |
105 | } | |
0e49bf66 RR |
106 | |
107 | #else /* CONFIG_X86_64 */ | |
108 | ||
109 | void __cpuinit fpu_init(void) | |
110 | { | |
111 | if (!smp_processor_id()) | |
112 | init_thread_xstate(); | |
113 | } | |
114 | ||
115 | #endif /* CONFIG_X86_32 */ | |
44210111 | 116 | |
5ee481da | 117 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 118 | { |
e8a496ac SS |
119 | #ifdef CONFIG_X86_32 |
120 | if (!HAVE_HWFP) { | |
86603283 AK |
121 | finit_soft_fpu(&fpu->state->soft); |
122 | return; | |
e8a496ac SS |
123 | } |
124 | #endif | |
125 | ||
1da177e4 | 126 | if (cpu_has_fxsr) { |
86603283 | 127 | struct i387_fxsave_struct *fx = &fpu->state->fxsave; |
61c4628b SS |
128 | |
129 | memset(fx, 0, xstate_size); | |
130 | fx->cwd = 0x37f; | |
1da177e4 | 131 | if (cpu_has_xmm) |
61c4628b | 132 | fx->mxcsr = MXCSR_DEFAULT; |
1da177e4 | 133 | } else { |
86603283 | 134 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
135 | memset(fp, 0, xstate_size); |
136 | fp->cwd = 0xffff037fu; | |
137 | fp->swd = 0xffff0000u; | |
138 | fp->twd = 0xffffffffu; | |
139 | fp->fos = 0xffff0000u; | |
1da177e4 | 140 | } |
86603283 | 141 | } |
5ee481da | 142 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 AK |
143 | |
144 | /* | |
145 | * The _current_ task is using the FPU for the first time | |
146 | * so initialize it and set the mxcsr to its default | |
147 | * value at reset if we support XMM instructions and then | |
148 | * remeber the current task has used the FPU. | |
149 | */ | |
150 | int init_fpu(struct task_struct *tsk) | |
151 | { | |
152 | int ret; | |
153 | ||
154 | if (tsk_used_math(tsk)) { | |
155 | if (HAVE_HWFP && tsk == current) | |
156 | unlazy_fpu(tsk); | |
157 | return 0; | |
158 | } | |
159 | ||
44210111 | 160 | /* |
86603283 | 161 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 162 | */ |
86603283 AK |
163 | ret = fpu_alloc(&tsk->thread.fpu); |
164 | if (ret) | |
165 | return ret; | |
166 | ||
167 | fpu_finit(&tsk->thread.fpu); | |
168 | ||
1da177e4 | 169 | set_stopped_child_used_math(tsk); |
aa283f49 | 170 | return 0; |
1da177e4 LT |
171 | } |
172 | ||
5b3efd50 SS |
173 | /* |
174 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
175 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
176 | * capabilites supported by the xsave. | |
177 | */ | |
44210111 RM |
178 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
179 | { | |
180 | return tsk_used_math(target) ? regset->n : 0; | |
181 | } | |
1da177e4 | 182 | |
44210111 | 183 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 184 | { |
44210111 RM |
185 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
186 | } | |
1da177e4 | 187 | |
44210111 RM |
188 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
189 | unsigned int pos, unsigned int count, | |
190 | void *kbuf, void __user *ubuf) | |
191 | { | |
aa283f49 SS |
192 | int ret; |
193 | ||
44210111 RM |
194 | if (!cpu_has_fxsr) |
195 | return -ENODEV; | |
196 | ||
aa283f49 SS |
197 | ret = init_fpu(target); |
198 | if (ret) | |
199 | return ret; | |
44210111 | 200 | |
29104e10 SS |
201 | sanitize_i387_state(target); |
202 | ||
44210111 | 203 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 204 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 205 | } |
44210111 RM |
206 | |
207 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
208 | unsigned int pos, unsigned int count, | |
209 | const void *kbuf, const void __user *ubuf) | |
210 | { | |
211 | int ret; | |
212 | ||
213 | if (!cpu_has_fxsr) | |
214 | return -ENODEV; | |
215 | ||
aa283f49 SS |
216 | ret = init_fpu(target); |
217 | if (ret) | |
218 | return ret; | |
219 | ||
29104e10 SS |
220 | sanitize_i387_state(target); |
221 | ||
44210111 | 222 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 223 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
224 | |
225 | /* | |
226 | * mxcsr reserved bits must be masked to zero for security reasons. | |
227 | */ | |
86603283 | 228 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 229 | |
42deec6f SS |
230 | /* |
231 | * update the header bits in the xsave header, indicating the | |
232 | * presence of FP and SSE state. | |
233 | */ | |
234 | if (cpu_has_xsave) | |
86603283 | 235 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 236 | |
44210111 RM |
237 | return ret; |
238 | } | |
239 | ||
5b3efd50 SS |
240 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
241 | unsigned int pos, unsigned int count, | |
242 | void *kbuf, void __user *ubuf) | |
243 | { | |
244 | int ret; | |
245 | ||
246 | if (!cpu_has_xsave) | |
247 | return -ENODEV; | |
248 | ||
249 | ret = init_fpu(target); | |
250 | if (ret) | |
251 | return ret; | |
252 | ||
253 | /* | |
ff7fbc72 SS |
254 | * Copy the 48bytes defined by the software first into the xstate |
255 | * memory layout in the thread struct, so that we can copy the entire | |
256 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 257 | */ |
86603283 | 258 | memcpy(&target->thread.fpu.state->fxsave.sw_reserved, |
ff7fbc72 | 259 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); |
5b3efd50 SS |
260 | |
261 | /* | |
ff7fbc72 | 262 | * Copy the xstate memory layout. |
5b3efd50 SS |
263 | */ |
264 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
86603283 | 265 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
266 | return ret; |
267 | } | |
268 | ||
269 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
270 | unsigned int pos, unsigned int count, | |
271 | const void *kbuf, const void __user *ubuf) | |
272 | { | |
273 | int ret; | |
274 | struct xsave_hdr_struct *xsave_hdr; | |
275 | ||
276 | if (!cpu_has_xsave) | |
277 | return -ENODEV; | |
278 | ||
279 | ret = init_fpu(target); | |
280 | if (ret) | |
281 | return ret; | |
282 | ||
283 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
86603283 | 284 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
285 | |
286 | /* | |
287 | * mxcsr reserved bits must be masked to zero for security reasons. | |
288 | */ | |
86603283 | 289 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
5b3efd50 | 290 | |
86603283 | 291 | xsave_hdr = &target->thread.fpu.state->xsave.xsave_hdr; |
5b3efd50 SS |
292 | |
293 | xsave_hdr->xstate_bv &= pcntxt_mask; | |
294 | /* | |
295 | * These bits must be zero. | |
296 | */ | |
297 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
44210111 | 302 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 303 | |
1da177e4 LT |
304 | /* |
305 | * FPU tag word conversions. | |
306 | */ | |
307 | ||
3b095a04 | 308 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
309 | { |
310 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 311 | |
1da177e4 | 312 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 313 | tmp = ~twd; |
44210111 | 314 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
315 | /* and move the valid bits to the lower byte. */ |
316 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
317 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
318 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 319 | |
3b095a04 | 320 | return tmp; |
1da177e4 LT |
321 | } |
322 | ||
1da177e4 | 323 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16); |
44210111 RM |
324 | #define FP_EXP_TAG_VALID 0 |
325 | #define FP_EXP_TAG_ZERO 1 | |
326 | #define FP_EXP_TAG_SPECIAL 2 | |
327 | #define FP_EXP_TAG_EMPTY 3 | |
328 | ||
329 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
330 | { | |
331 | struct _fpxreg *st; | |
332 | u32 tos = (fxsave->swd >> 11) & 7; | |
333 | u32 twd = (unsigned long) fxsave->twd; | |
334 | u32 tag; | |
335 | u32 ret = 0xffff0000u; | |
336 | int i; | |
1da177e4 | 337 | |
44210111 | 338 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
339 | if (twd & 0x1) { |
340 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 341 | |
3b095a04 | 342 | switch (st->exponent & 0x7fff) { |
1da177e4 | 343 | case 0x7fff: |
44210111 | 344 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
345 | break; |
346 | case 0x0000: | |
3b095a04 CG |
347 | if (!st->significand[0] && |
348 | !st->significand[1] && | |
349 | !st->significand[2] && | |
44210111 RM |
350 | !st->significand[3]) |
351 | tag = FP_EXP_TAG_ZERO; | |
352 | else | |
353 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
354 | break; |
355 | default: | |
44210111 RM |
356 | if (st->significand[3] & 0x8000) |
357 | tag = FP_EXP_TAG_VALID; | |
358 | else | |
359 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
360 | break; |
361 | } | |
362 | } else { | |
44210111 | 363 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 364 | } |
44210111 | 365 | ret |= tag << (2 * i); |
1da177e4 LT |
366 | } |
367 | return ret; | |
368 | } | |
369 | ||
370 | /* | |
44210111 | 371 | * FXSR floating point environment conversions. |
1da177e4 LT |
372 | */ |
373 | ||
f668964e IM |
374 | static void |
375 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) | |
1da177e4 | 376 | { |
86603283 | 377 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
378 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
379 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
380 | int i; | |
1da177e4 | 381 | |
44210111 RM |
382 | env->cwd = fxsave->cwd | 0xffff0000u; |
383 | env->swd = fxsave->swd | 0xffff0000u; | |
384 | env->twd = twd_fxsr_to_i387(fxsave); | |
385 | ||
386 | #ifdef CONFIG_X86_64 | |
387 | env->fip = fxsave->rip; | |
388 | env->foo = fxsave->rdp; | |
389 | if (tsk == current) { | |
390 | /* | |
391 | * should be actually ds/cs at fpu exception time, but | |
392 | * that information is not available in 64bit mode. | |
393 | */ | |
f668964e IM |
394 | asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos)); |
395 | asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs)); | |
1da177e4 | 396 | } else { |
44210111 | 397 | struct pt_regs *regs = task_pt_regs(tsk); |
f668964e | 398 | |
44210111 RM |
399 | env->fos = 0xffff0000 | tsk->thread.ds; |
400 | env->fcs = regs->cs; | |
1da177e4 | 401 | } |
44210111 RM |
402 | #else |
403 | env->fip = fxsave->fip; | |
609b5297 | 404 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
405 | env->foo = fxsave->foo; |
406 | env->fos = fxsave->fos; | |
407 | #endif | |
1da177e4 | 408 | |
44210111 RM |
409 | for (i = 0; i < 8; ++i) |
410 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
411 | } |
412 | ||
44210111 RM |
413 | static void convert_to_fxsr(struct task_struct *tsk, |
414 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 415 | |
1da177e4 | 416 | { |
86603283 | 417 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
418 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
419 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
420 | int i; | |
1da177e4 | 421 | |
44210111 RM |
422 | fxsave->cwd = env->cwd; |
423 | fxsave->swd = env->swd; | |
424 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
425 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
426 | #ifdef CONFIG_X86_64 | |
427 | fxsave->rip = env->fip; | |
428 | fxsave->rdp = env->foo; | |
429 | /* cs and ds ignored */ | |
430 | #else | |
431 | fxsave->fip = env->fip; | |
432 | fxsave->fcs = (env->fcs & 0xffff); | |
433 | fxsave->foo = env->foo; | |
434 | fxsave->fos = env->fos; | |
435 | #endif | |
1da177e4 | 436 | |
44210111 RM |
437 | for (i = 0; i < 8; ++i) |
438 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
439 | } |
440 | ||
44210111 RM |
441 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
442 | unsigned int pos, unsigned int count, | |
443 | void *kbuf, void __user *ubuf) | |
1da177e4 | 444 | { |
44210111 | 445 | struct user_i387_ia32_struct env; |
aa283f49 | 446 | int ret; |
1da177e4 | 447 | |
aa283f49 SS |
448 | ret = init_fpu(target); |
449 | if (ret) | |
450 | return ret; | |
1da177e4 | 451 | |
e8a496ac SS |
452 | if (!HAVE_HWFP) |
453 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
454 | ||
f668964e | 455 | if (!cpu_has_fxsr) { |
44210111 | 456 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 457 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 458 | -1); |
f668964e | 459 | } |
1da177e4 | 460 | |
29104e10 SS |
461 | sanitize_i387_state(target); |
462 | ||
44210111 RM |
463 | if (kbuf && pos == 0 && count == sizeof(env)) { |
464 | convert_from_fxsr(kbuf, target); | |
465 | return 0; | |
1da177e4 | 466 | } |
44210111 RM |
467 | |
468 | convert_from_fxsr(&env, target); | |
f668964e | 469 | |
44210111 | 470 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
471 | } |
472 | ||
44210111 RM |
473 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
474 | unsigned int pos, unsigned int count, | |
475 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 476 | { |
44210111 RM |
477 | struct user_i387_ia32_struct env; |
478 | int ret; | |
1da177e4 | 479 | |
aa283f49 SS |
480 | ret = init_fpu(target); |
481 | if (ret) | |
482 | return ret; | |
483 | ||
29104e10 SS |
484 | sanitize_i387_state(target); |
485 | ||
e8a496ac SS |
486 | if (!HAVE_HWFP) |
487 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
488 | ||
f668964e | 489 | if (!cpu_has_fxsr) { |
44210111 | 490 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 491 | &target->thread.fpu.state->fsave, 0, -1); |
f668964e | 492 | } |
44210111 RM |
493 | |
494 | if (pos > 0 || count < sizeof(env)) | |
495 | convert_from_fxsr(&env, target); | |
496 | ||
497 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
498 | if (!ret) | |
499 | convert_to_fxsr(target, &env); | |
500 | ||
42deec6f SS |
501 | /* |
502 | * update the header bit in the xsave header, indicating the | |
503 | * presence of FP. | |
504 | */ | |
505 | if (cpu_has_xsave) | |
86603283 | 506 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 507 | return ret; |
1da177e4 LT |
508 | } |
509 | ||
510 | /* | |
511 | * Signal frame handlers. | |
512 | */ | |
513 | ||
44210111 | 514 | static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
515 | { |
516 | struct task_struct *tsk = current; | |
86603283 | 517 | struct i387_fsave_struct *fp = &tsk->thread.fpu.state->fsave; |
1da177e4 | 518 | |
61c4628b SS |
519 | fp->status = fp->swd; |
520 | if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct))) | |
1da177e4 LT |
521 | return -1; |
522 | return 1; | |
523 | } | |
524 | ||
44210111 | 525 | static int save_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
526 | { |
527 | struct task_struct *tsk = current; | |
86603283 | 528 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave; |
44210111 | 529 | struct user_i387_ia32_struct env; |
1da177e4 LT |
530 | int err = 0; |
531 | ||
44210111 RM |
532 | convert_from_fxsr(&env, tsk); |
533 | if (__copy_to_user(buf, &env, sizeof(env))) | |
1da177e4 LT |
534 | return -1; |
535 | ||
61c4628b | 536 | err |= __put_user(fx->swd, &buf->status); |
3b095a04 CG |
537 | err |= __put_user(X86_FXSR_MAGIC, &buf->magic); |
538 | if (err) | |
1da177e4 LT |
539 | return -1; |
540 | ||
c37b5efe | 541 | if (__copy_to_user(&buf->_fxsr_env[0], fx, xstate_size)) |
1da177e4 LT |
542 | return -1; |
543 | return 1; | |
544 | } | |
545 | ||
c37b5efe SS |
546 | static int save_i387_xsave(void __user *buf) |
547 | { | |
04944b79 | 548 | struct task_struct *tsk = current; |
c37b5efe SS |
549 | struct _fpstate_ia32 __user *fx = buf; |
550 | int err = 0; | |
551 | ||
29104e10 SS |
552 | |
553 | sanitize_i387_state(tsk); | |
554 | ||
04944b79 SS |
555 | /* |
556 | * For legacy compatible, we always set FP/SSE bits in the bit | |
557 | * vector while saving the state to the user context. | |
558 | * This will enable us capturing any changes(during sigreturn) to | |
559 | * the FP/SSE bits by the legacy applications which don't touch | |
560 | * xstate_bv in the xsave header. | |
561 | * | |
562 | * xsave aware applications can change the xstate_bv in the xsave | |
563 | * header as well as change any contents in the memory layout. | |
564 | * xrestore as part of sigreturn will capture all the changes. | |
565 | */ | |
86603283 | 566 | tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
04944b79 | 567 | |
c37b5efe SS |
568 | if (save_i387_fxsave(fx) < 0) |
569 | return -1; | |
570 | ||
571 | err = __copy_to_user(&fx->sw_reserved, &fx_sw_reserved_ia32, | |
572 | sizeof(struct _fpx_sw_bytes)); | |
573 | err |= __put_user(FP_XSTATE_MAGIC2, | |
574 | (__u32 __user *) (buf + sig_xstate_ia32_size | |
575 | - FP_XSTATE_MAGIC2_SIZE)); | |
576 | if (err) | |
577 | return -1; | |
578 | ||
579 | return 1; | |
580 | } | |
581 | ||
ab513701 | 582 | int save_i387_xstate_ia32(void __user *buf) |
1da177e4 | 583 | { |
ab513701 SS |
584 | struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf; |
585 | struct task_struct *tsk = current; | |
586 | ||
3b095a04 | 587 | if (!used_math()) |
1da177e4 | 588 | return 0; |
ab513701 SS |
589 | |
590 | if (!access_ok(VERIFY_WRITE, buf, sig_xstate_ia32_size)) | |
591 | return -EACCES; | |
f668964e IM |
592 | /* |
593 | * This will cause a "finit" to be triggered by the next | |
1da177e4 LT |
594 | * attempted FPU operation by the 'current' process. |
595 | */ | |
596 | clear_used_math(); | |
597 | ||
f668964e | 598 | if (!HAVE_HWFP) { |
44210111 RM |
599 | return fpregs_soft_get(current, NULL, |
600 | 0, sizeof(struct user_i387_ia32_struct), | |
ab513701 | 601 | NULL, fp) ? -1 : 1; |
1da177e4 | 602 | } |
f668964e | 603 | |
ab513701 SS |
604 | unlazy_fpu(tsk); |
605 | ||
c37b5efe SS |
606 | if (cpu_has_xsave) |
607 | return save_i387_xsave(fp); | |
f668964e | 608 | if (cpu_has_fxsr) |
ab513701 | 609 | return save_i387_fxsave(fp); |
f668964e | 610 | else |
ab513701 | 611 | return save_i387_fsave(fp); |
1da177e4 LT |
612 | } |
613 | ||
44210111 | 614 | static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
615 | { |
616 | struct task_struct *tsk = current; | |
f668964e | 617 | |
86603283 | 618 | return __copy_from_user(&tsk->thread.fpu.state->fsave, buf, |
3b095a04 | 619 | sizeof(struct i387_fsave_struct)); |
1da177e4 LT |
620 | } |
621 | ||
c37b5efe SS |
622 | static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf, |
623 | unsigned int size) | |
1da177e4 | 624 | { |
1da177e4 | 625 | struct task_struct *tsk = current; |
44210111 | 626 | struct user_i387_ia32_struct env; |
f668964e IM |
627 | int err; |
628 | ||
86603283 | 629 | err = __copy_from_user(&tsk->thread.fpu.state->fxsave, &buf->_fxsr_env[0], |
c37b5efe | 630 | size); |
1da177e4 | 631 | /* mxcsr reserved bits must be masked to zero for security reasons */ |
86603283 | 632 | tsk->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
633 | if (err || __copy_from_user(&env, buf, sizeof(env))) |
634 | return 1; | |
635 | convert_to_fxsr(tsk, &env); | |
f668964e | 636 | |
44210111 | 637 | return 0; |
1da177e4 LT |
638 | } |
639 | ||
c37b5efe SS |
640 | static int restore_i387_xsave(void __user *buf) |
641 | { | |
642 | struct _fpx_sw_bytes fx_sw_user; | |
643 | struct _fpstate_ia32 __user *fx_user = | |
644 | ((struct _fpstate_ia32 __user *) buf); | |
645 | struct i387_fxsave_struct __user *fx = | |
646 | (struct i387_fxsave_struct __user *) &fx_user->_fxsr_env[0]; | |
647 | struct xsave_hdr_struct *xsave_hdr = | |
86603283 | 648 | ¤t->thread.fpu.state->xsave.xsave_hdr; |
6152e4b1 | 649 | u64 mask; |
c37b5efe SS |
650 | int err; |
651 | ||
652 | if (check_for_xstate(fx, buf, &fx_sw_user)) | |
653 | goto fx_only; | |
654 | ||
6152e4b1 | 655 | mask = fx_sw_user.xstate_bv; |
c37b5efe SS |
656 | |
657 | err = restore_i387_fxsave(buf, fx_sw_user.xstate_size); | |
658 | ||
6152e4b1 | 659 | xsave_hdr->xstate_bv &= pcntxt_mask; |
c37b5efe SS |
660 | /* |
661 | * These bits must be zero. | |
662 | */ | |
663 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
664 | ||
665 | /* | |
666 | * Init the state that is not present in the memory layout | |
667 | * and enabled by the OS. | |
668 | */ | |
6152e4b1 PA |
669 | mask = ~(pcntxt_mask & ~mask); |
670 | xsave_hdr->xstate_bv &= mask; | |
c37b5efe SS |
671 | |
672 | return err; | |
673 | fx_only: | |
674 | /* | |
675 | * Couldn't find the extended state information in the memory | |
676 | * layout. Restore the FP/SSE and init the other extended state | |
677 | * enabled by the OS. | |
678 | */ | |
679 | xsave_hdr->xstate_bv = XSTATE_FPSSE; | |
680 | return restore_i387_fxsave(buf, sizeof(struct i387_fxsave_struct)); | |
681 | } | |
682 | ||
ab513701 | 683 | int restore_i387_xstate_ia32(void __user *buf) |
1da177e4 LT |
684 | { |
685 | int err; | |
e8a496ac | 686 | struct task_struct *tsk = current; |
ab513701 | 687 | struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf; |
1da177e4 | 688 | |
e8a496ac | 689 | if (HAVE_HWFP) |
fd3c3ed5 SS |
690 | clear_fpu(tsk); |
691 | ||
ab513701 SS |
692 | if (!buf) { |
693 | if (used_math()) { | |
694 | clear_fpu(tsk); | |
695 | clear_used_math(); | |
696 | } | |
697 | ||
698 | return 0; | |
699 | } else | |
700 | if (!access_ok(VERIFY_READ, buf, sig_xstate_ia32_size)) | |
701 | return -EACCES; | |
702 | ||
e8a496ac SS |
703 | if (!used_math()) { |
704 | err = init_fpu(tsk); | |
705 | if (err) | |
706 | return err; | |
707 | } | |
fd3c3ed5 | 708 | |
e8a496ac | 709 | if (HAVE_HWFP) { |
c37b5efe SS |
710 | if (cpu_has_xsave) |
711 | err = restore_i387_xsave(buf); | |
712 | else if (cpu_has_fxsr) | |
713 | err = restore_i387_fxsave(fp, sizeof(struct | |
714 | i387_fxsave_struct)); | |
f668964e | 715 | else |
ab513701 | 716 | err = restore_i387_fsave(fp); |
1da177e4 | 717 | } else { |
44210111 RM |
718 | err = fpregs_soft_set(current, NULL, |
719 | 0, sizeof(struct user_i387_ia32_struct), | |
ab513701 | 720 | NULL, fp) != 0; |
1da177e4 LT |
721 | } |
722 | set_used_math(); | |
f668964e | 723 | |
1da177e4 LT |
724 | return err; |
725 | } | |
726 | ||
1da177e4 LT |
727 | /* |
728 | * FPU state for core dumps. | |
60b3b9af RM |
729 | * This is only used for a.out dumps now. |
730 | * It is declared generically using elf_fpregset_t (which is | |
731 | * struct user_i387_struct) but is in fact only used for 32-bit | |
732 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 733 | */ |
3b095a04 | 734 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 735 | { |
1da177e4 | 736 | struct task_struct *tsk = current; |
f668964e | 737 | int fpvalid; |
1da177e4 LT |
738 | |
739 | fpvalid = !!used_math(); | |
60b3b9af RM |
740 | if (fpvalid) |
741 | fpvalid = !fpregs_get(tsk, NULL, | |
742 | 0, sizeof(struct user_i387_ia32_struct), | |
743 | fpu, NULL); | |
1da177e4 LT |
744 | |
745 | return fpvalid; | |
746 | } | |
129f6946 | 747 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 748 | |
60b3b9af | 749 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |