[net-next-2.6.git] / arch / x86 / kernel / genx2apic_uv_x.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV APIC functions (note: not an Intel compatible APIC)
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/hardirq.h>
#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>
#include <asm/pgtable.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>

DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);

struct uv_blade_info *uv_blade_info;
EXPORT_SYMBOL_GPL(uv_blade_info);

short *uv_node_to_blade;
EXPORT_SYMBOL_GPL(uv_node_to_blade);

short *uv_cpu_to_blade;
EXPORT_SYMBOL_GPL(uv_cpu_to_blade);

short uv_possible_blades;
EXPORT_SYMBOL_GPL(uv_possible_blades);

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t uv_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t uv_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
{
	unsigned long val;
	int pnode;

	pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_INIT;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_STARTUP;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;
}

static void uv_send_IPI_one(int cpu, int vector)
{
	unsigned long val, apicid, lapicid;
	int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
	lapicid = apicid & 0x3f;		/* ZZZ macro needed */
	pnode = uv_apicid_to_pnode(apicid);
	val =
	    (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
					      UVH_IPI_INT_APIC_ID_SHFT) |
	    (vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

static void uv_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned int cpu;

	for (cpu = 0; cpu < NR_CPUS; ++cpu)
		if (cpu_isset(cpu, mask))
			uv_send_IPI_one(cpu, vector);
}

static void uv_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		uv_send_IPI_mask(mask, vector);
}

static void uv_send_IPI_all(int vector)
{
	uv_send_IPI_mask(cpu_online_map, vector);
}

static int uv_apic_id_registered(void)
{
	return 1;
}

static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < NR_CPUS)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int uv_read_apic_id(void)
{
	unsigned int id;

	WARN_ON(preemptible() && num_online_cpus() > 1);
	id = apic_read(APIC_ID) | __get_cpu_var(x2apic_extra_bits);

	return id;
}

static unsigned int phys_pkg_id(int index_msb)
{
	return uv_read_apic_id() >> index_msb;
}

#ifdef ZZZ		/* Needs x2apic patch */
static void uv_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}
#endif

struct genapic apic_x2apic_uv_x = {
	.name = "UV large system",
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = uv_target_cpus,
	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	.apic_id_registered = uv_apic_id_registered,
	.send_IPI_all = uv_send_IPI_all,
	.send_IPI_allbutself = uv_send_IPI_allbutself,
	.send_IPI_mask = uv_send_IPI_mask,
	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,	/* Fixme ZZZ */
	.read_apic_id = uv_read_apic_id,
};

static __cpuinit void set_x2apic_extra_bits(int pnode)
{
	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
}

/*
 * Called on boot cpu.
 */
static __init int boot_pnode_to_blade(int pnode)
{
	int blade;

	for (blade = 0; blade < uv_num_possible_blades(); blade++)
		if (pnode == uv_blade_info[blade].pnode)
			return blade;
	BUG();
}

struct redir_addr {
	unsigned long redirect;
	unsigned long alias;
};

#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

static __initdata struct redir_addr redir_addrs[] = {
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
};

static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
{
	union uvh_si_alias0_overlay_config_u alias;
	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	int i;

	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
		if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
		}
	}
	BUG();
}

static __init void map_low_mmrs(void)
{
	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
}

enum map_type {map_wb, map_uc};

static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
{
	unsigned long bytes, paddr;

	paddr = base << shift;
	bytes = (1UL << shift);
	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	       					paddr + bytes);
	if (map_type == map_uc)
		init_extra_mapping_uc(paddr, bytes);
	else
		init_extra_mapping_wb(paddr, bytes);

}
static __init void map_gru_high(int max_pnode)
{
	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;

	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	if (gru.s.enable)
		map_high("GRU", gru.s.base, shift, map_wb);
}

static __init void map_config_high(int max_pnode)
{
	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;

	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	if (cfg.s.enable)
		map_high("CONFIG", cfg.s.base, shift, map_uc);
}

static __init void map_mmr_high(int max_pnode)
{
	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	if (mmr.s.enable)
		map_high("MMR", mmr.s.base, shift, map_uc);
}

static __init void map_mmioh_high(int max_pnode)
{
	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	if (mmioh.s.enable)
		map_high("MMIOH", mmioh.s.base, shift, map_uc);
}

static __init void uv_system_init(void)
{
	union uvh_si_addr_map_config_u m_n_config;
	union uvh_node_id_u node_id;
	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
	int max_pnode = 0;
	unsigned long mmr_base, present;

	map_low_mmrs();

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
	m_val = m_n_config.s.m_skt;
	n_val = m_n_config.s.n_skt;
	mmr_base =
	    uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	    ~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
		uv_possible_blades +=
		  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = alloc_bootmem_pages(bytes);

	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_node_to_blade, 255, bytes);

	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_cpu_to_blade, 255, bytes);

	blade = 0;
	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
		for (j = 0; j < 64; j++) {
			if (!test_bit(j, &present))
				continue;
			uv_blade_info[blade].pnode = (i * 64 + j);
			uv_blade_info[blade].nr_possible_cpus = 0;
			uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
		}
	}

	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	gnode_upper = (((unsigned long)node_id.s.node_id) &
		       ~((1 << n_val) - 1)) << m_val;

	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
		blade = boot_pnode_to_blade(pnode);
		lcpu = uv_blade_info[blade].nr_possible_cpus;
		uv_blade_info[blade].nr_possible_cpus++;

		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
		uv_cpu_hub_info(cpu)->lowmem_remap_top =
					lowmem_redir_base + lowmem_redir_size;
		uv_cpu_hub_info(cpu)->m_val = m_val;
		uv_cpu_hub_info(cpu)->n_val = m_val;
		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
		uv_cpu_hub_info(cpu)->pnode = pnode;
		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
		uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
		uv_node_to_blade[nid] = blade;
		uv_cpu_to_blade[cpu] = blade;
		max_pnode = max(pnode, max_pnode);

		printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
			"lcpu %d, blade %d\n",
			cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}

	map_gru_high(max_pnode);
	map_mmr_high(max_pnode);
	map_config_high(max_pnode);
	map_mmioh_high(max_pnode);
}

/*
 * Called on each cpu to initialize the per_cpu UV data area.
 * 	ZZZ hotplug not supported yet
 */
void __cpuinit uv_cpu_init(void)
{
	if (!uv_node_to_blade)
		uv_system_init();

	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
		set_x2apic_extra_bits(uv_hub_info->pnode);
}
Commit	Line	Data
ac23d4ee JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV APIC functions (note: not an Intel compatible APIC)
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
ac23d4ee JS	9	*/
ac23d4ee JS	10
83f5d894	11	#include <linux/kernel.h>
ac23d4ee JS	12	#include <linux/threads.h>
	13	#include <linux/cpumask.h>
	14	#include <linux/string.h>
	15	#include <linux/kernel.h>
	16	#include <linux/ctype.h>
	17	#include <linux/init.h>
	18	#include <linux/sched.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/module.h>
0c81c746	21	#include <linux/hardirq.h>
ac23d4ee JS	22	#include <asm/smp.h>
	23	#include <asm/ipi.h>
	24	#include <asm/genapic.h>
83f5d894	25	#include <asm/pgtable.h>
ac23d4ee JS	26	#include <asm/uv/uv_mmrs.h>
	27	#include <asm/uv/uv_hub.h>
	28
	29	DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	30	EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
	31
	32	struct uv_blade_info *uv_blade_info;
	33	EXPORT_SYMBOL_GPL(uv_blade_info);
	34
	35	short *uv_node_to_blade;
	36	EXPORT_SYMBOL_GPL(uv_node_to_blade);
	37
	38	short *uv_cpu_to_blade;
	39	EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
	40
	41	short uv_possible_blades;
	42	EXPORT_SYMBOL_GPL(uv_possible_blades);
	43
	44	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	45
	46	static cpumask_t uv_target_cpus(void)
	47	{
	48	return cpumask_of_cpu(0);
	49	}
	50
	51	static cpumask_t uv_vector_allocation_domain(int cpu)
	52	{
	53	cpumask_t domain = CPU_MASK_NONE;
	54	cpu_set(cpu, domain);
	55	return domain;
	56	}
	57
	58	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	59	{
	60	unsigned long val;
9f5314fb	61	int pnode;
ac23d4ee	62
9f5314fb	63	pnode = uv_apicid_to_pnode(phys_apicid);
ac23d4ee JS	64	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	65	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	66	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
34d05591	67	APIC_DM_INIT;
9f5314fb	68	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591 JS	69	mdelay(10);
	70
	71	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	72	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	73	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	74	APIC_DM_STARTUP;
9f5314fb	75	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	76	return 0;
	77	}
	78
	79	static void uv_send_IPI_one(int cpu, int vector)
	80	{
34d05591	81	unsigned long val, apicid, lapicid;
9f5314fb	82	int pnode;
ac23d4ee JS	83
ac23d4ee JS	84	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
34d05591	85	lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb	86	pnode = uv_apicid_to_pnode(apicid);
ac23d4ee	87	val =
34d05591	88	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
ac23d4ee JS	89	UVH_IPI_INT_APIC_ID_SHFT) \|
ac23d4ee JS	90	(vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb	91	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	92	}
	93
	94	static void uv_send_IPI_mask(cpumask_t mask, int vector)
	95	{
	96	unsigned int cpu;
	97
	98	for (cpu = 0; cpu < NR_CPUS; ++cpu)
	99	if (cpu_isset(cpu, mask))
	100	uv_send_IPI_one(cpu, vector);
	101	}
	102
	103	static void uv_send_IPI_allbutself(int vector)
	104	{
	105	cpumask_t mask = cpu_online_map;
	106
	107	cpu_clear(smp_processor_id(), mask);
	108
	109	if (!cpus_empty(mask))
	110	uv_send_IPI_mask(mask, vector);
	111	}
	112
	113	static void uv_send_IPI_all(int vector)
	114	{
	115	uv_send_IPI_mask(cpu_online_map, vector);
	116	}
	117
	118	static int uv_apic_id_registered(void)
	119	{
	120	return 1;
	121	}
	122
	123	static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
	124	{
	125	int cpu;
	126
	127	/*
	128	* We're using fixed IRQ delivery, can only return one phys APIC ID.
	129	* May as well be the first.
	130	*/
	131	cpu = first_cpu(cpumask);
	132	if ((unsigned)cpu < NR_CPUS)
	133	return per_cpu(x86_cpu_to_apicid, cpu);
	134	else
	135	return BAD_APICID;
	136	}
	137
0c81c746 SS	138	static unsigned int uv_read_apic_id(void)
	139	{
	140	unsigned int id;
	141
	142	WARN_ON(preemptible() && num_online_cpus() > 1);
	143	id = apic_read(APIC_ID) \| __get_cpu_var(x2apic_extra_bits);
	144
	145	return id;
	146	}
	147
ac23d4ee JS	148	static unsigned int phys_pkg_id(int index_msb)
ac23d4ee JS	149	{
0c81c746	150	return uv_read_apic_id() >> index_msb;
ac23d4ee JS	151	}
	152
	153	#ifdef ZZZ /* Needs x2apic patch */
	154	static void uv_send_IPI_self(int vector)
	155	{
	156	apic_write(APIC_SELF_IPI, vector);
	157	}
	158	#endif
	159
	160	struct genapic apic_x2apic_uv_x = {
	161	.name = "UV large system",
	162	.int_delivery_mode = dest_Fixed,
	163	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	164	.target_cpus = uv_target_cpus,
	165	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	166	.apic_id_registered = uv_apic_id_registered,
	167	.send_IPI_all = uv_send_IPI_all,
	168	.send_IPI_allbutself = uv_send_IPI_allbutself,
	169	.send_IPI_mask = uv_send_IPI_mask,
	170	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	171	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	172	.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
0c81c746	173	.read_apic_id = uv_read_apic_id,
ac23d4ee JS	174	};
ac23d4ee JS	175
9f5314fb	176	static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee	177	{
9f5314fb	178	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
ac23d4ee JS	179	}
	180
	181	/*
	182	* Called on boot cpu.
	183	*/
9f5314fb JS	184	static __init int boot_pnode_to_blade(int pnode)
	185	{
	186	int blade;
	187
	188	for (blade = 0; blade < uv_num_possible_blades(); blade++)
	189	if (pnode == uv_blade_info[blade].pnode)
	190	return blade;
	191	BUG();
	192	}
	193
	194	struct redir_addr {
	195	unsigned long redirect;
	196	unsigned long alias;
	197	};
	198
	199	#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
	200
	201	static __initdata struct redir_addr redir_addrs[] = {
	202	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	203	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	204	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
	205	};
	206
	207	static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
	208	{
	209	union uvh_si_alias0_overlay_config_u alias;
	210	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	211	int i;
	212
	213	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
	214	alias.v = uv_read_local_mmr(redir_addrs[i].alias);
	215	if (alias.s.base == 0) {
	216	*size = (1UL << alias.s.m_alias);
	217	redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
	218	*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
	219	return;
	220	}
	221	}
	222	BUG();
	223	}
	224
83f5d894 JS	225	static __init void map_low_mmrs(void)
	226	{
	227	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	228	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
	229	}
	230
	231	enum map_type {map_wb, map_uc};
	232
	233	static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
	234	{
	235	unsigned long bytes, paddr;
	236
	237	paddr = base << shift;
	238	bytes = (1UL << shift);
	239	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	240	paddr + bytes);
	241	if (map_type == map_uc)
	242	init_extra_mapping_uc(paddr, bytes);
	243	else
	244	init_extra_mapping_wb(paddr, bytes);
	245
	246	}
	247	static __init void map_gru_high(int max_pnode)
	248	{
	249	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	250	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
	251
	252	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	253	if (gru.s.enable)
	254	map_high("GRU", gru.s.base, shift, map_wb);
	255	}
	256
	257	static __init void map_config_high(int max_pnode)
	258	{
	259	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	260	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
	261
	262	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	263	if (cfg.s.enable)
	264	map_high("CONFIG", cfg.s.base, shift, map_uc);
	265	}
	266
	267	static __init void map_mmr_high(int max_pnode)
	268	{
	269	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	270	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
	271
	272	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	273	if (mmr.s.enable)
	274	map_high("MMR", mmr.s.base, shift, map_uc);
	275	}
	276
	277	static __init void map_mmioh_high(int max_pnode)
	278	{
	279	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	280	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
	281
	282	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	283	if (mmioh.s.enable)
	284	map_high("MMIOH", mmioh.s.base, shift, map_uc);
	285	}
	286
ac23d4ee JS	287	static __init void uv_system_init(void)
	288	{
	289	union uvh_si_addr_map_config_u m_n_config;
9f5314fb JS	290	union uvh_node_id_u node_id;
	291	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	292	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894	293	int max_pnode = 0;
9f5314fb	294	unsigned long mmr_base, present;
ac23d4ee	295
83f5d894 JS	296	map_low_mmrs();
83f5d894 JS	297
ac23d4ee	298	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
9f5314fb JS	299	m_val = m_n_config.s.m_skt;
9f5314fb JS	300	n_val = m_n_config.s.n_skt;
ac23d4ee JS	301	mmr_base =
	302	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	303	~UV_MMR_ENABLE;
	304	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
	305
9f5314fb JS	306	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	307	uv_possible_blades +=
	308	hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
ac23d4ee JS	309	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
	310
	311	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	312	uv_blade_info = alloc_bootmem_pages(bytes);
	313
9f5314fb JS	314	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
9f5314fb JS	315
ac23d4ee JS	316	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	317	uv_node_to_blade = alloc_bootmem_pages(bytes);
	318	memset(uv_node_to_blade, 255, bytes);
	319
	320	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	321	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	322	memset(uv_cpu_to_blade, 255, bytes);
	323
9f5314fb JS	324	blade = 0;
	325	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	326	present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	327	for (j = 0; j < 64; j++) {
	328	if (!test_bit(j, &present))
	329	continue;
	330	uv_blade_info[blade].pnode = (i * 64 + j);
	331	uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee	332	uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb	333	blade++;
ac23d4ee	334	}
9f5314fb	335	}
ac23d4ee	336
9f5314fb JS	337	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	338	gnode_upper = (((unsigned long)node_id.s.node_id) &
	339	~((1 << n_val) - 1)) << m_val;
	340
	341	for_each_present_cpu(cpu) {
	342	nid = cpu_to_node(cpu);
	343	pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
	344	blade = boot_pnode_to_blade(pnode);
	345	lcpu = uv_blade_info[blade].nr_possible_cpus;
	346	uv_blade_info[blade].nr_possible_cpus++;
	347
	348	uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
	349	uv_cpu_hub_info(cpu)->lowmem_remap_top =
	350	lowmem_redir_base + lowmem_redir_size;
	351	uv_cpu_hub_info(cpu)->m_val = m_val;
	352	uv_cpu_hub_info(cpu)->n_val = m_val;
ac23d4ee JS	353	uv_cpu_hub_info(cpu)->numa_blade_id = blade;
ac23d4ee JS	354	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
9f5314fb JS	355	uv_cpu_hub_info(cpu)->pnode = pnode;
	356	uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	357	uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
	358	uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee JS	359	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
ac23d4ee JS	360	uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
ac23d4ee JS	361	uv_node_to_blade[nid] = blade;
ac23d4ee JS	362	uv_cpu_to_blade[cpu] = blade;
83f5d894	363	max_pnode = max(pnode, max_pnode);
ac23d4ee	364
83f5d894	365	printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
9f5314fb JS	366	"lcpu %d, blade %d\n",
	367	cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
	368	lcpu, blade);
ac23d4ee	369	}
83f5d894 JS	370
	371	map_gru_high(max_pnode);
	372	map_mmr_high(max_pnode);
	373	map_config_high(max_pnode);
	374	map_mmioh_high(max_pnode);
ac23d4ee JS	375	}
	376
	377	/*
	378	* Called on each cpu to initialize the per_cpu UV data area.
9f5314fb	379	* ZZZ hotplug not supported yet
ac23d4ee JS	380	*/
	381	void __cpuinit uv_cpu_init(void)
	382	{
	383	if (!uv_node_to_blade)
	384	uv_system_init();
	385
	386	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
	387
	388	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
9f5314fb	389	set_x2apic_extra_bits(uv_hub_info->pnode);
ac23d4ee	390	}