[net-next-2.6.git] / arch / x86 / kernel / early-quirks.c

/* Various workarounds for chipset bugs.
   This code runs very early and can't use the regular PCI subsystem
   The entries are keyed to PCI bridges which usually identify chipsets
   uniquely.
   This is only for whole classes of chipsets with specific problems which
   need early invasive action (e.g. before the timers are initialized).
   Most PCI device specific workarounds can be done later and should be
   in standard PCI quirks
   Mainboard specific bugs should be handled by DMI entries.
   CPU specific bugs in setup.c */

#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/pci_ids.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/io_apic.h>
#include <asm/apic.h>
#include <asm/iommu.h>
#include <asm/gart.h>
#include <asm/hpet.h>

static void __init fix_hypertransport_config(int num, int slot, int func)
{
	u32 htcfg;
	/*
	 * we found a hypertransport bus
	 * make sure that we are broadcasting
	 * interrupts to all cpus on the ht bus
	 * if we're using extended apic ids
	 */
	htcfg = read_pci_config(num, slot, func, 0x68);
	if (htcfg & (1 << 18)) {
		printk(KERN_INFO "Detected use of extended apic ids "
				 "on hypertransport bus\n");
		if ((htcfg & (1 << 17)) == 0) {
			printk(KERN_INFO "Enabling hypertransport extended "
					 "apic interrupt broadcast\n");
			printk(KERN_INFO "Note this is a bios bug, "
					 "please contact your hw vendor\n");
			htcfg |= (1 << 17);
			write_pci_config(num, slot, func, 0x68, htcfg);
		}
	}


}

static void __init via_bugs(int  num, int slot, int func)
{
#ifdef CONFIG_GART_IOMMU
	if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
	    !gart_iommu_aperture_allowed) {
		printk(KERN_INFO
		       "Looks like a VIA chipset. Disabling IOMMU."
		       " Override with iommu=allowed\n");
		gart_iommu_aperture_disabled = 1;
	}
#endif
}

#ifdef CONFIG_ACPI
#ifdef CONFIG_X86_IO_APIC

static int __init nvidia_hpet_check(struct acpi_table_header *header)
{
	return 0;
}
#endif /* CONFIG_X86_IO_APIC */
#endif /* CONFIG_ACPI */

static void __init nvidia_bugs(int num, int slot, int func)
{
#ifdef CONFIG_ACPI
#ifdef CONFIG_X86_IO_APIC
	/*
	 * All timer overrides on Nvidia are
	 * wrong unless HPET is enabled.
	 * Unfortunately that's not true on many Asus boards.
	 * We don't know yet how to detect this automatically, but
	 * at least allow a command line override.
	 */
	if (acpi_use_timer_override)
		return;

	if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
		acpi_skip_timer_override = 1;
		printk(KERN_INFO "Nvidia board "
		       "detected. Ignoring ACPI "
		       "timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
			"try acpi_use_timer_override\n");
	}
#endif
#endif
	/* RED-PEN skip them on mptables too? */

}

#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
{
	u32 d;
	u8  b;

	b = read_pci_config_byte(num, slot, func, 0xac);
	b &= ~(1<<5);
	write_pci_config_byte(num, slot, func, 0xac, b);

	d = read_pci_config(num, slot, func, 0x70);
	d |= 1<<8;
	write_pci_config(num, slot, func, 0x70, d);

	d = read_pci_config(num, slot, func, 0x8);
	d &= 0xff;
	return d;
}
#endif

static void __init ati_bugs(int num, int slot, int func)
{
	u32 d;
	u8  b;

	if (acpi_use_timer_override)
		return;

	d = ati_ixp4x0_rev(num, slot, func);
	if (d  < 0x82)
		acpi_skip_timer_override = 1;
	else {
		/* check for IRQ0 interrupt swap */
		outb(0x72, 0xcd6); b = inb(0xcd7);
		if (!(b & 0x2))
			acpi_skip_timer_override = 1;
	}

	if (acpi_skip_timer_override) {
		printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
		printk(KERN_INFO "Ignoring ACPI timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
		       "try acpi_use_timer_override\n");
	}
}

static u32 __init ati_sbx00_rev(int num, int slot, int func)
{
	u32 old, d;

	d = read_pci_config(num, slot, func, 0x70);
	old = d;
	d &= ~(1<<8);
	write_pci_config(num, slot, func, 0x70, d);
	d = read_pci_config(num, slot, func, 0x8);
	d &= 0xff;
	write_pci_config(num, slot, func, 0x70, old);

	return d;
}

static void __init ati_bugs_contd(int num, int slot, int func)
{
	u32 d, rev;

	if (acpi_use_timer_override)
		return;

	rev = ati_sbx00_rev(num, slot, func);
	if (rev > 0x13)
		return;

	/* check for IRQ0 interrupt swap */
	d = read_pci_config(num, slot, func, 0x64);
	if (!(d & (1<<14)))
		acpi_skip_timer_override = 1;

	if (acpi_skip_timer_override) {
		printk(KERN_INFO "SB600 revision 0x%x\n", rev);
		printk(KERN_INFO "Ignoring ACPI timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
		       "try acpi_use_timer_override\n");
	}
}
#else
static void __init ati_bugs(int num, int slot, int func)
{
}

static void __init ati_bugs_contd(int num, int slot, int func)
{
}
#endif

/*
 * Force the read back of the CMP register in hpet_next_event()
 * to work around the problem that the CMP register write seems to be
 * delayed. See hpet_next_event() for details.
 *
 * We do this on all SMBUS incarnations for now until we have more
 * information about the affected chipsets.
 */
static void __init ati_hpet_bugs(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
	hpet_readback_cmp = 1;
#endif
}

#define QFLAG_APPLY_ONCE 	0x1
#define QFLAG_APPLIED		0x2
#define QFLAG_DONE		(QFLAG_APPLY_ONCE|QFLAG_APPLIED)
struct chipset {
	u32 vendor;
	u32 device;
	u32 class;
	u32 class_mask;
	u32 flags;
	void (*f)(int num, int slot, int func);
};

/*
 * Only works for devices on the root bus. If you add any devices
 * not on bus 0 readd another loop level in early_quirks(). But
 * be careful because at least the Nvidia quirk here relies on
 * only matching on bus 0.
 */
static struct chipset early_qrk[] __initdata = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	  PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
	{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
	  PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
	  PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
	  PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	  PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
	{ PCI_VENDOR_ID_ATI, PCI_ANY_ID,
	  PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
	{}
};

/**
 * check_dev_quirk - apply early quirks to a given PCI device
 * @num: bus number
 * @slot: slot number
 * @func: PCI function
 *
 * Check the vendor & device ID against the early quirks table.
 *
 * If the device is single function, let early_quirks() know so we don't
 * poke at this device again.
 */
static int __init check_dev_quirk(int num, int slot, int func)
{
	u16 class;
	u16 vendor;
	u16 device;
	u8 type;
	int i;

	class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);

	if (class == 0xffff)
		return -1; /* no class, treat as single function */

	vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);

	device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);

	for (i = 0; early_qrk[i].f != NULL; i++) {
		if (((early_qrk[i].vendor == PCI_ANY_ID) ||
			(early_qrk[i].vendor == vendor)) &&
			((early_qrk[i].device == PCI_ANY_ID) ||
			(early_qrk[i].device == device)) &&
			(!((early_qrk[i].class ^ class) &
			    early_qrk[i].class_mask))) {
				if ((early_qrk[i].flags &
				     QFLAG_DONE) != QFLAG_DONE)
					early_qrk[i].f(num, slot, func);
				early_qrk[i].flags |= QFLAG_APPLIED;
			}
	}

	type = read_pci_config_byte(num, slot, func,
				    PCI_HEADER_TYPE);
	if (!(type & 0x80))
		return -1;

	return 0;
}

void __init early_quirks(void)
{
	int slot, func;

	if (!early_pci_allowed())
		return;

	/* Poor man's PCI discovery */
	/* Only scan the root bus */
	for (slot = 0; slot < 32; slot++)
		for (func = 0; func < 8; func++) {
			/* Only probe function 0 on single fn devices */
			if (check_dev_quirk(0, slot, func))
				break;
		}
}
Commit	Line	Data
dfa4698c AK	1	/* Various workarounds for chipset bugs.
	2	This code runs very early and can't use the regular PCI subsystem
	3	The entries are keyed to PCI bridges which usually identify chipsets
	4	uniquely.
	5	This is only for whole classes of chipsets with specific problems which
	6	need early invasive action (e.g. before the timers are initialized).
	7	Most PCI device specific workarounds can be done later and should be
	8	in standard PCI quirks
	9	Mainboard specific bugs should be handled by DMI entries.
	10	CPU specific bugs in setup.c */
	11
	12	#include <linux/pci.h>
	13	#include <linux/acpi.h>
	14	#include <linux/pci_ids.h>
	15	#include <asm/pci-direct.h>
dfa4698c	16	#include <asm/dma.h>
54ef3400 AK	17	#include <asm/io_apic.h>
54ef3400 AK	18	#include <asm/apic.h>
46a7fa27	19	#include <asm/iommu.h>
1d9b16d1	20	#include <asm/gart.h>
08be9796	21	#include <asm/hpet.h>
dfa4698c	22
c6b48324 NH	23	static void __init fix_hypertransport_config(int num, int slot, int func)
	24	{
	25	u32 htcfg;
	26	/*
	27	* we found a hypertransport bus
	28	* make sure that we are broadcasting
	29	* interrupts to all cpus on the ht bus
	30	* if we're using extended apic ids
	31	*/
	32	htcfg = read_pci_config(num, slot, func, 0x68);
	33	if (htcfg & (1 << 18)) {
7bcbc78d NH	34	printk(KERN_INFO "Detected use of extended apic ids "
7bcbc78d NH	35	"on hypertransport bus\n");
c6b48324	36	if ((htcfg & (1 << 17)) == 0) {
7bcbc78d NH	37	printk(KERN_INFO "Enabling hypertransport extended "
	38	"apic interrupt broadcast\n");
	39	printk(KERN_INFO "Note this is a bios bug, "
	40	"please contact your hw vendor\n");
c6b48324 NH	41	htcfg \|= (1 << 17);
	42	write_pci_config(num, slot, func, 0x68, htcfg);
	43	}
	44	}
	45
	46
	47	}
	48
	49	static void __init via_bugs(int num, int slot, int func)
dfa4698c	50	{
966396d3	51	#ifdef CONFIG_GART_IOMMU
c987d12f	52	if ((max_pfn > MAX_DMA32_PFN \|\| force_iommu) &&
0440d4c0	53	!gart_iommu_aperture_allowed) {
dfa4698c	54	printk(KERN_INFO
54ef3400 AK	55	"Looks like a VIA chipset. Disabling IOMMU."
54ef3400 AK	56	" Override with iommu=allowed\n");
0440d4c0	57	gart_iommu_aperture_disabled = 1;
dfa4698c AK	58	}
	59	#endif
	60	}
	61
	62	#ifdef CONFIG_ACPI
03d0d20e	63	#ifdef CONFIG_X86_IO_APIC
dfa4698c	64
15a58ed1	65	static int __init nvidia_hpet_check(struct acpi_table_header *header)
dfa4698c	66	{
dfa4698c AK	67	return 0;
dfa4698c AK	68	}
03d0d20e JG	69	#endif /* CONFIG_X86_IO_APIC */
03d0d20e JG	70	#endif /* CONFIG_ACPI */
dfa4698c	71
c6b48324	72	static void __init nvidia_bugs(int num, int slot, int func)
dfa4698c AK	73	{
dfa4698c AK	74	#ifdef CONFIG_ACPI
54ef3400	75	#ifdef CONFIG_X86_IO_APIC
dfa4698c AK	76	/*
	77	* All timer overrides on Nvidia are
	78	* wrong unless HPET is enabled.
fa18f477 AK	79	* Unfortunately that's not true on many Asus boards.
	80	* We don't know yet how to detect this automatically, but
	81	* at least allow a command line override.
dfa4698c	82	*/
fa18f477 AK	83	if (acpi_use_timer_override)
	84	return;
	85
fe699336	86	if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
dfa4698c AK	87	acpi_skip_timer_override = 1;
	88	printk(KERN_INFO "Nvidia board "
	89	"detected. Ignoring ACPI "
	90	"timer override.\n");
fa18f477 AK	91	printk(KERN_INFO "If you got timer trouble "
fa18f477 AK	92	"try acpi_use_timer_override\n");
dfa4698c	93	}
54ef3400	94	#endif
dfa4698c AK	95	#endif
	96	/* RED-PEN skip them on mptables too? */
	97
	98	}
	99
a59dacfd	100	#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
26adcfbf AH	101	#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
26adcfbf AH	102	static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
33fb0e4e AH	103	{
	104	u32 d;
	105	u8 b;
	106
	107	b = read_pci_config_byte(num, slot, func, 0xac);
	108	b &= ~(1<<5);
	109	write_pci_config_byte(num, slot, func, 0xac, b);
	110
	111	d = read_pci_config(num, slot, func, 0x70);
	112	d \|= 1<<8;
	113	write_pci_config(num, slot, func, 0x70, d);
	114
	115	d = read_pci_config(num, slot, func, 0x8);
	116	d &= 0xff;
	117	return d;
	118	}
a59dacfd	119	#endif
33fb0e4e AH	120
	121	static void __init ati_bugs(int num, int slot, int func)
	122	{
33fb0e4e AH	123	u32 d;
	124	u8 b;
	125
	126	if (acpi_use_timer_override)
	127	return;
	128
	129	d = ati_ixp4x0_rev(num, slot, func);
	130	if (d < 0x82)
	131	acpi_skip_timer_override = 1;
	132	else {
	133	/* check for IRQ0 interrupt swap */
	134	outb(0x72, 0xcd6); b = inb(0xcd7);
	135	if (!(b & 0x2))
	136	acpi_skip_timer_override = 1;
	137	}
	138
	139	if (acpi_skip_timer_override) {
	140	printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
	141	printk(KERN_INFO "Ignoring ACPI timer override.\n");
	142	printk(KERN_INFO "If you got timer trouble "
	143	"try acpi_use_timer_override\n");
	144	}
33fb0e4e AH	145	}
33fb0e4e AH	146
26adcfbf AH	147	static u32 __init ati_sbx00_rev(int num, int slot, int func)
	148	{
	149	u32 old, d;
	150
	151	d = read_pci_config(num, slot, func, 0x70);
	152	old = d;
	153	d &= ~(1<<8);
	154	write_pci_config(num, slot, func, 0x70, d);
	155	d = read_pci_config(num, slot, func, 0x8);
	156	d &= 0xff;
	157	write_pci_config(num, slot, func, 0x70, old);
	158
	159	return d;
	160	}
	161
	162	static void __init ati_bugs_contd(int num, int slot, int func)
	163	{
	164	u32 d, rev;
	165
	166	if (acpi_use_timer_override)
	167	return;
	168
	169	rev = ati_sbx00_rev(num, slot, func);
	170	if (rev > 0x13)
	171	return;
	172
	173	/* check for IRQ0 interrupt swap */
	174	d = read_pci_config(num, slot, func, 0x64);
	175	if (!(d & (1<<14)))
	176	acpi_skip_timer_override = 1;
	177
	178	if (acpi_skip_timer_override) {
	179	printk(KERN_INFO "SB600 revision 0x%x\n", rev);
	180	printk(KERN_INFO "Ignoring ACPI timer override.\n");
	181	printk(KERN_INFO "If you got timer trouble "
	182	"try acpi_use_timer_override\n");
	183	}
	184	}
	185	#else
	186	static void __init ati_bugs(int num, int slot, int func)
	187	{
	188	}
	189
	190	static void __init ati_bugs_contd(int num, int slot, int func)
	191	{
	192	}
	193	#endif
	194
08be9796 TG	195	/*
	196	* Force the read back of the CMP register in hpet_next_event()
	197	* to work around the problem that the CMP register write seems to be
	198	* delayed. See hpet_next_event() for details.
	199	*
	200	* We do this on all SMBUS incarnations for now until we have more
	201	* information about the affected chipsets.
	202	*/
	203	static void __init ati_hpet_bugs(int num, int slot, int func)
	204	{
	205	#ifdef CONFIG_HPET_TIMER
	206	hpet_readback_cmp = 1;
	207	#endif
	208	}
	209
c6b48324 NH	210	#define QFLAG_APPLY_ONCE 0x1
	211	#define QFLAG_APPLIED 0x2
	212	#define QFLAG_DONE (QFLAG_APPLY_ONCE\|QFLAG_APPLIED)
dfa4698c	213	struct chipset {
c6b48324 NH	214	u32 vendor;
	215	u32 device;
	216	u32 class;
	217	u32 class_mask;
	218	u32 flags;
	219	void (*f)(int num, int slot, int func);
dfa4698c AK	220	};
dfa4698c AK	221
8659c406 AK	222	/*
	223	* Only works for devices on the root bus. If you add any devices
	224	* not on bus 0 readd another loop level in early_quirks(). But
	225	* be careful because at least the Nvidia quirk here relies on
	226	* only matching on bus 0.
	227	*/
c993c735	228	static struct chipset early_qrk[] __initdata = {
c6b48324 NH	229	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	230	PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
	231	{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
	232	PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
c6b48324 NH	233	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
c6b48324 NH	234	PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
33fb0e4e AH	235	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
33fb0e4e AH	236	PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
26adcfbf AH	237	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
26adcfbf AH	238	PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
08be9796 TG	239	{ PCI_VENDOR_ID_ATI, PCI_ANY_ID,
08be9796 TG	240	PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
dfa4698c AK	241	{}
	242	};
	243
15650a2f JB	244	/**
	245	* check_dev_quirk - apply early quirks to a given PCI device
	246	* @num: bus number
	247	* @slot: slot number
	248	* @func: PCI function
	249	*
	250	* Check the vendor & device ID against the early quirks table.
	251	*
	252	* If the device is single function, let early_quirks() know so we don't
	253	* poke at this device again.
	254	*/
	255	static int __init check_dev_quirk(int num, int slot, int func)
7bcbc78d NH	256	{
	257	u16 class;
	258	u16 vendor;
	259	u16 device;
	260	u8 type;
	261	int i;
	262
	263	class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
	264
	265	if (class == 0xffff)
15650a2f	266	return -1; /* no class, treat as single function */
7bcbc78d NH	267
	268	vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
	269
	270	device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
	271
	272	for (i = 0; early_qrk[i].f != NULL; i++) {
	273	if (((early_qrk[i].vendor == PCI_ANY_ID) \|\|
	274	(early_qrk[i].vendor == vendor)) &&
	275	((early_qrk[i].device == PCI_ANY_ID) \|\|
	276	(early_qrk[i].device == device)) &&
	277	(!((early_qrk[i].class ^ class) &
	278	early_qrk[i].class_mask))) {
	279	if ((early_qrk[i].flags &
	280	QFLAG_DONE) != QFLAG_DONE)
	281	early_qrk[i].f(num, slot, func);
	282	early_qrk[i].flags \|= QFLAG_APPLIED;
	283	}
	284	}
	285
	286	type = read_pci_config_byte(num, slot, func,
	287	PCI_HEADER_TYPE);
	288	if (!(type & 0x80))
15650a2f JB	289	return -1;
	290
	291	return 0;
7bcbc78d NH	292	}
7bcbc78d NH	293
dfa4698c AK	294	void __init early_quirks(void)
dfa4698c AK	295	{
8659c406	296	int slot, func;
0637a70a AK	297
	298	if (!early_pci_allowed())
	299	return;
	300
dfa4698c	301	/* Poor man's PCI discovery */
8659c406 AK	302	/* Only scan the root bus */
	303	for (slot = 0; slot < 32; slot++)
	304	for (func = 0; func < 8; func++) {
	305	/* Only probe function 0 on single fn devices */
	306	if (check_dev_quirk(0, slot, func))
	307	break;
	308	}
dfa4698c	309	}