[net-next-2.6.git] / arch / x86 / kernel / early-quirks.c

/* Various workarounds for chipset bugs.
   This code runs very early and can't use the regular PCI subsystem
   The entries are keyed to PCI bridges which usually identify chipsets
   uniquely.
   This is only for whole classes of chipsets with specific problems which
   need early invasive action (e.g. before the timers are initialized).
   Most PCI device specific workarounds can be done later and should be
   in standard PCI quirks
   Mainboard specific bugs should be handled by DMI entries.
   CPU specific bugs in setup.c */

#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/pci_ids.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/io_apic.h>
#include <asm/apic.h>
#include <asm/iommu.h>

static void __init fix_hypertransport_config(int num, int slot, int func)
{
	u32 htcfg;
	/*
	 * we found a hypertransport bus
	 * make sure that we are broadcasting
	 * interrupts to all cpus on the ht bus
	 * if we're using extended apic ids
	 */
	htcfg = read_pci_config(num, slot, func, 0x68);
	if (htcfg & (1 << 18)) {
		printk(KERN_INFO "Detected use of extended apic ids "
				 "on hypertransport bus\n");
		if ((htcfg & (1 << 17)) == 0) {
			printk(KERN_INFO "Enabling hypertransport extended "
					 "apic interrupt broadcast\n");
			printk(KERN_INFO "Note this is a bios bug, "
					 "please contact your hw vendor\n");
			htcfg |= (1 << 17);
			write_pci_config(num, slot, func, 0x68, htcfg);
		}
	}


}

static void __init via_bugs(int  num, int slot, int func)
{
#ifdef CONFIG_GART_IOMMU
	if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
	    !gart_iommu_aperture_allowed) {
		printk(KERN_INFO
		       "Looks like a VIA chipset. Disabling IOMMU."
		       " Override with iommu=allowed\n");
		gart_iommu_aperture_disabled = 1;
	}
#endif
}

#ifdef CONFIG_ACPI
#ifdef CONFIG_X86_IO_APIC

static int __init nvidia_hpet_check(struct acpi_table_header *header)
{
	return 0;
}
#endif /* CONFIG_X86_IO_APIC */
#endif /* CONFIG_ACPI */

static void __init nvidia_bugs(int num, int slot, int func)
{
#ifdef CONFIG_ACPI
#ifdef CONFIG_X86_IO_APIC
	/*
	 * All timer overrides on Nvidia are
	 * wrong unless HPET is enabled.
	 * Unfortunately that's not true on many Asus boards.
	 * We don't know yet how to detect this automatically, but
	 * at least allow a command line override.
	 */
	if (acpi_use_timer_override)
		return;

	if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
		acpi_skip_timer_override = 1;
		printk(KERN_INFO "Nvidia board "
		       "detected. Ignoring ACPI "
		       "timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
			"try acpi_use_timer_override\n");
	}
#endif
#endif
	/* RED-PEN skip them on mptables too? */

}

#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
{
	u32 d;
	u8  b;

	b = read_pci_config_byte(num, slot, func, 0xac);
	b &= ~(1<<5);
	write_pci_config_byte(num, slot, func, 0xac, b);

	d = read_pci_config(num, slot, func, 0x70);
	d |= 1<<8;
	write_pci_config(num, slot, func, 0x70, d);

	d = read_pci_config(num, slot, func, 0x8);
	d &= 0xff;
	return d;
}

static void __init ati_bugs(int num, int slot, int func)
{
	u32 d;
	u8  b;

	if (acpi_use_timer_override)
		return;

	d = ati_ixp4x0_rev(num, slot, func);
	if (d  < 0x82)
		acpi_skip_timer_override = 1;
	else {
		/* check for IRQ0 interrupt swap */
		outb(0x72, 0xcd6); b = inb(0xcd7);
		if (!(b & 0x2))
			acpi_skip_timer_override = 1;
	}

	if (acpi_skip_timer_override) {
		printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
		printk(KERN_INFO "Ignoring ACPI timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
		       "try acpi_use_timer_override\n");
	}
}

static u32 __init ati_sbx00_rev(int num, int slot, int func)
{
	u32 old, d;

	d = read_pci_config(num, slot, func, 0x70);
	old = d;
	d &= ~(1<<8);
	write_pci_config(num, slot, func, 0x70, d);
	d = read_pci_config(num, slot, func, 0x8);
	d &= 0xff;
	write_pci_config(num, slot, func, 0x70, old);

	return d;
}

static void __init ati_bugs_contd(int num, int slot, int func)
{
	u32 d, rev;

	if (acpi_use_timer_override)
		return;

	rev = ati_sbx00_rev(num, slot, func);
	if (rev > 0x13)
		return;

	/* check for IRQ0 interrupt swap */
	d = read_pci_config(num, slot, func, 0x64);
	if (!(d & (1<<14)))
		acpi_skip_timer_override = 1;

	if (acpi_skip_timer_override) {
		printk(KERN_INFO "SB600 revision 0x%x\n", rev);
		printk(KERN_INFO "Ignoring ACPI timer override.\n");
		printk(KERN_INFO "If you got timer trouble "
		       "try acpi_use_timer_override\n");
	}
}
#else
static void __init ati_bugs(int num, int slot, int func)
{
}

static void __init ati_bugs_contd(int num, int slot, int func)
{
}
#endif

#ifdef CONFIG_DMAR
static void __init intel_g33_dmar(int num, int slot, int func)
{
	struct acpi_table_header *dmar_tbl;
	acpi_status status;

	status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
	if (ACPI_SUCCESS(status)) {
		printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n");
		dmar_disabled = 1;
	}
}
#endif

#define QFLAG_APPLY_ONCE 	0x1
#define QFLAG_APPLIED		0x2
#define QFLAG_DONE		(QFLAG_APPLY_ONCE|QFLAG_APPLIED)
struct chipset {
	u32 vendor;
	u32 device;
	u32 class;
	u32 class_mask;
	u32 flags;
	void (*f)(int num, int slot, int func);
};

static struct chipset early_qrk[] __initdata = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	  PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
	{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
	  PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
	  PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
	  PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	  PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
#ifdef CONFIG_DMAR
	{ PCI_VENDOR_ID_INTEL, 0x29c0,
	  PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar },
#endif
	{}
};

/**
 * check_dev_quirk - apply early quirks to a given PCI device
 * @num: bus number
 * @slot: slot number
 * @func: PCI function
 *
 * Check the vendor & device ID against the early quirks table.
 *
 * If the device is single function, let early_quirks() know so we don't
 * poke at this device again.
 */
static int __init check_dev_quirk(int num, int slot, int func)
{
	u16 class;
	u16 vendor;
	u16 device;
	u8 type;
	int i;

	class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);

	if (class == 0xffff)
		return -1; /* no class, treat as single function */

	vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);

	device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);

	for (i = 0; early_qrk[i].f != NULL; i++) {
		if (((early_qrk[i].vendor == PCI_ANY_ID) ||
			(early_qrk[i].vendor == vendor)) &&
			((early_qrk[i].device == PCI_ANY_ID) ||
			(early_qrk[i].device == device)) &&
			(!((early_qrk[i].class ^ class) &
			    early_qrk[i].class_mask))) {
				if ((early_qrk[i].flags &
				     QFLAG_DONE) != QFLAG_DONE)
					early_qrk[i].f(num, slot, func);
				early_qrk[i].flags |= QFLAG_APPLIED;
			}
	}

	type = read_pci_config_byte(num, slot, func,
				    PCI_HEADER_TYPE);
	if (!(type & 0x80))
		return -1;

	return 0;
}

void __init early_quirks(void)
{
	int num, slot, func;

	if (!early_pci_allowed())
		return;

	/* Poor man's PCI discovery */
	for (num = 0; num < 32; num++)
		for (slot = 0; slot < 32; slot++)
			for (func = 0; func < 8; func++) {
				/* Only probe function 0 on single fn devices */
				if (check_dev_quirk(num, slot, func))
					break;
			}
}
Commit	Line	Data
dfa4698c AK	1	/* Various workarounds for chipset bugs.
	2	This code runs very early and can't use the regular PCI subsystem
	3	The entries are keyed to PCI bridges which usually identify chipsets
	4	uniquely.
	5	This is only for whole classes of chipsets with specific problems which
	6	need early invasive action (e.g. before the timers are initialized).
	7	Most PCI device specific workarounds can be done later and should be
	8	in standard PCI quirks
	9	Mainboard specific bugs should be handled by DMI entries.
	10	CPU specific bugs in setup.c */
	11
	12	#include <linux/pci.h>
	13	#include <linux/acpi.h>
	14	#include <linux/pci_ids.h>
	15	#include <asm/pci-direct.h>
dfa4698c	16	#include <asm/dma.h>
54ef3400 AK	17	#include <asm/io_apic.h>
54ef3400 AK	18	#include <asm/apic.h>
46a7fa27	19	#include <asm/iommu.h>
dfa4698c	20
c6b48324 NH	21	static void __init fix_hypertransport_config(int num, int slot, int func)
	22	{
	23	u32 htcfg;
	24	/*
	25	* we found a hypertransport bus
	26	* make sure that we are broadcasting
	27	* interrupts to all cpus on the ht bus
	28	* if we're using extended apic ids
	29	*/
	30	htcfg = read_pci_config(num, slot, func, 0x68);
	31	if (htcfg & (1 << 18)) {
7bcbc78d NH	32	printk(KERN_INFO "Detected use of extended apic ids "
7bcbc78d NH	33	"on hypertransport bus\n");
c6b48324	34	if ((htcfg & (1 << 17)) == 0) {
7bcbc78d NH	35	printk(KERN_INFO "Enabling hypertransport extended "
	36	"apic interrupt broadcast\n");
	37	printk(KERN_INFO "Note this is a bios bug, "
	38	"please contact your hw vendor\n");
c6b48324 NH	39	htcfg \|= (1 << 17);
	40	write_pci_config(num, slot, func, 0x68, htcfg);
	41	}
	42	}
	43
	44
	45	}
	46
	47	static void __init via_bugs(int num, int slot, int func)
dfa4698c	48	{
966396d3	49	#ifdef CONFIG_GART_IOMMU
c987d12f	50	if ((max_pfn > MAX_DMA32_PFN \|\| force_iommu) &&
0440d4c0	51	!gart_iommu_aperture_allowed) {
dfa4698c	52	printk(KERN_INFO
54ef3400 AK	53	"Looks like a VIA chipset. Disabling IOMMU."
54ef3400 AK	54	" Override with iommu=allowed\n");
0440d4c0	55	gart_iommu_aperture_disabled = 1;
dfa4698c AK	56	}
	57	#endif
	58	}
	59
	60	#ifdef CONFIG_ACPI
03d0d20e	61	#ifdef CONFIG_X86_IO_APIC
dfa4698c	62
15a58ed1	63	static int __init nvidia_hpet_check(struct acpi_table_header *header)
dfa4698c	64	{
dfa4698c AK	65	return 0;
dfa4698c AK	66	}
03d0d20e JG	67	#endif /* CONFIG_X86_IO_APIC */
03d0d20e JG	68	#endif /* CONFIG_ACPI */
dfa4698c	69
c6b48324	70	static void __init nvidia_bugs(int num, int slot, int func)
dfa4698c AK	71	{
dfa4698c AK	72	#ifdef CONFIG_ACPI
54ef3400	73	#ifdef CONFIG_X86_IO_APIC
dfa4698c AK	74	/*
	75	* All timer overrides on Nvidia are
	76	* wrong unless HPET is enabled.
fa18f477 AK	77	* Unfortunately that's not true on many Asus boards.
	78	* We don't know yet how to detect this automatically, but
	79	* at least allow a command line override.
dfa4698c	80	*/
fa18f477 AK	81	if (acpi_use_timer_override)
	82	return;
	83
fe699336	84	if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
dfa4698c AK	85	acpi_skip_timer_override = 1;
	86	printk(KERN_INFO "Nvidia board "
	87	"detected. Ignoring ACPI "
	88	"timer override.\n");
fa18f477 AK	89	printk(KERN_INFO "If you got timer trouble "
fa18f477 AK	90	"try acpi_use_timer_override\n");
dfa4698c	91	}
54ef3400	92	#endif
dfa4698c AK	93	#endif
	94	/* RED-PEN skip them on mptables too? */
	95
	96	}
	97
26adcfbf AH	98	#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
26adcfbf AH	99	static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
33fb0e4e AH	100	{
	101	u32 d;
	102	u8 b;
	103
	104	b = read_pci_config_byte(num, slot, func, 0xac);
	105	b &= ~(1<<5);
	106	write_pci_config_byte(num, slot, func, 0xac, b);
	107
	108	d = read_pci_config(num, slot, func, 0x70);
	109	d \|= 1<<8;
	110	write_pci_config(num, slot, func, 0x70, d);
	111
	112	d = read_pci_config(num, slot, func, 0x8);
	113	d &= 0xff;
	114	return d;
	115	}
	116
	117	static void __init ati_bugs(int num, int slot, int func)
	118	{
33fb0e4e AH	119	u32 d;
	120	u8 b;
	121
	122	if (acpi_use_timer_override)
	123	return;
	124
	125	d = ati_ixp4x0_rev(num, slot, func);
	126	if (d < 0x82)
	127	acpi_skip_timer_override = 1;
	128	else {
	129	/* check for IRQ0 interrupt swap */
	130	outb(0x72, 0xcd6); b = inb(0xcd7);
	131	if (!(b & 0x2))
	132	acpi_skip_timer_override = 1;
	133	}
	134
	135	if (acpi_skip_timer_override) {
	136	printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
	137	printk(KERN_INFO "Ignoring ACPI timer override.\n");
	138	printk(KERN_INFO "If you got timer trouble "
	139	"try acpi_use_timer_override\n");
	140	}
33fb0e4e AH	141	}
33fb0e4e AH	142
26adcfbf AH	143	static u32 __init ati_sbx00_rev(int num, int slot, int func)
	144	{
	145	u32 old, d;
	146
	147	d = read_pci_config(num, slot, func, 0x70);
	148	old = d;
	149	d &= ~(1<<8);
	150	write_pci_config(num, slot, func, 0x70, d);
	151	d = read_pci_config(num, slot, func, 0x8);
	152	d &= 0xff;
	153	write_pci_config(num, slot, func, 0x70, old);
	154
	155	return d;
	156	}
	157
	158	static void __init ati_bugs_contd(int num, int slot, int func)
	159	{
	160	u32 d, rev;
	161
	162	if (acpi_use_timer_override)
	163	return;
	164
	165	rev = ati_sbx00_rev(num, slot, func);
	166	if (rev > 0x13)
	167	return;
	168
	169	/* check for IRQ0 interrupt swap */
	170	d = read_pci_config(num, slot, func, 0x64);
	171	if (!(d & (1<<14)))
	172	acpi_skip_timer_override = 1;
	173
	174	if (acpi_skip_timer_override) {
	175	printk(KERN_INFO "SB600 revision 0x%x\n", rev);
	176	printk(KERN_INFO "Ignoring ACPI timer override.\n");
	177	printk(KERN_INFO "If you got timer trouble "
	178	"try acpi_use_timer_override\n");
	179	}
	180	}
	181	#else
	182	static void __init ati_bugs(int num, int slot, int func)
	183	{
	184	}
	185
	186	static void __init ati_bugs_contd(int num, int slot, int func)
	187	{
	188	}
	189	#endif
	190
e51af663 DW	191	#ifdef CONFIG_DMAR
	192	static void __init intel_g33_dmar(int num, int slot, int func)
	193	{
	194	struct acpi_table_header *dmar_tbl;
	195	acpi_status status;
	196
	197	status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
	198	if (ACPI_SUCCESS(status)) {
	199	printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n");
	200	dmar_disabled = 1;
	201	}
	202	}
	203	#endif
	204
c6b48324 NH	205	#define QFLAG_APPLY_ONCE 0x1
	206	#define QFLAG_APPLIED 0x2
	207	#define QFLAG_DONE (QFLAG_APPLY_ONCE\|QFLAG_APPLIED)
dfa4698c	208	struct chipset {
c6b48324 NH	209	u32 vendor;
	210	u32 device;
	211	u32 class;
	212	u32 class_mask;
	213	u32 flags;
	214	void (*f)(int num, int slot, int func);
dfa4698c AK	215	};
dfa4698c AK	216
c993c735	217	static struct chipset early_qrk[] __initdata = {
c6b48324 NH	218	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	219	PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
	220	{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
	221	PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
c6b48324 NH	222	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
c6b48324 NH	223	PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
33fb0e4e AH	224	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
33fb0e4e AH	225	PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
26adcfbf AH	226	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
26adcfbf AH	227	PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
e51af663 DW	228	#ifdef CONFIG_DMAR
	229	{ PCI_VENDOR_ID_INTEL, 0x29c0,
	230	PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar },
	231	#endif
dfa4698c AK	232	{}
	233	};
	234
15650a2f JB	235	/**
	236	* check_dev_quirk - apply early quirks to a given PCI device
	237	* @num: bus number
	238	* @slot: slot number
	239	* @func: PCI function
	240	*
	241	* Check the vendor & device ID against the early quirks table.
	242	*
	243	* If the device is single function, let early_quirks() know so we don't
	244	* poke at this device again.
	245	*/
	246	static int __init check_dev_quirk(int num, int slot, int func)
7bcbc78d NH	247	{
	248	u16 class;
	249	u16 vendor;
	250	u16 device;
	251	u8 type;
	252	int i;
	253
	254	class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
	255
	256	if (class == 0xffff)
15650a2f	257	return -1; /* no class, treat as single function */
7bcbc78d NH	258
	259	vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
	260
	261	device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
	262
	263	for (i = 0; early_qrk[i].f != NULL; i++) {
	264	if (((early_qrk[i].vendor == PCI_ANY_ID) \|\|
	265	(early_qrk[i].vendor == vendor)) &&
	266	((early_qrk[i].device == PCI_ANY_ID) \|\|
	267	(early_qrk[i].device == device)) &&
	268	(!((early_qrk[i].class ^ class) &
	269	early_qrk[i].class_mask))) {
	270	if ((early_qrk[i].flags &
	271	QFLAG_DONE) != QFLAG_DONE)
	272	early_qrk[i].f(num, slot, func);
	273	early_qrk[i].flags \|= QFLAG_APPLIED;
	274	}
	275	}
	276
	277	type = read_pci_config_byte(num, slot, func,
	278	PCI_HEADER_TYPE);
	279	if (!(type & 0x80))
15650a2f JB	280	return -1;
	281
	282	return 0;
7bcbc78d NH	283	}
7bcbc78d NH	284
dfa4698c AK	285	void __init early_quirks(void)
	286	{
	287	int num, slot, func;
0637a70a AK	288
	289	if (!early_pci_allowed())
	290	return;
	291
dfa4698c	292	/* Poor man's PCI discovery */
7bcbc78d NH	293	for (num = 0; num < 32; num++)
7bcbc78d NH	294	for (slot = 0; slot < 32; slot++)
15650a2f JB	295	for (func = 0; func < 8; func++) {
	296	/* Only probe function 0 on single fn devices */
	297	if (check_dev_quirk(num, slot, func))
	298	break;
	299	}
dfa4698c	300	}