[net-next-2.6.git] / arch / x86 / kernel / cpu / perf_event_p6.c

#ifdef CONFIG_CPU_SUP_INTEL

/*
 * Not sure about some of these
 */
static const u64 p6_perfmon_event_map[] =
{
  [PERF_COUNT_HW_CPU_CYCLES]		= 0x0079,
  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
  [PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0f2e,
  [PERF_COUNT_HW_CACHE_MISSES]		= 0x012e,
  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,
  [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,
  [PERF_COUNT_HW_BUS_CYCLES]		= 0x0062,
};

static u64 p6_pmu_event_map(int hw_event)
{
	return p6_perfmon_event_map[hw_event];
}

/*
 * Event setting that is specified not to count anything.
 * We use this to effectively disable a counter.
 *
 * L2_RQSTS with 0 MESI unit mask.
 */
#define P6_NOP_EVENT			0x0000002EULL

static u64 p6_pmu_raw_event(u64 hw_event)
{
#define P6_EVNTSEL_EVENT_MASK		0x000000FFULL
#define P6_EVNTSEL_UNIT_MASK		0x0000FF00ULL
#define P6_EVNTSEL_EDGE_MASK		0x00040000ULL
#define P6_EVNTSEL_INV_MASK		0x00800000ULL
#define P6_EVNTSEL_REG_MASK		0xFF000000ULL

#define P6_EVNTSEL_MASK			\
	(P6_EVNTSEL_EVENT_MASK |	\
	 P6_EVNTSEL_UNIT_MASK  |	\
	 P6_EVNTSEL_EDGE_MASK  |	\
	 P6_EVNTSEL_INV_MASK   |	\
	 P6_EVNTSEL_REG_MASK)

	return hw_event & P6_EVNTSEL_MASK;
}

static struct event_constraint p6_event_constraints[] =
{
	INTEL_EVENT_CONSTRAINT(0xc1, 0x1),	/* FLOPS */
	INTEL_EVENT_CONSTRAINT(0x10, 0x1),	/* FP_COMP_OPS_EXE */
	INTEL_EVENT_CONSTRAINT(0x11, 0x1),	/* FP_ASSIST */
	INTEL_EVENT_CONSTRAINT(0x12, 0x2),	/* MUL */
	INTEL_EVENT_CONSTRAINT(0x13, 0x2),	/* DIV */
	INTEL_EVENT_CONSTRAINT(0x14, 0x1),	/* CYCLES_DIV_BUSY */
	EVENT_CONSTRAINT_END
};

static void p6_pmu_disable_all(void)
{
	u64 val;

	/* p6 only has one enable register */
	rdmsrl(MSR_P6_EVNTSEL0, val);
	val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
	wrmsrl(MSR_P6_EVNTSEL0, val);
}

static void p6_pmu_enable_all(int added)
{
	unsigned long val;

	/* p6 only has one enable register */
	rdmsrl(MSR_P6_EVNTSEL0, val);
	val |= ARCH_PERFMON_EVENTSEL_ENABLE;
	wrmsrl(MSR_P6_EVNTSEL0, val);
}

static inline void
p6_pmu_disable_event(struct perf_event *event)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	u64 val = P6_NOP_EVENT;

	if (cpuc->enabled)
		val |= ARCH_PERFMON_EVENTSEL_ENABLE;

	(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
}

static void p6_pmu_enable_event(struct perf_event *event)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	u64 val;

	val = hwc->config;
	if (cpuc->enabled)
		val |= ARCH_PERFMON_EVENTSEL_ENABLE;

	(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
}

static __initconst struct x86_pmu p6_pmu = {
	.name			= "p6",
	.handle_irq		= x86_pmu_handle_irq,
	.disable_all		= p6_pmu_disable_all,
	.enable_all		= p6_pmu_enable_all,
	.enable			= p6_pmu_enable_event,
	.disable		= p6_pmu_disable_event,
	.hw_config		= x86_hw_config,
	.schedule_events	= x86_schedule_events,
	.eventsel		= MSR_P6_EVNTSEL0,
	.perfctr		= MSR_P6_PERFCTR0,
	.event_map		= p6_pmu_event_map,
	.raw_event		= p6_pmu_raw_event,
	.max_events		= ARRAY_SIZE(p6_perfmon_event_map),
	.apic			= 1,
	.max_period		= (1ULL << 31) - 1,
	.version		= 0,
	.num_events		= 2,
	/*
	 * Events have 40 bits implemented. However they are designed such
	 * that bits [32-39] are sign extensions of bit 31. As such the
	 * effective width of a event for P6-like PMU is 32 bits only.
	 *
	 * See IA-32 Intel Architecture Software developer manual Vol 3B
	 */
	.event_bits		= 32,
	.event_mask		= (1ULL << 32) - 1,
	.get_event_constraints	= x86_get_event_constraints,
	.event_constraints	= p6_event_constraints,
};

static __init int p6_pmu_init(void)
{
	switch (boot_cpu_data.x86_model) {
	case 1:
	case 3:  /* Pentium Pro */
	case 5:
	case 6:  /* Pentium II */
	case 7:
	case 8:
	case 11: /* Pentium III */
	case 9:
	case 13:
		/* Pentium M */
		break;
	default:
		pr_cont("unsupported p6 CPU model %d ",
			boot_cpu_data.x86_model);
		return -ENODEV;
	}

	x86_pmu = p6_pmu;

	return 0;
}

#endif /* CONFIG_CPU_SUP_INTEL */
Commit	Line	Data
f22f54f4 PZ	1	#ifdef CONFIG_CPU_SUP_INTEL
	2
	3	/*
	4	* Not sure about some of these
	5	*/
	6	static const u64 p6_perfmon_event_map[] =
	7	{
	8	[PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
	9	[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
	10	[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
	11	[PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
	12	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
	13	[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
	14	[PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
	15	};
	16
	17	static u64 p6_pmu_event_map(int hw_event)
	18	{
	19	return p6_perfmon_event_map[hw_event];
	20	}
	21
	22	/*
	23	* Event setting that is specified not to count anything.
	24	* We use this to effectively disable a counter.
	25	*
	26	* L2_RQSTS with 0 MESI unit mask.
	27	*/
	28	#define P6_NOP_EVENT 0x0000002EULL
	29
	30	static u64 p6_pmu_raw_event(u64 hw_event)
	31	{
	32	#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
	33	#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
	34	#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
	35	#define P6_EVNTSEL_INV_MASK 0x00800000ULL
	36	#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
	37
	38	#define P6_EVNTSEL_MASK \
	39	(P6_EVNTSEL_EVENT_MASK \| \
	40	P6_EVNTSEL_UNIT_MASK \| \
	41	P6_EVNTSEL_EDGE_MASK \| \
	42	P6_EVNTSEL_INV_MASK \| \
	43	P6_EVNTSEL_REG_MASK)
	44
	45	return hw_event & P6_EVNTSEL_MASK;
	46	}
	47
	48	static struct event_constraint p6_event_constraints[] =
	49	{
	50	INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
	51	INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
	52	INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
	53	INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
	54	INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
	55	INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
	56	EVENT_CONSTRAINT_END
	57	};
	58
	59	static void p6_pmu_disable_all(void)
	60	{
	61	u64 val;
	62
	63	/* p6 only has one enable register */
	64	rdmsrl(MSR_P6_EVNTSEL0, val);
bb1165d6	65	val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4 PZ	66	wrmsrl(MSR_P6_EVNTSEL0, val);
	67	}
	68
11164cd4	69	static void p6_pmu_enable_all(int added)
f22f54f4 PZ	70	{
	71	unsigned long val;
	72
	73	/* p6 only has one enable register */
	74	rdmsrl(MSR_P6_EVNTSEL0, val);
bb1165d6	75	val \|= ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4 PZ	76	wrmsrl(MSR_P6_EVNTSEL0, val);
	77	}
	78
	79	static inline void
aff3d91a	80	p6_pmu_disable_event(struct perf_event *event)
f22f54f4 PZ	81	{
f22f54f4 PZ	82	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a	83	struct hw_perf_event *hwc = &event->hw;
f22f54f4 PZ	84	u64 val = P6_NOP_EVENT;
	85
	86	if (cpuc->enabled)
bb1165d6	87	val \|= ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4	88
aff3d91a	89	(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
f22f54f4 PZ	90	}
f22f54f4 PZ	91
aff3d91a	92	static void p6_pmu_enable_event(struct perf_event *event)
f22f54f4 PZ	93	{
f22f54f4 PZ	94	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a	95	struct hw_perf_event *hwc = &event->hw;
f22f54f4 PZ	96	u64 val;
	97
	98	val = hwc->config;
	99	if (cpuc->enabled)
bb1165d6	100	val \|= ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4	101
aff3d91a	102	(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
f22f54f4 PZ	103	}
	104
	105	static __initconst struct x86_pmu p6_pmu = {
	106	.name = "p6",
	107	.handle_irq = x86_pmu_handle_irq,
	108	.disable_all = p6_pmu_disable_all,
	109	.enable_all = p6_pmu_enable_all,
	110	.enable = p6_pmu_enable_event,
	111	.disable = p6_pmu_disable_event,
a072738e CG	112	.hw_config = x86_hw_config,
a072738e CG	113	.schedule_events = x86_schedule_events,
f22f54f4 PZ	114	.eventsel = MSR_P6_EVNTSEL0,
	115	.perfctr = MSR_P6_PERFCTR0,
	116	.event_map = p6_pmu_event_map,
	117	.raw_event = p6_pmu_raw_event,
	118	.max_events = ARRAY_SIZE(p6_perfmon_event_map),
	119	.apic = 1,
	120	.max_period = (1ULL << 31) - 1,
	121	.version = 0,
	122	.num_events = 2,
	123	/*
	124	* Events have 40 bits implemented. However they are designed such
	125	* that bits [32-39] are sign extensions of bit 31. As such the
	126	* effective width of a event for P6-like PMU is 32 bits only.
	127	*
	128	* See IA-32 Intel Architecture Software developer manual Vol 3B
	129	*/
	130	.event_bits = 32,
	131	.event_mask = (1ULL << 32) - 1,
	132	.get_event_constraints = x86_get_event_constraints,
	133	.event_constraints = p6_event_constraints,
	134	};
	135
	136	static __init int p6_pmu_init(void)
	137	{
	138	switch (boot_cpu_data.x86_model) {
	139	case 1:
	140	case 3: /* Pentium Pro */
	141	case 5:
	142	case 6: /* Pentium II */
	143	case 7:
	144	case 8:
	145	case 11: /* Pentium III */
	146	case 9:
	147	case 13:
	148	/* Pentium M */
	149	break;
	150	default:
	151	pr_cont("unsupported p6 CPU model %d ",
	152	boot_cpu_data.x86_model);
	153	return -ENODEV;
	154	}
	155
	156	x86_pmu = p6_pmu;
	157
	158	return 0;
	159	}
	160
	161	#endif /* CONFIG_CPU_SUP_INTEL */