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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
52 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
53 | unsigned long size, len = 0; | |
54 | struct page *page; | |
55 | void *map; | |
56 | int ret; | |
57 | ||
58 | do { | |
59 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
60 | if (!ret) | |
61 | break; | |
62 | ||
63 | offset = addr & (PAGE_SIZE - 1); | |
64 | size = min(PAGE_SIZE - offset, n - len); | |
65 | ||
66 | map = kmap_atomic(page, type); | |
67 | memcpy(to, map+offset, size); | |
68 | kunmap_atomic(map, type); | |
69 | put_page(page); | |
70 | ||
71 | len += size; | |
72 | to += size; | |
73 | addr += size; | |
74 | ||
75 | } while (len < n); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
caff2bef PZ |
97 | #define MAX_LBR_ENTRIES 16 |
98 | ||
cdd6c482 | 99 | struct cpu_hw_events { |
ca037701 PZ |
100 | /* |
101 | * Generic x86 PMC bits | |
102 | */ | |
1da53e02 | 103 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 104 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 105 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 106 | int enabled; |
241771ef | 107 | |
1da53e02 SE |
108 | int n_events; |
109 | int n_added; | |
90151c35 | 110 | int n_txn; |
1da53e02 | 111 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 112 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 113 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 114 | |
4d1c52b0 LM |
115 | unsigned int group_flag; |
116 | ||
ca037701 PZ |
117 | /* |
118 | * Intel DebugStore bits | |
119 | */ | |
120 | struct debug_store *ds; | |
121 | u64 pebs_enabled; | |
122 | ||
caff2bef PZ |
123 | /* |
124 | * Intel LBR bits | |
125 | */ | |
126 | int lbr_users; | |
127 | void *lbr_context; | |
128 | struct perf_branch_stack lbr_stack; | |
129 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
130 | ||
ca037701 PZ |
131 | /* |
132 | * AMD specific bits | |
133 | */ | |
38331f62 | 134 | struct amd_nb *amd_nb; |
b690081d SE |
135 | }; |
136 | ||
fce877e3 | 137 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 138 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
139 | .code = (c), \ |
140 | .cmask = (m), \ | |
fce877e3 | 141 | .weight = (w), \ |
c91e0f5d | 142 | } |
b690081d | 143 | |
fce877e3 PZ |
144 | #define EVENT_CONSTRAINT(c, n, m) \ |
145 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
146 | ||
ca037701 PZ |
147 | /* |
148 | * Constraint on the Event code. | |
149 | */ | |
ed8777fc | 150 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 151 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 152 | |
ca037701 PZ |
153 | /* |
154 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
155 | * |
156 | * filter mask to validate fixed counter events. | |
157 | * the following filters disqualify for fixed counters: | |
158 | * - inv | |
159 | * - edge | |
160 | * - cnt-mask | |
161 | * The other filters are supported by fixed counters. | |
162 | * The any-thread option is supported starting with v3. | |
ca037701 | 163 | */ |
ed8777fc | 164 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 165 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 166 | |
ca037701 PZ |
167 | /* |
168 | * Constraint on the Event code + UMask | |
169 | */ | |
170 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
171 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
172 | ||
ed8777fc PZ |
173 | #define EVENT_CONSTRAINT_END \ |
174 | EVENT_CONSTRAINT(0, 0, 0) | |
175 | ||
176 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 177 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 178 | |
8db909a7 PZ |
179 | union perf_capabilities { |
180 | struct { | |
181 | u64 lbr_format : 6; | |
182 | u64 pebs_trap : 1; | |
183 | u64 pebs_arch_reg : 1; | |
184 | u64 pebs_format : 4; | |
185 | u64 smm_freeze : 1; | |
186 | }; | |
187 | u64 capabilities; | |
188 | }; | |
189 | ||
241771ef | 190 | /* |
5f4ec28f | 191 | * struct x86_pmu - generic x86 pmu |
241771ef | 192 | */ |
5f4ec28f | 193 | struct x86_pmu { |
ca037701 PZ |
194 | /* |
195 | * Generic x86 PMC bits | |
196 | */ | |
faa28ae0 RR |
197 | const char *name; |
198 | int version; | |
a3288106 | 199 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 200 | void (*disable_all)(void); |
11164cd4 | 201 | void (*enable_all)(int added); |
aff3d91a PZ |
202 | void (*enable)(struct perf_event *); |
203 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 204 | int (*hw_config)(struct perf_event *event); |
a072738e | 205 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
206 | unsigned eventsel; |
207 | unsigned perfctr; | |
b0f3f28e | 208 | u64 (*event_map)(int); |
169e41eb | 209 | int max_events; |
948b1bb8 RR |
210 | int num_counters; |
211 | int num_counters_fixed; | |
212 | int cntval_bits; | |
213 | u64 cntval_mask; | |
04da8a43 | 214 | int apic; |
c619b8ff | 215 | u64 max_period; |
63b14649 PZ |
216 | struct event_constraint * |
217 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
218 | struct perf_event *event); | |
219 | ||
c91e0f5d PZ |
220 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
221 | struct perf_event *event); | |
63b14649 | 222 | struct event_constraint *event_constraints; |
3c44780b | 223 | void (*quirks)(void); |
68aa00ac | 224 | int perfctr_second_write; |
3f6da390 | 225 | |
b38b24ea | 226 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
227 | void (*cpu_starting)(int cpu); |
228 | void (*cpu_dying)(int cpu); | |
229 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
230 | |
231 | /* | |
232 | * Intel Arch Perfmon v2+ | |
233 | */ | |
8db909a7 PZ |
234 | u64 intel_ctrl; |
235 | union perf_capabilities intel_cap; | |
ca037701 PZ |
236 | |
237 | /* | |
238 | * Intel DebugStore bits | |
239 | */ | |
240 | int bts, pebs; | |
241 | int pebs_record_size; | |
242 | void (*drain_pebs)(struct pt_regs *regs); | |
243 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
244 | |
245 | /* | |
246 | * Intel LBR | |
247 | */ | |
248 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
249 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
250 | }; |
251 | ||
4a06bd85 | 252 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 253 | |
cdd6c482 | 254 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
255 | .enabled = 1, |
256 | }; | |
241771ef | 257 | |
07088edb | 258 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 259 | |
8326f44d | 260 | /* |
dfc65094 | 261 | * Generalized hw caching related hw_event table, filled |
8326f44d | 262 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
263 | * 'not supported', -1 means 'hw_event makes no sense on |
264 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
265 | * ID. |
266 | */ | |
267 | ||
268 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
269 | ||
270 | static u64 __read_mostly hw_cache_event_ids | |
271 | [PERF_COUNT_HW_CACHE_MAX] | |
272 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
273 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
274 | ||
ee06094f | 275 | /* |
cdd6c482 IM |
276 | * Propagate event elapsed time into the generic event. |
277 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
278 | * Returns the delta events processed. |
279 | */ | |
4b7bfd0d | 280 | static u64 |
cc2ad4ba | 281 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 282 | { |
cc2ad4ba | 283 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 284 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 285 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 286 | int idx = hwc->idx; |
ec3232bd | 287 | s64 delta; |
ee06094f | 288 | |
30dd568c MM |
289 | if (idx == X86_PMC_IDX_FIXED_BTS) |
290 | return 0; | |
291 | ||
ee06094f | 292 | /* |
cdd6c482 | 293 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
294 | * |
295 | * Our tactic to handle this is to first atomically read and | |
296 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 297 | * count to the generic event atomically: |
ee06094f IM |
298 | */ |
299 | again: | |
e7850595 | 300 | prev_raw_count = local64_read(&hwc->prev_count); |
cdd6c482 | 301 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f | 302 | |
e7850595 | 303 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
304 | new_raw_count) != prev_raw_count) |
305 | goto again; | |
306 | ||
307 | /* | |
308 | * Now we have the new raw value and have updated the prev | |
309 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 310 | * (event-)time and add that to the generic event. |
ee06094f IM |
311 | * |
312 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 313 | * of the count. |
ee06094f | 314 | */ |
ec3232bd PZ |
315 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
316 | delta >>= shift; | |
ee06094f | 317 | |
e7850595 PZ |
318 | local64_add(delta, &event->count); |
319 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
320 | |
321 | return new_raw_count; | |
ee06094f IM |
322 | } |
323 | ||
cdd6c482 | 324 | static atomic_t active_events; |
4e935e47 PZ |
325 | static DEFINE_MUTEX(pmc_reserve_mutex); |
326 | ||
b27ea29c RR |
327 | #ifdef CONFIG_X86_LOCAL_APIC |
328 | ||
4e935e47 PZ |
329 | static bool reserve_pmc_hardware(void) |
330 | { | |
331 | int i; | |
332 | ||
333 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
334 | disable_lapic_nmi_watchdog(); | |
335 | ||
948b1bb8 | 336 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 337 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
338 | goto perfctr_fail; |
339 | } | |
340 | ||
948b1bb8 | 341 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 342 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
343 | goto eventsel_fail; |
344 | } | |
345 | ||
346 | return true; | |
347 | ||
348 | eventsel_fail: | |
349 | for (i--; i >= 0; i--) | |
4a06bd85 | 350 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 351 | |
948b1bb8 | 352 | i = x86_pmu.num_counters; |
4e935e47 PZ |
353 | |
354 | perfctr_fail: | |
355 | for (i--; i >= 0; i--) | |
4a06bd85 | 356 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
357 | |
358 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
359 | enable_lapic_nmi_watchdog(); | |
360 | ||
361 | return false; | |
362 | } | |
363 | ||
364 | static void release_pmc_hardware(void) | |
365 | { | |
366 | int i; | |
367 | ||
948b1bb8 | 368 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
369 | release_perfctr_nmi(x86_pmu.perfctr + i); |
370 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
371 | } |
372 | ||
373 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
374 | enable_lapic_nmi_watchdog(); | |
375 | } | |
376 | ||
b27ea29c RR |
377 | #else |
378 | ||
379 | static bool reserve_pmc_hardware(void) { return true; } | |
380 | static void release_pmc_hardware(void) {} | |
381 | ||
382 | #endif | |
383 | ||
ca037701 PZ |
384 | static int reserve_ds_buffers(void); |
385 | static void release_ds_buffers(void); | |
30dd568c | 386 | |
cdd6c482 | 387 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 388 | { |
cdd6c482 | 389 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 390 | release_pmc_hardware(); |
ca037701 | 391 | release_ds_buffers(); |
4e935e47 PZ |
392 | mutex_unlock(&pmc_reserve_mutex); |
393 | } | |
394 | } | |
395 | ||
85cf9dba RR |
396 | static inline int x86_pmu_initialized(void) |
397 | { | |
398 | return x86_pmu.handle_irq != NULL; | |
399 | } | |
400 | ||
8326f44d | 401 | static inline int |
cdd6c482 | 402 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
403 | { |
404 | unsigned int cache_type, cache_op, cache_result; | |
405 | u64 config, val; | |
406 | ||
407 | config = attr->config; | |
408 | ||
409 | cache_type = (config >> 0) & 0xff; | |
410 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
411 | return -EINVAL; | |
412 | ||
413 | cache_op = (config >> 8) & 0xff; | |
414 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
415 | return -EINVAL; | |
416 | ||
417 | cache_result = (config >> 16) & 0xff; | |
418 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
419 | return -EINVAL; | |
420 | ||
421 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
422 | ||
423 | if (val == 0) | |
424 | return -ENOENT; | |
425 | ||
426 | if (val == -1) | |
427 | return -EINVAL; | |
428 | ||
429 | hwc->config |= val; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
c1726f34 RR |
434 | static int x86_setup_perfctr(struct perf_event *event) |
435 | { | |
436 | struct perf_event_attr *attr = &event->attr; | |
437 | struct hw_perf_event *hwc = &event->hw; | |
438 | u64 config; | |
439 | ||
440 | if (!hwc->sample_period) { | |
441 | hwc->sample_period = x86_pmu.max_period; | |
442 | hwc->last_period = hwc->sample_period; | |
e7850595 | 443 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
444 | } else { |
445 | /* | |
446 | * If we have a PMU initialized but no APIC | |
447 | * interrupts, we cannot sample hardware | |
448 | * events (user-space has to fall back and | |
449 | * sample via a hrtimer based software event): | |
450 | */ | |
451 | if (!x86_pmu.apic) | |
452 | return -EOPNOTSUPP; | |
453 | } | |
454 | ||
455 | if (attr->type == PERF_TYPE_RAW) | |
456 | return 0; | |
457 | ||
458 | if (attr->type == PERF_TYPE_HW_CACHE) | |
459 | return set_ext_hw_attr(hwc, attr); | |
460 | ||
461 | if (attr->config >= x86_pmu.max_events) | |
462 | return -EINVAL; | |
463 | ||
464 | /* | |
465 | * The generic map: | |
466 | */ | |
467 | config = x86_pmu.event_map(attr->config); | |
468 | ||
469 | if (config == 0) | |
470 | return -ENOENT; | |
471 | ||
472 | if (config == -1LL) | |
473 | return -EINVAL; | |
474 | ||
475 | /* | |
476 | * Branch tracing: | |
477 | */ | |
478 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
479 | (hwc->sample_period == 1)) { | |
480 | /* BTS is not supported by this architecture. */ | |
481 | if (!x86_pmu.bts) | |
482 | return -EOPNOTSUPP; | |
483 | ||
484 | /* BTS is currently only allowed for user-mode. */ | |
485 | if (!attr->exclude_kernel) | |
486 | return -EOPNOTSUPP; | |
487 | } | |
488 | ||
489 | hwc->config |= config; | |
490 | ||
491 | return 0; | |
492 | } | |
4261e0e0 | 493 | |
b4cdc5c2 | 494 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 495 | { |
ab608344 PZ |
496 | if (event->attr.precise_ip) { |
497 | int precise = 0; | |
498 | ||
499 | /* Support for constant skid */ | |
500 | if (x86_pmu.pebs) | |
501 | precise++; | |
502 | ||
503 | /* Support for IP fixup */ | |
504 | if (x86_pmu.lbr_nr) | |
505 | precise++; | |
506 | ||
507 | if (event->attr.precise_ip > precise) | |
508 | return -EOPNOTSUPP; | |
509 | } | |
510 | ||
a072738e CG |
511 | /* |
512 | * Generate PMC IRQs: | |
513 | * (keep 'enabled' bit clear for now) | |
514 | */ | |
b4cdc5c2 | 515 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
516 | |
517 | /* | |
518 | * Count user and OS events unless requested not to | |
519 | */ | |
b4cdc5c2 PZ |
520 | if (!event->attr.exclude_user) |
521 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
522 | if (!event->attr.exclude_kernel) | |
523 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 524 | |
b4cdc5c2 PZ |
525 | if (event->attr.type == PERF_TYPE_RAW) |
526 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 527 | |
9d0fcba6 | 528 | return x86_setup_perfctr(event); |
a098f448 RR |
529 | } |
530 | ||
241771ef | 531 | /* |
0d48696f | 532 | * Setup the hardware configuration for a given attr_type |
241771ef | 533 | */ |
cdd6c482 | 534 | static int __hw_perf_event_init(struct perf_event *event) |
241771ef | 535 | { |
4e935e47 | 536 | int err; |
241771ef | 537 | |
85cf9dba RR |
538 | if (!x86_pmu_initialized()) |
539 | return -ENODEV; | |
241771ef | 540 | |
4e935e47 | 541 | err = 0; |
cdd6c482 | 542 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 543 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 544 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
545 | if (!reserve_pmc_hardware()) |
546 | err = -EBUSY; | |
4b24a88b | 547 | else { |
ca037701 | 548 | err = reserve_ds_buffers(); |
4b24a88b SE |
549 | if (err) |
550 | release_pmc_hardware(); | |
551 | } | |
30dd568c MM |
552 | } |
553 | if (!err) | |
cdd6c482 | 554 | atomic_inc(&active_events); |
4e935e47 PZ |
555 | mutex_unlock(&pmc_reserve_mutex); |
556 | } | |
557 | if (err) | |
558 | return err; | |
559 | ||
cdd6c482 | 560 | event->destroy = hw_perf_event_destroy; |
a1792cda | 561 | |
4261e0e0 RR |
562 | event->hw.idx = -1; |
563 | event->hw.last_cpu = -1; | |
564 | event->hw.last_tag = ~0ULL; | |
b690081d | 565 | |
9d0fcba6 | 566 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
567 | } |
568 | ||
8c48e444 | 569 | static void x86_pmu_disable_all(void) |
f87ad35d | 570 | { |
cdd6c482 | 571 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
572 | int idx; |
573 | ||
948b1bb8 | 574 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
575 | u64 val; |
576 | ||
43f6201a | 577 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 578 | continue; |
8c48e444 | 579 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 580 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 581 | continue; |
bb1165d6 | 582 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 583 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 584 | } |
f87ad35d JSR |
585 | } |
586 | ||
9e35ad38 | 587 | void hw_perf_disable(void) |
b56a3802 | 588 | { |
1da53e02 SE |
589 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
590 | ||
85cf9dba | 591 | if (!x86_pmu_initialized()) |
9e35ad38 | 592 | return; |
1da53e02 | 593 | |
1a6e21f7 PZ |
594 | if (!cpuc->enabled) |
595 | return; | |
596 | ||
597 | cpuc->n_added = 0; | |
598 | cpuc->enabled = 0; | |
599 | barrier(); | |
1da53e02 SE |
600 | |
601 | x86_pmu.disable_all(); | |
b56a3802 | 602 | } |
241771ef | 603 | |
11164cd4 | 604 | static void x86_pmu_enable_all(int added) |
f87ad35d | 605 | { |
cdd6c482 | 606 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
607 | int idx; |
608 | ||
948b1bb8 | 609 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 610 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 611 | u64 val; |
b0f3f28e | 612 | |
43f6201a | 613 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 614 | continue; |
984b838c | 615 | |
cdd6c482 | 616 | val = event->hw.config; |
bb1165d6 | 617 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 618 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
619 | } |
620 | } | |
621 | ||
1da53e02 SE |
622 | static const struct pmu pmu; |
623 | ||
624 | static inline int is_x86_event(struct perf_event *event) | |
625 | { | |
626 | return event->pmu == &pmu; | |
627 | } | |
628 | ||
629 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
630 | { | |
63b14649 | 631 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 632 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 633 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
634 | struct hw_perf_event *hwc; |
635 | ||
636 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
637 | ||
638 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
639 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
640 | constraints[i] = c; | |
1da53e02 SE |
641 | } |
642 | ||
8113070d SE |
643 | /* |
644 | * fastpath, try to reuse previous register | |
645 | */ | |
c933c1a6 | 646 | for (i = 0; i < n; i++) { |
8113070d | 647 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 648 | c = constraints[i]; |
8113070d SE |
649 | |
650 | /* never assigned */ | |
651 | if (hwc->idx == -1) | |
652 | break; | |
653 | ||
654 | /* constraint still honored */ | |
63b14649 | 655 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
656 | break; |
657 | ||
658 | /* not already used */ | |
659 | if (test_bit(hwc->idx, used_mask)) | |
660 | break; | |
661 | ||
34538ee7 | 662 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
663 | if (assign) |
664 | assign[i] = hwc->idx; | |
665 | } | |
c933c1a6 | 666 | if (i == n) |
8113070d SE |
667 | goto done; |
668 | ||
669 | /* | |
670 | * begin slow path | |
671 | */ | |
672 | ||
673 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
674 | ||
1da53e02 SE |
675 | /* |
676 | * weight = number of possible counters | |
677 | * | |
678 | * 1 = most constrained, only works on one counter | |
679 | * wmax = least constrained, works on any counter | |
680 | * | |
681 | * assign events to counters starting with most | |
682 | * constrained events. | |
683 | */ | |
948b1bb8 | 684 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
685 | |
686 | /* | |
687 | * when fixed event counters are present, | |
688 | * wmax is incremented by 1 to account | |
689 | * for one more choice | |
690 | */ | |
948b1bb8 | 691 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
692 | wmax++; |
693 | ||
8113070d | 694 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 695 | /* for each event */ |
8113070d | 696 | for (i = 0; num && i < n; i++) { |
81269a08 | 697 | c = constraints[i]; |
1da53e02 SE |
698 | hwc = &cpuc->event_list[i]->hw; |
699 | ||
272d30be | 700 | if (c->weight != w) |
1da53e02 SE |
701 | continue; |
702 | ||
984b3f57 | 703 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
704 | if (!test_bit(j, used_mask)) |
705 | break; | |
706 | } | |
707 | ||
708 | if (j == X86_PMC_IDX_MAX) | |
709 | break; | |
1da53e02 | 710 | |
34538ee7 | 711 | __set_bit(j, used_mask); |
8113070d | 712 | |
1da53e02 SE |
713 | if (assign) |
714 | assign[i] = j; | |
715 | num--; | |
716 | } | |
717 | } | |
8113070d | 718 | done: |
1da53e02 SE |
719 | /* |
720 | * scheduling failed or is just a simulation, | |
721 | * free resources if necessary | |
722 | */ | |
723 | if (!assign || num) { | |
724 | for (i = 0; i < n; i++) { | |
725 | if (x86_pmu.put_event_constraints) | |
726 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
727 | } | |
728 | } | |
729 | return num ? -ENOSPC : 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * dogrp: true if must collect siblings events (group) | |
734 | * returns total number of events and error code | |
735 | */ | |
736 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
737 | { | |
738 | struct perf_event *event; | |
739 | int n, max_count; | |
740 | ||
948b1bb8 | 741 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
742 | |
743 | /* current number of events already accepted */ | |
744 | n = cpuc->n_events; | |
745 | ||
746 | if (is_x86_event(leader)) { | |
747 | if (n >= max_count) | |
748 | return -ENOSPC; | |
749 | cpuc->event_list[n] = leader; | |
750 | n++; | |
751 | } | |
752 | if (!dogrp) | |
753 | return n; | |
754 | ||
755 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
756 | if (!is_x86_event(event) || | |
8113070d | 757 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
758 | continue; |
759 | ||
760 | if (n >= max_count) | |
761 | return -ENOSPC; | |
762 | ||
763 | cpuc->event_list[n] = event; | |
764 | n++; | |
765 | } | |
766 | return n; | |
767 | } | |
768 | ||
1da53e02 | 769 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 770 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 771 | { |
447a194b SE |
772 | struct hw_perf_event *hwc = &event->hw; |
773 | ||
774 | hwc->idx = cpuc->assign[i]; | |
775 | hwc->last_cpu = smp_processor_id(); | |
776 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
777 | |
778 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
779 | hwc->config_base = 0; | |
780 | hwc->event_base = 0; | |
781 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
782 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
783 | /* | |
784 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
785 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
786 | */ | |
787 | hwc->event_base = | |
788 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
789 | } else { | |
790 | hwc->config_base = x86_pmu.eventsel; | |
791 | hwc->event_base = x86_pmu.perfctr; | |
792 | } | |
793 | } | |
794 | ||
447a194b SE |
795 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
796 | struct cpu_hw_events *cpuc, | |
797 | int i) | |
798 | { | |
799 | return hwc->idx == cpuc->assign[i] && | |
800 | hwc->last_cpu == smp_processor_id() && | |
801 | hwc->last_tag == cpuc->tags[i]; | |
802 | } | |
803 | ||
c08053e6 | 804 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 805 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 806 | |
9e35ad38 | 807 | void hw_perf_enable(void) |
ee06094f | 808 | { |
1da53e02 SE |
809 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
810 | struct perf_event *event; | |
811 | struct hw_perf_event *hwc; | |
11164cd4 | 812 | int i, added = cpuc->n_added; |
1da53e02 | 813 | |
85cf9dba | 814 | if (!x86_pmu_initialized()) |
2b9ff0db | 815 | return; |
1a6e21f7 PZ |
816 | |
817 | if (cpuc->enabled) | |
818 | return; | |
819 | ||
1da53e02 | 820 | if (cpuc->n_added) { |
19925ce7 | 821 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
822 | /* |
823 | * apply assignment obtained either from | |
824 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
825 | * | |
826 | * step1: save events moving to new counters | |
827 | * step2: reprogram moved events into new counters | |
828 | */ | |
19925ce7 | 829 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
830 | event = cpuc->event_list[i]; |
831 | hwc = &event->hw; | |
832 | ||
447a194b SE |
833 | /* |
834 | * we can avoid reprogramming counter if: | |
835 | * - assigned same counter as last time | |
836 | * - running on same CPU as last time | |
837 | * - no other event has used the counter since | |
838 | */ | |
839 | if (hwc->idx == -1 || | |
840 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
841 | continue; |
842 | ||
d76a0812 | 843 | x86_pmu_stop(event); |
1da53e02 SE |
844 | } |
845 | ||
846 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
847 | event = cpuc->event_list[i]; |
848 | hwc = &event->hw; | |
849 | ||
45e16a68 | 850 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 851 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
852 | else if (i < n_running) |
853 | continue; | |
1da53e02 | 854 | |
c08053e6 | 855 | x86_pmu_start(event); |
1da53e02 SE |
856 | } |
857 | cpuc->n_added = 0; | |
858 | perf_events_lapic_init(); | |
859 | } | |
1a6e21f7 PZ |
860 | |
861 | cpuc->enabled = 1; | |
862 | barrier(); | |
863 | ||
11164cd4 | 864 | x86_pmu.enable_all(added); |
ee06094f | 865 | } |
ee06094f | 866 | |
31fa58af RR |
867 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
868 | u64 enable_mask) | |
b0f3f28e | 869 | { |
31fa58af | 870 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
b0f3f28e PZ |
871 | } |
872 | ||
aff3d91a | 873 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 874 | { |
aff3d91a | 875 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
876 | |
877 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
878 | } |
879 | ||
245b2e70 | 880 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 881 | |
ee06094f IM |
882 | /* |
883 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 884 | * To be called with the event disabled in hw: |
ee06094f | 885 | */ |
e4abb5d4 | 886 | static int |
07088edb | 887 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 888 | { |
07088edb | 889 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 890 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 891 | s64 period = hwc->sample_period; |
7645a24c | 892 | int ret = 0, idx = hwc->idx; |
ee06094f | 893 | |
30dd568c MM |
894 | if (idx == X86_PMC_IDX_FIXED_BTS) |
895 | return 0; | |
896 | ||
ee06094f | 897 | /* |
af901ca1 | 898 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
899 | */ |
900 | if (unlikely(left <= -period)) { | |
901 | left = period; | |
e7850595 | 902 | local64_set(&hwc->period_left, left); |
9e350de3 | 903 | hwc->last_period = period; |
e4abb5d4 | 904 | ret = 1; |
ee06094f IM |
905 | } |
906 | ||
907 | if (unlikely(left <= 0)) { | |
908 | left += period; | |
e7850595 | 909 | local64_set(&hwc->period_left, left); |
9e350de3 | 910 | hwc->last_period = period; |
e4abb5d4 | 911 | ret = 1; |
ee06094f | 912 | } |
1c80f4b5 | 913 | /* |
dfc65094 | 914 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
915 | */ |
916 | if (unlikely(left < 2)) | |
917 | left = 2; | |
241771ef | 918 | |
e4abb5d4 PZ |
919 | if (left > x86_pmu.max_period) |
920 | left = x86_pmu.max_period; | |
921 | ||
245b2e70 | 922 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
923 | |
924 | /* | |
cdd6c482 | 925 | * The hw event starts counting from this event offset, |
ee06094f IM |
926 | * mark it to be able to extra future deltas: |
927 | */ | |
e7850595 | 928 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 929 | |
68aa00ac CG |
930 | wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); |
931 | ||
932 | /* | |
933 | * Due to erratum on certan cpu we need | |
934 | * a second write to be sure the register | |
935 | * is updated properly | |
936 | */ | |
937 | if (x86_pmu.perfctr_second_write) { | |
938 | wrmsrl(hwc->event_base + idx, | |
948b1bb8 | 939 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 940 | } |
e4abb5d4 | 941 | |
cdd6c482 | 942 | perf_event_update_userpage(event); |
194002b2 | 943 | |
e4abb5d4 | 944 | return ret; |
2f18d1e8 IM |
945 | } |
946 | ||
aff3d91a | 947 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 948 | { |
cdd6c482 | 949 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 950 | if (cpuc->enabled) |
31fa58af RR |
951 | __x86_pmu_enable_event(&event->hw, |
952 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
953 | } |
954 | ||
b690081d | 955 | /* |
1da53e02 SE |
956 | * activate a single event |
957 | * | |
958 | * The event is added to the group of enabled events | |
959 | * but only if it can be scehduled with existing events. | |
960 | * | |
961 | * Called with PMU disabled. If successful and return value 1, | |
962 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
963 | */ |
964 | static int x86_pmu_enable(struct perf_event *event) | |
965 | { | |
966 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
967 | struct hw_perf_event *hwc; |
968 | int assign[X86_PMC_IDX_MAX]; | |
969 | int n, n0, ret; | |
fe9081cc | 970 | |
1da53e02 | 971 | hwc = &event->hw; |
fe9081cc | 972 | |
1da53e02 SE |
973 | n0 = cpuc->n_events; |
974 | n = collect_events(cpuc, event, false); | |
975 | if (n < 0) | |
976 | return n; | |
53b441a5 | 977 | |
4d1c52b0 LM |
978 | /* |
979 | * If group events scheduling transaction was started, | |
980 | * skip the schedulability test here, it will be peformed | |
981 | * at commit time(->commit_txn) as a whole | |
982 | */ | |
8d2cacbb | 983 | if (cpuc->group_flag & PERF_EVENT_TXN) |
4d1c52b0 LM |
984 | goto out; |
985 | ||
a072738e | 986 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 SE |
987 | if (ret) |
988 | return ret; | |
989 | /* | |
990 | * copy new assignment, now we know it is possible | |
991 | * will be used by hw_perf_enable() | |
992 | */ | |
993 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 994 | |
4d1c52b0 | 995 | out: |
1da53e02 | 996 | cpuc->n_events = n; |
356e1f2e | 997 | cpuc->n_added += n - n0; |
90151c35 | 998 | cpuc->n_txn += n - n0; |
95cdd2e7 IM |
999 | |
1000 | return 0; | |
241771ef IM |
1001 | } |
1002 | ||
d76a0812 SE |
1003 | static int x86_pmu_start(struct perf_event *event) |
1004 | { | |
c08053e6 PZ |
1005 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1006 | int idx = event->hw.idx; | |
1007 | ||
1008 | if (idx == -1) | |
d76a0812 SE |
1009 | return -EAGAIN; |
1010 | ||
07088edb | 1011 | x86_perf_event_set_period(event); |
c08053e6 PZ |
1012 | cpuc->events[idx] = event; |
1013 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1014 | __set_bit(idx, cpuc->running); |
aff3d91a | 1015 | x86_pmu.enable(event); |
c08053e6 | 1016 | perf_event_update_userpage(event); |
d76a0812 SE |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
cdd6c482 | 1021 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 1022 | { |
71e2d282 PZ |
1023 | int ret = x86_pmu_start(event); |
1024 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
1025 | } |
1026 | ||
cdd6c482 | 1027 | void perf_event_print_debug(void) |
241771ef | 1028 | { |
2f18d1e8 | 1029 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1030 | u64 pebs; |
cdd6c482 | 1031 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1032 | unsigned long flags; |
1e125676 IM |
1033 | int cpu, idx; |
1034 | ||
948b1bb8 | 1035 | if (!x86_pmu.num_counters) |
1e125676 | 1036 | return; |
241771ef | 1037 | |
5bb9efe3 | 1038 | local_irq_save(flags); |
241771ef IM |
1039 | |
1040 | cpu = smp_processor_id(); | |
cdd6c482 | 1041 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1042 | |
faa28ae0 | 1043 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1044 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1045 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1046 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1047 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1048 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1049 | |
1050 | pr_info("\n"); | |
1051 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1052 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1053 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1054 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1055 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1056 | } |
7645a24c | 1057 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1058 | |
948b1bb8 | 1059 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1060 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1061 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1062 | |
245b2e70 | 1063 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1064 | |
a1ef58f4 | 1065 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1066 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1067 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1068 | cpu, idx, pmc_count); |
a1ef58f4 | 1069 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1070 | cpu, idx, prev_left); |
241771ef | 1071 | } |
948b1bb8 | 1072 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1073 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1074 | ||
a1ef58f4 | 1075 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1076 | cpu, idx, pmc_count); |
1077 | } | |
5bb9efe3 | 1078 | local_irq_restore(flags); |
241771ef IM |
1079 | } |
1080 | ||
d76a0812 | 1081 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1082 | { |
d76a0812 | 1083 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1084 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1085 | int idx = hwc->idx; |
241771ef | 1086 | |
71e2d282 PZ |
1087 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1088 | return; | |
1089 | ||
aff3d91a | 1090 | x86_pmu.disable(event); |
241771ef | 1091 | |
ee06094f | 1092 | /* |
cdd6c482 | 1093 | * Drain the remaining delta count out of a event |
ee06094f IM |
1094 | * that we are disabling: |
1095 | */ | |
cc2ad4ba | 1096 | x86_perf_event_update(event); |
30dd568c | 1097 | |
cdd6c482 | 1098 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1099 | } |
1100 | ||
1101 | static void x86_pmu_disable(struct perf_event *event) | |
1102 | { | |
1103 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1104 | int i; | |
1105 | ||
90151c35 SE |
1106 | /* |
1107 | * If we're called during a txn, we don't need to do anything. | |
1108 | * The events never got scheduled and ->cancel_txn will truncate | |
1109 | * the event_list. | |
1110 | */ | |
8d2cacbb | 1111 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1112 | return; |
1113 | ||
d76a0812 | 1114 | x86_pmu_stop(event); |
194002b2 | 1115 | |
1da53e02 SE |
1116 | for (i = 0; i < cpuc->n_events; i++) { |
1117 | if (event == cpuc->event_list[i]) { | |
1118 | ||
1119 | if (x86_pmu.put_event_constraints) | |
1120 | x86_pmu.put_event_constraints(cpuc, event); | |
1121 | ||
1122 | while (++i < cpuc->n_events) | |
1123 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1124 | ||
1125 | --cpuc->n_events; | |
6c9687ab | 1126 | break; |
1da53e02 SE |
1127 | } |
1128 | } | |
cdd6c482 | 1129 | perf_event_update_userpage(event); |
241771ef IM |
1130 | } |
1131 | ||
8c48e444 | 1132 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1133 | { |
df1a132b | 1134 | struct perf_sample_data data; |
cdd6c482 IM |
1135 | struct cpu_hw_events *cpuc; |
1136 | struct perf_event *event; | |
1137 | struct hw_perf_event *hwc; | |
11d1578f | 1138 | int idx, handled = 0; |
9029a5e3 IM |
1139 | u64 val; |
1140 | ||
dc1d628a | 1141 | perf_sample_data_init(&data, 0); |
df1a132b | 1142 | |
cdd6c482 | 1143 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1144 | |
948b1bb8 | 1145 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1146 | if (!test_bit(idx, cpuc->active_mask)) { |
1147 | /* | |
1148 | * Though we deactivated the counter some cpus | |
1149 | * might still deliver spurious interrupts still | |
1150 | * in flight. Catch them: | |
1151 | */ | |
1152 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1153 | handled++; | |
a29aa8a7 | 1154 | continue; |
63e6be6d | 1155 | } |
962bf7a6 | 1156 | |
cdd6c482 IM |
1157 | event = cpuc->events[idx]; |
1158 | hwc = &event->hw; | |
a4016a79 | 1159 | |
cc2ad4ba | 1160 | val = x86_perf_event_update(event); |
948b1bb8 | 1161 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1162 | continue; |
962bf7a6 | 1163 | |
9e350de3 | 1164 | /* |
cdd6c482 | 1165 | * event overflow |
9e350de3 | 1166 | */ |
4177c42a | 1167 | handled++; |
cdd6c482 | 1168 | data.period = event->hw.last_period; |
9e350de3 | 1169 | |
07088edb | 1170 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1171 | continue; |
1172 | ||
cdd6c482 | 1173 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1174 | x86_pmu_stop(event); |
a29aa8a7 | 1175 | } |
962bf7a6 | 1176 | |
9e350de3 PZ |
1177 | if (handled) |
1178 | inc_irq_stat(apic_perf_irqs); | |
1179 | ||
a29aa8a7 RR |
1180 | return handled; |
1181 | } | |
39d81eab | 1182 | |
b6276f35 PZ |
1183 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1184 | { | |
1185 | irq_enter(); | |
1186 | ack_APIC_irq(); | |
1187 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1188 | perf_event_do_pending(); |
b6276f35 PZ |
1189 | irq_exit(); |
1190 | } | |
1191 | ||
cdd6c482 | 1192 | void set_perf_event_pending(void) |
b6276f35 | 1193 | { |
04da8a43 | 1194 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1195 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1196 | return; | |
1197 | ||
b6276f35 | 1198 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1199 | #endif |
b6276f35 PZ |
1200 | } |
1201 | ||
cdd6c482 | 1202 | void perf_events_lapic_init(void) |
241771ef | 1203 | { |
04da8a43 | 1204 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1205 | return; |
85cf9dba | 1206 | |
241771ef | 1207 | /* |
c323d95f | 1208 | * Always use NMI for PMU |
241771ef | 1209 | */ |
c323d95f | 1210 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1211 | } |
1212 | ||
4177c42a RR |
1213 | struct pmu_nmi_state { |
1214 | unsigned int marked; | |
1215 | int handled; | |
1216 | }; | |
1217 | ||
1218 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1219 | ||
241771ef | 1220 | static int __kprobes |
cdd6c482 | 1221 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1222 | unsigned long cmd, void *__args) |
1223 | { | |
1224 | struct die_args *args = __args; | |
4177c42a RR |
1225 | unsigned int this_nmi; |
1226 | int handled; | |
b0f3f28e | 1227 | |
cdd6c482 | 1228 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1229 | return NOTIFY_DONE; |
1230 | ||
b0f3f28e PZ |
1231 | switch (cmd) { |
1232 | case DIE_NMI: | |
1233 | case DIE_NMI_IPI: | |
1234 | break; | |
4177c42a RR |
1235 | case DIE_NMIUNKNOWN: |
1236 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1237 | if (this_nmi != __get_cpu_var(pmu_nmi).marked) | |
1238 | /* let the kernel handle the unknown nmi */ | |
1239 | return NOTIFY_DONE; | |
1240 | /* | |
1241 | * This one is a PMU back-to-back nmi. Two events | |
1242 | * trigger 'simultaneously' raising two back-to-back | |
1243 | * NMIs. If the first NMI handles both, the latter | |
1244 | * will be empty and daze the CPU. So, we drop it to | |
1245 | * avoid false-positive 'unknown nmi' messages. | |
1246 | */ | |
1247 | return NOTIFY_STOP; | |
b0f3f28e | 1248 | default: |
241771ef | 1249 | return NOTIFY_DONE; |
b0f3f28e | 1250 | } |
241771ef | 1251 | |
241771ef | 1252 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1253 | |
1254 | handled = x86_pmu.handle_irq(args->regs); | |
1255 | if (!handled) | |
1256 | return NOTIFY_DONE; | |
1257 | ||
1258 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1259 | if ((handled > 1) || | |
1260 | /* the next nmi could be a back-to-back nmi */ | |
1261 | ((__get_cpu_var(pmu_nmi).marked == this_nmi) && | |
1262 | (__get_cpu_var(pmu_nmi).handled > 1))) { | |
1263 | /* | |
1264 | * We could have two subsequent back-to-back nmis: The | |
1265 | * first handles more than one counter, the 2nd | |
1266 | * handles only one counter and the 3rd handles no | |
1267 | * counter. | |
1268 | * | |
1269 | * This is the 2nd nmi because the previous was | |
1270 | * handling more than one counter. We will mark the | |
1271 | * next (3rd) and then drop it if unhandled. | |
1272 | */ | |
1273 | __get_cpu_var(pmu_nmi).marked = this_nmi + 1; | |
1274 | __get_cpu_var(pmu_nmi).handled = handled; | |
1275 | } | |
241771ef | 1276 | |
a4016a79 | 1277 | return NOTIFY_STOP; |
241771ef IM |
1278 | } |
1279 | ||
f22f54f4 PZ |
1280 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1281 | .notifier_call = perf_event_nmi_handler, | |
1282 | .next = NULL, | |
1283 | .priority = 1 | |
1284 | }; | |
1285 | ||
63b14649 | 1286 | static struct event_constraint unconstrained; |
38331f62 | 1287 | static struct event_constraint emptyconstraint; |
63b14649 | 1288 | |
63b14649 | 1289 | static struct event_constraint * |
f22f54f4 | 1290 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1291 | { |
63b14649 | 1292 | struct event_constraint *c; |
1da53e02 | 1293 | |
1da53e02 SE |
1294 | if (x86_pmu.event_constraints) { |
1295 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1296 | if ((event->hw.config & c->cmask) == c->code) |
1297 | return c; | |
1da53e02 SE |
1298 | } |
1299 | } | |
63b14649 PZ |
1300 | |
1301 | return &unconstrained; | |
1da53e02 SE |
1302 | } |
1303 | ||
f22f54f4 PZ |
1304 | #include "perf_event_amd.c" |
1305 | #include "perf_event_p6.c" | |
a072738e | 1306 | #include "perf_event_p4.c" |
caff2bef | 1307 | #include "perf_event_intel_lbr.c" |
ca037701 | 1308 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1309 | #include "perf_event_intel.c" |
f87ad35d | 1310 | |
3f6da390 PZ |
1311 | static int __cpuinit |
1312 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1313 | { | |
1314 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1315 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1316 | |
1317 | switch (action & ~CPU_TASKS_FROZEN) { | |
1318 | case CPU_UP_PREPARE: | |
1319 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1320 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1321 | break; |
1322 | ||
1323 | case CPU_STARTING: | |
1324 | if (x86_pmu.cpu_starting) | |
1325 | x86_pmu.cpu_starting(cpu); | |
1326 | break; | |
1327 | ||
1328 | case CPU_DYING: | |
1329 | if (x86_pmu.cpu_dying) | |
1330 | x86_pmu.cpu_dying(cpu); | |
1331 | break; | |
1332 | ||
b38b24ea | 1333 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1334 | case CPU_DEAD: |
1335 | if (x86_pmu.cpu_dead) | |
1336 | x86_pmu.cpu_dead(cpu); | |
1337 | break; | |
1338 | ||
1339 | default: | |
1340 | break; | |
1341 | } | |
1342 | ||
b38b24ea | 1343 | return ret; |
3f6da390 PZ |
1344 | } |
1345 | ||
12558038 CG |
1346 | static void __init pmu_check_apic(void) |
1347 | { | |
1348 | if (cpu_has_apic) | |
1349 | return; | |
1350 | ||
1351 | x86_pmu.apic = 0; | |
1352 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1353 | pr_info("no hardware sampling interrupt available.\n"); | |
1354 | } | |
1355 | ||
cdd6c482 | 1356 | void __init init_hw_perf_events(void) |
b56a3802 | 1357 | { |
b622d644 | 1358 | struct event_constraint *c; |
72eae04d RR |
1359 | int err; |
1360 | ||
cdd6c482 | 1361 | pr_info("Performance Events: "); |
1123e3ad | 1362 | |
b56a3802 JSR |
1363 | switch (boot_cpu_data.x86_vendor) { |
1364 | case X86_VENDOR_INTEL: | |
72eae04d | 1365 | err = intel_pmu_init(); |
b56a3802 | 1366 | break; |
f87ad35d | 1367 | case X86_VENDOR_AMD: |
72eae04d | 1368 | err = amd_pmu_init(); |
f87ad35d | 1369 | break; |
4138960a RR |
1370 | default: |
1371 | return; | |
b56a3802 | 1372 | } |
1123e3ad | 1373 | if (err != 0) { |
cdd6c482 | 1374 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1375 | return; |
1123e3ad | 1376 | } |
b56a3802 | 1377 | |
12558038 CG |
1378 | pmu_check_apic(); |
1379 | ||
1123e3ad | 1380 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1381 | |
3c44780b PZ |
1382 | if (x86_pmu.quirks) |
1383 | x86_pmu.quirks(); | |
1384 | ||
948b1bb8 | 1385 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1386 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1387 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1388 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1389 | } |
948b1bb8 RR |
1390 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
1391 | perf_max_events = x86_pmu.num_counters; | |
241771ef | 1392 | |
948b1bb8 | 1393 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1394 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1395 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1396 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1397 | } |
862a1a5f | 1398 | |
d6dc0b4e | 1399 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1400 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1401 | |
cdd6c482 IM |
1402 | perf_events_lapic_init(); |
1403 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1404 | |
63b14649 | 1405 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1406 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1407 | 0, x86_pmu.num_counters); | |
63b14649 | 1408 | |
b622d644 PZ |
1409 | if (x86_pmu.event_constraints) { |
1410 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1411 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1412 | continue; |
1413 | ||
948b1bb8 RR |
1414 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1415 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1416 | } |
1417 | } | |
1418 | ||
57c0c15b | 1419 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1420 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1421 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1422 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1423 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1424 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1425 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 PZ |
1426 | |
1427 | perf_cpu_notifier(x86_pmu_notifier); | |
241771ef | 1428 | } |
621a01ea | 1429 | |
cdd6c482 | 1430 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1431 | { |
cc2ad4ba | 1432 | x86_perf_event_update(event); |
ee06094f IM |
1433 | } |
1434 | ||
4d1c52b0 LM |
1435 | /* |
1436 | * Start group events scheduling transaction | |
1437 | * Set the flag to make pmu::enable() not perform the | |
1438 | * schedulability test, it will be performed at commit time | |
1439 | */ | |
1440 | static void x86_pmu_start_txn(const struct pmu *pmu) | |
1441 | { | |
1442 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1443 | ||
8d2cacbb | 1444 | cpuc->group_flag |= PERF_EVENT_TXN; |
90151c35 | 1445 | cpuc->n_txn = 0; |
4d1c52b0 LM |
1446 | } |
1447 | ||
1448 | /* | |
1449 | * Stop group events scheduling transaction | |
1450 | * Clear the flag and pmu::enable() will perform the | |
1451 | * schedulability test. | |
1452 | */ | |
1453 | static void x86_pmu_cancel_txn(const struct pmu *pmu) | |
1454 | { | |
1455 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1456 | ||
8d2cacbb | 1457 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 SE |
1458 | /* |
1459 | * Truncate the collected events. | |
1460 | */ | |
1461 | cpuc->n_added -= cpuc->n_txn; | |
1462 | cpuc->n_events -= cpuc->n_txn; | |
4d1c52b0 LM |
1463 | } |
1464 | ||
1465 | /* | |
1466 | * Commit group events scheduling transaction | |
1467 | * Perform the group schedulability test as a whole | |
1468 | * Return 0 if success | |
1469 | */ | |
1470 | static int x86_pmu_commit_txn(const struct pmu *pmu) | |
1471 | { | |
1472 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1473 | int assign[X86_PMC_IDX_MAX]; | |
1474 | int n, ret; | |
1475 | ||
1476 | n = cpuc->n_events; | |
1477 | ||
1478 | if (!x86_pmu_initialized()) | |
1479 | return -EAGAIN; | |
1480 | ||
1481 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1482 | if (ret) | |
1483 | return ret; | |
1484 | ||
1485 | /* | |
1486 | * copy new assignment, now we know it is possible | |
1487 | * will be used by hw_perf_enable() | |
1488 | */ | |
1489 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1490 | ||
8d2cacbb | 1491 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 | 1492 | |
4d1c52b0 LM |
1493 | return 0; |
1494 | } | |
1495 | ||
4aeb0b42 RR |
1496 | static const struct pmu pmu = { |
1497 | .enable = x86_pmu_enable, | |
1498 | .disable = x86_pmu_disable, | |
d76a0812 SE |
1499 | .start = x86_pmu_start, |
1500 | .stop = x86_pmu_stop, | |
4aeb0b42 | 1501 | .read = x86_pmu_read, |
a78ac325 | 1502 | .unthrottle = x86_pmu_unthrottle, |
4d1c52b0 LM |
1503 | .start_txn = x86_pmu_start_txn, |
1504 | .cancel_txn = x86_pmu_cancel_txn, | |
1505 | .commit_txn = x86_pmu_commit_txn, | |
621a01ea IM |
1506 | }; |
1507 | ||
ca037701 PZ |
1508 | /* |
1509 | * validate that we can schedule this event | |
1510 | */ | |
1511 | static int validate_event(struct perf_event *event) | |
1512 | { | |
1513 | struct cpu_hw_events *fake_cpuc; | |
1514 | struct event_constraint *c; | |
1515 | int ret = 0; | |
1516 | ||
1517 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1518 | if (!fake_cpuc) | |
1519 | return -ENOMEM; | |
1520 | ||
1521 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1522 | ||
1523 | if (!c || !c->weight) | |
1524 | ret = -ENOSPC; | |
1525 | ||
1526 | if (x86_pmu.put_event_constraints) | |
1527 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1528 | ||
1529 | kfree(fake_cpuc); | |
1530 | ||
1531 | return ret; | |
1532 | } | |
1533 | ||
1da53e02 SE |
1534 | /* |
1535 | * validate a single event group | |
1536 | * | |
1537 | * validation include: | |
184f412c IM |
1538 | * - check events are compatible which each other |
1539 | * - events do not compete for the same counter | |
1540 | * - number of events <= number of counters | |
1da53e02 SE |
1541 | * |
1542 | * validation ensures the group can be loaded onto the | |
1543 | * PMU if it was the only group available. | |
1544 | */ | |
fe9081cc PZ |
1545 | static int validate_group(struct perf_event *event) |
1546 | { | |
1da53e02 | 1547 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1548 | struct cpu_hw_events *fake_cpuc; |
1549 | int ret, n; | |
fe9081cc | 1550 | |
502568d5 PZ |
1551 | ret = -ENOMEM; |
1552 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1553 | if (!fake_cpuc) | |
1554 | goto out; | |
fe9081cc | 1555 | |
1da53e02 SE |
1556 | /* |
1557 | * the event is not yet connected with its | |
1558 | * siblings therefore we must first collect | |
1559 | * existing siblings, then add the new event | |
1560 | * before we can simulate the scheduling | |
1561 | */ | |
502568d5 PZ |
1562 | ret = -ENOSPC; |
1563 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1564 | if (n < 0) |
502568d5 | 1565 | goto out_free; |
fe9081cc | 1566 | |
502568d5 PZ |
1567 | fake_cpuc->n_events = n; |
1568 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1569 | if (n < 0) |
502568d5 | 1570 | goto out_free; |
fe9081cc | 1571 | |
502568d5 | 1572 | fake_cpuc->n_events = n; |
1da53e02 | 1573 | |
a072738e | 1574 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1575 | |
1576 | out_free: | |
1577 | kfree(fake_cpuc); | |
1578 | out: | |
1579 | return ret; | |
fe9081cc PZ |
1580 | } |
1581 | ||
cdd6c482 | 1582 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
621a01ea | 1583 | { |
8113070d | 1584 | const struct pmu *tmp; |
621a01ea IM |
1585 | int err; |
1586 | ||
cdd6c482 | 1587 | err = __hw_perf_event_init(event); |
fe9081cc | 1588 | if (!err) { |
8113070d SE |
1589 | /* |
1590 | * we temporarily connect event to its pmu | |
1591 | * such that validate_group() can classify | |
1592 | * it as an x86 event using is_x86_event() | |
1593 | */ | |
1594 | tmp = event->pmu; | |
1595 | event->pmu = &pmu; | |
1596 | ||
fe9081cc PZ |
1597 | if (event->group_leader != event) |
1598 | err = validate_group(event); | |
ca037701 PZ |
1599 | else |
1600 | err = validate_event(event); | |
8113070d SE |
1601 | |
1602 | event->pmu = tmp; | |
fe9081cc | 1603 | } |
a1792cda | 1604 | if (err) { |
cdd6c482 IM |
1605 | if (event->destroy) |
1606 | event->destroy(event); | |
9ea98e19 | 1607 | return ERR_PTR(err); |
a1792cda | 1608 | } |
621a01ea | 1609 | |
4aeb0b42 | 1610 | return &pmu; |
621a01ea | 1611 | } |
d7d59fb3 PZ |
1612 | |
1613 | /* | |
1614 | * callchain support | |
1615 | */ | |
1616 | ||
1617 | static inline | |
f9188e02 | 1618 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1619 | { |
f9188e02 | 1620 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1621 | entry->ip[entry->nr++] = ip; |
1622 | } | |
1623 | ||
245b2e70 TH |
1624 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
1625 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
d7d59fb3 PZ |
1626 | |
1627 | ||
1628 | static void | |
1629 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1630 | { | |
1631 | /* Ignore warnings */ | |
1632 | } | |
1633 | ||
1634 | static void backtrace_warning(void *data, char *msg) | |
1635 | { | |
1636 | /* Ignore warnings */ | |
1637 | } | |
1638 | ||
1639 | static int backtrace_stack(void *data, char *name) | |
1640 | { | |
038e836e | 1641 | return 0; |
d7d59fb3 PZ |
1642 | } |
1643 | ||
1644 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1645 | { | |
1646 | struct perf_callchain_entry *entry = data; | |
1647 | ||
6f4dee06 | 1648 | callchain_store(entry, addr); |
d7d59fb3 PZ |
1649 | } |
1650 | ||
1651 | static const struct stacktrace_ops backtrace_ops = { | |
1652 | .warning = backtrace_warning, | |
1653 | .warning_symbol = backtrace_warning_symbol, | |
1654 | .stack = backtrace_stack, | |
1655 | .address = backtrace_address, | |
06d65bda | 1656 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1657 | }; |
1658 | ||
1659 | static void | |
1660 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1661 | { | |
f9188e02 | 1662 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1663 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1664 | |
48b5ba9c | 1665 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1666 | } |
1667 | ||
257ef9d2 TE |
1668 | #ifdef CONFIG_COMPAT |
1669 | static inline int | |
1670 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1671 | { |
257ef9d2 TE |
1672 | /* 32-bit process in 64-bit kernel. */ |
1673 | struct stack_frame_ia32 frame; | |
1674 | const void __user *fp; | |
74193ef0 | 1675 | |
257ef9d2 TE |
1676 | if (!test_thread_flag(TIF_IA32)) |
1677 | return 0; | |
1678 | ||
1679 | fp = compat_ptr(regs->bp); | |
1680 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1681 | unsigned long bytes; | |
1682 | frame.next_frame = 0; | |
1683 | frame.return_address = 0; | |
1684 | ||
1685 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1686 | if (bytes != sizeof(frame)) | |
1687 | break; | |
74193ef0 | 1688 | |
257ef9d2 TE |
1689 | if (fp < compat_ptr(regs->sp)) |
1690 | break; | |
74193ef0 | 1691 | |
257ef9d2 TE |
1692 | callchain_store(entry, frame.return_address); |
1693 | fp = compat_ptr(frame.next_frame); | |
1694 | } | |
1695 | return 1; | |
d7d59fb3 | 1696 | } |
257ef9d2 TE |
1697 | #else |
1698 | static inline int | |
1699 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1700 | { | |
1701 | return 0; | |
1702 | } | |
1703 | #endif | |
d7d59fb3 PZ |
1704 | |
1705 | static void | |
1706 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1707 | { | |
1708 | struct stack_frame frame; | |
1709 | const void __user *fp; | |
1710 | ||
5a6cec3a IM |
1711 | if (!user_mode(regs)) |
1712 | regs = task_pt_regs(current); | |
1713 | ||
74193ef0 | 1714 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1715 | |
f9188e02 | 1716 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1717 | callchain_store(entry, regs->ip); |
1718 | ||
257ef9d2 TE |
1719 | if (perf_callchain_user32(regs, entry)) |
1720 | return; | |
1721 | ||
f9188e02 | 1722 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1723 | unsigned long bytes; |
038e836e | 1724 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1725 | frame.return_address = 0; |
1726 | ||
257ef9d2 TE |
1727 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1728 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1729 | break; |
1730 | ||
5a6cec3a | 1731 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1732 | break; |
1733 | ||
1734 | callchain_store(entry, frame.return_address); | |
038e836e | 1735 | fp = frame.next_frame; |
d7d59fb3 PZ |
1736 | } |
1737 | } | |
1738 | ||
1739 | static void | |
1740 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1741 | { | |
1742 | int is_user; | |
1743 | ||
1744 | if (!regs) | |
1745 | return; | |
1746 | ||
1747 | is_user = user_mode(regs); | |
1748 | ||
d7d59fb3 PZ |
1749 | if (is_user && current->state != TASK_RUNNING) |
1750 | return; | |
1751 | ||
1752 | if (!is_user) | |
1753 | perf_callchain_kernel(regs, entry); | |
1754 | ||
1755 | if (current->mm) | |
1756 | perf_callchain_user(regs, entry); | |
1757 | } | |
1758 | ||
1759 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1760 | { | |
1761 | struct perf_callchain_entry *entry; | |
1762 | ||
39447b38 ZY |
1763 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1764 | /* TODO: We don't support guest os callchain now */ | |
1765 | return NULL; | |
1766 | } | |
1767 | ||
d7d59fb3 | 1768 | if (in_nmi()) |
245b2e70 | 1769 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 1770 | else |
245b2e70 | 1771 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
1772 | |
1773 | entry->nr = 0; | |
1774 | ||
1775 | perf_do_callchain(regs, entry); | |
1776 | ||
1777 | return entry; | |
1778 | } | |
5331d7b8 | 1779 | |
39447b38 ZY |
1780 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1781 | { | |
1782 | unsigned long ip; | |
dcf46b94 | 1783 | |
39447b38 ZY |
1784 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1785 | ip = perf_guest_cbs->get_guest_ip(); | |
1786 | else | |
1787 | ip = instruction_pointer(regs); | |
dcf46b94 | 1788 | |
39447b38 ZY |
1789 | return ip; |
1790 | } | |
1791 | ||
1792 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1793 | { | |
1794 | int misc = 0; | |
dcf46b94 | 1795 | |
39447b38 | 1796 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1797 | if (perf_guest_cbs->is_user_mode()) |
1798 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1799 | else | |
1800 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1801 | } else { | |
1802 | if (user_mode(regs)) | |
1803 | misc |= PERF_RECORD_MISC_USER; | |
1804 | else | |
1805 | misc |= PERF_RECORD_MISC_KERNEL; | |
1806 | } | |
1807 | ||
39447b38 | 1808 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1809 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1810 | |
1811 | return misc; | |
1812 | } |