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Commit | Line | Data |
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15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
3222b36f | 21 | #include <linux/sysdev.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 HS |
27 | #include <asm/processor.h> |
28 | #include <asm/system.h> | |
29 | #include <asm/apic.h> | |
a65c88dd HS |
30 | #include <asm/idle.h> |
31 | #include <asm/mce.h> | |
895287c0 | 32 | #include <asm/msr.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
0199114c FY |
37 | #define THERMAL_THROTTLING_EVENT 0 |
38 | #define POWER_LIMIT_EVENT 1 | |
39 | ||
39676840 | 40 | /* |
0199114c | 41 | * Current thermal event state: |
39676840 | 42 | */ |
55d435a2 | 43 | struct _thermal_state { |
0199114c FY |
44 | bool new_event; |
45 | int event; | |
39676840 | 46 | u64 next_check; |
0199114c FY |
47 | unsigned long count; |
48 | unsigned long last_count; | |
39676840 | 49 | }; |
cb6f3c15 | 50 | |
55d435a2 | 51 | struct thermal_state { |
0199114c FY |
52 | struct _thermal_state core_throttle; |
53 | struct _thermal_state core_power_limit; | |
54 | struct _thermal_state package_throttle; | |
55 | struct _thermal_state package_power_limit; | |
55d435a2 FY |
56 | }; |
57 | ||
39676840 IM |
58 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
59 | ||
60 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 61 | |
a2202aa2 YW |
62 | static u32 lvtthmr_init __read_mostly; |
63 | ||
3222b36f | 64 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 65 | #define define_therm_throt_sysdev_one_ro(_name) \ |
55d435a2 FY |
66 | static SYSDEV_ATTR(_name, 0444, \ |
67 | therm_throt_sysdev_show_##_name, \ | |
68 | NULL) \ | |
cb6f3c15 | 69 | |
0199114c | 70 | #define define_therm_throt_sysdev_show_func(event, name) \ |
39676840 | 71 | \ |
0199114c | 72 | static ssize_t therm_throt_sysdev_show_##event##_##name( \ |
39676840 IM |
73 | struct sys_device *dev, \ |
74 | struct sysdev_attribute *attr, \ | |
75 | char *buf) \ | |
cb6f3c15 IM |
76 | { \ |
77 | unsigned int cpu = dev->id; \ | |
78 | ssize_t ret; \ | |
79 | \ | |
80 | preempt_disable(); /* CPU hotplug */ \ | |
55d435a2 | 81 | if (cpu_online(cpu)) { \ |
cb6f3c15 | 82 | ret = sprintf(buf, "%lu\n", \ |
0199114c | 83 | per_cpu(thermal_state, cpu).event.name); \ |
55d435a2 | 84 | } else \ |
cb6f3c15 IM |
85 | ret = 0; \ |
86 | preempt_enable(); \ | |
87 | \ | |
88 | return ret; \ | |
3222b36f DZ |
89 | } |
90 | ||
0199114c | 91 | define_therm_throt_sysdev_show_func(core_throttle, count); |
55d435a2 FY |
92 | define_therm_throt_sysdev_one_ro(core_throttle_count); |
93 | ||
0199114c FY |
94 | define_therm_throt_sysdev_show_func(core_power_limit, count); |
95 | define_therm_throt_sysdev_one_ro(core_power_limit_count); | |
96 | ||
97 | define_therm_throt_sysdev_show_func(package_throttle, count); | |
55d435a2 | 98 | define_therm_throt_sysdev_one_ro(package_throttle_count); |
3222b36f | 99 | |
0199114c FY |
100 | define_therm_throt_sysdev_show_func(package_power_limit, count); |
101 | define_therm_throt_sysdev_one_ro(package_power_limit_count); | |
102 | ||
3222b36f | 103 | static struct attribute *thermal_throttle_attrs[] = { |
55d435a2 | 104 | &attr_core_throttle_count.attr, |
3222b36f DZ |
105 | NULL |
106 | }; | |
107 | ||
0199114c | 108 | static struct attribute_group thermal_attr_group = { |
cb6f3c15 IM |
109 | .attrs = thermal_throttle_attrs, |
110 | .name = "thermal_throttle" | |
3222b36f DZ |
111 | }; |
112 | #endif /* CONFIG_SYSFS */ | |
15d5f839 | 113 | |
0199114c FY |
114 | #define CORE_LEVEL 0 |
115 | #define PACKAGE_LEVEL 1 | |
116 | ||
15d5f839 | 117 | /*** |
3222b36f | 118 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
119 | * @curr: Whether the condition is current or not (boolean), since the |
120 | * thermal interrupt normally gets called both when the thermal | |
121 | * event begins and once the event has ended. | |
122 | * | |
3222b36f | 123 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
124 | * IRQ has been acknowledged. |
125 | * | |
126 | * It will take care of rate limiting and printing messages to the syslog. | |
127 | * | |
128 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
129 | * "timeout" from previous log message. | |
130 | * 1 : Event should be logged further, and a message has been | |
131 | * printed to the syslog. | |
132 | */ | |
0199114c | 133 | static int therm_throt_process(bool new_event, int event, int level) |
15d5f839 | 134 | { |
55d435a2 | 135 | struct _thermal_state *state; |
0199114c FY |
136 | unsigned int this_cpu = smp_processor_id(); |
137 | bool old_event; | |
39676840 | 138 | u64 now; |
0199114c | 139 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); |
39676840 | 140 | |
39676840 | 141 | now = get_jiffies_64(); |
0199114c FY |
142 | if (level == CORE_LEVEL) { |
143 | if (event == THERMAL_THROTTLING_EVENT) | |
144 | state = &pstate->core_throttle; | |
145 | else if (event == POWER_LIMIT_EVENT) | |
146 | state = &pstate->core_power_limit; | |
147 | else | |
148 | return 0; | |
149 | } else if (level == PACKAGE_LEVEL) { | |
150 | if (event == THERMAL_THROTTLING_EVENT) | |
151 | state = &pstate->package_throttle; | |
152 | else if (event == POWER_LIMIT_EVENT) | |
153 | state = &pstate->package_power_limit; | |
154 | else | |
155 | return 0; | |
156 | } else | |
157 | return 0; | |
39676840 | 158 | |
0199114c FY |
159 | old_event = state->new_event; |
160 | state->new_event = new_event; | |
15d5f839 | 161 | |
0199114c FY |
162 | if (new_event) |
163 | state->count++; | |
3222b36f | 164 | |
b417c9fd | 165 | if (time_before64(now, state->next_check) && |
0199114c | 166 | state->count != state->last_count) |
15d5f839 DZ |
167 | return 0; |
168 | ||
39676840 | 169 | state->next_check = now + CHECK_INTERVAL; |
0199114c | 170 | state->last_count = state->count; |
15d5f839 DZ |
171 | |
172 | /* if we just entered the thermal event */ | |
0199114c FY |
173 | if (new_event) { |
174 | if (event == THERMAL_THROTTLING_EVENT) | |
175 | printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n", | |
176 | this_cpu, | |
177 | level == CORE_LEVEL ? "Core" : "Package", | |
178 | state->count); | |
179 | else | |
180 | printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n", | |
181 | this_cpu, | |
182 | level == CORE_LEVEL ? "Core" : "Package", | |
183 | state->count); | |
3222b36f | 184 | |
15d5f839 | 185 | add_taint(TAINT_MACHINE_CHECK); |
4e5c25d4 HD |
186 | return 1; |
187 | } | |
0199114c FY |
188 | if (old_event) { |
189 | if (event == THERMAL_THROTTLING_EVENT) | |
190 | printk(KERN_INFO "CPU%d: %s temperature/speed normal\n", | |
191 | this_cpu, | |
192 | level == CORE_LEVEL ? "Core" : "Package"); | |
193 | else | |
194 | printk(KERN_INFO "CPU%d: %s power limit normal\n", | |
195 | this_cpu, | |
196 | level == CORE_LEVEL ? "Core" : "Package"); | |
4e5c25d4 | 197 | return 1; |
15d5f839 DZ |
198 | } |
199 | ||
4e5c25d4 | 200 | return 0; |
15d5f839 | 201 | } |
3222b36f DZ |
202 | |
203 | #ifdef CONFIG_SYSFS | |
cb6f3c15 | 204 | /* Add/Remove thermal_throttle interface for CPU device: */ |
51e3c1b5 SS |
205 | static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev, |
206 | unsigned int cpu) | |
3222b36f | 207 | { |
55d435a2 | 208 | int err; |
51e3c1b5 | 209 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
55d435a2 | 210 | |
0199114c | 211 | err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group); |
55d435a2 FY |
212 | if (err) |
213 | return err; | |
214 | ||
0199114c FY |
215 | if (cpu_has(c, X86_FEATURE_PLN)) |
216 | err = sysfs_add_file_to_group(&sys_dev->kobj, | |
217 | &attr_core_power_limit_count.attr, | |
218 | thermal_attr_group.name); | |
b62be8ea | 219 | if (cpu_has(c, X86_FEATURE_PTS)) { |
55d435a2 FY |
220 | err = sysfs_add_file_to_group(&sys_dev->kobj, |
221 | &attr_package_throttle_count.attr, | |
0199114c FY |
222 | thermal_attr_group.name); |
223 | if (cpu_has(c, X86_FEATURE_PLN)) | |
224 | err = sysfs_add_file_to_group(&sys_dev->kobj, | |
225 | &attr_package_power_limit_count.attr, | |
226 | thermal_attr_group.name); | |
b62be8ea | 227 | } |
55d435a2 FY |
228 | |
229 | return err; | |
3222b36f DZ |
230 | } |
231 | ||
6569345a | 232 | static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev) |
3222b36f | 233 | { |
0199114c | 234 | sysfs_remove_group(&sys_dev->kobj, &thermal_attr_group); |
3222b36f DZ |
235 | } |
236 | ||
cb6f3c15 | 237 | /* Mutex protecting device creation against CPU hotplug: */ |
3222b36f DZ |
238 | static DEFINE_MUTEX(therm_cpu_lock); |
239 | ||
240 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | |
cb6f3c15 IM |
241 | static __cpuinit int |
242 | thermal_throttle_cpu_callback(struct notifier_block *nfb, | |
243 | unsigned long action, | |
244 | void *hcpu) | |
3222b36f DZ |
245 | { |
246 | unsigned int cpu = (unsigned long)hcpu; | |
247 | struct sys_device *sys_dev; | |
c7e38a9c | 248 | int err = 0; |
3222b36f DZ |
249 | |
250 | sys_dev = get_cpu_sysdev(cpu); | |
cb6f3c15 | 251 | |
3222b36f | 252 | switch (action) { |
c7e38a9c AM |
253 | case CPU_UP_PREPARE: |
254 | case CPU_UP_PREPARE_FROZEN: | |
38ef6d19 | 255 | mutex_lock(&therm_cpu_lock); |
51e3c1b5 | 256 | err = thermal_throttle_add_dev(sys_dev, cpu); |
38ef6d19 | 257 | mutex_unlock(&therm_cpu_lock); |
6569345a | 258 | WARN_ON(err); |
3222b36f | 259 | break; |
c7e38a9c AM |
260 | case CPU_UP_CANCELED: |
261 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 262 | case CPU_DEAD: |
8bb78442 | 263 | case CPU_DEAD_FROZEN: |
38ef6d19 | 264 | mutex_lock(&therm_cpu_lock); |
3222b36f | 265 | thermal_throttle_remove_dev(sys_dev); |
38ef6d19 | 266 | mutex_unlock(&therm_cpu_lock); |
3222b36f DZ |
267 | break; |
268 | } | |
a94247e7 | 269 | return notifier_from_errno(err); |
3222b36f DZ |
270 | } |
271 | ||
25d1b516 | 272 | static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = |
3222b36f DZ |
273 | { |
274 | .notifier_call = thermal_throttle_cpu_callback, | |
275 | }; | |
3222b36f DZ |
276 | |
277 | static __init int thermal_throttle_init_device(void) | |
278 | { | |
279 | unsigned int cpu = 0; | |
6569345a | 280 | int err; |
3222b36f DZ |
281 | |
282 | if (!atomic_read(&therm_throt_en)) | |
283 | return 0; | |
284 | ||
285 | register_hotcpu_notifier(&thermal_throttle_cpu_notifier); | |
286 | ||
287 | #ifdef CONFIG_HOTPLUG_CPU | |
288 | mutex_lock(&therm_cpu_lock); | |
289 | #endif | |
290 | /* connect live CPUs to sysfs */ | |
6569345a | 291 | for_each_online_cpu(cpu) { |
51e3c1b5 | 292 | err = thermal_throttle_add_dev(get_cpu_sysdev(cpu), cpu); |
6569345a SH |
293 | WARN_ON(err); |
294 | } | |
3222b36f DZ |
295 | #ifdef CONFIG_HOTPLUG_CPU |
296 | mutex_unlock(&therm_cpu_lock); | |
297 | #endif | |
298 | ||
299 | return 0; | |
300 | } | |
3222b36f | 301 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 302 | |
3222b36f | 303 | #endif /* CONFIG_SYSFS */ |
a65c88dd | 304 | |
0199114c FY |
305 | /* |
306 | * Set up the most two significant bit to notify mce log that this thermal | |
307 | * event type. | |
308 | * This is a temp solution. May be changed in the future with mce log | |
309 | * infrasture. | |
310 | */ | |
311 | #define CORE_THROTTLED (0) | |
312 | #define CORE_POWER_LIMIT ((__u64)1 << 62) | |
313 | #define PACKAGE_THROTTLED ((__u64)2 << 62) | |
314 | #define PACKAGE_POWER_LIMIT ((__u64)3 << 62) | |
315 | ||
a65c88dd | 316 | /* Thermal transition interrupt handler */ |
8363fc82 | 317 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
318 | { |
319 | __u64 msr_val; | |
55d435a2 | 320 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
a65c88dd HS |
321 | |
322 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
0199114c | 323 | |
55d435a2 | 324 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT, |
0199114c | 325 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 326 | CORE_LEVEL) != 0) |
0199114c FY |
327 | mce_log_therm_throt_event(CORE_THROTTLED | msr_val); |
328 | ||
329 | if (cpu_has(c, X86_FEATURE_PLN)) | |
330 | if (therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, | |
331 | POWER_LIMIT_EVENT, | |
332 | CORE_LEVEL) != 0) | |
333 | mce_log_therm_throt_event(CORE_POWER_LIMIT | msr_val); | |
55d435a2 FY |
334 | |
335 | if (cpu_has(c, X86_FEATURE_PTS)) { | |
336 | rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); | |
337 | if (therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, | |
0199114c | 338 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 339 | PACKAGE_LEVEL) != 0) |
0199114c FY |
340 | mce_log_therm_throt_event(PACKAGE_THROTTLED | msr_val); |
341 | if (cpu_has(c, X86_FEATURE_PLN)) | |
342 | if (therm_throt_process(msr_val & | |
343 | PACKAGE_THERM_STATUS_POWER_LIMIT, | |
344 | POWER_LIMIT_EVENT, | |
345 | PACKAGE_LEVEL) != 0) | |
346 | mce_log_therm_throt_event(PACKAGE_POWER_LIMIT | |
347 | | msr_val); | |
55d435a2 | 348 | } |
a65c88dd HS |
349 | } |
350 | ||
351 | static void unexpected_thermal_interrupt(void) | |
352 | { | |
353 | printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", | |
354 | smp_processor_id()); | |
355 | add_taint(TAINT_MACHINE_CHECK); | |
356 | } | |
357 | ||
358 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
359 | ||
360 | asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) | |
361 | { | |
362 | exit_idle(); | |
363 | irq_enter(); | |
364 | inc_irq_stat(irq_thermal_count); | |
365 | smp_thermal_vector(); | |
366 | irq_exit(); | |
367 | /* Ack only at the end to avoid potential reentry */ | |
368 | ack_APIC_irq(); | |
369 | } | |
370 | ||
70fe4407 HS |
371 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
372 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
373 | { | |
374 | if (!cpu_has_apic) | |
375 | return 0; | |
376 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
377 | return 0; | |
378 | return 1; | |
379 | } | |
380 | ||
ce6b5d76 | 381 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
382 | { |
383 | /* | |
384 | * This function is only called on boot CPU. Save the init thermal | |
385 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
386 | * entry BIOS programmed later | |
387 | */ | |
70fe4407 | 388 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
389 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
390 | } | |
391 | ||
cffd377e | 392 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
393 | { |
394 | unsigned int cpu = smp_processor_id(); | |
395 | int tm2 = 0; | |
396 | u32 l, h; | |
397 | ||
70fe4407 | 398 | if (!intel_thermal_supported(c)) |
895287c0 HS |
399 | return; |
400 | ||
401 | /* | |
402 | * First check if its enabled already, in which case there might | |
403 | * be some SMM goo which handles it, so we can't even put a handler | |
404 | * since it might be delivered via SMI already: | |
405 | */ | |
406 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 YW |
407 | |
408 | /* | |
409 | * The initial value of thermal LVT entries on all APs always reads | |
410 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
411 | * sequence to them and LVT registers are reset to 0s except for | |
412 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
413 | * Always restore the value that BIOS has programmed on AP based on | |
414 | * BSP's info we saved since BIOS is always setting the same value | |
415 | * for all threads/cores | |
416 | */ | |
417 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
418 | ||
419 | h = lvtthmr_init; | |
420 | ||
895287c0 HS |
421 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
422 | printk(KERN_DEBUG | |
423 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | |
424 | return; | |
425 | } | |
426 | ||
895287c0 HS |
427 | /* Check whether a vector already exists */ |
428 | if (h & APIC_VECTOR_MASK) { | |
429 | printk(KERN_DEBUG | |
430 | "CPU%d: Thermal LVT vector (%#x) already installed\n", | |
431 | cpu, (h & APIC_VECTOR_MASK)); | |
432 | return; | |
433 | } | |
434 | ||
f3a0867b BZ |
435 | /* early Pentium M models use different method for enabling TM2 */ |
436 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
437 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
438 | rdmsr(MSR_THERM2_CTL, l, h); | |
439 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
440 | tm2 = 1; | |
441 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
442 | tm2 = 1; | |
443 | } | |
444 | ||
895287c0 HS |
445 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
446 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
447 | apic_write(APIC_LVTTHMR, h); | |
448 | ||
449 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
0199114c FY |
450 | if (cpu_has(c, X86_FEATURE_PLN)) |
451 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
452 | l | (THERM_INT_LOW_ENABLE | |
453 | | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); | |
454 | else | |
455 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
456 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
895287c0 | 457 | |
55d435a2 FY |
458 | if (cpu_has(c, X86_FEATURE_PTS)) { |
459 | rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
0199114c FY |
460 | if (cpu_has(c, X86_FEATURE_PLN)) |
461 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
462 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
463 | | PACKAGE_THERM_INT_HIGH_ENABLE | |
464 | | PACKAGE_THERM_INT_PLN_ENABLE), h); | |
465 | else | |
466 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
467 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
468 | | PACKAGE_THERM_INT_HIGH_ENABLE), h); | |
55d435a2 FY |
469 | } |
470 | ||
8363fc82 | 471 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
472 | |
473 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
474 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
475 | ||
476 | /* Unmask the thermal vector: */ | |
477 | l = apic_read(APIC_LVTTHMR); | |
478 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
479 | ||
2eaad1fd MT |
480 | printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n", |
481 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
482 | |
483 | /* enable thermal throttle processing */ | |
484 | atomic_set(&therm_throt_en, 1); | |
485 | } |