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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
5be9ed25 | 37 | #include <linux/debugfs.h> |
e9eee03e | 38 | |
d88203d1 | 39 | #include <asm/processor.h> |
ccc3c319 AK |
40 | #include <asm/hw_irq.h> |
41 | #include <asm/apic.h> | |
e02e68d3 | 42 | #include <asm/idle.h> |
ccc3c319 | 43 | #include <asm/ipi.h> |
e9eee03e IM |
44 | #include <asm/mce.h> |
45 | #include <asm/msr.h> | |
1da177e4 | 46 | |
bd19a5e6 | 47 | #include "mce-internal.h" |
711c2e48 | 48 | |
4e5b3e69 | 49 | int mce_disabled __read_mostly; |
04b2b1a4 | 50 | |
e9eee03e | 51 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 52 | |
3c079792 AK |
53 | #define SPINUNIT 100 /* 100ns */ |
54 | ||
553f265f AK |
55 | atomic_t mce_entry; |
56 | ||
01ca79f1 AK |
57 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
58 | ||
bd78432c TH |
59 | /* |
60 | * Tolerant levels: | |
61 | * 0: always panic on uncorrected errors, log corrected errors | |
62 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
63 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
64 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
65 | */ | |
4e5b3e69 HS |
66 | static int tolerant __read_mostly = 1; |
67 | static int banks __read_mostly; | |
4e5b3e69 HS |
68 | static int rip_msr __read_mostly; |
69 | static int mce_bootlog __read_mostly = -1; | |
70 | static int monarch_timeout __read_mostly = -1; | |
71 | static int mce_panic_timeout __read_mostly; | |
72 | static int mce_dont_log_ce __read_mostly; | |
73 | int mce_cmci_disabled __read_mostly; | |
74 | int mce_ignore_ce __read_mostly; | |
75 | int mce_ser __read_mostly; | |
a98f0dd3 | 76 | |
cebe1820 AK |
77 | struct mce_bank *mce_banks __read_mostly; |
78 | ||
1020bcbc HS |
79 | /* User mode helper program triggered by machine check event */ |
80 | static unsigned long mce_need_notify; | |
81 | static char mce_helper[128]; | |
82 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 83 | |
e02e68d3 | 84 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
85 | static DEFINE_PER_CPU(struct mce, mces_seen); |
86 | static int cpu_missing; | |
87 | ||
fb253195 BP |
88 | /* |
89 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
90 | * MCE errors in a human-readable form. | |
91 | */ | |
92 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
93 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
94 | ||
95 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, | |
96 | void *data) | |
f436f8bb IM |
97 | { |
98 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); | |
99 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); | |
fb253195 BP |
100 | |
101 | return NOTIFY_STOP; | |
f436f8bb IM |
102 | } |
103 | ||
fb253195 BP |
104 | static struct notifier_block mce_dec_nb = { |
105 | .notifier_call = default_decode_mce, | |
106 | .priority = -1, | |
107 | }; | |
e02e68d3 | 108 | |
ee031c31 AK |
109 | /* MCA banks polled by the period polling timer for corrected events */ |
110 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
111 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
112 | }; | |
113 | ||
9b1beaf2 AK |
114 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
115 | ||
b5f2fa4e AK |
116 | /* Do initial initialization of a struct mce */ |
117 | void mce_setup(struct mce *m) | |
118 | { | |
119 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 120 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 121 | rdtscll(m->tsc); |
8ee08347 AK |
122 | /* We hope get_seconds stays lockless */ |
123 | m->time = get_seconds(); | |
124 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
125 | m->cpuid = cpuid_eax(1); | |
126 | #ifdef CONFIG_SMP | |
127 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
128 | #endif | |
129 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
130 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
131 | } |
132 | ||
ea149b36 AK |
133 | DEFINE_PER_CPU(struct mce, injectm); |
134 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
135 | ||
1da177e4 LT |
136 | /* |
137 | * Lockless MCE logging infrastructure. | |
138 | * This avoids deadlocks on printk locks without having to break locks. Also | |
139 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
140 | */ | |
141 | ||
231fd906 | 142 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
143 | .signature = MCE_LOG_SIGNATURE, |
144 | .len = MCE_LOG_LEN, | |
145 | .recordlen = sizeof(struct mce), | |
d88203d1 | 146 | }; |
1da177e4 LT |
147 | |
148 | void mce_log(struct mce *mce) | |
149 | { | |
150 | unsigned next, entry; | |
e9eee03e | 151 | |
1da177e4 | 152 | mce->finished = 0; |
7644143c | 153 | wmb(); |
1da177e4 LT |
154 | for (;;) { |
155 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 156 | for (;;) { |
e9eee03e IM |
157 | /* |
158 | * When the buffer fills up discard new entries. | |
159 | * Assume that the earlier errors are the more | |
160 | * interesting ones: | |
161 | */ | |
673242c1 | 162 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
163 | set_bit(MCE_OVERFLOW, |
164 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
165 | return; |
166 | } | |
e9eee03e | 167 | /* Old left over entry. Skip: */ |
673242c1 AK |
168 | if (mcelog.entry[entry].finished) { |
169 | entry++; | |
170 | continue; | |
171 | } | |
7644143c | 172 | break; |
1da177e4 | 173 | } |
1da177e4 LT |
174 | smp_rmb(); |
175 | next = entry + 1; | |
176 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
177 | break; | |
178 | } | |
179 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 180 | wmb(); |
1da177e4 | 181 | mcelog.entry[entry].finished = 1; |
7644143c | 182 | wmb(); |
1da177e4 | 183 | |
a0189c70 | 184 | mce->finished = 1; |
1020bcbc | 185 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
186 | } |
187 | ||
77e26cca | 188 | static void print_mce(struct mce *m) |
1da177e4 | 189 | { |
f436f8bb | 190 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 191 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 192 | |
65ea5b03 | 193 | if (m->ip) { |
f436f8bb IM |
194 | pr_emerg("RIP%s %02x:<%016Lx> ", |
195 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
196 | m->cs, m->ip); | |
197 | ||
1da177e4 | 198 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 199 | print_symbol("{%s}", m->ip); |
f436f8bb | 200 | pr_cont("\n"); |
1da177e4 | 201 | } |
f436f8bb IM |
202 | |
203 | pr_emerg("TSC %llx ", m->tsc); | |
1da177e4 | 204 | if (m->addr) |
f436f8bb | 205 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 206 | if (m->misc) |
f436f8bb | 207 | pr_cont("MISC %llx ", m->misc); |
549d042d | 208 | |
f436f8bb IM |
209 | pr_cont("\n"); |
210 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
211 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); | |
212 | ||
213 | /* | |
214 | * Print out human-readable details about the MCE error, | |
fb253195 | 215 | * (if the CPU has an implementation for that) |
f436f8bb | 216 | */ |
fb253195 | 217 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
86503560 AK |
218 | } |
219 | ||
77e26cca HS |
220 | static void print_mce_head(void) |
221 | { | |
f436f8bb | 222 | pr_emerg("\nHARDWARE ERROR\n"); |
77e26cca HS |
223 | } |
224 | ||
86503560 AK |
225 | static void print_mce_tail(void) |
226 | { | |
f436f8bb | 227 | pr_emerg("This is not a software problem!\n"); |
1da177e4 LT |
228 | } |
229 | ||
f94b61c2 AK |
230 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
231 | ||
232 | static atomic_t mce_paniced; | |
233 | ||
bf783f9f HY |
234 | static int fake_panic; |
235 | static atomic_t mce_fake_paniced; | |
236 | ||
f94b61c2 AK |
237 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
238 | static void wait_for_panic(void) | |
239 | { | |
240 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 241 | |
f94b61c2 AK |
242 | preempt_disable(); |
243 | local_irq_enable(); | |
244 | while (timeout-- > 0) | |
245 | udelay(1); | |
29b0f591 AK |
246 | if (panic_timeout == 0) |
247 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
248 | panic("Panicing machine check CPU died"); |
249 | } | |
250 | ||
bd19a5e6 | 251 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 252 | { |
1da177e4 | 253 | int i; |
e02e68d3 | 254 | |
bf783f9f HY |
255 | if (!fake_panic) { |
256 | /* | |
257 | * Make sure only one CPU runs in machine check panic | |
258 | */ | |
259 | if (atomic_inc_return(&mce_paniced) > 1) | |
260 | wait_for_panic(); | |
261 | barrier(); | |
f94b61c2 | 262 | |
bf783f9f HY |
263 | bust_spinlocks(1); |
264 | console_verbose(); | |
265 | } else { | |
266 | /* Don't log too much for fake panic */ | |
267 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
268 | return; | |
269 | } | |
77e26cca | 270 | print_mce_head(); |
a0189c70 | 271 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 272 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 273 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
274 | if (!(m->status & MCI_STATUS_VAL)) |
275 | continue; | |
276 | if (!(m->status & MCI_STATUS_UC)) | |
277 | print_mce(m); | |
a0189c70 AK |
278 | } |
279 | /* Now print uncorrected but with the final one last */ | |
280 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
281 | struct mce *m = &mcelog.entry[i]; | |
282 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 283 | continue; |
77e26cca HS |
284 | if (!(m->status & MCI_STATUS_UC)) |
285 | continue; | |
a0189c70 | 286 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 287 | print_mce(m); |
1da177e4 | 288 | } |
a0189c70 | 289 | if (final) |
77e26cca | 290 | print_mce(final); |
3c079792 AK |
291 | if (cpu_missing) |
292 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 293 | print_mce_tail(); |
bd19a5e6 AK |
294 | if (exp) |
295 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
296 | if (!fake_panic) { |
297 | if (panic_timeout == 0) | |
298 | panic_timeout = mce_panic_timeout; | |
299 | panic(msg); | |
300 | } else | |
301 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 302 | } |
1da177e4 | 303 | |
ea149b36 AK |
304 | /* Support code for software error injection */ |
305 | ||
306 | static int msr_to_offset(u32 msr) | |
307 | { | |
308 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 309 | |
ea149b36 AK |
310 | if (msr == rip_msr) |
311 | return offsetof(struct mce, ip); | |
a2d32bcb | 312 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 313 | return offsetof(struct mce, status); |
a2d32bcb | 314 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 315 | return offsetof(struct mce, addr); |
a2d32bcb | 316 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
317 | return offsetof(struct mce, misc); |
318 | if (msr == MSR_IA32_MCG_STATUS) | |
319 | return offsetof(struct mce, mcgstatus); | |
320 | return -1; | |
321 | } | |
322 | ||
5f8c1a54 AK |
323 | /* MSR access wrappers used for error injection */ |
324 | static u64 mce_rdmsrl(u32 msr) | |
325 | { | |
326 | u64 v; | |
11868a2d | 327 | |
ea149b36 AK |
328 | if (__get_cpu_var(injectm).finished) { |
329 | int offset = msr_to_offset(msr); | |
11868a2d | 330 | |
ea149b36 AK |
331 | if (offset < 0) |
332 | return 0; | |
333 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
334 | } | |
11868a2d IM |
335 | |
336 | if (rdmsrl_safe(msr, &v)) { | |
337 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
338 | /* | |
339 | * Return zero in case the access faulted. This should | |
340 | * not happen normally but can happen if the CPU does | |
341 | * something weird, or if the code is buggy. | |
342 | */ | |
343 | v = 0; | |
344 | } | |
345 | ||
5f8c1a54 AK |
346 | return v; |
347 | } | |
348 | ||
349 | static void mce_wrmsrl(u32 msr, u64 v) | |
350 | { | |
ea149b36 AK |
351 | if (__get_cpu_var(injectm).finished) { |
352 | int offset = msr_to_offset(msr); | |
11868a2d | 353 | |
ea149b36 AK |
354 | if (offset >= 0) |
355 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
356 | return; | |
357 | } | |
5f8c1a54 AK |
358 | wrmsrl(msr, v); |
359 | } | |
360 | ||
9b1beaf2 AK |
361 | /* |
362 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
363 | * process context work function. This is vastly simplified because there's | |
364 | * only a single reader and a single writer. | |
365 | */ | |
366 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
367 | ||
368 | struct mce_ring { | |
369 | unsigned short start; | |
370 | unsigned short end; | |
371 | unsigned long ring[MCE_RING_SIZE]; | |
372 | }; | |
373 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
374 | ||
375 | /* Runs with CPU affinity in workqueue */ | |
376 | static int mce_ring_empty(void) | |
377 | { | |
378 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
379 | ||
380 | return r->start == r->end; | |
381 | } | |
382 | ||
383 | static int mce_ring_get(unsigned long *pfn) | |
384 | { | |
385 | struct mce_ring *r; | |
386 | int ret = 0; | |
387 | ||
388 | *pfn = 0; | |
389 | get_cpu(); | |
390 | r = &__get_cpu_var(mce_ring); | |
391 | if (r->start == r->end) | |
392 | goto out; | |
393 | *pfn = r->ring[r->start]; | |
394 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
395 | ret = 1; | |
396 | out: | |
397 | put_cpu(); | |
398 | return ret; | |
399 | } | |
400 | ||
401 | /* Always runs in MCE context with preempt off */ | |
402 | static int mce_ring_add(unsigned long pfn) | |
403 | { | |
404 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
405 | unsigned next; | |
406 | ||
407 | next = (r->end + 1) % MCE_RING_SIZE; | |
408 | if (next == r->start) | |
409 | return -1; | |
410 | r->ring[r->end] = pfn; | |
411 | wmb(); | |
412 | r->end = next; | |
413 | return 0; | |
414 | } | |
415 | ||
88ccbedd | 416 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 417 | { |
04b2b1a4 | 418 | if (mce_disabled) |
5b4408fd | 419 | return 0; |
3d1712c9 | 420 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
421 | } |
422 | ||
9b1beaf2 AK |
423 | static void mce_schedule_work(void) |
424 | { | |
425 | if (!mce_ring_empty()) { | |
426 | struct work_struct *work = &__get_cpu_var(mce_work); | |
427 | if (!work_pending(work)) | |
428 | schedule_work(work); | |
429 | } | |
430 | } | |
431 | ||
1b2797dc HY |
432 | /* |
433 | * Get the address of the instruction at the time of the machine check | |
434 | * error. | |
435 | */ | |
94ad8474 AK |
436 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
437 | { | |
1b2797dc HY |
438 | |
439 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 440 | m->ip = regs->ip; |
94ad8474 AK |
441 | m->cs = regs->cs; |
442 | } else { | |
65ea5b03 | 443 | m->ip = 0; |
94ad8474 AK |
444 | m->cs = 0; |
445 | } | |
1b2797dc | 446 | if (rip_msr) |
5f8c1a54 | 447 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
448 | } |
449 | ||
11868a2d | 450 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
451 | /* |
452 | * Called after interrupts have been reenabled again | |
453 | * when a MCE happened during an interrupts off region | |
454 | * in the kernel. | |
455 | */ | |
456 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
457 | { | |
458 | ack_APIC_irq(); | |
459 | exit_idle(); | |
460 | irq_enter(); | |
9ff36ee9 | 461 | mce_notify_irq(); |
9b1beaf2 | 462 | mce_schedule_work(); |
ccc3c319 AK |
463 | irq_exit(); |
464 | } | |
465 | #endif | |
466 | ||
467 | static void mce_report_event(struct pt_regs *regs) | |
468 | { | |
469 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 470 | mce_notify_irq(); |
9b1beaf2 AK |
471 | /* |
472 | * Triggering the work queue here is just an insurance | |
473 | * policy in case the syscall exit notify handler | |
474 | * doesn't run soon enough or ends up running on the | |
475 | * wrong CPU (can happen when audit sleeps) | |
476 | */ | |
477 | mce_schedule_work(); | |
ccc3c319 AK |
478 | return; |
479 | } | |
480 | ||
481 | #ifdef CONFIG_X86_LOCAL_APIC | |
482 | /* | |
483 | * Without APIC do not notify. The event will be picked | |
484 | * up eventually. | |
485 | */ | |
486 | if (!cpu_has_apic) | |
487 | return; | |
488 | ||
489 | /* | |
490 | * When interrupts are disabled we cannot use | |
491 | * kernel services safely. Trigger an self interrupt | |
492 | * through the APIC to instead do the notification | |
493 | * after interrupts are reenabled again. | |
494 | */ | |
495 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
496 | ||
497 | /* | |
498 | * Wait for idle afterwards again so that we don't leave the | |
499 | * APIC in a non idle state because the normal APIC writes | |
500 | * cannot exclude us. | |
501 | */ | |
502 | apic_wait_icr_idle(); | |
503 | #endif | |
504 | } | |
505 | ||
ca84f696 AK |
506 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
507 | ||
d88203d1 | 508 | /* |
b79109c3 AK |
509 | * Poll for corrected events or events that happened before reset. |
510 | * Those are just logged through /dev/mcelog. | |
511 | * | |
512 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
513 | * |
514 | * Note: spec recommends to panic for fatal unsignalled | |
515 | * errors here. However this would be quite problematic -- | |
516 | * we would need to reimplement the Monarch handling and | |
517 | * it would mess up the exclusion between exception handler | |
518 | * and poll hander -- * so we skip this for now. | |
519 | * These cases should not happen anyways, or only when the CPU | |
520 | * is already totally * confused. In this case it's likely it will | |
521 | * not fully execute the machine check handler either. | |
b79109c3 | 522 | */ |
ee031c31 | 523 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
524 | { |
525 | struct mce m; | |
526 | int i; | |
527 | ||
ca84f696 AK |
528 | __get_cpu_var(mce_poll_count)++; |
529 | ||
b79109c3 AK |
530 | mce_setup(&m); |
531 | ||
5f8c1a54 | 532 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 533 | for (i = 0; i < banks; i++) { |
cebe1820 | 534 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
535 | continue; |
536 | ||
537 | m.misc = 0; | |
538 | m.addr = 0; | |
539 | m.bank = i; | |
540 | m.tsc = 0; | |
541 | ||
542 | barrier(); | |
a2d32bcb | 543 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
544 | if (!(m.status & MCI_STATUS_VAL)) |
545 | continue; | |
546 | ||
547 | /* | |
ed7290d0 AK |
548 | * Uncorrected or signalled events are handled by the exception |
549 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
550 | * |
551 | * TBD do the same check for MCI_STATUS_EN here? | |
552 | */ | |
ed7290d0 AK |
553 | if (!(flags & MCP_UC) && |
554 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
555 | continue; |
556 | ||
557 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 558 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 559 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 560 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
561 | |
562 | if (!(flags & MCP_TIMESTAMP)) | |
563 | m.tsc = 0; | |
564 | /* | |
565 | * Don't get the IP here because it's unlikely to | |
566 | * have anything to do with the actual error location. | |
567 | */ | |
62fdac59 | 568 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
569 | mce_log(&m); |
570 | add_taint(TAINT_MACHINE_CHECK); | |
571 | } | |
b79109c3 AK |
572 | |
573 | /* | |
574 | * Clear state for this bank. | |
575 | */ | |
a2d32bcb | 576 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
577 | } |
578 | ||
579 | /* | |
580 | * Don't clear MCG_STATUS here because it's only defined for | |
581 | * exceptions. | |
582 | */ | |
88921be3 AK |
583 | |
584 | sync_core(); | |
b79109c3 | 585 | } |
ea149b36 | 586 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 587 | |
bd19a5e6 AK |
588 | /* |
589 | * Do a quick check if any of the events requires a panic. | |
590 | * This decides if we keep the events around or clear them. | |
591 | */ | |
592 | static int mce_no_way_out(struct mce *m, char **msg) | |
593 | { | |
594 | int i; | |
595 | ||
596 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 597 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
598 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
599 | return 1; | |
600 | } | |
601 | return 0; | |
602 | } | |
603 | ||
3c079792 AK |
604 | /* |
605 | * Variable to establish order between CPUs while scanning. | |
606 | * Each CPU spins initially until executing is equal its number. | |
607 | */ | |
608 | static atomic_t mce_executing; | |
609 | ||
610 | /* | |
611 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
612 | */ | |
613 | static atomic_t mce_callin; | |
614 | ||
615 | /* | |
616 | * Check if a timeout waiting for other CPUs happened. | |
617 | */ | |
618 | static int mce_timed_out(u64 *t) | |
619 | { | |
620 | /* | |
621 | * The others already did panic for some reason. | |
622 | * Bail out like in a timeout. | |
623 | * rmb() to tell the compiler that system_state | |
624 | * might have been modified by someone else. | |
625 | */ | |
626 | rmb(); | |
627 | if (atomic_read(&mce_paniced)) | |
628 | wait_for_panic(); | |
629 | if (!monarch_timeout) | |
630 | goto out; | |
631 | if ((s64)*t < SPINUNIT) { | |
632 | /* CHECKME: Make panic default for 1 too? */ | |
633 | if (tolerant < 1) | |
634 | mce_panic("Timeout synchronizing machine check over CPUs", | |
635 | NULL, NULL); | |
636 | cpu_missing = 1; | |
637 | return 1; | |
638 | } | |
639 | *t -= SPINUNIT; | |
640 | out: | |
641 | touch_nmi_watchdog(); | |
642 | return 0; | |
643 | } | |
644 | ||
645 | /* | |
646 | * The Monarch's reign. The Monarch is the CPU who entered | |
647 | * the machine check handler first. It waits for the others to | |
648 | * raise the exception too and then grades them. When any | |
649 | * error is fatal panic. Only then let the others continue. | |
650 | * | |
651 | * The other CPUs entering the MCE handler will be controlled by the | |
652 | * Monarch. They are called Subjects. | |
653 | * | |
654 | * This way we prevent any potential data corruption in a unrecoverable case | |
655 | * and also makes sure always all CPU's errors are examined. | |
656 | * | |
680b6cfd | 657 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
658 | * space (not detected by any CPUs) In this case some external agent wants |
659 | * us to shut down, so panic too. | |
660 | * | |
661 | * The other CPUs might still decide to panic if the handler happens | |
662 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
663 | * state and won't corrupt anything by itself. It's ok to let the others | |
664 | * continue for a bit first. | |
665 | * | |
666 | * All the spin loops have timeouts; when a timeout happens a CPU | |
667 | * typically elects itself to be Monarch. | |
668 | */ | |
669 | static void mce_reign(void) | |
670 | { | |
671 | int cpu; | |
672 | struct mce *m = NULL; | |
673 | int global_worst = 0; | |
674 | char *msg = NULL; | |
675 | char *nmsg = NULL; | |
676 | ||
677 | /* | |
678 | * This CPU is the Monarch and the other CPUs have run | |
679 | * through their handlers. | |
680 | * Grade the severity of the errors of all the CPUs. | |
681 | */ | |
682 | for_each_possible_cpu(cpu) { | |
683 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
684 | &nmsg); | |
685 | if (severity > global_worst) { | |
686 | msg = nmsg; | |
687 | global_worst = severity; | |
688 | m = &per_cpu(mces_seen, cpu); | |
689 | } | |
690 | } | |
691 | ||
692 | /* | |
693 | * Cannot recover? Panic here then. | |
694 | * This dumps all the mces in the log buffer and stops the | |
695 | * other CPUs. | |
696 | */ | |
697 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 698 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
699 | |
700 | /* | |
701 | * For UC somewhere we let the CPU who detects it handle it. | |
702 | * Also must let continue the others, otherwise the handling | |
703 | * CPU could deadlock on a lock. | |
704 | */ | |
705 | ||
706 | /* | |
707 | * No machine check event found. Must be some external | |
708 | * source or one CPU is hung. Panic. | |
709 | */ | |
680b6cfd | 710 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
711 | mce_panic("Machine check from unknown source", NULL, NULL); |
712 | ||
713 | /* | |
714 | * Now clear all the mces_seen so that they don't reappear on | |
715 | * the next mce. | |
716 | */ | |
717 | for_each_possible_cpu(cpu) | |
718 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
719 | } | |
720 | ||
721 | static atomic_t global_nwo; | |
722 | ||
723 | /* | |
724 | * Start of Monarch synchronization. This waits until all CPUs have | |
725 | * entered the exception handler and then determines if any of them | |
726 | * saw a fatal event that requires panic. Then it executes them | |
727 | * in the entry order. | |
728 | * TBD double check parallel CPU hotunplug | |
729 | */ | |
7fb06fc9 | 730 | static int mce_start(int *no_way_out) |
3c079792 | 731 | { |
7fb06fc9 | 732 | int order; |
3c079792 AK |
733 | int cpus = num_online_cpus(); |
734 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
735 | ||
7fb06fc9 HS |
736 | if (!timeout) |
737 | return -1; | |
3c079792 | 738 | |
7fb06fc9 | 739 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
740 | /* |
741 | * global_nwo should be updated before mce_callin | |
742 | */ | |
743 | smp_wmb(); | |
a95436e4 | 744 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
745 | |
746 | /* | |
747 | * Wait for everyone. | |
748 | */ | |
749 | while (atomic_read(&mce_callin) != cpus) { | |
750 | if (mce_timed_out(&timeout)) { | |
751 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 752 | return -1; |
3c079792 AK |
753 | } |
754 | ndelay(SPINUNIT); | |
755 | } | |
756 | ||
184e1fdf HY |
757 | /* |
758 | * mce_callin should be read before global_nwo | |
759 | */ | |
760 | smp_rmb(); | |
3c079792 | 761 | |
7fb06fc9 HS |
762 | if (order == 1) { |
763 | /* | |
764 | * Monarch: Starts executing now, the others wait. | |
765 | */ | |
3c079792 | 766 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
767 | } else { |
768 | /* | |
769 | * Subject: Now start the scanning loop one by one in | |
770 | * the original callin order. | |
771 | * This way when there are any shared banks it will be | |
772 | * only seen by one CPU before cleared, avoiding duplicates. | |
773 | */ | |
774 | while (atomic_read(&mce_executing) < order) { | |
775 | if (mce_timed_out(&timeout)) { | |
776 | atomic_set(&global_nwo, 0); | |
777 | return -1; | |
778 | } | |
779 | ndelay(SPINUNIT); | |
780 | } | |
3c079792 AK |
781 | } |
782 | ||
783 | /* | |
7fb06fc9 | 784 | * Cache the global no_way_out state. |
3c079792 | 785 | */ |
7fb06fc9 HS |
786 | *no_way_out = atomic_read(&global_nwo); |
787 | ||
788 | return order; | |
3c079792 AK |
789 | } |
790 | ||
791 | /* | |
792 | * Synchronize between CPUs after main scanning loop. | |
793 | * This invokes the bulk of the Monarch processing. | |
794 | */ | |
795 | static int mce_end(int order) | |
796 | { | |
797 | int ret = -1; | |
798 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
799 | ||
800 | if (!timeout) | |
801 | goto reset; | |
802 | if (order < 0) | |
803 | goto reset; | |
804 | ||
805 | /* | |
806 | * Allow others to run. | |
807 | */ | |
808 | atomic_inc(&mce_executing); | |
809 | ||
810 | if (order == 1) { | |
811 | /* CHECKME: Can this race with a parallel hotplug? */ | |
812 | int cpus = num_online_cpus(); | |
813 | ||
814 | /* | |
815 | * Monarch: Wait for everyone to go through their scanning | |
816 | * loops. | |
817 | */ | |
818 | while (atomic_read(&mce_executing) <= cpus) { | |
819 | if (mce_timed_out(&timeout)) | |
820 | goto reset; | |
821 | ndelay(SPINUNIT); | |
822 | } | |
823 | ||
824 | mce_reign(); | |
825 | barrier(); | |
826 | ret = 0; | |
827 | } else { | |
828 | /* | |
829 | * Subject: Wait for Monarch to finish. | |
830 | */ | |
831 | while (atomic_read(&mce_executing) != 0) { | |
832 | if (mce_timed_out(&timeout)) | |
833 | goto reset; | |
834 | ndelay(SPINUNIT); | |
835 | } | |
836 | ||
837 | /* | |
838 | * Don't reset anything. That's done by the Monarch. | |
839 | */ | |
840 | return 0; | |
841 | } | |
842 | ||
843 | /* | |
844 | * Reset all global state. | |
845 | */ | |
846 | reset: | |
847 | atomic_set(&global_nwo, 0); | |
848 | atomic_set(&mce_callin, 0); | |
849 | barrier(); | |
850 | ||
851 | /* | |
852 | * Let others run again. | |
853 | */ | |
854 | atomic_set(&mce_executing, 0); | |
855 | return ret; | |
856 | } | |
857 | ||
9b1beaf2 AK |
858 | /* |
859 | * Check if the address reported by the CPU is in a format we can parse. | |
860 | * It would be possible to add code for most other cases, but all would | |
861 | * be somewhat complicated (e.g. segment offset would require an instruction | |
862 | * parser). So only support physical addresses upto page granuality for now. | |
863 | */ | |
864 | static int mce_usable_address(struct mce *m) | |
865 | { | |
866 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
867 | return 0; | |
868 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
869 | return 0; | |
870 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
871 | return 0; | |
872 | return 1; | |
873 | } | |
874 | ||
3c079792 AK |
875 | static void mce_clear_state(unsigned long *toclear) |
876 | { | |
877 | int i; | |
878 | ||
879 | for (i = 0; i < banks; i++) { | |
880 | if (test_bit(i, toclear)) | |
a2d32bcb | 881 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
882 | } |
883 | } | |
884 | ||
b79109c3 AK |
885 | /* |
886 | * The actual machine check handler. This only handles real | |
887 | * exceptions when something got corrupted coming in through int 18. | |
888 | * | |
889 | * This is executed in NMI context not subject to normal locking rules. This | |
890 | * implies that most kernel services cannot be safely used. Don't even | |
891 | * think about putting a printk in there! | |
3c079792 AK |
892 | * |
893 | * On Intel systems this is entered on all CPUs in parallel through | |
894 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
895 | * so be always careful when synchronizing with others. | |
1da177e4 | 896 | */ |
e9eee03e | 897 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 898 | { |
3c079792 | 899 | struct mce m, *final; |
1da177e4 | 900 | int i; |
3c079792 AK |
901 | int worst = 0; |
902 | int severity; | |
903 | /* | |
904 | * Establish sequential order between the CPUs entering the machine | |
905 | * check handler. | |
906 | */ | |
7fb06fc9 | 907 | int order; |
bd78432c TH |
908 | /* |
909 | * If no_way_out gets set, there is no safe way to recover from this | |
910 | * MCE. If tolerant is cranked up, we'll try anyway. | |
911 | */ | |
912 | int no_way_out = 0; | |
913 | /* | |
914 | * If kill_it gets set, there might be a way to recover from this | |
915 | * error. | |
916 | */ | |
917 | int kill_it = 0; | |
b79109c3 | 918 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 919 | char *msg = "Unknown"; |
1da177e4 | 920 | |
553f265f AK |
921 | atomic_inc(&mce_entry); |
922 | ||
01ca79f1 AK |
923 | __get_cpu_var(mce_exception_count)++; |
924 | ||
b79109c3 | 925 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 926 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 927 | goto out; |
b79109c3 | 928 | if (!banks) |
32561696 | 929 | goto out; |
1da177e4 | 930 | |
b5f2fa4e AK |
931 | mce_setup(&m); |
932 | ||
5f8c1a54 | 933 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
934 | final = &__get_cpu_var(mces_seen); |
935 | *final = m; | |
936 | ||
680b6cfd HS |
937 | no_way_out = mce_no_way_out(&m, &msg); |
938 | ||
1da177e4 LT |
939 | barrier(); |
940 | ||
ed7290d0 AK |
941 | /* |
942 | * When no restart IP must always kill or panic. | |
943 | */ | |
944 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
945 | kill_it = 1; | |
946 | ||
3c079792 AK |
947 | /* |
948 | * Go through all the banks in exclusion of the other CPUs. | |
949 | * This way we don't report duplicated events on shared banks | |
950 | * because the first one to see it will clear it. | |
951 | */ | |
7fb06fc9 | 952 | order = mce_start(&no_way_out); |
1da177e4 | 953 | for (i = 0; i < banks; i++) { |
b79109c3 | 954 | __clear_bit(i, toclear); |
cebe1820 | 955 | if (!mce_banks[i].ctl) |
1da177e4 | 956 | continue; |
d88203d1 TG |
957 | |
958 | m.misc = 0; | |
1da177e4 LT |
959 | m.addr = 0; |
960 | m.bank = i; | |
1da177e4 | 961 | |
a2d32bcb | 962 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
963 | if ((m.status & MCI_STATUS_VAL) == 0) |
964 | continue; | |
965 | ||
b79109c3 | 966 | /* |
ed7290d0 AK |
967 | * Non uncorrected or non signaled errors are handled by |
968 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 969 | */ |
ed7290d0 AK |
970 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
971 | !no_way_out) | |
b79109c3 AK |
972 | continue; |
973 | ||
974 | /* | |
975 | * Set taint even when machine check was not enabled. | |
976 | */ | |
977 | add_taint(TAINT_MACHINE_CHECK); | |
978 | ||
ed7290d0 | 979 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 980 | |
ed7290d0 AK |
981 | /* |
982 | * When machine check was for corrected handler don't touch, | |
983 | * unless we're panicing. | |
984 | */ | |
985 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
986 | continue; | |
987 | __set_bit(i, toclear); | |
988 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
989 | /* |
990 | * Machine check event was not enabled. Clear, but | |
991 | * ignore. | |
992 | */ | |
993 | continue; | |
1da177e4 LT |
994 | } |
995 | ||
ed7290d0 AK |
996 | /* |
997 | * Kill on action required. | |
998 | */ | |
999 | if (severity == MCE_AR_SEVERITY) | |
1000 | kill_it = 1; | |
1001 | ||
1da177e4 | 1002 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1003 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1004 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1005 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1006 | |
9b1beaf2 AK |
1007 | /* |
1008 | * Action optional error. Queue address for later processing. | |
1009 | * When the ring overflows we just ignore the AO error. | |
1010 | * RED-PEN add some logging mechanism when | |
1011 | * usable_address or mce_add_ring fails. | |
1012 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1013 | */ | |
1014 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1015 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1016 | ||
94ad8474 | 1017 | mce_get_rip(&m, regs); |
b79109c3 | 1018 | mce_log(&m); |
1da177e4 | 1019 | |
3c079792 AK |
1020 | if (severity > worst) { |
1021 | *final = m; | |
1022 | worst = severity; | |
1da177e4 | 1023 | } |
1da177e4 LT |
1024 | } |
1025 | ||
3c079792 AK |
1026 | if (!no_way_out) |
1027 | mce_clear_state(toclear); | |
1028 | ||
e9eee03e | 1029 | /* |
3c079792 AK |
1030 | * Do most of the synchronization with other CPUs. |
1031 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1032 | */ |
3c079792 AK |
1033 | if (mce_end(order) < 0) |
1034 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1035 | |
1036 | /* | |
1037 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1038 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1039 | * |
1040 | * This is mainly used in the case when the system doesn't | |
1041 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1042 | */ |
1043 | if (no_way_out && tolerant < 3) | |
ac960375 | 1044 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1045 | |
1046 | /* | |
1047 | * If the error seems to be unrecoverable, something should be | |
1048 | * done. Try to kill as little as possible. If we can kill just | |
1049 | * one task, do that. If the user has set the tolerance very | |
1050 | * high, don't try to do anything at all. | |
1051 | */ | |
bd78432c | 1052 | |
ed7290d0 AK |
1053 | if (kill_it && tolerant < 3) |
1054 | force_sig(SIGBUS, current); | |
1da177e4 | 1055 | |
e02e68d3 TH |
1056 | /* notify userspace ASAP */ |
1057 | set_thread_flag(TIF_MCE_NOTIFY); | |
1058 | ||
3c079792 AK |
1059 | if (worst > 0) |
1060 | mce_report_event(regs); | |
5f8c1a54 | 1061 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1062 | out: |
553f265f | 1063 | atomic_dec(&mce_entry); |
88921be3 | 1064 | sync_core(); |
1da177e4 | 1065 | } |
ea149b36 | 1066 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1067 | |
9b1beaf2 AK |
1068 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1069 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1070 | { | |
1071 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * Called after mce notification in process context. This code | |
1076 | * is allowed to sleep. Call the high level VM handler to process | |
1077 | * any corrupted pages. | |
1078 | * Assume that the work queue code only calls this one at a time | |
1079 | * per CPU. | |
1080 | * Note we don't disable preemption, so this code might run on the wrong | |
1081 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1082 | * This is merely a fast path to expedite processing in some common | |
1083 | * cases. | |
1084 | */ | |
1085 | void mce_notify_process(void) | |
1086 | { | |
1087 | unsigned long pfn; | |
1088 | mce_notify_irq(); | |
1089 | while (mce_ring_get(&pfn)) | |
1090 | memory_failure(pfn, MCE_VECTOR); | |
1091 | } | |
1092 | ||
1093 | static void mce_process_work(struct work_struct *dummy) | |
1094 | { | |
1095 | mce_notify_process(); | |
1096 | } | |
1097 | ||
15d5f839 DZ |
1098 | #ifdef CONFIG_X86_MCE_INTEL |
1099 | /*** | |
1100 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1101 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1102 | * @status: Event status information |
1103 | * | |
1104 | * This function should be called by the thermal interrupt after the | |
1105 | * event has been processed and the decision was made to log the event | |
1106 | * further. | |
1107 | * | |
1108 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1109 | * and historically has been the register value of the | |
1110 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1111 | */ | |
b5f2fa4e | 1112 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1113 | { |
1114 | struct mce m; | |
1115 | ||
b5f2fa4e | 1116 | mce_setup(&m); |
15d5f839 DZ |
1117 | m.bank = MCE_THERMAL_BANK; |
1118 | m.status = status; | |
15d5f839 DZ |
1119 | mce_log(&m); |
1120 | } | |
1121 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1122 | ||
1da177e4 | 1123 | /* |
8a336b0a TH |
1124 | * Periodic polling timer for "silent" machine check errors. If the |
1125 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1126 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1127 | */ |
1da177e4 | 1128 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1129 | |
245b2e70 | 1130 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1131 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1132 | |
52d168e2 | 1133 | static void mcheck_timer(unsigned long data) |
1da177e4 | 1134 | { |
52d168e2 | 1135 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1136 | int *n; |
52d168e2 AK |
1137 | |
1138 | WARN_ON(smp_processor_id() != data); | |
1139 | ||
e9eee03e | 1140 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1141 | machine_check_poll(MCP_TIMESTAMP, |
1142 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1143 | } |
1da177e4 LT |
1144 | |
1145 | /* | |
e02e68d3 TH |
1146 | * Alert userspace if needed. If we logged an MCE, reduce the |
1147 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1148 | */ |
245b2e70 | 1149 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1150 | if (mce_notify_irq()) |
6298c512 | 1151 | *n = max(*n/2, HZ/100); |
14a02530 | 1152 | else |
6298c512 | 1153 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1154 | |
6298c512 | 1155 | t->expires = jiffies + *n; |
5be6066a | 1156 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1157 | } |
1158 | ||
9bd98405 AK |
1159 | static void mce_do_trigger(struct work_struct *work) |
1160 | { | |
1020bcbc | 1161 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1162 | } |
1163 | ||
1164 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1165 | ||
e02e68d3 | 1166 | /* |
9bd98405 AK |
1167 | * Notify the user(s) about new machine check events. |
1168 | * Can be called from interrupt context, but not from machine check/NMI | |
1169 | * context. | |
e02e68d3 | 1170 | */ |
9ff36ee9 | 1171 | int mce_notify_irq(void) |
e02e68d3 | 1172 | { |
8457c84d AK |
1173 | /* Not more than two messages every minute */ |
1174 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1175 | ||
e02e68d3 | 1176 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1177 | |
1020bcbc | 1178 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1179 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1180 | |
1181 | /* | |
1182 | * There is no risk of missing notifications because | |
1183 | * work_pending is always cleared before the function is | |
1184 | * executed. | |
1185 | */ | |
1020bcbc | 1186 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1187 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1188 | |
8457c84d | 1189 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1190 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1191 | |
1192 | return 1; | |
1da177e4 | 1193 | } |
e02e68d3 TH |
1194 | return 0; |
1195 | } | |
9ff36ee9 | 1196 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1197 | |
cebe1820 AK |
1198 | static int mce_banks_init(void) |
1199 | { | |
1200 | int i; | |
1201 | ||
1202 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1203 | if (!mce_banks) | |
1204 | return -ENOMEM; | |
1205 | for (i = 0; i < banks; i++) { | |
1206 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1207 | |
cebe1820 AK |
1208 | b->ctl = -1ULL; |
1209 | b->init = 1; | |
1210 | } | |
1211 | return 0; | |
1212 | } | |
1213 | ||
d88203d1 | 1214 | /* |
1da177e4 LT |
1215 | * Initialize Machine Checks for a CPU. |
1216 | */ | |
419d6162 | 1217 | static int __cpuinit mce_cap_init(void) |
1da177e4 | 1218 | { |
0d7482e3 | 1219 | unsigned b; |
e9eee03e | 1220 | u64 cap; |
1da177e4 LT |
1221 | |
1222 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1223 | |
1224 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
1225 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
1226 | ||
0d7482e3 AK |
1227 | if (b > MAX_NR_BANKS) { |
1228 | printk(KERN_WARNING | |
1229 | "MCE: Using only %u machine check banks out of %u\n", | |
1230 | MAX_NR_BANKS, b); | |
1231 | b = MAX_NR_BANKS; | |
1232 | } | |
1233 | ||
1234 | /* Don't support asymmetric configurations today */ | |
1235 | WARN_ON(banks != 0 && b != banks); | |
1236 | banks = b; | |
cebe1820 AK |
1237 | if (!mce_banks) { |
1238 | int err = mce_banks_init(); | |
11868a2d | 1239 | |
cebe1820 AK |
1240 | if (err) |
1241 | return err; | |
1da177e4 | 1242 | } |
0d7482e3 | 1243 | |
94ad8474 | 1244 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1245 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1246 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1247 | |
ed7290d0 AK |
1248 | if (cap & MCG_SER_P) |
1249 | mce_ser = 1; | |
1250 | ||
0d7482e3 AK |
1251 | return 0; |
1252 | } | |
1253 | ||
8be91105 | 1254 | static void mce_init(void) |
0d7482e3 | 1255 | { |
e9eee03e | 1256 | mce_banks_t all_banks; |
0d7482e3 AK |
1257 | u64 cap; |
1258 | int i; | |
1259 | ||
b79109c3 AK |
1260 | /* |
1261 | * Log the machine checks left over from the previous reset. | |
1262 | */ | |
ee031c31 | 1263 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1264 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1265 | |
1266 | set_in_cr4(X86_CR4_MCE); | |
1267 | ||
0d7482e3 | 1268 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1269 | if (cap & MCG_CTL_P) |
1270 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1271 | ||
1272 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1273 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1274 | |
cebe1820 | 1275 | if (!b->init) |
06b7a7a5 | 1276 | continue; |
a2d32bcb AK |
1277 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1278 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1279 | } |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | /* Add per CPU specific workarounds here */ | |
df58bee2 | 1283 | static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1284 | { |
e412cd25 IM |
1285 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1286 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1287 | return -EOPNOTSUPP; | |
1288 | } | |
1289 | ||
1da177e4 | 1290 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1291 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1292 | if (c->x86 == 15 && banks > 4) { |
1293 | /* | |
1294 | * disable GART TBL walk error reporting, which | |
1295 | * trips off incorrectly with the IOMMU & 3ware | |
1296 | * & Cerberus: | |
1297 | */ | |
cebe1820 | 1298 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1299 | } |
1300 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1301 | /* | |
1302 | * Lots of broken BIOS around that don't clear them | |
1303 | * by default and leave crap in there. Don't log: | |
1304 | */ | |
911f6a7b | 1305 | mce_bootlog = 0; |
e9eee03e | 1306 | } |
2e6f694f AK |
1307 | /* |
1308 | * Various K7s with broken bank 0 around. Always disable | |
1309 | * by default. | |
1310 | */ | |
203abd67 | 1311 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1312 | mce_banks[0].ctl = 0; |
1da177e4 | 1313 | } |
e583538f | 1314 | |
06b7a7a5 AK |
1315 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1316 | /* | |
1317 | * SDM documents that on family 6 bank 0 should not be written | |
1318 | * because it aliases to another special BIOS controlled | |
1319 | * register. | |
1320 | * But it's not aliased anymore on model 0x1a+ | |
1321 | * Don't ignore bank 0 completely because there could be a | |
1322 | * valid event later, merely don't write CTL0. | |
1323 | */ | |
1324 | ||
cebe1820 AK |
1325 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1326 | mce_banks[0].init = 0; | |
3c079792 AK |
1327 | |
1328 | /* | |
1329 | * All newer Intel systems support MCE broadcasting. Enable | |
1330 | * synchronization with a one second timeout. | |
1331 | */ | |
1332 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1333 | monarch_timeout < 0) | |
1334 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1335 | |
e412cd25 IM |
1336 | /* |
1337 | * There are also broken BIOSes on some Pentium M and | |
1338 | * earlier systems: | |
1339 | */ | |
1340 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1341 | mce_bootlog = 0; |
06b7a7a5 | 1342 | } |
3c079792 AK |
1343 | if (monarch_timeout < 0) |
1344 | monarch_timeout = 0; | |
29b0f591 AK |
1345 | if (mce_bootlog != 0) |
1346 | mce_panic_timeout = 30; | |
e412cd25 IM |
1347 | |
1348 | return 0; | |
d88203d1 | 1349 | } |
1da177e4 | 1350 | |
4efc0670 AK |
1351 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
1352 | { | |
1353 | if (c->x86 != 5) | |
1354 | return; | |
1355 | switch (c->x86_vendor) { | |
1356 | case X86_VENDOR_INTEL: | |
c6978369 | 1357 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1358 | break; |
1359 | case X86_VENDOR_CENTAUR: | |
1360 | winchip_mcheck_init(c); | |
1361 | break; | |
1362 | } | |
1363 | } | |
1364 | ||
cc3ca220 | 1365 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
1366 | { |
1367 | switch (c->x86_vendor) { | |
1368 | case X86_VENDOR_INTEL: | |
1369 | mce_intel_feature_init(c); | |
1370 | break; | |
89b831ef JS |
1371 | case X86_VENDOR_AMD: |
1372 | mce_amd_feature_init(c); | |
1373 | break; | |
1da177e4 LT |
1374 | default: |
1375 | break; | |
1376 | } | |
1377 | } | |
1378 | ||
52d168e2 AK |
1379 | static void mce_init_timer(void) |
1380 | { | |
1381 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1382 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1383 | |
62fdac59 HS |
1384 | if (mce_ignore_ce) |
1385 | return; | |
1386 | ||
6298c512 AK |
1387 | *n = check_interval * HZ; |
1388 | if (!*n) | |
52d168e2 AK |
1389 | return; |
1390 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 1391 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1392 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1393 | } |
1394 | ||
9eda8cb3 AK |
1395 | /* Handle unconfigured int18 (should never happen) */ |
1396 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1397 | { | |
1398 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1399 | smp_processor_id()); | |
1400 | } | |
1401 | ||
1402 | /* Call the installed machine check handler for this CPU setup. */ | |
1403 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1404 | unexpected_machine_check; | |
1405 | ||
d88203d1 | 1406 | /* |
1da177e4 | 1407 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1408 | * Must be called with preempt off: |
1da177e4 | 1409 | */ |
e6982c67 | 1410 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 1411 | { |
4efc0670 AK |
1412 | if (mce_disabled) |
1413 | return; | |
1414 | ||
1415 | mce_ancient_init(c); | |
1416 | ||
5b4408fd | 1417 | if (!mce_available(c)) |
1da177e4 LT |
1418 | return; |
1419 | ||
e412cd25 | 1420 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
04b2b1a4 | 1421 | mce_disabled = 1; |
0d7482e3 AK |
1422 | return; |
1423 | } | |
0d7482e3 | 1424 | |
5d727926 AK |
1425 | machine_check_vector = do_machine_check; |
1426 | ||
8be91105 | 1427 | mce_init(); |
1da177e4 | 1428 | mce_cpu_features(c); |
52d168e2 | 1429 | mce_init_timer(); |
9b1beaf2 | 1430 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
fb253195 BP |
1431 | |
1432 | if (raw_smp_processor_id() == 0) | |
1433 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); | |
1da177e4 LT |
1434 | } |
1435 | ||
1436 | /* | |
1437 | * Character device to read and clear the MCE log. | |
1438 | */ | |
1439 | ||
f528e7ba | 1440 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1441 | static int open_count; /* #times opened */ |
1442 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1443 | |
1444 | static int mce_open(struct inode *inode, struct file *file) | |
1445 | { | |
1446 | spin_lock(&mce_state_lock); | |
1447 | ||
1448 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1449 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1450 | |
f528e7ba TH |
1451 | return -EBUSY; |
1452 | } | |
1453 | ||
1454 | if (file->f_flags & O_EXCL) | |
1455 | open_exclu = 1; | |
1456 | open_count++; | |
1457 | ||
1458 | spin_unlock(&mce_state_lock); | |
1459 | ||
bd78432c | 1460 | return nonseekable_open(inode, file); |
f528e7ba TH |
1461 | } |
1462 | ||
1463 | static int mce_release(struct inode *inode, struct file *file) | |
1464 | { | |
1465 | spin_lock(&mce_state_lock); | |
1466 | ||
1467 | open_count--; | |
1468 | open_exclu = 0; | |
1469 | ||
1470 | spin_unlock(&mce_state_lock); | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
d88203d1 TG |
1475 | static void collect_tscs(void *data) |
1476 | { | |
1da177e4 | 1477 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1478 | |
1da177e4 | 1479 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1480 | } |
1da177e4 | 1481 | |
e9eee03e IM |
1482 | static DEFINE_MUTEX(mce_read_mutex); |
1483 | ||
d88203d1 TG |
1484 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1485 | loff_t *off) | |
1da177e4 | 1486 | { |
e9eee03e | 1487 | char __user *buf = ubuf; |
f0de53bb | 1488 | unsigned long *cpu_tsc; |
ef41df43 | 1489 | unsigned prev, next; |
1da177e4 LT |
1490 | int i, err; |
1491 | ||
6bca67f9 | 1492 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1493 | if (!cpu_tsc) |
1494 | return -ENOMEM; | |
1495 | ||
8c8b8859 | 1496 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1497 | next = rcu_dereference(mcelog.next); |
1498 | ||
1499 | /* Only supports full reads right now */ | |
d88203d1 | 1500 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1501 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1502 | kfree(cpu_tsc); |
e9eee03e | 1503 | |
1da177e4 LT |
1504 | return -EINVAL; |
1505 | } | |
1506 | ||
1507 | err = 0; | |
ef41df43 HY |
1508 | prev = 0; |
1509 | do { | |
1510 | for (i = prev; i < next; i++) { | |
1511 | unsigned long start = jiffies; | |
1512 | ||
1513 | while (!mcelog.entry[i].finished) { | |
1514 | if (time_after_eq(jiffies, start + 2)) { | |
1515 | memset(mcelog.entry + i, 0, | |
1516 | sizeof(struct mce)); | |
1517 | goto timeout; | |
1518 | } | |
1519 | cpu_relax(); | |
673242c1 | 1520 | } |
ef41df43 HY |
1521 | smp_rmb(); |
1522 | err |= copy_to_user(buf, mcelog.entry + i, | |
1523 | sizeof(struct mce)); | |
1524 | buf += sizeof(struct mce); | |
1525 | timeout: | |
1526 | ; | |
673242c1 | 1527 | } |
1da177e4 | 1528 | |
ef41df43 HY |
1529 | memset(mcelog.entry + prev, 0, |
1530 | (next - prev) * sizeof(struct mce)); | |
1531 | prev = next; | |
1532 | next = cmpxchg(&mcelog.next, prev, 0); | |
1533 | } while (next != prev); | |
1da177e4 | 1534 | |
b2b18660 | 1535 | synchronize_sched(); |
1da177e4 | 1536 | |
d88203d1 TG |
1537 | /* |
1538 | * Collect entries that were still getting written before the | |
1539 | * synchronize. | |
1540 | */ | |
15c8b6c1 | 1541 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1542 | |
d88203d1 TG |
1543 | for (i = next; i < MCE_LOG_LEN; i++) { |
1544 | if (mcelog.entry[i].finished && | |
1545 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1546 | err |= copy_to_user(buf, mcelog.entry+i, | |
1547 | sizeof(struct mce)); | |
1da177e4 LT |
1548 | smp_rmb(); |
1549 | buf += sizeof(struct mce); | |
1550 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1551 | } | |
d88203d1 | 1552 | } |
8c8b8859 | 1553 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1554 | kfree(cpu_tsc); |
e9eee03e | 1555 | |
d88203d1 | 1556 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1557 | } |
1558 | ||
e02e68d3 TH |
1559 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1560 | { | |
1561 | poll_wait(file, &mce_wait, wait); | |
1562 | if (rcu_dereference(mcelog.next)) | |
1563 | return POLLIN | POLLRDNORM; | |
1564 | return 0; | |
1565 | } | |
1566 | ||
c68461b6 | 1567 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1568 | { |
1569 | int __user *p = (int __user *)arg; | |
d88203d1 | 1570 | |
1da177e4 | 1571 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1572 | return -EPERM; |
e9eee03e | 1573 | |
1da177e4 | 1574 | switch (cmd) { |
d88203d1 | 1575 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1576 | return put_user(sizeof(struct mce), p); |
1577 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1578 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1579 | case MCE_GETCLEAR_FLAGS: { |
1580 | unsigned flags; | |
d88203d1 TG |
1581 | |
1582 | do { | |
1da177e4 | 1583 | flags = mcelog.flags; |
d88203d1 | 1584 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1585 | |
d88203d1 | 1586 | return put_user(flags, p); |
1da177e4 LT |
1587 | } |
1588 | default: | |
d88203d1 TG |
1589 | return -ENOTTY; |
1590 | } | |
1da177e4 LT |
1591 | } |
1592 | ||
a1ff41bf | 1593 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1594 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1595 | .open = mce_open, |
1596 | .release = mce_release, | |
1597 | .read = mce_read, | |
1598 | .poll = mce_poll, | |
1599 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1600 | }; |
ea149b36 | 1601 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1602 | |
1603 | static struct miscdevice mce_log_device = { | |
1604 | MISC_MCELOG_MINOR, | |
1605 | "mcelog", | |
1606 | &mce_chrdev_ops, | |
1607 | }; | |
1608 | ||
13503fa9 | 1609 | /* |
62fdac59 HS |
1610 | * mce=off Disables machine check |
1611 | * mce=no_cmci Disables CMCI | |
1612 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1613 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1614 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1615 | * monarchtimeout is how long to wait for other CPUs on machine | |
1616 | * check, or 0 to not wait | |
13503fa9 HS |
1617 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1618 | * mce=nobootlog Don't log MCEs from before booting. | |
1619 | */ | |
1da177e4 LT |
1620 | static int __init mcheck_enable(char *str) |
1621 | { | |
e3346fc4 | 1622 | if (*str == 0) { |
4efc0670 | 1623 | enable_p5_mce(); |
e3346fc4 BZ |
1624 | return 1; |
1625 | } | |
4efc0670 AK |
1626 | if (*str == '=') |
1627 | str++; | |
1da177e4 | 1628 | if (!strcmp(str, "off")) |
04b2b1a4 | 1629 | mce_disabled = 1; |
62fdac59 HS |
1630 | else if (!strcmp(str, "no_cmci")) |
1631 | mce_cmci_disabled = 1; | |
1632 | else if (!strcmp(str, "dont_log_ce")) | |
1633 | mce_dont_log_ce = 1; | |
1634 | else if (!strcmp(str, "ignore_ce")) | |
1635 | mce_ignore_ce = 1; | |
13503fa9 HS |
1636 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1637 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1638 | else if (isdigit(str[0])) { |
8c566ef5 | 1639 | get_option(&str, &tolerant); |
3c079792 AK |
1640 | if (*str == ',') { |
1641 | ++str; | |
1642 | get_option(&str, &monarch_timeout); | |
1643 | } | |
1644 | } else { | |
4efc0670 | 1645 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1646 | str); |
1647 | return 0; | |
1648 | } | |
9b41046c | 1649 | return 1; |
1da177e4 | 1650 | } |
4efc0670 | 1651 | __setup("mce", mcheck_enable); |
1da177e4 | 1652 | |
d88203d1 | 1653 | /* |
1da177e4 | 1654 | * Sysfs support |
d88203d1 | 1655 | */ |
1da177e4 | 1656 | |
973a2dd1 AK |
1657 | /* |
1658 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1659 | * them later. | |
1660 | */ | |
1661 | static int mce_disable(void) | |
1662 | { | |
1663 | int i; | |
1664 | ||
06b7a7a5 | 1665 | for (i = 0; i < banks; i++) { |
cebe1820 | 1666 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1667 | |
cebe1820 | 1668 | if (b->init) |
a2d32bcb | 1669 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1670 | } |
973a2dd1 AK |
1671 | return 0; |
1672 | } | |
1673 | ||
1674 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1675 | { | |
1676 | return mce_disable(); | |
1677 | } | |
1678 | ||
1679 | static int mce_shutdown(struct sys_device *dev) | |
1680 | { | |
1681 | return mce_disable(); | |
1682 | } | |
1683 | ||
e9eee03e IM |
1684 | /* |
1685 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1686 | * Only one CPU is active at this time, the others get re-added later using | |
1687 | * CPU hotplug: | |
1688 | */ | |
1da177e4 LT |
1689 | static int mce_resume(struct sys_device *dev) |
1690 | { | |
8be91105 | 1691 | mce_init(); |
6ec68bff | 1692 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1693 | |
1da177e4 LT |
1694 | return 0; |
1695 | } | |
1696 | ||
52d168e2 AK |
1697 | static void mce_cpu_restart(void *data) |
1698 | { | |
1699 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1700 | if (!mce_available(¤t_cpu_data)) |
1701 | return; | |
1702 | mce_init(); | |
52d168e2 AK |
1703 | mce_init_timer(); |
1704 | } | |
1705 | ||
1da177e4 | 1706 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1707 | static void mce_restart(void) |
1708 | { | |
52d168e2 | 1709 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1710 | } |
1711 | ||
9af43b54 HS |
1712 | /* Toggle features for corrected errors */ |
1713 | static void mce_disable_ce(void *all) | |
1714 | { | |
1715 | if (!mce_available(¤t_cpu_data)) | |
1716 | return; | |
1717 | if (all) | |
1718 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1719 | cmci_clear(); | |
1720 | } | |
1721 | ||
1722 | static void mce_enable_ce(void *all) | |
1723 | { | |
1724 | if (!mce_available(¤t_cpu_data)) | |
1725 | return; | |
1726 | cmci_reenable(); | |
1727 | cmci_recheck(); | |
1728 | if (all) | |
1729 | mce_init_timer(); | |
1730 | } | |
1731 | ||
1da177e4 | 1732 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1733 | .suspend = mce_suspend, |
1734 | .shutdown = mce_shutdown, | |
1735 | .resume = mce_resume, | |
1736 | .name = "machinecheck", | |
1da177e4 LT |
1737 | }; |
1738 | ||
cb491fca | 1739 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1740 | |
1741 | __cpuinitdata | |
1742 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1743 | |
cebe1820 AK |
1744 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1745 | { | |
1746 | return container_of(attr, struct mce_bank, attr); | |
1747 | } | |
0d7482e3 AK |
1748 | |
1749 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1750 | char *buf) | |
1751 | { | |
cebe1820 | 1752 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1753 | } |
1754 | ||
1755 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1756 | const char *buf, size_t size) |
0d7482e3 | 1757 | { |
9319cec8 | 1758 | u64 new; |
e9eee03e | 1759 | |
9319cec8 | 1760 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1761 | return -EINVAL; |
e9eee03e | 1762 | |
cebe1820 | 1763 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1764 | mce_restart(); |
e9eee03e | 1765 | |
9319cec8 | 1766 | return size; |
0d7482e3 | 1767 | } |
a98f0dd3 | 1768 | |
e9eee03e IM |
1769 | static ssize_t |
1770 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1771 | { |
1020bcbc | 1772 | strcpy(buf, mce_helper); |
a98f0dd3 | 1773 | strcat(buf, "\n"); |
1020bcbc | 1774 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1775 | } |
1776 | ||
4a0b2b4d | 1777 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1778 | const char *buf, size_t siz) |
a98f0dd3 AK |
1779 | { |
1780 | char *p; | |
e9eee03e | 1781 | |
1020bcbc HS |
1782 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1783 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1784 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1785 | |
e9084ec9 | 1786 | if (p) |
e9eee03e IM |
1787 | *p = 0; |
1788 | ||
e9084ec9 | 1789 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1790 | } |
1791 | ||
9af43b54 HS |
1792 | static ssize_t set_ignore_ce(struct sys_device *s, |
1793 | struct sysdev_attribute *attr, | |
1794 | const char *buf, size_t size) | |
1795 | { | |
1796 | u64 new; | |
1797 | ||
1798 | if (strict_strtoull(buf, 0, &new) < 0) | |
1799 | return -EINVAL; | |
1800 | ||
1801 | if (mce_ignore_ce ^ !!new) { | |
1802 | if (new) { | |
1803 | /* disable ce features */ | |
1804 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1805 | mce_ignore_ce = 1; | |
1806 | } else { | |
1807 | /* enable ce features */ | |
1808 | mce_ignore_ce = 0; | |
1809 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1810 | } | |
1811 | } | |
1812 | return size; | |
1813 | } | |
1814 | ||
1815 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1816 | struct sysdev_attribute *attr, | |
1817 | const char *buf, size_t size) | |
1818 | { | |
1819 | u64 new; | |
1820 | ||
1821 | if (strict_strtoull(buf, 0, &new) < 0) | |
1822 | return -EINVAL; | |
1823 | ||
1824 | if (mce_cmci_disabled ^ !!new) { | |
1825 | if (new) { | |
1826 | /* disable cmci */ | |
1827 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1828 | mce_cmci_disabled = 1; | |
1829 | } else { | |
1830 | /* enable cmci */ | |
1831 | mce_cmci_disabled = 0; | |
1832 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1833 | } | |
1834 | } | |
1835 | return size; | |
1836 | } | |
1837 | ||
b56f642d AK |
1838 | static ssize_t store_int_with_restart(struct sys_device *s, |
1839 | struct sysdev_attribute *attr, | |
1840 | const char *buf, size_t size) | |
1841 | { | |
1842 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1843 | mce_restart(); | |
1844 | return ret; | |
1845 | } | |
1846 | ||
a98f0dd3 | 1847 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1848 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1849 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1850 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1851 | |
b56f642d AK |
1852 | static struct sysdev_ext_attribute attr_check_interval = { |
1853 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1854 | store_int_with_restart), | |
1855 | &check_interval | |
1856 | }; | |
e9eee03e | 1857 | |
9af43b54 HS |
1858 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1859 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1860 | &mce_ignore_ce | |
1861 | }; | |
1862 | ||
1863 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1864 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1865 | &mce_cmci_disabled |
1866 | }; | |
1867 | ||
cb491fca | 1868 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1869 | &attr_tolerant.attr, |
1870 | &attr_check_interval.attr, | |
1871 | &attr_trigger, | |
3c079792 | 1872 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1873 | &attr_dont_log_ce.attr, |
1874 | &attr_ignore_ce.attr, | |
1875 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1876 | NULL |
1877 | }; | |
1da177e4 | 1878 | |
cb491fca | 1879 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1880 | |
e9eee03e | 1881 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1882 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1883 | { |
1884 | int err; | |
b1f49f95 | 1885 | int i, j; |
92cb7612 | 1886 | |
90367556 | 1887 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1888 | return -EIO; |
1889 | ||
cb491fca IM |
1890 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1891 | per_cpu(mce_dev, cpu).id = cpu; | |
1892 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1893 | |
cb491fca | 1894 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1895 | if (err) |
1896 | return err; | |
1897 | ||
cb491fca IM |
1898 | for (i = 0; mce_attrs[i]; i++) { |
1899 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1900 | if (err) |
1901 | goto error; | |
1902 | } | |
b1f49f95 | 1903 | for (j = 0; j < banks; j++) { |
cb491fca | 1904 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1905 | &mce_banks[j].attr); |
0d7482e3 AK |
1906 | if (err) |
1907 | goto error2; | |
1908 | } | |
cb491fca | 1909 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1910 | |
d435d862 | 1911 | return 0; |
0d7482e3 | 1912 | error2: |
b1f49f95 | 1913 | while (--j >= 0) |
cebe1820 | 1914 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1915 | error: |
cb491fca | 1916 | while (--i >= 0) |
cebe1820 | 1917 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1918 | |
1919 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1920 | |
91c6d400 AK |
1921 | return err; |
1922 | } | |
1923 | ||
2d9cd6c2 | 1924 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1925 | { |
73ca5358 SL |
1926 | int i; |
1927 | ||
cb491fca | 1928 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1929 | return; |
1930 | ||
cb491fca IM |
1931 | for (i = 0; mce_attrs[i]; i++) |
1932 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1933 | ||
0d7482e3 | 1934 | for (i = 0; i < banks; i++) |
cebe1820 | 1935 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1936 | |
1937 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1938 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1939 | } |
91c6d400 | 1940 | |
d6b75584 | 1941 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1942 | static void mce_disable_cpu(void *h) |
d6b75584 | 1943 | { |
88ccbedd | 1944 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1945 | int i; |
d6b75584 AK |
1946 | |
1947 | if (!mce_available(¤t_cpu_data)) | |
1948 | return; | |
88ccbedd AK |
1949 | if (!(action & CPU_TASKS_FROZEN)) |
1950 | cmci_clear(); | |
06b7a7a5 | 1951 | for (i = 0; i < banks; i++) { |
cebe1820 | 1952 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1953 | |
cebe1820 | 1954 | if (b->init) |
a2d32bcb | 1955 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1956 | } |
d6b75584 AK |
1957 | } |
1958 | ||
ec5b3d32 | 1959 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1960 | { |
88ccbedd | 1961 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1962 | int i; |
d6b75584 AK |
1963 | |
1964 | if (!mce_available(¤t_cpu_data)) | |
1965 | return; | |
e9eee03e | 1966 | |
88ccbedd AK |
1967 | if (!(action & CPU_TASKS_FROZEN)) |
1968 | cmci_reenable(); | |
06b7a7a5 | 1969 | for (i = 0; i < banks; i++) { |
cebe1820 | 1970 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1971 | |
cebe1820 | 1972 | if (b->init) |
a2d32bcb | 1973 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 1974 | } |
d6b75584 AK |
1975 | } |
1976 | ||
91c6d400 | 1977 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1978 | static int __cpuinit |
1979 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1980 | { |
1981 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1982 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1983 | |
1984 | switch (action) { | |
bae19fe0 AH |
1985 | case CPU_ONLINE: |
1986 | case CPU_ONLINE_FROZEN: | |
1987 | mce_create_device(cpu); | |
8735728e RW |
1988 | if (threshold_cpu_callback) |
1989 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1990 | break; |
91c6d400 | 1991 | case CPU_DEAD: |
8bb78442 | 1992 | case CPU_DEAD_FROZEN: |
8735728e RW |
1993 | if (threshold_cpu_callback) |
1994 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1995 | mce_remove_device(cpu); |
1996 | break; | |
52d168e2 AK |
1997 | case CPU_DOWN_PREPARE: |
1998 | case CPU_DOWN_PREPARE_FROZEN: | |
1999 | del_timer_sync(t); | |
88ccbedd | 2000 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2001 | break; |
2002 | case CPU_DOWN_FAILED: | |
2003 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 | 2004 | t->expires = round_jiffies(jiffies + |
245b2e70 | 2005 | __get_cpu_var(mce_next_interval)); |
52d168e2 | 2006 | add_timer_on(t, cpu); |
88ccbedd AK |
2007 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2008 | break; | |
2009 | case CPU_POST_DEAD: | |
2010 | /* intentionally ignoring frozen here */ | |
2011 | cmci_rediscover(cpu); | |
52d168e2 | 2012 | break; |
91c6d400 | 2013 | } |
bae19fe0 | 2014 | return NOTIFY_OK; |
91c6d400 AK |
2015 | } |
2016 | ||
1e35669d | 2017 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2018 | .notifier_call = mce_cpu_callback, |
2019 | }; | |
2020 | ||
cebe1820 | 2021 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2022 | { |
2023 | int i; | |
2024 | ||
0d7482e3 | 2025 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2026 | struct mce_bank *b = &mce_banks[i]; |
2027 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2028 | |
cebe1820 AK |
2029 | a->attr.name = b->attrname; |
2030 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2031 | |
2032 | a->attr.mode = 0644; | |
2033 | a->show = show_bank; | |
2034 | a->store = set_bank; | |
0d7482e3 | 2035 | } |
0d7482e3 AK |
2036 | } |
2037 | ||
91c6d400 AK |
2038 | static __init int mce_init_device(void) |
2039 | { | |
2040 | int err; | |
2041 | int i = 0; | |
2042 | ||
1da177e4 LT |
2043 | if (!mce_available(&boot_cpu_data)) |
2044 | return -EIO; | |
0d7482e3 | 2045 | |
e92fae06 | 2046 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2047 | |
cebe1820 | 2048 | mce_init_banks(); |
0d7482e3 | 2049 | |
1da177e4 | 2050 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2051 | if (err) |
2052 | return err; | |
91c6d400 AK |
2053 | |
2054 | for_each_online_cpu(i) { | |
d435d862 AM |
2055 | err = mce_create_device(i); |
2056 | if (err) | |
2057 | return err; | |
91c6d400 AK |
2058 | } |
2059 | ||
be6b5a35 | 2060 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2061 | misc_register(&mce_log_device); |
e9eee03e | 2062 | |
1da177e4 | 2063 | return err; |
1da177e4 | 2064 | } |
91c6d400 | 2065 | |
1da177e4 | 2066 | device_initcall(mce_init_device); |
a988d334 | 2067 | |
d7c3c9a6 AK |
2068 | /* |
2069 | * Old style boot options parsing. Only for compatibility. | |
2070 | */ | |
2071 | static int __init mcheck_disable(char *str) | |
2072 | { | |
2073 | mce_disabled = 1; | |
2074 | return 1; | |
2075 | } | |
2076 | __setup("nomce", mcheck_disable); | |
a988d334 | 2077 | |
5be9ed25 HY |
2078 | #ifdef CONFIG_DEBUG_FS |
2079 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2080 | { |
5be9ed25 | 2081 | static struct dentry *dmce; |
a988d334 | 2082 | |
5be9ed25 HY |
2083 | if (!dmce) |
2084 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2085 | |
5be9ed25 HY |
2086 | return dmce; |
2087 | } | |
a988d334 | 2088 | |
bf783f9f HY |
2089 | static void mce_reset(void) |
2090 | { | |
2091 | cpu_missing = 0; | |
2092 | atomic_set(&mce_fake_paniced, 0); | |
2093 | atomic_set(&mce_executing, 0); | |
2094 | atomic_set(&mce_callin, 0); | |
2095 | atomic_set(&global_nwo, 0); | |
2096 | } | |
a988d334 | 2097 | |
bf783f9f HY |
2098 | static int fake_panic_get(void *data, u64 *val) |
2099 | { | |
2100 | *val = fake_panic; | |
2101 | return 0; | |
a988d334 IM |
2102 | } |
2103 | ||
bf783f9f | 2104 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2105 | { |
bf783f9f HY |
2106 | mce_reset(); |
2107 | fake_panic = val; | |
2108 | return 0; | |
a988d334 | 2109 | } |
a988d334 | 2110 | |
bf783f9f HY |
2111 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2112 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2113 | |
bf783f9f | 2114 | static int __init mce_debugfs_init(void) |
d7c3c9a6 | 2115 | { |
bf783f9f HY |
2116 | struct dentry *dmce, *ffake_panic; |
2117 | ||
2118 | dmce = mce_get_debugfs_dir(); | |
2119 | if (!dmce) | |
2120 | return -ENOMEM; | |
2121 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2122 | &fake_panic_fops); | |
2123 | if (!ffake_panic) | |
2124 | return -ENOMEM; | |
2125 | ||
2126 | return 0; | |
d7c3c9a6 | 2127 | } |
bf783f9f | 2128 | late_initcall(mce_debugfs_init); |
5be9ed25 | 2129 | #endif |