[net-next-2.6.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/ds.h>
#include <asm/bugs.h>

#ifdef CONFIG_X86_64
#include <asm/topology.h>
#include <asm/numa_64.h>
#endif

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	u64 misc_enable;

	/* Unmask CPUID levels if masked */
	if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
	    (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
		misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
		wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
		c->cpuid_level = cpuid_eax(0);
	}

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#else
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
#endif

	/*
	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	 * with P/T states and does not stop in deep C-states
	 */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	}

}

#ifdef CONFIG_X86_32
/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	/*
	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	 * model 3 mask 3
	 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * P4 Xeon errata 037 workaround.
	 * Hardware prefetcher may cause stale data to be loaded into the cache.
	 */
	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & (1<<9)) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= (1<<9);	/* Disable hw prefetching */
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);


#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif
}
#else
static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
}
#endif

static void __cpuinit srat_detect_node(void)
{
#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	unsigned node;
	int cpu = smp_processor_id();
	int apicid = hard_smp_processor_id();

	/* Don't do the funky fallback heuristics the AMD version employs
	   for now. */
	node = apicid_to_node[apicid];
	if (node == NUMA_NO_NODE || !node_online(node))
		node = first_node(node_online_map);
	numa_set_node(cpu, node);

	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
#endif
}

/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	/* Intel VMX MSR indicated features */
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	clear_cpu_cap(c, X86_FEATURE_VNMI);
	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	clear_cpu_cap(c, X86_FEATURE_EPT);
	clear_cpu_cap(c, X86_FEATURE_VPID);

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;

	early_init_intel(c);

	intel_workarounds(c);

	/*
	 * Detect the extended topology information if available. This
	 * will reinitialise the initial_apicid which will be used
	 * in init_intel_cacheinfo()
	 */
	detect_extended_topology(c);

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
		ds_init_intel(c);
	}

#ifdef CONFIG_X86_64
	if (c->x86 == 15)
		c->x86_cache_alignment = c->x86_clflush_size * 2;
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
#else
	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		char *p = NULL;

		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}

		if (p)
			strcpy(c->x86_model_id, p);
	}

	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
#endif

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
#ifdef CONFIG_X86_32
		detect_ht(c);
#endif
	}

	/* Work around errata */
	srat_detect_node();

	if (cpu_has(c, X86_FEATURE_VMX))
		detect_vmx_virtcap(c);
}

#ifdef CONFIG_X86_32
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}
#endif

static struct cpu_dev intel_cpu_dev __cpuinitdata = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
#ifdef CONFIG_X86_32
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_size_cache	= intel_size_cache,
#endif
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
	7	#include <linux/thread_info.h>
53e86b91	8	#include <linux/module.h>
1da177e4 LT	9
1da177e4 LT	10	#include <asm/processor.h>
d72b1b4f	11	#include <asm/pgtable.h>
1da177e4 LT	12	#include <asm/msr.h>
1da177e4 LT	13	#include <asm/uaccess.h>
eee3af4a	14	#include <asm/ds.h>
73bdb73f	15	#include <asm/bugs.h>
1da177e4	16
185f3b9d YL	17	#ifdef CONFIG_X86_64
	18	#include <asm/topology.h>
	19	#include <asm/numa_64.h>
	20	#endif
	21
1da177e4 LT	22	#include "cpu.h"
	23
	24	#ifdef CONFIG_X86_LOCAL_APIC
	25	#include <asm/mpspec.h>
	26	#include <asm/apic.h>
	27	#include <mach_apic.h>
	28	#endif
	29
03ae5768	30	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	31	{
066941bd PA	32	u64 misc_enable;
	33
	34	/* Unmask CPUID levels if masked */
	35	if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
	36	(misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
	37	misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
	38	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	39	c->cpuid_level = cpuid_eax(0);
	40	}
	41
2b16a235 AK	42	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	43	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	44	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d YL	45
	46	#ifdef CONFIG_X86_64
	47	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	48	#else
	49	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	50	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	51	c->x86_cache_alignment = 128;
	52	#endif
40fb1715 VP	53
	54	/*
	55	* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	56	* with P/T states and does not stop in deep C-states
	57	*/
	58	if (c->x86_power & (1 << 8)) {
	59	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	60	set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	61	}
	62
1da177e4 LT	63	}
1da177e4 LT	64
185f3b9d	65	#ifdef CONFIG_X86_32
1da177e4 LT	66	/*
	67	* Early probe support logic for ppro memory erratum #50
	68	*
	69	* This is called before we do cpu ident work
	70	*/
65eb6b43	71
3bc9b76b	72	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	73	{
	74	/* Uses data from early_cpu_detect now */
	75	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	76	boot_cpu_data.x86 == 6 &&
	77	boot_cpu_data.x86_model == 1 &&
	78	boot_cpu_data.x86_mask < 8) {
	79	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	80	return 1;
	81	}
	82	return 0;
	83	}
65eb6b43	84
4052704d YL	85	#ifdef CONFIG_X86_F00F_BUG
	86	static void __cpuinit trap_init_f00f_bug(void)
	87	{
	88	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
1da177e4	89
4052704d YL	90	/*
	91	* Update the IDT descriptor and reload the IDT so that
	92	* it uses the read-only mapped virtual address.
	93	*/
	94	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	95	load_idt(&idt_descr);
	96	}
	97	#endif
	98
	99	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	100	{
	101	unsigned long lo, hi;
	102
4052704d YL	103	#ifdef CONFIG_X86_F00F_BUG
	104	/*
	105	* All current models of Pentium and Pentium with MMX technology CPUs
	106	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	107	* Note that the workaround only should be initialized once...
	108	*/
	109	c->f00f_bug = 0;
	110	if (!paravirt_enabled() && c->x86 == 5) {
	111	static int f00f_workaround_enabled;
	112
	113	c->f00f_bug = 1;
	114	if (!f00f_workaround_enabled) {
	115	trap_init_f00f_bug();
	116	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	117	f00f_workaround_enabled = 1;
	118	}
	119	}
	120	#endif
	121
	122	/*
	123	* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	124	* model 3 mask 3
	125	*/
	126	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	127	clear_cpu_cap(c, X86_FEATURE_SEP);
	128
	129	/*
	130	* P4 Xeon errata 037 workaround.
	131	* Hardware prefetcher may cause stale data to be loaded into the cache.
	132	*/
1da177e4	133	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	134	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
1da177e4 LT	135	if ((lo & (1<<9)) == 0) {
	136	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
	137	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
	138	lo \|= (1<<9); /* Disable hw prefetching */
	139	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	140	}
	141	}
1da177e4	142
4052704d YL	143	/*
	144	* See if we have a good local APIC by checking for buggy Pentia,
	145	* i.e. all B steppings and the C2 stepping of P54C when using their
	146	* integrated APIC (see 11AP erratum in "Pentium Processor
	147	* Specification Update").
	148	*/
	149	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	150	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	151	set_cpu_cap(c, X86_FEATURE_11AP);
185f3b9d	152
185f3b9d	153
4052704d	154	#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d	155	/*
4052704d	156	* Set up the preferred alignment for movsl bulk memory moves
185f3b9d	157	*/
4052704d YL	158	switch (c->x86) {
	159	case 4: /* 486: untested */
	160	break;
	161	case 5: /* Old Pentia: untested */
	162	break;
	163	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	164	movsl_mask.mask = 7;
	165	break;
	166	case 15: /* P4 is OK down to 8-byte alignment */
	167	movsl_mask.mask = 7;
	168	break;
	169	}
185f3b9d	170	#endif
4052704d YL	171
	172	#ifdef CONFIG_X86_NUMAQ
	173	numaq_tsc_disable();
	174	#endif
	175	}
	176	#else
	177	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
	178	{
	179	}
185f3b9d YL	180	#endif
	181
	182	static void __cpuinit srat_detect_node(void)
	183	{
	184	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	185	unsigned node;
	186	int cpu = smp_processor_id();
	187	int apicid = hard_smp_processor_id();
	188
	189	/* Don't do the funky fallback heuristics the AMD version employs
	190	for now. */
	191	node = apicid_to_node[apicid];
	192	if (node == NUMA_NO_NODE \|\| !node_online(node))
	193	node = first_node(node_online_map);
	194	numa_set_node(cpu, node);
	195
823b259b	196	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
185f3b9d YL	197	#endif
	198	}
	199
3dd9d514 AK	200	/*
	201	* find out the number of processor cores on the die
	202	*/
f69feff7	203	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	204	{
f2ab4461	205	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	206
	207	if (c->cpuid_level < 4)
	208	return 1;
	209
f2ab4461 ZA	210	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	211	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	212	if (eax & 0x1f)
	213	return ((eax >> 26) + 1);
	214	else
	215	return 1;
	216	}
	217
e38e05a8 SY	218	static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
	219	{
	220	/* Intel VMX MSR indicated features */
	221	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	222	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	223	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	224	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	225	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	226	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	227
	228	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	229
	230	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	231	clear_cpu_cap(c, X86_FEATURE_VNMI);
	232	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	233	clear_cpu_cap(c, X86_FEATURE_EPT);
	234	clear_cpu_cap(c, X86_FEATURE_VPID);
	235
	236	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	237	msr_ctl = vmx_msr_high \| vmx_msr_low;
	238	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	239	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	240	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	241	set_cpu_cap(c, X86_FEATURE_VNMI);
	242	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	243	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	244	vmx_msr_low, vmx_msr_high);
	245	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	246	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	247	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	248	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	249	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	250	set_cpu_cap(c, X86_FEATURE_EPT);
	251	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	252	set_cpu_cap(c, X86_FEATURE_VPID);
	253	}
	254	}
	255
3bc9b76b	256	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	257	{
1da177e4 LT	258	unsigned int l2 = 0;
1da177e4	259
2b16a235 AK	260	early_init_intel(c);
2b16a235 AK	261
4052704d	262	intel_workarounds(c);
1da177e4	263
345077cd SS	264	/*
	265	* Detect the extended topology information if available. This
	266	* will reinitialise the initial_apicid which will be used
	267	* in init_intel_cacheinfo()
	268	*/
	269	detect_extended_topology(c);
	270
1da177e4	271	l2 = init_intel_cacheinfo(c);
65eb6b43	272	if (c->cpuid_level > 9) {
0080e667 VP	273	unsigned eax = cpuid_eax(10);
	274	/* Check for version and the number of counters */
	275	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	276	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	277	}
1da177e4	278
4052704d YL	279	if (cpu_has_xmm2)
	280	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	281	if (cpu_has_ds) {
	282	unsigned int l1;
	283	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
	284	if (!(l1 & (1<<11)))
	285	set_cpu_cap(c, X86_FEATURE_BTS);
	286	if (!(l1 & (1<<12)))
	287	set_cpu_cap(c, X86_FEATURE_PEBS);
	288	ds_init_intel(c);
	289	}
1da177e4	290
4052704d YL	291	#ifdef CONFIG_X86_64
	292	if (c->x86 == 15)
	293	c->x86_cache_alignment = c->x86_clflush_size * 2;
	294	if (c->x86 == 6)
	295	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	296	#else
65eb6b43 PC	297	/*
	298	* Names for the Pentium II/Celeron processors
	299	* detectable only by also checking the cache size.
	300	* Dixon is NOT a Celeron.
	301	*/
1da177e4	302	if (c->x86 == 6) {
4052704d YL	303	char *p = NULL;
4052704d YL	304
1da177e4 LT	305	switch (c->x86_model) {
	306	case 5:
	307	if (c->x86_mask == 0) {
	308	if (l2 == 0)
	309	p = "Celeron (Covington)";
	310	else if (l2 == 256)
	311	p = "Mobile Pentium II (Dixon)";
	312	}
	313	break;
65eb6b43	314
1da177e4 LT	315	case 6:
	316	if (l2 == 128)
	317	p = "Celeron (Mendocino)";
	318	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	319	p = "Celeron-A";
	320	break;
65eb6b43	321
1da177e4 LT	322	case 8:
	323	if (l2 == 128)
	324	p = "Celeron (Coppermine)";
	325	break;
	326	}
1da177e4	327
4052704d YL	328	if (p)
4052704d YL	329	strcpy(c->x86_model_id, p);
1da177e4	330	}
1da177e4	331
185f3b9d YL	332	if (c->x86 == 15)
	333	set_cpu_cap(c, X86_FEATURE_P4);
	334	if (c->x86 == 6)
	335	set_cpu_cap(c, X86_FEATURE_P3);
f4166c54	336	#endif
185f3b9d	337
185f3b9d YL	338	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	339	/*
	340	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	341	* detection.
	342	*/
	343	c->x86_max_cores = intel_num_cpu_cores(c);
	344	#ifdef CONFIG_X86_32
	345	detect_ht(c);
	346	#endif
	347	}
	348
	349	/* Work around errata */
	350	srat_detect_node();
e38e05a8 SY	351
	352	if (cpu_has(c, X86_FEATURE_VMX))
	353	detect_vmx_virtcap(c);
42ed458a	354	}
1da177e4	355
185f3b9d	356	#ifdef CONFIG_X86_32
65eb6b43	357	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	358	{
65eb6b43 PC	359	/*
65eb6b43 PC	360	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	361	* One has 256kb of cache, the other 512. We have no way
	362	* to determine which, so we use a boottime override
	363	* for the 512kb model, and assume 256 otherwise.
	364	*/
	365	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	366	size = 256;
	367	return size;
	368	}
185f3b9d	369	#endif
1da177e4	370
3bc9b76b	371	static struct cpu_dev intel_cpu_dev __cpuinitdata = {
1da177e4	372	.c_vendor = "Intel",
65eb6b43	373	.c_ident = { "GenuineIntel" },
185f3b9d	374	#ifdef CONFIG_X86_32
1da177e4	375	.c_models = {
65eb6b43 PC	376	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	377	{
	378	[0] = "486 DX-25/33",
	379	[1] = "486 DX-50",
	380	[2] = "486 SX",
	381	[3] = "486 DX/2",
	382	[4] = "486 SL",
	383	[5] = "486 SX/2",
	384	[7] = "486 DX/2-WB",
	385	[8] = "486 DX/4",
1da177e4 LT	386	[9] = "486 DX/4-WB"
	387	}
	388	},
	389	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	390	{
	391	[0] = "Pentium 60/66 A-step",
	392	[1] = "Pentium 60/66",
1da177e4	393	[2] = "Pentium 75 - 200",
65eb6b43	394	[3] = "OverDrive PODP5V83",
1da177e4	395	[4] = "Pentium MMX",
65eb6b43	396	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	397	[8] = "Mobile Pentium MMX"
	398	}
	399	},
	400	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	401	{
1da177e4	402	[0] = "Pentium Pro A-step",
65eb6b43 PC	403	[1] = "Pentium Pro",
	404	[3] = "Pentium II (Klamath)",
	405	[4] = "Pentium II (Deschutes)",
	406	[5] = "Pentium II (Deschutes)",
1da177e4	407	[6] = "Mobile Pentium II",
65eb6b43 PC	408	[7] = "Pentium III (Katmai)",
65eb6b43 PC	409	[8] = "Pentium III (Coppermine)",
1da177e4 LT	410	[10] = "Pentium III (Cascades)",
	411	[11] = "Pentium III (Tualatin)",
	412	}
	413	},
	414	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	415	{
	416	[0] = "Pentium 4 (Unknown)",
	417	[1] = "Pentium 4 (Willamette)",
	418	[2] = "Pentium 4 (Northwood)",
	419	[4] = "Pentium 4 (Foster)",
	420	[5] = "Pentium 4 (Foster)",
	421	}
	422	},
	423	},
185f3b9d YL	424	.c_size_cache = intel_size_cache,
185f3b9d YL	425	#endif
03ae5768	426	.c_early_init = early_init_intel,
1da177e4	427	.c_init = init_intel,
10a434fc	428	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	429	};
1da177e4 LT	430
10a434fc	431	cpu_dev_register(intel_cpu_dev);
1da177e4	432