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f580366f | 1 | #include <linux/init.h> |
0f0124fa YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
4 | #include <linux/string.h> | |
5 | #include <linux/bootmem.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
f580366f YL |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
f580366f | 12 | #include <linux/percpu.h> |
f580366f YL |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
cbcd79c2 | 16 | #include <asm/linkage.h> |
f580366f YL |
17 | #include <asm/mmu_context.h> |
18 | #include <asm/mtrr.h> | |
19 | #include <asm/mce.h> | |
20 | #include <asm/pat.h> | |
b6734c35 | 21 | #include <asm/asm.h> |
f580366f YL |
22 | #include <asm/numa.h> |
23 | #ifdef CONFIG_X86_LOCAL_APIC | |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
27 | #endif | |
0f0124fa YL |
28 | #include <asm/pda.h> |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/processor.h> | |
31 | #include <asm/desc.h> | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/proto.h> | |
34 | #include <asm/sections.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/genapic.h> | |
f580366f YL |
37 | |
38 | #include "cpu.h" | |
39 | ||
40 | /* We need valid kernel segments for data and code in long mode too | |
41 | * IRET will check the segment types kkeil 2000/10/28 | |
42 | * Also sysret mandates a special GDT layout | |
43 | */ | |
44 | /* The TLS descriptors are currently at a different place compared to i386. | |
45 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
46 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
47 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
48 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
49 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
50 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
51 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
52 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
53 | } }; | |
54 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
55 | ||
56 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; | |
57 | ||
58 | /* Current gdt points %fs at the "master" per-cpu area: after this, | |
59 | * it's on the real one. */ | |
60 | void switch_to_new_gdt(void) | |
61 | { | |
62 | struct desc_ptr gdt_descr; | |
63 | ||
64 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
65 | gdt_descr.size = GDT_SIZE - 1; | |
66 | load_gdt(&gdt_descr); | |
67 | } | |
68 | ||
69 | struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; | |
70 | ||
71 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
72 | { | |
73 | display_cacheinfo(c); | |
74 | } | |
75 | ||
76 | static struct cpu_dev __cpuinitdata default_cpu = { | |
77 | .c_init = default_init, | |
78 | .c_vendor = "Unknown", | |
79 | }; | |
80 | static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
81 | ||
82 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
83 | { | |
84 | unsigned int *v; | |
85 | ||
86 | if (c->extended_cpuid_level < 0x80000004) | |
87 | return 0; | |
88 | ||
89 | v = (unsigned int *) c->x86_model_id; | |
90 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
91 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
92 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
93 | c->x86_model_id[48] = 0; | |
94 | return 1; | |
95 | } | |
96 | ||
97 | ||
98 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) | |
99 | { | |
87a1c441 | 100 | unsigned int n, dummy, ebx, ecx, edx; |
f580366f YL |
101 | |
102 | n = c->extended_cpuid_level; | |
103 | ||
104 | if (n >= 0x80000005) { | |
105 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
106 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " | |
107 | "D cache %dK (%d bytes/line)\n", | |
108 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
109 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
110 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
111 | c->x86_tlbsize = 0; | |
112 | } | |
113 | ||
114 | if (n >= 0x80000006) { | |
115 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
116 | ecx = cpuid_ecx(0x80000006); | |
117 | c->x86_cache_size = ecx >> 16; | |
118 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
119 | ||
120 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
121 | c->x86_cache_size, ecx & 0xFF); | |
122 | } | |
f580366f YL |
123 | } |
124 | ||
125 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
126 | { | |
127 | #ifdef CONFIG_SMP | |
128 | u32 eax, ebx, ecx, edx; | |
129 | int index_msb, core_bits; | |
130 | ||
131 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
132 | ||
133 | ||
134 | if (!cpu_has(c, X86_FEATURE_HT)) | |
135 | return; | |
136 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
137 | goto out; | |
138 | ||
139 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
140 | ||
141 | if (smp_num_siblings == 1) { | |
142 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
143 | } else if (smp_num_siblings > 1) { | |
144 | ||
145 | if (smp_num_siblings > NR_CPUS) { | |
146 | printk(KERN_WARNING "CPU: Unsupported number of " | |
147 | "siblings %d", smp_num_siblings); | |
148 | smp_num_siblings = 1; | |
149 | return; | |
150 | } | |
151 | ||
152 | index_msb = get_count_order(smp_num_siblings); | |
153 | c->phys_proc_id = phys_pkg_id(index_msb); | |
154 | ||
155 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
156 | ||
157 | index_msb = get_count_order(smp_num_siblings); | |
158 | ||
159 | core_bits = get_count_order(c->x86_max_cores); | |
160 | ||
161 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
162 | ((1 << core_bits) - 1); | |
163 | } | |
164 | out: | |
165 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
166 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
167 | c->phys_proc_id); | |
168 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
169 | c->cpu_core_id); | |
170 | } | |
171 | ||
172 | #endif | |
173 | } | |
174 | ||
175 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
176 | { | |
177 | char *v = c->x86_vendor_id; | |
178 | int i; | |
179 | static int printed; | |
180 | ||
181 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
182 | if (cpu_devs[i]) { | |
183 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
184 | (cpu_devs[i]->c_ident[1] && | |
185 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
186 | c->x86_vendor = i; | |
187 | this_cpu = cpu_devs[i]; | |
188 | return; | |
189 | } | |
190 | } | |
191 | } | |
192 | if (!printed) { | |
193 | printed++; | |
194 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
195 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
196 | } | |
197 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
198 | } | |
199 | ||
200 | static void __init early_cpu_support_print(void) | |
201 | { | |
202 | int i,j; | |
203 | struct cpu_dev *cpu_devx; | |
204 | ||
205 | printk("KERNEL supported cpus:\n"); | |
206 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
207 | cpu_devx = cpu_devs[i]; | |
208 | if (!cpu_devx) | |
209 | continue; | |
210 | for (j = 0; j < 2; j++) { | |
211 | if (!cpu_devx->c_ident[j]) | |
212 | continue; | |
213 | printk(" %s %s\n", cpu_devx->c_vendor, | |
214 | cpu_devx->c_ident[j]); | |
215 | } | |
216 | } | |
217 | } | |
218 | ||
b6734c35 PA |
219 | /* |
220 | * The NOPL instruction is supposed to exist on all CPUs with | |
221 | * family >= 6, unfortunately, that's not true in practice because | |
222 | * of early VIA chips and (more importantly) broken virtualizers that | |
223 | * are not easy to detect. Hence, probe for it based on first | |
224 | * principles. | |
225 | * | |
226 | * Note: no 64-bit chip is known to lack these, but put the code here | |
227 | * for consistency with 32 bits, and to make it utterly trivial to | |
228 | * diagnose the problem should it ever surface. | |
229 | */ | |
230 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
231 | { | |
232 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
233 | u32 has_nopl = nopl_signature; | |
234 | ||
235 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
236 | if (c->x86 >= 6) { | |
237 | asm volatile("\n" | |
238 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
239 | "2:\n" | |
240 | " .section .fixup,\"ax\"\n" | |
241 | "3: xor %0,%0\n" | |
242 | " jmp 2b\n" | |
243 | " .previous\n" | |
244 | _ASM_EXTABLE(1b,3b) | |
245 | : "+a" (has_nopl)); | |
246 | ||
247 | if (has_nopl == nopl_signature) | |
248 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
249 | } | |
250 | } | |
251 | ||
f580366f YL |
252 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c); |
253 | ||
254 | void __init early_cpu_init(void) | |
255 | { | |
256 | struct cpu_vendor_dev *cvdev; | |
257 | ||
258 | for (cvdev = __x86cpuvendor_start ; | |
259 | cvdev < __x86cpuvendor_end ; | |
260 | cvdev++) | |
261 | cpu_devs[cvdev->vendor] = cvdev->cpu_dev; | |
262 | early_cpu_support_print(); | |
263 | early_identify_cpu(&boot_cpu_data); | |
264 | } | |
265 | ||
266 | /* Do some early cpuid on the boot CPU to get some parameter that are | |
267 | needed before check_bugs. Everything advanced is in identify_cpu | |
268 | below. */ | |
269 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) | |
270 | { | |
271 | u32 tfms, xlvl; | |
272 | ||
273 | c->loops_per_jiffy = loops_per_jiffy; | |
274 | c->x86_cache_size = -1; | |
275 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
276 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
277 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
278 | c->x86_model_id[0] = '\0'; /* Unset */ | |
279 | c->x86_clflush_size = 64; | |
280 | c->x86_cache_alignment = c->x86_clflush_size; | |
281 | c->x86_max_cores = 1; | |
282 | c->x86_coreid_bits = 0; | |
283 | c->extended_cpuid_level = 0; | |
284 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
285 | ||
286 | /* Get vendor name */ | |
287 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
288 | (unsigned int *)&c->x86_vendor_id[0], | |
289 | (unsigned int *)&c->x86_vendor_id[8], | |
290 | (unsigned int *)&c->x86_vendor_id[4]); | |
291 | ||
292 | get_cpu_vendor(c); | |
293 | ||
294 | /* Initialize the standard set of capabilities */ | |
295 | /* Note that the vendor-specific code below might override */ | |
296 | ||
297 | /* Intel-defined flags: level 0x00000001 */ | |
298 | if (c->cpuid_level >= 0x00000001) { | |
299 | __u32 misc; | |
300 | cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], | |
301 | &c->x86_capability[0]); | |
302 | c->x86 = (tfms >> 8) & 0xf; | |
303 | c->x86_model = (tfms >> 4) & 0xf; | |
304 | c->x86_mask = tfms & 0xf; | |
305 | if (c->x86 == 0xf) | |
306 | c->x86 += (tfms >> 20) & 0xff; | |
307 | if (c->x86 >= 0x6) | |
308 | c->x86_model += ((tfms >> 16) & 0xF) << 4; | |
309 | if (test_cpu_cap(c, X86_FEATURE_CLFLSH)) | |
310 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
311 | } else { | |
312 | /* Have CPUID level 0 only - unheard of */ | |
313 | c->x86 = 4; | |
314 | } | |
315 | ||
316 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff; | |
317 | #ifdef CONFIG_SMP | |
318 | c->phys_proc_id = c->initial_apicid; | |
319 | #endif | |
320 | /* AMD-defined flags: level 0x80000001 */ | |
321 | xlvl = cpuid_eax(0x80000000); | |
322 | c->extended_cpuid_level = xlvl; | |
323 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
324 | if (xlvl >= 0x80000001) { | |
325 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
326 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
327 | } | |
328 | if (xlvl >= 0x80000004) | |
329 | get_model_name(c); /* Default name */ | |
330 | } | |
331 | ||
332 | /* Transmeta-defined flags: level 0x80860001 */ | |
333 | xlvl = cpuid_eax(0x80860000); | |
334 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
335 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
336 | if (xlvl >= 0x80860001) | |
337 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
338 | } | |
339 | ||
f580366f YL |
340 | if (c->extended_cpuid_level >= 0x80000007) |
341 | c->x86_power = cpuid_edx(0x80000007); | |
342 | ||
87a1c441 YL |
343 | if (c->extended_cpuid_level >= 0x80000008) { |
344 | u32 eax = cpuid_eax(0x80000008); | |
345 | ||
346 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
347 | c->x86_phys_bits = eax & 0xff; | |
348 | } | |
349 | ||
b6734c35 PA |
350 | detect_nopl(c); |
351 | ||
f580366f YL |
352 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
353 | cpu_devs[c->x86_vendor]->c_early_init) | |
354 | cpu_devs[c->x86_vendor]->c_early_init(c); | |
355 | ||
356 | validate_pat_support(c); | |
f580366f YL |
357 | } |
358 | ||
359 | /* | |
360 | * This does the hard work of actually picking apart the CPU stuff... | |
361 | */ | |
9a250347 | 362 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
f580366f YL |
363 | { |
364 | int i; | |
365 | ||
366 | early_identify_cpu(c); | |
367 | ||
368 | init_scattered_cpuid_features(c); | |
369 | ||
370 | c->apicid = phys_pkg_id(0); | |
371 | ||
372 | /* | |
373 | * Vendor-specific initialization. In this section we | |
374 | * canonicalize the feature flags, meaning if there are | |
375 | * features a certain CPU supports which CPUID doesn't | |
376 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
377 | * we handle them here. | |
378 | * | |
379 | * At the end of this section, c->x86_capability better | |
380 | * indicate the features this CPU genuinely supports! | |
381 | */ | |
382 | if (this_cpu->c_init) | |
383 | this_cpu->c_init(c); | |
384 | ||
385 | detect_ht(c); | |
386 | ||
387 | /* | |
388 | * On SMP, boot_cpu_data holds the common feature set between | |
389 | * all CPUs; so make sure that we indicate which features are | |
390 | * common between the CPUs. The first time this routine gets | |
391 | * executed, c == &boot_cpu_data. | |
392 | */ | |
393 | if (c != &boot_cpu_data) { | |
394 | /* AND the already accumulated flags with these */ | |
395 | for (i = 0; i < NCAPINTS; i++) | |
396 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
397 | } | |
398 | ||
399 | /* Clear all flags overriden by options */ | |
400 | for (i = 0; i < NCAPINTS; i++) | |
401 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; | |
402 | ||
403 | #ifdef CONFIG_X86_MCE | |
404 | mcheck_init(c); | |
405 | #endif | |
406 | select_idle_routine(c); | |
407 | ||
408 | #ifdef CONFIG_NUMA | |
409 | numa_add_cpu(smp_processor_id()); | |
410 | #endif | |
411 | ||
412 | } | |
413 | ||
414 | void __cpuinit identify_boot_cpu(void) | |
415 | { | |
416 | identify_cpu(&boot_cpu_data); | |
417 | } | |
418 | ||
419 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
420 | { | |
421 | BUG_ON(c == &boot_cpu_data); | |
422 | identify_cpu(c); | |
423 | mtrr_ap_init(); | |
424 | } | |
425 | ||
426 | static __init int setup_noclflush(char *arg) | |
427 | { | |
428 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
429 | return 1; | |
430 | } | |
431 | __setup("noclflush", setup_noclflush); | |
432 | ||
433 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) | |
434 | { | |
435 | if (c->x86_model_id[0]) | |
436 | printk(KERN_CONT "%s", c->x86_model_id); | |
437 | ||
438 | if (c->x86_mask || c->cpuid_level >= 0) | |
439 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
440 | else | |
441 | printk(KERN_CONT "\n"); | |
442 | } | |
443 | ||
444 | static __init int setup_disablecpuid(char *arg) | |
445 | { | |
446 | int bit; | |
447 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
448 | setup_clear_cpu_cap(bit); | |
449 | else | |
450 | return 0; | |
451 | return 1; | |
452 | } | |
453 | __setup("clearcpuid=", setup_disablecpuid); | |
0f0124fa | 454 | |
0f0124fa YL |
455 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
456 | ||
457 | struct x8664_pda **_cpu_pda __read_mostly; | |
458 | EXPORT_SYMBOL(_cpu_pda); | |
459 | ||
460 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
461 | ||
462 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
463 | ||
464 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
465 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
466 | ||
467 | static int do_not_nx __cpuinitdata; | |
468 | ||
469 | /* noexec=on|off | |
470 | Control non executable mappings for 64bit processes. | |
471 | ||
472 | on Enable(default) | |
473 | off Disable | |
474 | */ | |
475 | static int __init nonx_setup(char *str) | |
476 | { | |
477 | if (!str) | |
478 | return -EINVAL; | |
479 | if (!strncmp(str, "on", 2)) { | |
480 | __supported_pte_mask |= _PAGE_NX; | |
481 | do_not_nx = 0; | |
482 | } else if (!strncmp(str, "off", 3)) { | |
483 | do_not_nx = 1; | |
484 | __supported_pte_mask &= ~_PAGE_NX; | |
485 | } | |
486 | return 0; | |
487 | } | |
488 | early_param("noexec", nonx_setup); | |
489 | ||
490 | int force_personality32; | |
491 | ||
492 | /* noexec32=on|off | |
493 | Control non executable heap for 32bit processes. | |
494 | To control the stack too use noexec=off | |
495 | ||
496 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
497 | off PROT_READ implies PROT_EXEC | |
498 | */ | |
499 | static int __init nonx32_setup(char *str) | |
500 | { | |
501 | if (!strcmp(str, "on")) | |
502 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
503 | else if (!strcmp(str, "off")) | |
504 | force_personality32 |= READ_IMPLIES_EXEC; | |
505 | return 1; | |
506 | } | |
507 | __setup("noexec32=", nonx32_setup); | |
508 | ||
509 | void pda_init(int cpu) | |
510 | { | |
511 | struct x8664_pda *pda = cpu_pda(cpu); | |
512 | ||
513 | /* Setup up data that may be needed in __get_free_pages early */ | |
ada85708 JF |
514 | loadsegment(fs, 0); |
515 | loadsegment(gs, 0); | |
0f0124fa YL |
516 | /* Memory clobbers used to order PDA accessed */ |
517 | mb(); | |
518 | wrmsrl(MSR_GS_BASE, pda); | |
519 | mb(); | |
520 | ||
521 | pda->cpunumber = cpu; | |
522 | pda->irqcount = -1; | |
523 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
524 | PDA_STACKOFFSET + THREAD_SIZE; | |
525 | pda->active_mm = &init_mm; | |
526 | pda->mmu_state = 0; | |
527 | ||
528 | if (cpu == 0) { | |
529 | /* others are initialized in smpboot.c */ | |
530 | pda->pcurrent = &init_task; | |
531 | pda->irqstackptr = boot_cpu_stack; | |
d04ec773 | 532 | pda->irqstackptr += IRQSTACKSIZE - 64; |
0f0124fa | 533 | } else { |
d04ec773 AH |
534 | if (!pda->irqstackptr) { |
535 | pda->irqstackptr = (char *) | |
536 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
537 | if (!pda->irqstackptr) | |
538 | panic("cannot allocate irqstack for cpu %d", | |
539 | cpu); | |
540 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
541 | } | |
0f0124fa YL |
542 | |
543 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
544 | pda->nodenumber = cpu_to_node(cpu); | |
545 | } | |
0f0124fa YL |
546 | } |
547 | ||
548 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
cbcd79c2 | 549 | DEBUG_STKSZ] __page_aligned_bss; |
0f0124fa YL |
550 | |
551 | extern asmlinkage void ignore_sysret(void); | |
552 | ||
553 | /* May not be marked __init: used by software suspend */ | |
554 | void syscall_init(void) | |
555 | { | |
556 | /* | |
557 | * LSTAR and STAR live in a bit strange symbiosis. | |
558 | * They both write to the same internal register. STAR allows to | |
559 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
560 | */ | |
561 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
562 | wrmsrl(MSR_LSTAR, system_call); | |
563 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
564 | ||
565 | #ifdef CONFIG_IA32_EMULATION | |
566 | syscall32_cpu_init(); | |
567 | #endif | |
568 | ||
569 | /* Flags to clear on syscall */ | |
570 | wrmsrl(MSR_SYSCALL_MASK, | |
571 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
572 | } | |
573 | ||
574 | void __cpuinit check_efer(void) | |
575 | { | |
576 | unsigned long efer; | |
577 | ||
578 | rdmsrl(MSR_EFER, efer); | |
579 | if (!(efer & EFER_NX) || do_not_nx) | |
580 | __supported_pte_mask &= ~_PAGE_NX; | |
581 | } | |
582 | ||
583 | unsigned long kernel_eflags; | |
584 | ||
585 | /* | |
586 | * Copies of the original ist values from the tss are only accessed during | |
587 | * debugging, no special alignment required. | |
588 | */ | |
589 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
590 | ||
591 | /* | |
592 | * cpu_init() initializes state that is per-CPU. Some data is already | |
593 | * initialized (naturally) in the bootstrap process, such as the GDT | |
594 | * and IDT. We reload them nevertheless, this function acts as a | |
595 | * 'CPU state barrier', nothing should get across. | |
596 | * A lot of state is already set up in PDA init. | |
597 | */ | |
598 | void __cpuinit cpu_init(void) | |
599 | { | |
600 | int cpu = stack_smp_processor_id(); | |
601 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
602 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
603 | unsigned long v; | |
604 | char *estacks = NULL; | |
605 | struct task_struct *me; | |
606 | int i; | |
607 | ||
608 | /* CPU 0 is initialised in head64.c */ | |
609 | if (cpu != 0) | |
610 | pda_init(cpu); | |
611 | else | |
612 | estacks = boot_exception_stacks; | |
613 | ||
614 | me = current; | |
615 | ||
616 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
617 | panic("CPU#%d already initialized!\n", cpu); | |
618 | ||
619 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
620 | ||
621 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
622 | ||
623 | /* | |
624 | * Initialize the per-CPU GDT with the boot GDT, | |
625 | * and set up the GDT descriptor: | |
626 | */ | |
627 | ||
628 | switch_to_new_gdt(); | |
629 | load_idt((const struct desc_ptr *)&idt_descr); | |
630 | ||
631 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
632 | syscall_init(); | |
633 | ||
634 | wrmsrl(MSR_FS_BASE, 0); | |
635 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
636 | barrier(); | |
637 | ||
638 | check_efer(); | |
639 | ||
640 | /* | |
641 | * set up and load the per-CPU TSS | |
642 | */ | |
23952a96 | 643 | if (!orig_ist->ist[0]) { |
0f0124fa | 644 | static const unsigned int order[N_EXCEPTION_STACKS] = { |
23952a96 AH |
645 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, |
646 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
0f0124fa | 647 | }; |
23952a96 AH |
648 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
649 | if (cpu) { | |
650 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
651 | if (!estacks) | |
652 | panic("Cannot allocate exception " | |
653 | "stack %ld %d\n", v, cpu); | |
654 | } | |
655 | estacks += PAGE_SIZE << order[v]; | |
656 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
657 | (unsigned long)estacks; | |
0f0124fa | 658 | } |
0f0124fa YL |
659 | } |
660 | ||
661 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
662 | /* | |
663 | * <= is required because the CPU will access up to | |
664 | * 8 bits beyond the end of the IO permission bitmap. | |
665 | */ | |
666 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
667 | t->io_bitmap[i] = ~0UL; | |
668 | ||
669 | atomic_inc(&init_mm.mm_count); | |
670 | me->active_mm = &init_mm; | |
671 | if (me->mm) | |
672 | BUG(); | |
673 | enter_lazy_tlb(&init_mm, me); | |
674 | ||
675 | load_sp0(t, ¤t->thread); | |
676 | set_tss_desc(cpu, t); | |
677 | load_TR_desc(); | |
678 | load_LDT(&init_mm.context); | |
679 | ||
680 | #ifdef CONFIG_KGDB | |
681 | /* | |
682 | * If the kgdb is connected no debug regs should be altered. This | |
683 | * is only applicable when KGDB and a KGDB I/O module are built | |
684 | * into the kernel and you are using early debugging with | |
685 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
686 | */ | |
687 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
688 | arch_kgdb_ops.correct_hw_break(); | |
689 | else { | |
690 | #endif | |
691 | /* | |
692 | * Clear all 6 debug registers: | |
693 | */ | |
694 | ||
695 | set_debugreg(0UL, 0); | |
696 | set_debugreg(0UL, 1); | |
697 | set_debugreg(0UL, 2); | |
698 | set_debugreg(0UL, 3); | |
699 | set_debugreg(0UL, 6); | |
700 | set_debugreg(0UL, 7); | |
701 | #ifdef CONFIG_KGDB | |
702 | /* If the kgdb is connected no debug regs should be altered. */ | |
703 | } | |
704 | #endif | |
705 | ||
706 | fpu_init(); | |
707 | ||
708 | raw_local_save_flags(kernel_eflags); | |
709 | ||
710 | if (is_uv_system()) | |
711 | uv_cpu_init(); | |
712 | } |