[net-next-2.6.git] / arch / x86 / kernel / apic / numaq_32.c

/*
 * Written by: Patricia Gaughen, IBM Corporation
 *
 * Copyright (C) 2002, IBM Corp.
 * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <gone@us.ibm.com>
 */
#include <linux/nodemask.h>
#include <linux/topology.h>
#include <linux/bootmem.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/kernel.h>
#include <linux/mmzone.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/numa.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <asm/processor.h>
#include <asm/fixmap.h>
#include <asm/mpspec.h>
#include <asm/numaq.h>
#include <asm/setup.h>
#include <asm/apic.h>
#include <asm/e820.h>
#include <asm/ipi.h>

#define	MB_TO_PAGES(addr)		((addr) << (20 - PAGE_SHIFT))

int found_numaq;

/*
 * Have to match translation table entries to main table entries by counter
 * hence the mpc_record variable .... can't see a less disgusting way of
 * doing this ....
 */
struct mpc_trans {
	unsigned char			mpc_type;
	unsigned char			trans_len;
	unsigned char			trans_type;
	unsigned char			trans_quad;
	unsigned char			trans_global;
	unsigned char			trans_local;
	unsigned short			trans_reserved;
};

static int				mpc_record;

static struct mpc_trans			*translation_table[MAX_MPC_ENTRY];

int					mp_bus_id_to_node[MAX_MP_BUSSES];
int					mp_bus_id_to_local[MAX_MP_BUSSES];
int					quad_local_to_mp_bus_id[NR_CPUS/4][4];


static inline void numaq_register_node(int node, struct sys_cfg_data *scd)
{
	struct eachquadmem *eq = scd->eq + node;

	node_set_online(node);

	/* Convert to pages */
	node_start_pfn[node] =
		 MB_TO_PAGES(eq->hi_shrd_mem_start - eq->priv_mem_size);

	node_end_pfn[node] =
		 MB_TO_PAGES(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size);

	e820_register_active_regions(node, node_start_pfn[node],
						node_end_pfn[node]);

	memory_present(node, node_start_pfn[node], node_end_pfn[node]);

	node_remap_size[node] = node_memmap_size_bytes(node,
					node_start_pfn[node],
					node_end_pfn[node]);
}

/*
 * Function: smp_dump_qct()
 *
 * Description: gets memory layout from the quad config table.  This
 * function also updates node_online_map with the nodes (quads) present.
 */
static void __init smp_dump_qct(void)
{
	struct sys_cfg_data *scd;
	int node;

	scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR);

	nodes_clear(node_online_map);
	for_each_node(node) {
		if (scd->quads_present31_0 & (1 << node))
			numaq_register_node(node, scd);
	}
}

void __cpuinit numaq_tsc_disable(void)
{
	if (!found_numaq)
		return;

	if (num_online_nodes() > 1) {
		printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
		setup_clear_cpu_cap(X86_FEATURE_TSC);
	}
}

static void __init numaq_tsc_init(void)
{
	numaq_tsc_disable();
}

static inline int generate_logical_apicid(int quad, int phys_apicid)
{
	return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
}

/* x86_quirks member */
static int mpc_apic_id(struct mpc_cpu *m)
{
	int quad = translation_table[mpc_record]->trans_quad;
	int logical_apicid = generate_logical_apicid(quad, m->apicid);

	printk(KERN_DEBUG
		"Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
		 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
		(m->cpufeature & CPU_MODEL_MASK) >> 4,
		 m->apicver, quad, logical_apicid);

	return logical_apicid;
}

/* x86_quirks member */
static void mpc_oem_bus_info(struct mpc_bus *m, char *name)
{
	int quad = translation_table[mpc_record]->trans_quad;
	int local = translation_table[mpc_record]->trans_local;

	mp_bus_id_to_node[m->busid] = quad;
	mp_bus_id_to_local[m->busid] = local;

	printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad);
}

/* x86_quirks member */
static void mpc_oem_pci_bus(struct mpc_bus *m)
{
	int quad = translation_table[mpc_record]->trans_quad;
	int local = translation_table[mpc_record]->trans_local;

	quad_local_to_mp_bus_id[quad][local] = m->busid;
}

/*
 * Called from mpparse code.
 * mode = 0: prescan
 * mode = 1: one mpc entry scanned
 */
static void numaq_mpc_record(unsigned int mode)
{
	if (!mode)
		mpc_record = 0;
	else
		mpc_record++;
}

static void __init MP_translation_info(struct mpc_trans *m)
{
	printk(KERN_INFO
	    "Translation: record %d, type %d, quad %d, global %d, local %d\n",
	       mpc_record, m->trans_type, m->trans_quad, m->trans_global,
	       m->trans_local);

	if (mpc_record >= MAX_MPC_ENTRY)
		printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
	else
		translation_table[mpc_record] = m; /* stash this for later */

	if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
		node_set_online(m->trans_quad);
}

static int __init mpf_checksum(unsigned char *mp, int len)
{
	int sum = 0;

	while (len--)
		sum += *mp++;

	return sum & 0xFF;
}

/*
 * Read/parse the MPC oem tables
 */
static void __init smp_read_mpc_oem(struct mpc_table *mpc)
{
	struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr;
	int count = sizeof(*oemtable);	/* the header size */
	unsigned char *oemptr = ((unsigned char *)oemtable) + count;

	mpc_record = 0;
	printk(KERN_INFO
		"Found an OEM MPC table at %8p - parsing it ... \n", oemtable);

	if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
		printk(KERN_WARNING
		       "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
		       oemtable->signature[0], oemtable->signature[1],
		       oemtable->signature[2], oemtable->signature[3]);
		return;
	}

	if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
		printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
		return;
	}

	while (count < oemtable->length) {
		switch (*oemptr) {
		case MP_TRANSLATION:
			{
				struct mpc_trans *m = (void *)oemptr;

				MP_translation_info(m);
				oemptr += sizeof(*m);
				count += sizeof(*m);
				++mpc_record;
				break;
			}
		default:
			printk(KERN_WARNING
			       "Unrecognised OEM table entry type! - %d\n",
			       (int)*oemptr);
			return;
		}
	}
}

static __init void early_check_numaq(void)
{
	/*
	 * Find possible boot-time SMP configuration:
	 */
	early_find_smp_config();

	/*
	 * get boot-time SMP configuration:
	 */
	if (smp_found_config)
		early_get_smp_config();

	if (found_numaq) {
		x86_init.mpparse.mpc_record = numaq_mpc_record;
		x86_init.mpparse.setup_ioapic_ids = x86_init_noop;
		x86_init.mpparse.mpc_apic_id = mpc_apic_id;
		x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem;
		x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus;
		x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info;
		x86_init.timers.tsc_pre_init = numaq_tsc_init;
	}
}

int __init get_memcfg_numaq(void)
{
	early_check_numaq();
	if (!found_numaq)
		return 0;
	smp_dump_qct();

	return 1;
}

#define NUMAQ_APIC_DFR_VALUE	(APIC_DFR_CLUSTER)

static inline unsigned int numaq_get_apic_id(unsigned long x)
{
	return (x >> 24) & 0x0F;
}

static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
{
	default_send_IPI_mask_sequence_logical(mask, vector);
}

static inline void numaq_send_IPI_allbutself(int vector)
{
	default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
}

static inline void numaq_send_IPI_all(int vector)
{
	numaq_send_IPI_mask(cpu_online_mask, vector);
}

#define NUMAQ_TRAMPOLINE_PHYS_LOW	(0x8)
#define NUMAQ_TRAMPOLINE_PHYS_HIGH	(0xa)

/*
 * Because we use NMIs rather than the INIT-STARTUP sequence to
 * bootstrap the CPUs, the APIC may be in a weird state. Kick it:
 */
static inline void numaq_smp_callin_clear_local_apic(void)
{
	clear_local_APIC();
}

static inline const struct cpumask *numaq_target_cpus(void)
{
	return cpu_all_mask;
}

static inline unsigned long
numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
{
	return physid_isset(apicid, bitmap);
}

static inline unsigned long numaq_check_apicid_present(int bit)
{
	return physid_isset(bit, phys_cpu_present_map);
}

static inline int numaq_apic_id_registered(void)
{
	return 1;
}

static inline void numaq_init_apic_ldr(void)
{
	/* Already done in NUMA-Q firmware */
}

static inline void numaq_setup_apic_routing(void)
{
	printk(KERN_INFO
		"Enabling APIC mode:  NUMA-Q.  Using %d I/O APICs\n",
		nr_ioapics);
}

/*
 * Skip adding the timer int on secondary nodes, which causes
 * a small but painful rift in the time-space continuum.
 */
static inline int numaq_multi_timer_check(int apic, int irq)
{
	return apic != 0 && irq == 0;
}

static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
{
	/* We don't have a good way to do this yet - hack */
	return physids_promote(0xFUL);
}

static inline int numaq_cpu_to_logical_apicid(int cpu)
{
	if (cpu >= nr_cpu_ids)
		return BAD_APICID;
	return cpu_2_logical_apicid[cpu];
}

/*
 * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
 * cpu to APIC ID relation to properly interact with the intelligent
 * mode of the cluster controller.
 */
static inline int numaq_cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < 60)
		return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
	else
		return BAD_APICID;
}

static inline int numaq_apicid_to_node(int logical_apicid)
{
	return logical_apicid >> 4;
}

static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
{
	int node = numaq_apicid_to_node(logical_apicid);
	int cpu = __ffs(logical_apicid & 0xf);

	return physid_mask_of_physid(cpu + 4*node);
}

/* Where the IO area was mapped on multiquad, always 0 otherwise */
void *xquad_portio;

static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
{
	return 1;
}

/*
 * We use physical apicids here, not logical, so just return the default
 * physical broadcast to stop people from breaking us
 */
static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
	return 0x0F;
}

static inline unsigned int
numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
			     const struct cpumask *andmask)
{
	return 0x0F;
}

/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

static int
numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
{
	if (strncmp(oem, "IBM NUMA", 8))
		printk(KERN_ERR "Warning! Not a NUMA-Q system!\n");
	else
		found_numaq = 1;

	return found_numaq;
}

static int probe_numaq(void)
{
	/* already know from get_memcfg_numaq() */
	return found_numaq;
}

static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask)
{
	/* Careful. Some cpus do not strictly honor the set of cpus
	 * specified in the interrupt destination when using lowest
	 * priority interrupt delivery mode.
	 *
	 * In particular there was a hyperthreading cpu observed to
	 * deliver interrupts to the wrong hyperthread when only one
	 * hyperthread was specified in the interrupt desitination.
	 */
	cpumask_clear(retmask);
	cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
}

static void numaq_setup_portio_remap(void)
{
	int num_quads = num_online_nodes();

	if (num_quads <= 1)
		return;

	printk(KERN_INFO
		"Remapping cross-quad port I/O for %d quads\n", num_quads);

	xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);

	printk(KERN_INFO
		"xquad_portio vaddr 0x%08lx, len %08lx\n",
		(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
}

/* Use __refdata to keep false positive warning calm.	*/
struct apic __refdata apic_numaq = {

	.name				= "NUMAQ",
	.probe				= probe_numaq,
	.acpi_madt_oem_check		= NULL,
	.apic_id_registered		= numaq_apic_id_registered,

	.irq_delivery_mode		= dest_LowestPrio,
	/* physical delivery on LOCAL quad: */
	.irq_dest_mode			= 0,

	.target_cpus			= numaq_target_cpus,
	.disable_esr			= 1,
	.dest_logical			= APIC_DEST_LOGICAL,
	.check_apicid_used		= numaq_check_apicid_used,
	.check_apicid_present		= numaq_check_apicid_present,

	.vector_allocation_domain	= numaq_vector_allocation_domain,
	.init_apic_ldr			= numaq_init_apic_ldr,

	.ioapic_phys_id_map		= numaq_ioapic_phys_id_map,
	.setup_apic_routing		= numaq_setup_apic_routing,
	.multi_timer_check		= numaq_multi_timer_check,
	.apicid_to_node			= numaq_apicid_to_node,
	.cpu_to_logical_apicid		= numaq_cpu_to_logical_apicid,
	.cpu_present_to_apicid		= numaq_cpu_present_to_apicid,
	.apicid_to_cpu_present		= numaq_apicid_to_cpu_present,
	.setup_portio_remap		= numaq_setup_portio_remap,
	.check_phys_apicid_present	= numaq_check_phys_apicid_present,
	.enable_apic_mode		= NULL,
	.phys_pkg_id			= numaq_phys_pkg_id,
	.mps_oem_check			= numaq_mps_oem_check,

	.get_apic_id			= numaq_get_apic_id,
	.set_apic_id			= NULL,
	.apic_id_mask			= 0x0F << 24,

	.cpu_mask_to_apicid		= numaq_cpu_mask_to_apicid,
	.cpu_mask_to_apicid_and		= numaq_cpu_mask_to_apicid_and,

	.send_IPI_mask			= numaq_send_IPI_mask,
	.send_IPI_mask_allbutself	= NULL,
	.send_IPI_allbutself		= numaq_send_IPI_allbutself,
	.send_IPI_all			= numaq_send_IPI_all,
	.send_IPI_self			= default_send_IPI_self,

	.wakeup_secondary_cpu		= wakeup_secondary_cpu_via_nmi,
	.trampoline_phys_low		= NUMAQ_TRAMPOLINE_PHYS_LOW,
	.trampoline_phys_high		= NUMAQ_TRAMPOLINE_PHYS_HIGH,

	/* We don't do anything here because we use NMI's to boot instead */
	.wait_for_init_deassert		= NULL,

	.smp_callin_clear_local_apic	= numaq_smp_callin_clear_local_apic,
	.inquire_remote_apic		= NULL,

	.read				= native_apic_mem_read,
	.write				= native_apic_mem_write,
	.icr_read			= native_apic_icr_read,
	.icr_write			= native_apic_icr_write,
	.wait_icr_idle			= native_apic_wait_icr_idle,
	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Written by: Patricia Gaughen, IBM Corporation
	3	*
	4	* Copyright (C) 2002, IBM Corp.
cb81eaed	5	* Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
1da177e4	6	*
4f179d12	7	* All rights reserved.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	17	* NON INFRINGEMENT. See the GNU General Public License for more
	18	* details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*
	24	* Send feedback to <gone@us.ibm.com>
	25	*/
4f179d12	26	#include <linux/nodemask.h>
cb81eaed	27	#include <linux/topology.h>
1da177e4	28	#include <linux/bootmem.h>
36afc3af IM	29	#include <linux/threads.h>
	30	#include <linux/cpumask.h>
	31	#include <linux/kernel.h>
1da177e4 LT	32	#include <linux/mmzone.h>
1da177e4 LT	33	#include <linux/module.h>
36afc3af IM	34	#include <linux/string.h>
	35	#include <linux/init.h>
	36	#include <linux/numa.h>
	37	#include <linux/smp.h>
cb81eaed	38	#include <linux/io.h>
4f179d12 IM	39	#include <linux/mm.h>
4f179d12 IM	40
e1474e2d	41	#include <asm/processor.h>
36afc3af IM	42	#include <asm/fixmap.h>
36afc3af IM	43	#include <asm/mpspec.h>
4f179d12	44	#include <asm/numaq.h>
64898a8b	45	#include <asm/setup.h>
36afc3af	46	#include <asm/apic.h>
4f179d12	47	#include <asm/e820.h>
36afc3af	48	#include <asm/ipi.h>
1da177e4	49
36afc3af IM	50	#define MB_TO_PAGES(addr) ((addr) << (20 - PAGE_SHIFT))
36afc3af IM	51
cb81eaed IM	52	int found_numaq;
	53
	54	/*
	55	* Have to match translation table entries to main table entries by counter
	56	* hence the mpc_record variable .... can't see a less disgusting way of
	57	* doing this ....
	58	*/
	59	struct mpc_trans {
	60	unsigned char mpc_type;
	61	unsigned char trans_len;
	62	unsigned char trans_type;
	63	unsigned char trans_quad;
	64	unsigned char trans_global;
	65	unsigned char trans_local;
	66	unsigned short trans_reserved;
	67	};
	68
cb81eaed IM	69	static int mpc_record;
cb81eaed IM	70
b6122b38	71	static struct mpc_trans *translation_table[MAX_MPC_ENTRY];
cb81eaed IM	72
	73	int mp_bus_id_to_node[MAX_MP_BUSSES];
	74	int mp_bus_id_to_local[MAX_MP_BUSSES];
	75	int quad_local_to_mp_bus_id[NR_CPUS/4][4];
	76
	77
36afc3af IM	78	static inline void numaq_register_node(int node, struct sys_cfg_data *scd)
	79	{
	80	struct eachquadmem *eq = scd->eq + node;
	81
	82	node_set_online(node);
	83
	84	/* Convert to pages */
	85	node_start_pfn[node] =
	86	MB_TO_PAGES(eq->hi_shrd_mem_start - eq->priv_mem_size);
	87
	88	node_end_pfn[node] =
	89	MB_TO_PAGES(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size);
	90
	91	e820_register_active_regions(node, node_start_pfn[node],
	92	node_end_pfn[node]);
	93
	94	memory_present(node, node_start_pfn[node], node_end_pfn[node]);
	95
	96	node_remap_size[node] = node_memmap_size_bytes(node,
	97	node_start_pfn[node],
	98	node_end_pfn[node]);
	99	}
1da177e4 LT	100
	101	/*
	102	* Function: smp_dump_qct()
	103	*
	104	* Description: gets memory layout from the quad config table. This
	105	* function also updates node_online_map with the nodes (quads) present.
	106	*/
	107	static void __init smp_dump_qct(void)
	108	{
36afc3af	109	struct sys_cfg_data *scd;
1da177e4	110	int node;
36afc3af IM	111
36afc3af IM	112	scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR);
1da177e4 LT	113
	114	nodes_clear(node_online_map);
	115	for_each_node(node) {
36afc3af IM	116	if (scd->quads_present31_0 & (1 << node))
36afc3af IM	117	numaq_register_node(node, scd);
1da177e4 LT	118	}
	119	}
	120
b2a6a58c	121	void __cpuinit numaq_tsc_disable(void)
64898a8b YL	122	{
	123	if (!found_numaq)
	124	return;
	125
	126	if (num_online_nodes() > 1) {
	127	printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
	128	setup_clear_cpu_cap(X86_FEATURE_TSC);
	129	}
	130	}
	131
845b3944	132	static void __init numaq_tsc_init(void)
63b5d7af YL	133	{
63b5d7af YL	134	numaq_tsc_disable();
63b5d7af YL	135	}
63b5d7af YL	136
64898a8b YL	137	static inline int generate_logical_apicid(int quad, int phys_apicid)
	138	{
	139	return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
	140	}
	141
	142	/* x86_quirks member */
f4f21b71	143	static int mpc_apic_id(struct mpc_cpu *m)
64898a8b YL	144	{
64898a8b YL	145	int quad = translation_table[mpc_record]->trans_quad;
c4563826	146	int logical_apicid = generate_logical_apicid(quad, m->apicid);
64898a8b	147
36afc3af IM	148	printk(KERN_DEBUG
	149	"Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
	150	m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
	151	(m->cpufeature & CPU_MODEL_MASK) >> 4,
	152	m->apicver, quad, logical_apicid);
	153
64898a8b YL	154	return logical_apicid;
	155	}
	156
64898a8b	157	/* x86_quirks member */
00fb8606	158	static void mpc_oem_bus_info(struct mpc_bus m, char name)
64898a8b YL	159	{
	160	int quad = translation_table[mpc_record]->trans_quad;
	161	int local = translation_table[mpc_record]->trans_local;
	162
d4c715fa JSR	163	mp_bus_id_to_node[m->busid] = quad;
d4c715fa JSR	164	mp_bus_id_to_local[m->busid] = local;
36afc3af IM	165
36afc3af IM	166	printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad);
64898a8b YL	167	}
64898a8b YL	168
64898a8b	169	/* x86_quirks member */
00fb8606	170	static void mpc_oem_pci_bus(struct mpc_bus *m)
64898a8b YL	171	{
	172	int quad = translation_table[mpc_record]->trans_quad;
	173	int local = translation_table[mpc_record]->trans_local;
	174
d4c715fa	175	quad_local_to_mp_bus_id[quad][local] = m->busid;
64898a8b YL	176	}
64898a8b YL	177
f4848472 TG	178	/*
	179	* Called from mpparse code.
	180	* mode = 0: prescan
	181	* mode = 1: one mpc entry scanned
	182	*/
	183	static void numaq_mpc_record(unsigned int mode)
	184	{
	185	if (!mode)
	186	mpc_record = 0;
	187	else
	188	mpc_record++;
	189	}
	190
36afc3af	191	static void __init MP_translation_info(struct mpc_trans *m)
64898a8b YL	192	{
64898a8b YL	193	printk(KERN_INFO
cb81eaed	194	"Translation: record %d, type %d, quad %d, global %d, local %d\n",
64898a8b YL	195	mpc_record, m->trans_type, m->trans_quad, m->trans_global,
	196	m->trans_local);
	197
	198	if (mpc_record >= MAX_MPC_ENTRY)
	199	printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
	200	else
36afc3af IM	201	translation_table[mpc_record] = m; /* stash this for later */
36afc3af IM	202
64898a8b YL	203	if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
	204	node_set_online(m->trans_quad);
	205	}
	206
	207	static int __init mpf_checksum(unsigned char *mp, int len)
	208	{
	209	int sum = 0;
	210
	211	while (len--)
	212	sum += *mp++;
	213
	214	return sum & 0xFF;
	215	}
	216
	217	/*
	218	* Read/parse the MPC oem tables
	219	*/
72302142	220	static void __init smp_read_mpc_oem(struct mpc_table *mpc)
64898a8b	221	{
72302142	222	struct mpc_oemtable oemtable = (void )(long)mpc->oemptr;
64898a8b YL	223	int count = sizeof(oemtable); / the header size */
	224	unsigned char oemptr = ((unsigned char )oemtable) + count;
	225
	226	mpc_record = 0;
36afc3af IM	227	printk(KERN_INFO
	228	"Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
	229
a1d0272a	230	if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
64898a8b YL	231	printk(KERN_WARNING
64898a8b YL	232	"SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
a1d0272a JSR	233	oemtable->signature[0], oemtable->signature[1],
a1d0272a JSR	234	oemtable->signature[2], oemtable->signature[3]);
64898a8b YL	235	return;
64898a8b YL	236	}
36afc3af	237
a1d0272a	238	if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
64898a8b YL	239	printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
	240	return;
	241	}
36afc3af	242
a1d0272a	243	while (count < oemtable->length) {
64898a8b YL	244	switch (*oemptr) {
	245	case MP_TRANSLATION:
	246	{
36afc3af IM	247	struct mpc_trans m = (void )oemptr;
36afc3af IM	248
64898a8b YL	249	MP_translation_info(m);
	250	oemptr += sizeof(*m);
	251	count += sizeof(*m);
	252	++mpc_record;
	253	break;
	254	}
	255	default:
36afc3af IM	256	printk(KERN_WARNING
	257	"Unrecognised OEM table entry type! - %d\n",
	258	(int)*oemptr);
	259	return;
64898a8b YL	260	}
	261	}
	262	}
	263
ab530e1f YL	264	static __init void early_check_numaq(void)
	265	{
	266	/*
	267	* Find possible boot-time SMP configuration:
	268	*/
	269	early_find_smp_config();
36afc3af	270
ab530e1f YL	271	/*
	272	* get boot-time SMP configuration:
	273	*/
	274	if (smp_found_config)
	275	early_get_smp_config();
64898a8b	276
f4848472	277	if (found_numaq) {
f4848472	278	x86_init.mpparse.mpc_record = numaq_mpc_record;
de934103	279	x86_init.mpparse.setup_ioapic_ids = x86_init_noop;
fd6c6661	280	x86_init.mpparse.mpc_apic_id = mpc_apic_id;
72302142	281	x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem;
52fdb568	282	x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus;
90e1c696	283	x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info;
845b3944	284	x86_init.timers.tsc_pre_init = numaq_tsc_init;
f4848472	285	}
ab530e1f YL	286	}
ab530e1f YL	287
1da177e4 LT	288	int __init get_memcfg_numaq(void)
1da177e4 LT	289	{
ab530e1f YL	290	early_check_numaq();
	291	if (!found_numaq)
	292	return 0;
1da177e4	293	smp_dump_qct();
36afc3af	294
1da177e4 LT	295	return 1;
1da177e4 LT	296	}
61b90b7c	297
61b90b7c IM	298	#define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
	299
	300	static inline unsigned int numaq_get_apic_id(unsigned long x)
	301	{
	302	return (x >> 24) & 0x0F;
	303	}
	304
61b90b7c IM	305	static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
61b90b7c IM	306	{
43f39890	307	default_send_IPI_mask_sequence_logical(mask, vector);
61b90b7c IM	308	}
	309
	310	static inline void numaq_send_IPI_allbutself(int vector)
	311	{
43f39890	312	default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
61b90b7c IM	313	}
	314
	315	static inline void numaq_send_IPI_all(int vector)
	316	{
	317	numaq_send_IPI_mask(cpu_online_mask, vector);
	318	}
	319
36afc3af IM	320	#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
36afc3af IM	321	#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
61b90b7c IM	322
	323	/*
	324	* Because we use NMIs rather than the INIT-STARTUP sequence to
	325	* bootstrap the CPUs, the APIC may be in a weird state. Kick it:
	326	*/
	327	static inline void numaq_smp_callin_clear_local_apic(void)
	328	{
	329	clear_local_APIC();
	330	}
	331
73e907de	332	static inline const struct cpumask *numaq_target_cpus(void)
61b90b7c	333	{
101aaca1	334	return cpu_all_mask;
61b90b7c IM	335	}
	336
	337	static inline unsigned long
	338	numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
	339	{
	340	return physid_isset(apicid, bitmap);
	341	}
	342
	343	static inline unsigned long numaq_check_apicid_present(int bit)
	344	{
	345	return physid_isset(bit, phys_cpu_present_map);
	346	}
	347
61b90b7c IM	348	static inline int numaq_apic_id_registered(void)
	349	{
	350	return 1;
	351	}
	352
	353	static inline void numaq_init_apic_ldr(void)
	354	{
	355	/* Already done in NUMA-Q firmware */
	356	}
	357
	358	static inline void numaq_setup_apic_routing(void)
	359	{
cb81eaed IM	360	printk(KERN_INFO
	361	"Enabling APIC mode: NUMA-Q. Using %d I/O APICs\n",
	362	nr_ioapics);
61b90b7c IM	363	}
	364
	365	/*
	366	* Skip adding the timer int on secondary nodes, which causes
	367	* a small but painful rift in the time-space continuum.
	368	*/
	369	static inline int numaq_multi_timer_check(int apic, int irq)
	370	{
	371	return apic != 0 && irq == 0;
	372	}
	373
	374	static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
	375	{
	376	/* We don't have a good way to do this yet - hack */
	377	return physids_promote(0xFUL);
	378	}
	379
61b90b7c IM	380	static inline int numaq_cpu_to_logical_apicid(int cpu)
	381	{
	382	if (cpu >= nr_cpu_ids)
	383	return BAD_APICID;
2f205bc4	384	return cpu_2_logical_apicid[cpu];
61b90b7c IM	385	}
	386
	387	/*
	388	* Supporting over 60 cpus on NUMA-Q requires a locality-dependent
	389	* cpu to APIC ID relation to properly interact with the intelligent
	390	* mode of the cluster controller.
	391	*/
	392	static inline int numaq_cpu_present_to_apicid(int mps_cpu)
	393	{
	394	if (mps_cpu < 60)
	395	return ((mps_cpu >> 2) << 4) \| (1 << (mps_cpu & 0x3));
	396	else
	397	return BAD_APICID;
	398	}
	399
36afc3af	400	static inline int numaq_apicid_to_node(int logical_apicid)
61b90b7c IM	401	{
	402	return logical_apicid >> 4;
	403	}
	404
	405	static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
	406	{
	407	int node = numaq_apicid_to_node(logical_apicid);
	408	int cpu = __ffs(logical_apicid & 0xf);
	409
	410	return physid_mask_of_physid(cpu + 4*node);
	411	}
	412
4f179d12 IM	413	/* Where the IO area was mapped on multiquad, always 0 otherwise */
4f179d12 IM	414	void *xquad_portio;
61b90b7c IM	415
	416	static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
	417	{
	418	return 1;
	419	}
	420
	421	/*
	422	* We use physical apicids here, not logical, so just return the default
	423	* physical broadcast to stop people from breaking us
	424	*/
73e907de	425	static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask)
61b90b7c IM	426	{
	427	return 0x0F;
	428	}
	429
	430	static inline unsigned int
	431	numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
	432	const struct cpumask *andmask)
	433	{
	434	return 0x0F;
	435	}
	436
	437	/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
	438	static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
	439	{
	440	return cpuid_apic >> index_msb;
	441	}
36afc3af IM	442
36afc3af IM	443	static int
cb81eaed	444	numaq_mps_oem_check(struct mpc_table mpc, char oem, char *productid)
61b90b7c	445	{
cb81eaed IM	446	if (strncmp(oem, "IBM NUMA", 8))
	447	printk(KERN_ERR "Warning! Not a NUMA-Q system!\n");
	448	else
	449	found_numaq = 1;
	450
61b90b7c IM	451	return found_numaq;
	452	}
	453
	454	static int probe_numaq(void)
	455	{
	456	/* already know from get_memcfg_numaq() */
	457	return found_numaq;
	458	}
	459
73e907de	460	static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask)
61b90b7c IM	461	{
	462	/* Careful. Some cpus do not strictly honor the set of cpus
	463	* specified in the interrupt destination when using lowest
	464	* priority interrupt delivery mode.
	465	*
	466	* In particular there was a hyperthreading cpu observed to
	467	* deliver interrupts to the wrong hyperthread when only one
	468	* hyperthread was specified in the interrupt desitination.
	469	*/
5c6cb5e2 RR	470	cpumask_clear(retmask);
5c6cb5e2 RR	471	cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
61b90b7c IM	472	}
	473
	474	static void numaq_setup_portio_remap(void)
	475	{
	476	int num_quads = num_online_nodes();
	477
	478	if (num_quads <= 1)
4f179d12	479	return;
61b90b7c	480
cb81eaed IM	481	printk(KERN_INFO
	482	"Remapping cross-quad port I/O for %d quads\n", num_quads);
	483
61b90b7c	484	xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
cb81eaed IM	485
	486	printk(KERN_INFO
	487	"xquad_portio vaddr 0x%08lx, len %08lx\n",
61b90b7c IM	488	(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
	489	}
	490
7473727b RM	491	/* Use __refdata to keep false positive warning calm. */
7473727b RM	492	struct apic __refdata apic_numaq = {
61b90b7c IM	493
	494	.name = "NUMAQ",
	495	.probe = probe_numaq,
	496	.acpi_madt_oem_check = NULL,
	497	.apic_id_registered = numaq_apic_id_registered,
	498
	499	.irq_delivery_mode = dest_LowestPrio,
	500	/* physical delivery on LOCAL quad: */
	501	.irq_dest_mode = 0,
	502
	503	.target_cpus = numaq_target_cpus,
	504	.disable_esr = 1,
	505	.dest_logical = APIC_DEST_LOGICAL,
	506	.check_apicid_used = numaq_check_apicid_used,
	507	.check_apicid_present = numaq_check_apicid_present,
	508
	509	.vector_allocation_domain = numaq_vector_allocation_domain,
	510	.init_apic_ldr = numaq_init_apic_ldr,
	511
	512	.ioapic_phys_id_map = numaq_ioapic_phys_id_map,
	513	.setup_apic_routing = numaq_setup_apic_routing,
	514	.multi_timer_check = numaq_multi_timer_check,
	515	.apicid_to_node = numaq_apicid_to_node,
	516	.cpu_to_logical_apicid = numaq_cpu_to_logical_apicid,
	517	.cpu_present_to_apicid = numaq_cpu_present_to_apicid,
	518	.apicid_to_cpu_present = numaq_apicid_to_cpu_present,
	519	.setup_portio_remap = numaq_setup_portio_remap,
	520	.check_phys_apicid_present = numaq_check_phys_apicid_present,
	521	.enable_apic_mode = NULL,
	522	.phys_pkg_id = numaq_phys_pkg_id,
cb81eaed	523	.mps_oem_check = numaq_mps_oem_check,
61b90b7c IM	524
	525	.get_apic_id = numaq_get_apic_id,
	526	.set_apic_id = NULL,
	527	.apic_id_mask = 0x0F << 24,
	528
	529	.cpu_mask_to_apicid = numaq_cpu_mask_to_apicid,
	530	.cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and,
	531
	532	.send_IPI_mask = numaq_send_IPI_mask,
	533	.send_IPI_mask_allbutself = NULL,
	534	.send_IPI_allbutself = numaq_send_IPI_allbutself,
	535	.send_IPI_all = numaq_send_IPI_all,
6b64ee02	536	.send_IPI_self = default_send_IPI_self,
61b90b7c	537
1f5bcabf	538	.wakeup_secondary_cpu = wakeup_secondary_cpu_via_nmi,
61b90b7c IM	539	.trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW,
	540	.trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH,
	541
	542	/* We don't do anything here because we use NMI's to boot instead */
	543	.wait_for_init_deassert = NULL,
	544
	545	.smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic,
61b90b7c	546	.inquire_remote_apic = NULL,
c1eeb2de YL	547
	548	.read = native_apic_mem_read,
	549	.write = native_apic_mem_write,
	550	.icr_read = native_apic_icr_read,
	551	.icr_write = native_apic_icr_write,
	552	.wait_icr_idle = native_apic_wait_icr_idle,
	553	.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
61b90b7c	554	};