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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Written by: Patricia Gaughen, IBM Corporation | |
3 | * | |
4 | * Copyright (C) 2002, IBM Corp. | |
cb81eaed | 5 | * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar |
1da177e4 | 6 | * |
4f179d12 | 7 | * All rights reserved. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
17 | * NON INFRINGEMENT. See the GNU General Public License for more | |
18 | * details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * | |
24 | * Send feedback to <gone@us.ibm.com> | |
25 | */ | |
4f179d12 | 26 | #include <linux/nodemask.h> |
cb81eaed | 27 | #include <linux/topology.h> |
1da177e4 | 28 | #include <linux/bootmem.h> |
a9ce6bc1 | 29 | #include <linux/memblock.h> |
36afc3af IM |
30 | #include <linux/threads.h> |
31 | #include <linux/cpumask.h> | |
32 | #include <linux/kernel.h> | |
1da177e4 LT |
33 | #include <linux/mmzone.h> |
34 | #include <linux/module.h> | |
36afc3af IM |
35 | #include <linux/string.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/numa.h> | |
38 | #include <linux/smp.h> | |
cb81eaed | 39 | #include <linux/io.h> |
4f179d12 IM |
40 | #include <linux/mm.h> |
41 | ||
e1474e2d | 42 | #include <asm/processor.h> |
36afc3af IM |
43 | #include <asm/fixmap.h> |
44 | #include <asm/mpspec.h> | |
4f179d12 | 45 | #include <asm/numaq.h> |
64898a8b | 46 | #include <asm/setup.h> |
36afc3af | 47 | #include <asm/apic.h> |
4f179d12 | 48 | #include <asm/e820.h> |
36afc3af | 49 | #include <asm/ipi.h> |
1da177e4 | 50 | |
36afc3af IM |
51 | #define MB_TO_PAGES(addr) ((addr) << (20 - PAGE_SHIFT)) |
52 | ||
cb81eaed IM |
53 | int found_numaq; |
54 | ||
55 | /* | |
56 | * Have to match translation table entries to main table entries by counter | |
57 | * hence the mpc_record variable .... can't see a less disgusting way of | |
58 | * doing this .... | |
59 | */ | |
60 | struct mpc_trans { | |
61 | unsigned char mpc_type; | |
62 | unsigned char trans_len; | |
63 | unsigned char trans_type; | |
64 | unsigned char trans_quad; | |
65 | unsigned char trans_global; | |
66 | unsigned char trans_local; | |
67 | unsigned short trans_reserved; | |
68 | }; | |
69 | ||
cb81eaed IM |
70 | static int mpc_record; |
71 | ||
b6122b38 | 72 | static struct mpc_trans *translation_table[MAX_MPC_ENTRY]; |
cb81eaed IM |
73 | |
74 | int mp_bus_id_to_node[MAX_MP_BUSSES]; | |
75 | int mp_bus_id_to_local[MAX_MP_BUSSES]; | |
76 | int quad_local_to_mp_bus_id[NR_CPUS/4][4]; | |
77 | ||
78 | ||
36afc3af IM |
79 | static inline void numaq_register_node(int node, struct sys_cfg_data *scd) |
80 | { | |
81 | struct eachquadmem *eq = scd->eq + node; | |
82 | ||
83 | node_set_online(node); | |
84 | ||
85 | /* Convert to pages */ | |
86 | node_start_pfn[node] = | |
87 | MB_TO_PAGES(eq->hi_shrd_mem_start - eq->priv_mem_size); | |
88 | ||
89 | node_end_pfn[node] = | |
90 | MB_TO_PAGES(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size); | |
91 | ||
a9ce6bc1 | 92 | memblock_x86_register_active_regions(node, node_start_pfn[node], |
36afc3af IM |
93 | node_end_pfn[node]); |
94 | ||
95 | memory_present(node, node_start_pfn[node], node_end_pfn[node]); | |
96 | ||
97 | node_remap_size[node] = node_memmap_size_bytes(node, | |
98 | node_start_pfn[node], | |
99 | node_end_pfn[node]); | |
100 | } | |
1da177e4 LT |
101 | |
102 | /* | |
103 | * Function: smp_dump_qct() | |
104 | * | |
105 | * Description: gets memory layout from the quad config table. This | |
106 | * function also updates node_online_map with the nodes (quads) present. | |
107 | */ | |
108 | static void __init smp_dump_qct(void) | |
109 | { | |
36afc3af | 110 | struct sys_cfg_data *scd; |
1da177e4 | 111 | int node; |
36afc3af IM |
112 | |
113 | scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR); | |
1da177e4 LT |
114 | |
115 | nodes_clear(node_online_map); | |
116 | for_each_node(node) { | |
36afc3af IM |
117 | if (scd->quads_present31_0 & (1 << node)) |
118 | numaq_register_node(node, scd); | |
1da177e4 LT |
119 | } |
120 | } | |
121 | ||
b2a6a58c | 122 | void __cpuinit numaq_tsc_disable(void) |
64898a8b YL |
123 | { |
124 | if (!found_numaq) | |
125 | return; | |
126 | ||
127 | if (num_online_nodes() > 1) { | |
128 | printk(KERN_DEBUG "NUMAQ: disabling TSC\n"); | |
129 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
130 | } | |
131 | } | |
132 | ||
845b3944 | 133 | static void __init numaq_tsc_init(void) |
63b5d7af YL |
134 | { |
135 | numaq_tsc_disable(); | |
63b5d7af YL |
136 | } |
137 | ||
64898a8b YL |
138 | static inline int generate_logical_apicid(int quad, int phys_apicid) |
139 | { | |
140 | return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1); | |
141 | } | |
142 | ||
143 | /* x86_quirks member */ | |
f4f21b71 | 144 | static int mpc_apic_id(struct mpc_cpu *m) |
64898a8b YL |
145 | { |
146 | int quad = translation_table[mpc_record]->trans_quad; | |
c4563826 | 147 | int logical_apicid = generate_logical_apicid(quad, m->apicid); |
64898a8b | 148 | |
36afc3af IM |
149 | printk(KERN_DEBUG |
150 | "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n", | |
151 | m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8, | |
152 | (m->cpufeature & CPU_MODEL_MASK) >> 4, | |
153 | m->apicver, quad, logical_apicid); | |
154 | ||
64898a8b YL |
155 | return logical_apicid; |
156 | } | |
157 | ||
64898a8b | 158 | /* x86_quirks member */ |
00fb8606 | 159 | static void mpc_oem_bus_info(struct mpc_bus *m, char *name) |
64898a8b YL |
160 | { |
161 | int quad = translation_table[mpc_record]->trans_quad; | |
162 | int local = translation_table[mpc_record]->trans_local; | |
163 | ||
d4c715fa JSR |
164 | mp_bus_id_to_node[m->busid] = quad; |
165 | mp_bus_id_to_local[m->busid] = local; | |
36afc3af IM |
166 | |
167 | printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad); | |
64898a8b YL |
168 | } |
169 | ||
64898a8b | 170 | /* x86_quirks member */ |
00fb8606 | 171 | static void mpc_oem_pci_bus(struct mpc_bus *m) |
64898a8b YL |
172 | { |
173 | int quad = translation_table[mpc_record]->trans_quad; | |
174 | int local = translation_table[mpc_record]->trans_local; | |
175 | ||
d4c715fa | 176 | quad_local_to_mp_bus_id[quad][local] = m->busid; |
64898a8b YL |
177 | } |
178 | ||
f4848472 TG |
179 | /* |
180 | * Called from mpparse code. | |
181 | * mode = 0: prescan | |
182 | * mode = 1: one mpc entry scanned | |
183 | */ | |
184 | static void numaq_mpc_record(unsigned int mode) | |
185 | { | |
186 | if (!mode) | |
187 | mpc_record = 0; | |
188 | else | |
189 | mpc_record++; | |
190 | } | |
191 | ||
36afc3af | 192 | static void __init MP_translation_info(struct mpc_trans *m) |
64898a8b YL |
193 | { |
194 | printk(KERN_INFO | |
cb81eaed | 195 | "Translation: record %d, type %d, quad %d, global %d, local %d\n", |
64898a8b YL |
196 | mpc_record, m->trans_type, m->trans_quad, m->trans_global, |
197 | m->trans_local); | |
198 | ||
199 | if (mpc_record >= MAX_MPC_ENTRY) | |
200 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); | |
201 | else | |
36afc3af IM |
202 | translation_table[mpc_record] = m; /* stash this for later */ |
203 | ||
64898a8b YL |
204 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
205 | node_set_online(m->trans_quad); | |
206 | } | |
207 | ||
208 | static int __init mpf_checksum(unsigned char *mp, int len) | |
209 | { | |
210 | int sum = 0; | |
211 | ||
212 | while (len--) | |
213 | sum += *mp++; | |
214 | ||
215 | return sum & 0xFF; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Read/parse the MPC oem tables | |
220 | */ | |
72302142 | 221 | static void __init smp_read_mpc_oem(struct mpc_table *mpc) |
64898a8b | 222 | { |
72302142 | 223 | struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr; |
64898a8b YL |
224 | int count = sizeof(*oemtable); /* the header size */ |
225 | unsigned char *oemptr = ((unsigned char *)oemtable) + count; | |
226 | ||
227 | mpc_record = 0; | |
36afc3af | 228 | printk(KERN_INFO |
3235dc3f | 229 | "Found an OEM MPC table at %8p - parsing it...\n", oemtable); |
36afc3af | 230 | |
a1d0272a | 231 | if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) { |
64898a8b YL |
232 | printk(KERN_WARNING |
233 | "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
a1d0272a JSR |
234 | oemtable->signature[0], oemtable->signature[1], |
235 | oemtable->signature[2], oemtable->signature[3]); | |
64898a8b YL |
236 | return; |
237 | } | |
36afc3af | 238 | |
a1d0272a | 239 | if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) { |
64898a8b YL |
240 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
241 | return; | |
242 | } | |
36afc3af | 243 | |
a1d0272a | 244 | while (count < oemtable->length) { |
64898a8b YL |
245 | switch (*oemptr) { |
246 | case MP_TRANSLATION: | |
247 | { | |
36afc3af IM |
248 | struct mpc_trans *m = (void *)oemptr; |
249 | ||
64898a8b YL |
250 | MP_translation_info(m); |
251 | oemptr += sizeof(*m); | |
252 | count += sizeof(*m); | |
253 | ++mpc_record; | |
254 | break; | |
255 | } | |
256 | default: | |
36afc3af IM |
257 | printk(KERN_WARNING |
258 | "Unrecognised OEM table entry type! - %d\n", | |
259 | (int)*oemptr); | |
260 | return; | |
64898a8b YL |
261 | } |
262 | } | |
263 | } | |
264 | ||
ab530e1f YL |
265 | static __init void early_check_numaq(void) |
266 | { | |
ab530e1f YL |
267 | /* |
268 | * get boot-time SMP configuration: | |
269 | */ | |
270 | if (smp_found_config) | |
271 | early_get_smp_config(); | |
64898a8b | 272 | |
f4848472 | 273 | if (found_numaq) { |
f4848472 | 274 | x86_init.mpparse.mpc_record = numaq_mpc_record; |
de934103 | 275 | x86_init.mpparse.setup_ioapic_ids = x86_init_noop; |
fd6c6661 | 276 | x86_init.mpparse.mpc_apic_id = mpc_apic_id; |
72302142 | 277 | x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem; |
52fdb568 | 278 | x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus; |
90e1c696 | 279 | x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info; |
845b3944 | 280 | x86_init.timers.tsc_pre_init = numaq_tsc_init; |
b72d0db9 | 281 | x86_init.pci.init = pci_numaq_init; |
f4848472 | 282 | } |
ab530e1f YL |
283 | } |
284 | ||
1da177e4 LT |
285 | int __init get_memcfg_numaq(void) |
286 | { | |
ab530e1f YL |
287 | early_check_numaq(); |
288 | if (!found_numaq) | |
289 | return 0; | |
1da177e4 | 290 | smp_dump_qct(); |
36afc3af | 291 | |
1da177e4 LT |
292 | return 1; |
293 | } | |
61b90b7c | 294 | |
61b90b7c IM |
295 | #define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER) |
296 | ||
297 | static inline unsigned int numaq_get_apic_id(unsigned long x) | |
298 | { | |
299 | return (x >> 24) & 0x0F; | |
300 | } | |
301 | ||
61b90b7c IM |
302 | static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector) |
303 | { | |
43f39890 | 304 | default_send_IPI_mask_sequence_logical(mask, vector); |
61b90b7c IM |
305 | } |
306 | ||
307 | static inline void numaq_send_IPI_allbutself(int vector) | |
308 | { | |
43f39890 | 309 | default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector); |
61b90b7c IM |
310 | } |
311 | ||
312 | static inline void numaq_send_IPI_all(int vector) | |
313 | { | |
314 | numaq_send_IPI_mask(cpu_online_mask, vector); | |
315 | } | |
316 | ||
36afc3af IM |
317 | #define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8) |
318 | #define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa) | |
61b90b7c IM |
319 | |
320 | /* | |
321 | * Because we use NMIs rather than the INIT-STARTUP sequence to | |
322 | * bootstrap the CPUs, the APIC may be in a weird state. Kick it: | |
323 | */ | |
324 | static inline void numaq_smp_callin_clear_local_apic(void) | |
325 | { | |
326 | clear_local_APIC(); | |
327 | } | |
328 | ||
73e907de | 329 | static inline const struct cpumask *numaq_target_cpus(void) |
61b90b7c | 330 | { |
101aaca1 | 331 | return cpu_all_mask; |
61b90b7c IM |
332 | } |
333 | ||
7abc0753 | 334 | static unsigned long numaq_check_apicid_used(physid_mask_t *map, int apicid) |
61b90b7c | 335 | { |
7abc0753 | 336 | return physid_isset(apicid, *map); |
61b90b7c IM |
337 | } |
338 | ||
339 | static inline unsigned long numaq_check_apicid_present(int bit) | |
340 | { | |
341 | return physid_isset(bit, phys_cpu_present_map); | |
342 | } | |
343 | ||
61b90b7c IM |
344 | static inline int numaq_apic_id_registered(void) |
345 | { | |
346 | return 1; | |
347 | } | |
348 | ||
349 | static inline void numaq_init_apic_ldr(void) | |
350 | { | |
351 | /* Already done in NUMA-Q firmware */ | |
352 | } | |
353 | ||
354 | static inline void numaq_setup_apic_routing(void) | |
355 | { | |
cb81eaed IM |
356 | printk(KERN_INFO |
357 | "Enabling APIC mode: NUMA-Q. Using %d I/O APICs\n", | |
358 | nr_ioapics); | |
61b90b7c IM |
359 | } |
360 | ||
361 | /* | |
362 | * Skip adding the timer int on secondary nodes, which causes | |
363 | * a small but painful rift in the time-space continuum. | |
364 | */ | |
365 | static inline int numaq_multi_timer_check(int apic, int irq) | |
366 | { | |
367 | return apic != 0 && irq == 0; | |
368 | } | |
369 | ||
7abc0753 | 370 | static inline void numaq_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
61b90b7c IM |
371 | { |
372 | /* We don't have a good way to do this yet - hack */ | |
7abc0753 | 373 | return physids_promote(0xFUL, retmap); |
61b90b7c IM |
374 | } |
375 | ||
61b90b7c IM |
376 | static inline int numaq_cpu_to_logical_apicid(int cpu) |
377 | { | |
378 | if (cpu >= nr_cpu_ids) | |
379 | return BAD_APICID; | |
2f205bc4 | 380 | return cpu_2_logical_apicid[cpu]; |
61b90b7c IM |
381 | } |
382 | ||
383 | /* | |
384 | * Supporting over 60 cpus on NUMA-Q requires a locality-dependent | |
385 | * cpu to APIC ID relation to properly interact with the intelligent | |
386 | * mode of the cluster controller. | |
387 | */ | |
388 | static inline int numaq_cpu_present_to_apicid(int mps_cpu) | |
389 | { | |
390 | if (mps_cpu < 60) | |
391 | return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3)); | |
392 | else | |
393 | return BAD_APICID; | |
394 | } | |
395 | ||
36afc3af | 396 | static inline int numaq_apicid_to_node(int logical_apicid) |
61b90b7c IM |
397 | { |
398 | return logical_apicid >> 4; | |
399 | } | |
400 | ||
7abc0753 | 401 | static void numaq_apicid_to_cpu_present(int logical_apicid, physid_mask_t *retmap) |
61b90b7c IM |
402 | { |
403 | int node = numaq_apicid_to_node(logical_apicid); | |
404 | int cpu = __ffs(logical_apicid & 0xf); | |
405 | ||
7abc0753 | 406 | physid_set_mask_of_physid(cpu + 4*node, retmap); |
61b90b7c IM |
407 | } |
408 | ||
4f179d12 IM |
409 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ |
410 | void *xquad_portio; | |
61b90b7c | 411 | |
e11dadab | 412 | static inline int numaq_check_phys_apicid_present(int phys_apicid) |
61b90b7c IM |
413 | { |
414 | return 1; | |
415 | } | |
416 | ||
417 | /* | |
418 | * We use physical apicids here, not logical, so just return the default | |
419 | * physical broadcast to stop people from breaking us | |
420 | */ | |
73e907de | 421 | static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask) |
61b90b7c IM |
422 | { |
423 | return 0x0F; | |
424 | } | |
425 | ||
426 | static inline unsigned int | |
427 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
428 | const struct cpumask *andmask) | |
429 | { | |
430 | return 0x0F; | |
431 | } | |
432 | ||
433 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | |
434 | static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb) | |
435 | { | |
436 | return cpuid_apic >> index_msb; | |
437 | } | |
36afc3af IM |
438 | |
439 | static int | |
cb81eaed | 440 | numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid) |
61b90b7c | 441 | { |
cb81eaed IM |
442 | if (strncmp(oem, "IBM NUMA", 8)) |
443 | printk(KERN_ERR "Warning! Not a NUMA-Q system!\n"); | |
444 | else | |
445 | found_numaq = 1; | |
446 | ||
61b90b7c IM |
447 | return found_numaq; |
448 | } | |
449 | ||
450 | static int probe_numaq(void) | |
451 | { | |
452 | /* already know from get_memcfg_numaq() */ | |
453 | return found_numaq; | |
454 | } | |
455 | ||
73e907de | 456 | static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask) |
61b90b7c IM |
457 | { |
458 | /* Careful. Some cpus do not strictly honor the set of cpus | |
459 | * specified in the interrupt destination when using lowest | |
460 | * priority interrupt delivery mode. | |
461 | * | |
462 | * In particular there was a hyperthreading cpu observed to | |
463 | * deliver interrupts to the wrong hyperthread when only one | |
464 | * hyperthread was specified in the interrupt desitination. | |
465 | */ | |
5c6cb5e2 RR |
466 | cpumask_clear(retmask); |
467 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
61b90b7c IM |
468 | } |
469 | ||
470 | static void numaq_setup_portio_remap(void) | |
471 | { | |
472 | int num_quads = num_online_nodes(); | |
473 | ||
474 | if (num_quads <= 1) | |
4f179d12 | 475 | return; |
61b90b7c | 476 | |
cb81eaed IM |
477 | printk(KERN_INFO |
478 | "Remapping cross-quad port I/O for %d quads\n", num_quads); | |
479 | ||
61b90b7c | 480 | xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD); |
cb81eaed IM |
481 | |
482 | printk(KERN_INFO | |
483 | "xquad_portio vaddr 0x%08lx, len %08lx\n", | |
61b90b7c IM |
484 | (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD); |
485 | } | |
486 | ||
7473727b RM |
487 | /* Use __refdata to keep false positive warning calm. */ |
488 | struct apic __refdata apic_numaq = { | |
61b90b7c IM |
489 | |
490 | .name = "NUMAQ", | |
491 | .probe = probe_numaq, | |
492 | .acpi_madt_oem_check = NULL, | |
493 | .apic_id_registered = numaq_apic_id_registered, | |
494 | ||
495 | .irq_delivery_mode = dest_LowestPrio, | |
496 | /* physical delivery on LOCAL quad: */ | |
497 | .irq_dest_mode = 0, | |
498 | ||
499 | .target_cpus = numaq_target_cpus, | |
500 | .disable_esr = 1, | |
501 | .dest_logical = APIC_DEST_LOGICAL, | |
502 | .check_apicid_used = numaq_check_apicid_used, | |
503 | .check_apicid_present = numaq_check_apicid_present, | |
504 | ||
505 | .vector_allocation_domain = numaq_vector_allocation_domain, | |
506 | .init_apic_ldr = numaq_init_apic_ldr, | |
507 | ||
508 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, | |
509 | .setup_apic_routing = numaq_setup_apic_routing, | |
510 | .multi_timer_check = numaq_multi_timer_check, | |
511 | .apicid_to_node = numaq_apicid_to_node, | |
512 | .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid, | |
513 | .cpu_present_to_apicid = numaq_cpu_present_to_apicid, | |
514 | .apicid_to_cpu_present = numaq_apicid_to_cpu_present, | |
515 | .setup_portio_remap = numaq_setup_portio_remap, | |
516 | .check_phys_apicid_present = numaq_check_phys_apicid_present, | |
517 | .enable_apic_mode = NULL, | |
518 | .phys_pkg_id = numaq_phys_pkg_id, | |
cb81eaed | 519 | .mps_oem_check = numaq_mps_oem_check, |
61b90b7c IM |
520 | |
521 | .get_apic_id = numaq_get_apic_id, | |
522 | .set_apic_id = NULL, | |
523 | .apic_id_mask = 0x0F << 24, | |
524 | ||
525 | .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid, | |
526 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, | |
527 | ||
528 | .send_IPI_mask = numaq_send_IPI_mask, | |
529 | .send_IPI_mask_allbutself = NULL, | |
530 | .send_IPI_allbutself = numaq_send_IPI_allbutself, | |
531 | .send_IPI_all = numaq_send_IPI_all, | |
6b64ee02 | 532 | .send_IPI_self = default_send_IPI_self, |
61b90b7c | 533 | |
1f5bcabf | 534 | .wakeup_secondary_cpu = wakeup_secondary_cpu_via_nmi, |
61b90b7c IM |
535 | .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW, |
536 | .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH, | |
537 | ||
538 | /* We don't do anything here because we use NMI's to boot instead */ | |
539 | .wait_for_init_deassert = NULL, | |
540 | ||
541 | .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic, | |
61b90b7c | 542 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
543 | |
544 | .read = native_apic_mem_read, | |
545 | .write = native_apic_mem_write, | |
546 | .icr_read = native_apic_icr_read, | |
547 | .icr_write = native_apic_icr_write, | |
548 | .wait_icr_idle = native_apic_wait_icr_idle, | |
549 | .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, | |
61b90b7c | 550 | }; |