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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
85ac16d0 | 132 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
133 | { |
134 | struct irq_pin_list *pin; | |
0b8f1efa YL |
135 | |
136 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
137 | |
138 | return pin; | |
139 | } | |
140 | ||
a1420f39 | 141 | struct irq_cfg { |
0f978f45 | 142 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
143 | cpumask_var_t domain; |
144 | cpumask_var_t old_domain; | |
497c9a19 | 145 | unsigned move_cleanup_count; |
a1420f39 | 146 | u8 vector; |
497c9a19 | 147 | u8 move_in_progress : 1; |
a1420f39 YL |
148 | }; |
149 | ||
a1420f39 | 150 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
151 | #ifdef CONFIG_SPARSE_IRQ |
152 | static struct irq_cfg irq_cfgx[] = { | |
153 | #else | |
d6c88a50 | 154 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 155 | #endif |
22f65d31 MT |
156 | [0] = { .vector = IRQ0_VECTOR, }, |
157 | [1] = { .vector = IRQ1_VECTOR, }, | |
158 | [2] = { .vector = IRQ2_VECTOR, }, | |
159 | [3] = { .vector = IRQ3_VECTOR, }, | |
160 | [4] = { .vector = IRQ4_VECTOR, }, | |
161 | [5] = { .vector = IRQ5_VECTOR, }, | |
162 | [6] = { .vector = IRQ6_VECTOR, }, | |
163 | [7] = { .vector = IRQ7_VECTOR, }, | |
164 | [8] = { .vector = IRQ8_VECTOR, }, | |
165 | [9] = { .vector = IRQ9_VECTOR, }, | |
166 | [10] = { .vector = IRQ10_VECTOR, }, | |
167 | [11] = { .vector = IRQ11_VECTOR, }, | |
168 | [12] = { .vector = IRQ12_VECTOR, }, | |
169 | [13] = { .vector = IRQ13_VECTOR, }, | |
170 | [14] = { .vector = IRQ14_VECTOR, }, | |
171 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
172 | }; |
173 | ||
13a0c3c2 | 174 | int __init arch_early_irq_init(void) |
8f09cd20 | 175 | { |
0b8f1efa YL |
176 | struct irq_cfg *cfg; |
177 | struct irq_desc *desc; | |
178 | int count; | |
179 | int i; | |
d6c88a50 | 180 | |
0b8f1efa YL |
181 | cfg = irq_cfgx; |
182 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 183 | |
0b8f1efa YL |
184 | for (i = 0; i < count; i++) { |
185 | desc = irq_to_desc(i); | |
186 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
187 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
188 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
189 | if (i < NR_IRQS_LEGACY) | |
190 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 191 | } |
13a0c3c2 YL |
192 | |
193 | return 0; | |
0b8f1efa | 194 | } |
8f09cd20 | 195 | |
0b8f1efa | 196 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 197 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 198 | { |
0b8f1efa YL |
199 | struct irq_cfg *cfg = NULL; |
200 | struct irq_desc *desc; | |
1da177e4 | 201 | |
0b8f1efa YL |
202 | desc = irq_to_desc(irq); |
203 | if (desc) | |
204 | cfg = desc->chip_data; | |
0f978f45 | 205 | |
0b8f1efa | 206 | return cfg; |
8f09cd20 | 207 | } |
d6c88a50 | 208 | |
85ac16d0 | 209 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 210 | { |
0b8f1efa | 211 | struct irq_cfg *cfg; |
0f978f45 | 212 | |
0b8f1efa | 213 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 214 | if (cfg) { |
80855f73 | 215 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
216 | kfree(cfg); |
217 | cfg = NULL; | |
80855f73 MT |
218 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
219 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
220 | free_cpumask_var(cfg->domain); |
221 | kfree(cfg); | |
222 | cfg = NULL; | |
223 | } else { | |
224 | cpumask_clear(cfg->domain); | |
225 | cpumask_clear(cfg->old_domain); | |
226 | } | |
227 | } | |
0f978f45 | 228 | |
0b8f1efa | 229 | return cfg; |
8f09cd20 YL |
230 | } |
231 | ||
85ac16d0 | 232 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 233 | { |
0b8f1efa | 234 | struct irq_cfg *cfg; |
d6c88a50 | 235 | |
0b8f1efa YL |
236 | cfg = desc->chip_data; |
237 | if (!cfg) { | |
85ac16d0 | 238 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
239 | if (!desc->chip_data) { |
240 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
241 | BUG_ON(1); | |
242 | } | |
243 | } | |
1da177e4 | 244 | |
13a0c3c2 | 245 | return 0; |
0b8f1efa | 246 | } |
0f978f45 | 247 | |
fcef5911 | 248 | /* for move_irq_desc */ |
48a1b10a | 249 | static void |
85ac16d0 | 250 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 251 | { |
48a1b10a YL |
252 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
253 | ||
254 | cfg->irq_2_pin = NULL; | |
255 | old_entry = old_cfg->irq_2_pin; | |
256 | if (!old_entry) | |
257 | return; | |
0f978f45 | 258 | |
85ac16d0 | 259 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
260 | if (!entry) |
261 | return; | |
0f978f45 | 262 | |
48a1b10a YL |
263 | entry->apic = old_entry->apic; |
264 | entry->pin = old_entry->pin; | |
265 | head = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | while (old_entry) { | |
85ac16d0 | 269 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
270 | if (!entry) { |
271 | entry = head; | |
272 | while (entry) { | |
273 | head = entry->next; | |
274 | kfree(entry); | |
275 | entry = head; | |
276 | } | |
277 | /* still use the old one */ | |
278 | return; | |
279 | } | |
280 | entry->apic = old_entry->apic; | |
281 | entry->pin = old_entry->pin; | |
282 | tail->next = entry; | |
283 | tail = entry; | |
284 | old_entry = old_entry->next; | |
285 | } | |
0f978f45 | 286 | |
48a1b10a YL |
287 | tail->next = NULL; |
288 | cfg->irq_2_pin = head; | |
0f978f45 | 289 | } |
0f978f45 | 290 | |
48a1b10a | 291 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 292 | { |
48a1b10a | 293 | struct irq_pin_list *entry, *next; |
0f978f45 | 294 | |
48a1b10a YL |
295 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
296 | return; | |
301e6190 | 297 | |
48a1b10a | 298 | entry = old_cfg->irq_2_pin; |
0f978f45 | 299 | |
48a1b10a YL |
300 | while (entry) { |
301 | next = entry->next; | |
302 | kfree(entry); | |
303 | entry = next; | |
304 | } | |
305 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 306 | } |
0f978f45 | 307 | |
48a1b10a | 308 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 309 | struct irq_desc *desc, int node) |
0f978f45 | 310 | { |
48a1b10a YL |
311 | struct irq_cfg *cfg; |
312 | struct irq_cfg *old_cfg; | |
0f978f45 | 313 | |
85ac16d0 | 314 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 315 | |
48a1b10a YL |
316 | if (!cfg) |
317 | return; | |
318 | ||
319 | desc->chip_data = cfg; | |
320 | ||
321 | old_cfg = old_desc->chip_data; | |
322 | ||
323 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
324 | ||
85ac16d0 | 325 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 326 | } |
1da177e4 | 327 | |
48a1b10a YL |
328 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
329 | { | |
330 | kfree(old_cfg); | |
331 | } | |
332 | ||
333 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
334 | { | |
335 | struct irq_cfg *old_cfg, *cfg; | |
336 | ||
337 | old_cfg = old_desc->chip_data; | |
338 | cfg = desc->chip_data; | |
339 | ||
340 | if (old_cfg == cfg) | |
341 | return; | |
342 | ||
343 | if (old_cfg) { | |
344 | free_irq_2_pin(old_cfg, cfg); | |
345 | free_irq_cfg(old_cfg); | |
346 | old_desc->chip_data = NULL; | |
347 | } | |
348 | } | |
fcef5911 | 349 | /* end for move_irq_desc */ |
48a1b10a | 350 | |
0b8f1efa YL |
351 | #else |
352 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
353 | { | |
354 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 355 | } |
1da177e4 | 356 | |
0b8f1efa YL |
357 | #endif |
358 | ||
130fe05d LT |
359 | struct io_apic { |
360 | unsigned int index; | |
361 | unsigned int unused[3]; | |
362 | unsigned int data; | |
0280f7c4 SS |
363 | unsigned int unused2[11]; |
364 | unsigned int eoi; | |
130fe05d LT |
365 | }; |
366 | ||
367 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
368 | { | |
369 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 370 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
371 | } |
372 | ||
0280f7c4 SS |
373 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
374 | { | |
375 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
376 | writel(vector, &io_apic->eoi); | |
377 | } | |
378 | ||
130fe05d LT |
379 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
380 | { | |
381 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
382 | writel(reg, &io_apic->index); | |
383 | return readl(&io_apic->data); | |
384 | } | |
385 | ||
386 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
387 | { | |
388 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
389 | writel(reg, &io_apic->index); | |
390 | writel(value, &io_apic->data); | |
391 | } | |
392 | ||
393 | /* | |
394 | * Re-write a value: to be used for read-modify-write | |
395 | * cycles where the read already set up the index register. | |
396 | * | |
397 | * Older SiS APIC requires we rewrite the index register | |
398 | */ | |
399 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
400 | { | |
54168ed7 | 401 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
402 | |
403 | if (sis_apic_bug) | |
404 | writel(reg, &io_apic->index); | |
130fe05d LT |
405 | writel(value, &io_apic->data); |
406 | } | |
407 | ||
3145e941 | 408 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
409 | { |
410 | struct irq_pin_list *entry; | |
411 | unsigned long flags; | |
047c8fdb YL |
412 | |
413 | spin_lock_irqsave(&ioapic_lock, flags); | |
414 | entry = cfg->irq_2_pin; | |
415 | for (;;) { | |
416 | unsigned int reg; | |
417 | int pin; | |
418 | ||
419 | if (!entry) | |
420 | break; | |
421 | pin = entry->pin; | |
422 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
423 | /* Is the remote IRR bit set? */ | |
424 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
425 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
426 | return true; | |
427 | } | |
428 | if (!entry->next) | |
429 | break; | |
430 | entry = entry->next; | |
431 | } | |
432 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
433 | ||
434 | return false; | |
435 | } | |
047c8fdb | 436 | |
cf4c6a2f AK |
437 | union entry_union { |
438 | struct { u32 w1, w2; }; | |
439 | struct IO_APIC_route_entry entry; | |
440 | }; | |
441 | ||
442 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
443 | { | |
444 | union entry_union eu; | |
445 | unsigned long flags; | |
446 | spin_lock_irqsave(&ioapic_lock, flags); | |
447 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
448 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
449 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
450 | return eu.entry; | |
451 | } | |
452 | ||
f9dadfa7 LT |
453 | /* |
454 | * When we write a new IO APIC routing entry, we need to write the high | |
455 | * word first! If the mask bit in the low word is clear, we will enable | |
456 | * the interrupt, and we need to make sure the entry is fully populated | |
457 | * before that happens. | |
458 | */ | |
d15512f4 AK |
459 | static void |
460 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 461 | { |
cf4c6a2f AK |
462 | union entry_union eu; |
463 | eu.entry = e; | |
f9dadfa7 LT |
464 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
465 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
466 | } |
467 | ||
ca97ab90 | 468 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
469 | { |
470 | unsigned long flags; | |
471 | spin_lock_irqsave(&ioapic_lock, flags); | |
472 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
473 | spin_unlock_irqrestore(&ioapic_lock, flags); |
474 | } | |
475 | ||
476 | /* | |
477 | * When we mask an IO APIC routing entry, we need to write the low | |
478 | * word first, in order to set the mask bit before we change the | |
479 | * high bits! | |
480 | */ | |
481 | static void ioapic_mask_entry(int apic, int pin) | |
482 | { | |
483 | unsigned long flags; | |
484 | union entry_union eu = { .entry.mask = 1 }; | |
485 | ||
cf4c6a2f AK |
486 | spin_lock_irqsave(&ioapic_lock, flags); |
487 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
488 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
489 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
490 | } | |
491 | ||
1da177e4 LT |
492 | /* |
493 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
494 | * shared ISA-space IRQs, so we have to support them. We are super | |
495 | * fast in the common case, and fast for shared ISA-space IRQs. | |
496 | */ | |
85ac16d0 | 497 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 498 | { |
0f978f45 YL |
499 | struct irq_pin_list *entry; |
500 | ||
0f978f45 YL |
501 | entry = cfg->irq_2_pin; |
502 | if (!entry) { | |
85ac16d0 | 503 | entry = get_one_free_irq_2_pin(node); |
0b8f1efa YL |
504 | if (!entry) { |
505 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
506 | apic, pin); | |
507 | return; | |
508 | } | |
0f978f45 YL |
509 | cfg->irq_2_pin = entry; |
510 | entry->apic = apic; | |
511 | entry->pin = pin; | |
0f978f45 YL |
512 | return; |
513 | } | |
1da177e4 | 514 | |
0f978f45 YL |
515 | while (entry->next) { |
516 | /* not again, please */ | |
517 | if (entry->apic == apic && entry->pin == pin) | |
518 | return; | |
1da177e4 | 519 | |
0f978f45 | 520 | entry = entry->next; |
1da177e4 | 521 | } |
0f978f45 | 522 | |
85ac16d0 | 523 | entry->next = get_one_free_irq_2_pin(node); |
0f978f45 | 524 | entry = entry->next; |
1da177e4 LT |
525 | entry->apic = apic; |
526 | entry->pin = pin; | |
527 | } | |
528 | ||
529 | /* | |
530 | * Reroute an IRQ to a different pin. | |
531 | */ | |
85ac16d0 | 532 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
1da177e4 LT |
533 | int oldapic, int oldpin, |
534 | int newapic, int newpin) | |
535 | { | |
0f978f45 YL |
536 | struct irq_pin_list *entry = cfg->irq_2_pin; |
537 | int replaced = 0; | |
1da177e4 | 538 | |
0f978f45 | 539 | while (entry) { |
1da177e4 LT |
540 | if (entry->apic == oldapic && entry->pin == oldpin) { |
541 | entry->apic = newapic; | |
542 | entry->pin = newpin; | |
0f978f45 YL |
543 | replaced = 1; |
544 | /* every one is different, right? */ | |
1da177e4 | 545 | break; |
0f978f45 YL |
546 | } |
547 | entry = entry->next; | |
1da177e4 | 548 | } |
0f978f45 YL |
549 | |
550 | /* why? call replace before add? */ | |
551 | if (!replaced) | |
85ac16d0 | 552 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
1da177e4 LT |
553 | } |
554 | ||
3145e941 | 555 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
556 | int mask_and, int mask_or, |
557 | void (*final)(struct irq_pin_list *entry)) | |
558 | { | |
559 | int pin; | |
87783be4 | 560 | struct irq_pin_list *entry; |
047c8fdb | 561 | |
87783be4 CG |
562 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
563 | unsigned int reg; | |
564 | pin = entry->pin; | |
565 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
566 | reg &= mask_and; | |
567 | reg |= mask_or; | |
568 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
569 | if (final) | |
570 | final(entry); | |
571 | } | |
572 | } | |
047c8fdb | 573 | |
3145e941 | 574 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 575 | { |
3145e941 | 576 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 577 | } |
047c8fdb | 578 | |
4e738e2f | 579 | #ifdef CONFIG_X86_64 |
7f3e632f | 580 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 581 | { |
87783be4 CG |
582 | /* |
583 | * Synchronize the IO-APIC and the CPU by doing | |
584 | * a dummy read from the IO-APIC | |
585 | */ | |
586 | struct io_apic __iomem *io_apic; | |
587 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 588 | readl(&io_apic->data); |
1da177e4 LT |
589 | } |
590 | ||
3145e941 | 591 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 592 | { |
3145e941 | 593 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
594 | } |
595 | #else /* CONFIG_X86_32 */ | |
3145e941 | 596 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 597 | { |
3145e941 | 598 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 599 | } |
1da177e4 | 600 | |
3145e941 | 601 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 602 | { |
3145e941 | 603 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
604 | IO_APIC_REDIR_MASKED, NULL); |
605 | } | |
1da177e4 | 606 | |
3145e941 | 607 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 608 | { |
3145e941 | 609 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
610 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
611 | } | |
612 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 613 | |
3145e941 | 614 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 615 | { |
3145e941 | 616 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
617 | unsigned long flags; |
618 | ||
3145e941 YL |
619 | BUG_ON(!cfg); |
620 | ||
1da177e4 | 621 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 622 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
623 | spin_unlock_irqrestore(&ioapic_lock, flags); |
624 | } | |
625 | ||
3145e941 | 626 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 627 | { |
3145e941 | 628 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
629 | unsigned long flags; |
630 | ||
631 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 632 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
633 | spin_unlock_irqrestore(&ioapic_lock, flags); |
634 | } | |
635 | ||
3145e941 YL |
636 | static void mask_IO_APIC_irq(unsigned int irq) |
637 | { | |
638 | struct irq_desc *desc = irq_to_desc(irq); | |
639 | ||
640 | mask_IO_APIC_irq_desc(desc); | |
641 | } | |
642 | static void unmask_IO_APIC_irq(unsigned int irq) | |
643 | { | |
644 | struct irq_desc *desc = irq_to_desc(irq); | |
645 | ||
646 | unmask_IO_APIC_irq_desc(desc); | |
647 | } | |
648 | ||
1da177e4 LT |
649 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
650 | { | |
651 | struct IO_APIC_route_entry entry; | |
36062448 | 652 | |
1da177e4 | 653 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 654 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
655 | if (entry.delivery_mode == dest_SMI) |
656 | return; | |
1da177e4 LT |
657 | /* |
658 | * Disable it in the IO-APIC irq-routing table: | |
659 | */ | |
f9dadfa7 | 660 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
661 | } |
662 | ||
54168ed7 | 663 | static void clear_IO_APIC (void) |
1da177e4 LT |
664 | { |
665 | int apic, pin; | |
666 | ||
667 | for (apic = 0; apic < nr_ioapics; apic++) | |
668 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
669 | clear_IO_APIC_pin(apic, pin); | |
670 | } | |
671 | ||
54168ed7 | 672 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
673 | /* |
674 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
675 | * specific CPU-side IRQs. | |
676 | */ | |
677 | ||
678 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
679 | static int pirq_entries[MAX_PIRQS] = { |
680 | [0 ... MAX_PIRQS - 1] = -1 | |
681 | }; | |
1da177e4 | 682 | |
1da177e4 LT |
683 | static int __init ioapic_pirq_setup(char *str) |
684 | { | |
685 | int i, max; | |
686 | int ints[MAX_PIRQS+1]; | |
687 | ||
688 | get_options(str, ARRAY_SIZE(ints), ints); | |
689 | ||
1da177e4 LT |
690 | apic_printk(APIC_VERBOSE, KERN_INFO |
691 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
692 | max = MAX_PIRQS; | |
693 | if (ints[0] < MAX_PIRQS) | |
694 | max = ints[0]; | |
695 | ||
696 | for (i = 0; i < max; i++) { | |
697 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
698 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
699 | /* | |
700 | * PIRQs are mapped upside down, usually. | |
701 | */ | |
702 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
703 | } | |
704 | return 1; | |
705 | } | |
706 | ||
707 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
708 | #endif /* CONFIG_X86_32 */ |
709 | ||
b24696bc FY |
710 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
711 | { | |
712 | int apic; | |
713 | struct IO_APIC_route_entry **ioapic_entries; | |
714 | ||
715 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
716 | GFP_ATOMIC); | |
717 | if (!ioapic_entries) | |
718 | return 0; | |
719 | ||
720 | for (apic = 0; apic < nr_ioapics; apic++) { | |
721 | ioapic_entries[apic] = | |
722 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
723 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
724 | if (!ioapic_entries[apic]) | |
725 | goto nomem; | |
726 | } | |
727 | ||
728 | return ioapic_entries; | |
729 | ||
730 | nomem: | |
731 | while (--apic >= 0) | |
732 | kfree(ioapic_entries[apic]); | |
733 | kfree(ioapic_entries); | |
734 | ||
735 | return 0; | |
736 | } | |
54168ed7 IM |
737 | |
738 | /* | |
05c3dc2c | 739 | * Saves all the IO-APIC RTE's |
54168ed7 | 740 | */ |
b24696bc | 741 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 742 | { |
54168ed7 IM |
743 | int apic, pin; |
744 | ||
b24696bc FY |
745 | if (!ioapic_entries) |
746 | return -ENOMEM; | |
54168ed7 IM |
747 | |
748 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
749 | if (!ioapic_entries[apic]) |
750 | return -ENOMEM; | |
54168ed7 | 751 | |
05c3dc2c | 752 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 753 | ioapic_entries[apic][pin] = |
54168ed7 | 754 | ioapic_read_entry(apic, pin); |
b24696bc | 755 | } |
5ffa4eb2 | 756 | |
54168ed7 IM |
757 | return 0; |
758 | } | |
759 | ||
b24696bc FY |
760 | /* |
761 | * Mask all IO APIC entries. | |
762 | */ | |
763 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
764 | { |
765 | int apic, pin; | |
766 | ||
b24696bc FY |
767 | if (!ioapic_entries) |
768 | return; | |
769 | ||
05c3dc2c | 770 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 771 | if (!ioapic_entries[apic]) |
05c3dc2c | 772 | break; |
b24696bc | 773 | |
05c3dc2c SS |
774 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
775 | struct IO_APIC_route_entry entry; | |
776 | ||
b24696bc | 777 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
778 | if (!entry.mask) { |
779 | entry.mask = 1; | |
780 | ioapic_write_entry(apic, pin, entry); | |
781 | } | |
782 | } | |
783 | } | |
784 | } | |
785 | ||
b24696bc FY |
786 | /* |
787 | * Restore IO APIC entries which was saved in ioapic_entries. | |
788 | */ | |
789 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
790 | { |
791 | int apic, pin; | |
792 | ||
b24696bc FY |
793 | if (!ioapic_entries) |
794 | return -ENOMEM; | |
795 | ||
5ffa4eb2 | 796 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
797 | if (!ioapic_entries[apic]) |
798 | return -ENOMEM; | |
799 | ||
54168ed7 IM |
800 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
801 | ioapic_write_entry(apic, pin, | |
b24696bc | 802 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 803 | } |
b24696bc | 804 | return 0; |
54168ed7 IM |
805 | } |
806 | ||
b24696bc FY |
807 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
808 | { | |
809 | int apic; | |
810 | ||
811 | for (apic = 0; apic < nr_ioapics; apic++) | |
812 | kfree(ioapic_entries[apic]); | |
813 | ||
814 | kfree(ioapic_entries); | |
54168ed7 | 815 | } |
1da177e4 LT |
816 | |
817 | /* | |
818 | * Find the IRQ entry number of a certain pin. | |
819 | */ | |
820 | static int find_irq_entry(int apic, int pin, int type) | |
821 | { | |
822 | int i; | |
823 | ||
824 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
825 | if (mp_irqs[i].irqtype == type && |
826 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
827 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
828 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
829 | return i; |
830 | ||
831 | return -1; | |
832 | } | |
833 | ||
834 | /* | |
835 | * Find the pin to which IRQ[irq] (ISA) is connected | |
836 | */ | |
fcfd636a | 837 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
838 | { |
839 | int i; | |
840 | ||
841 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 842 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 843 | |
d27e2b8e | 844 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
845 | (mp_irqs[i].irqtype == type) && |
846 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 847 | |
c2c21745 | 848 | return mp_irqs[i].dstirq; |
1da177e4 LT |
849 | } |
850 | return -1; | |
851 | } | |
852 | ||
fcfd636a EB |
853 | static int __init find_isa_irq_apic(int irq, int type) |
854 | { | |
855 | int i; | |
856 | ||
857 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 858 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 859 | |
73b2961b | 860 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
861 | (mp_irqs[i].irqtype == type) && |
862 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
863 | break; |
864 | } | |
865 | if (i < mp_irq_entries) { | |
866 | int apic; | |
54168ed7 | 867 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 868 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
869 | return apic; |
870 | } | |
871 | } | |
872 | ||
873 | return -1; | |
874 | } | |
875 | ||
c0a282c2 | 876 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
877 | /* |
878 | * EISA Edge/Level control register, ELCR | |
879 | */ | |
880 | static int EISA_ELCR(unsigned int irq) | |
881 | { | |
99d093d1 | 882 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
883 | unsigned int port = 0x4d0 + (irq >> 3); |
884 | return (inb(port) >> (irq & 7)) & 1; | |
885 | } | |
886 | apic_printk(APIC_VERBOSE, KERN_INFO | |
887 | "Broken MPtable reports ISA irq %d\n", irq); | |
888 | return 0; | |
889 | } | |
54168ed7 | 890 | |
c0a282c2 | 891 | #endif |
1da177e4 | 892 | |
6728801d AS |
893 | /* ISA interrupts are always polarity zero edge triggered, |
894 | * when listed as conforming in the MP table. */ | |
895 | ||
896 | #define default_ISA_trigger(idx) (0) | |
897 | #define default_ISA_polarity(idx) (0) | |
898 | ||
1da177e4 LT |
899 | /* EISA interrupts are always polarity zero and can be edge or level |
900 | * trigger depending on the ELCR value. If an interrupt is listed as | |
901 | * EISA conforming in the MP table, that means its trigger type must | |
902 | * be read in from the ELCR */ | |
903 | ||
c2c21745 | 904 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 905 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
906 | |
907 | /* PCI interrupts are always polarity one level triggered, | |
908 | * when listed as conforming in the MP table. */ | |
909 | ||
910 | #define default_PCI_trigger(idx) (1) | |
911 | #define default_PCI_polarity(idx) (1) | |
912 | ||
913 | /* MCA interrupts are always polarity zero level triggered, | |
914 | * when listed as conforming in the MP table. */ | |
915 | ||
916 | #define default_MCA_trigger(idx) (1) | |
6728801d | 917 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 918 | |
61fd47e0 | 919 | static int MPBIOS_polarity(int idx) |
1da177e4 | 920 | { |
c2c21745 | 921 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
922 | int polarity; |
923 | ||
924 | /* | |
925 | * Determine IRQ line polarity (high active or low active): | |
926 | */ | |
c2c21745 | 927 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 928 | { |
54168ed7 IM |
929 | case 0: /* conforms, ie. bus-type dependent polarity */ |
930 | if (test_bit(bus, mp_bus_not_pci)) | |
931 | polarity = default_ISA_polarity(idx); | |
932 | else | |
933 | polarity = default_PCI_polarity(idx); | |
934 | break; | |
935 | case 1: /* high active */ | |
936 | { | |
937 | polarity = 0; | |
938 | break; | |
939 | } | |
940 | case 2: /* reserved */ | |
941 | { | |
942 | printk(KERN_WARNING "broken BIOS!!\n"); | |
943 | polarity = 1; | |
944 | break; | |
945 | } | |
946 | case 3: /* low active */ | |
947 | { | |
948 | polarity = 1; | |
949 | break; | |
950 | } | |
951 | default: /* invalid */ | |
952 | { | |
953 | printk(KERN_WARNING "broken BIOS!!\n"); | |
954 | polarity = 1; | |
955 | break; | |
956 | } | |
1da177e4 LT |
957 | } |
958 | return polarity; | |
959 | } | |
960 | ||
961 | static int MPBIOS_trigger(int idx) | |
962 | { | |
c2c21745 | 963 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
964 | int trigger; |
965 | ||
966 | /* | |
967 | * Determine IRQ trigger mode (edge or level sensitive): | |
968 | */ | |
c2c21745 | 969 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 970 | { |
54168ed7 IM |
971 | case 0: /* conforms, ie. bus-type dependent */ |
972 | if (test_bit(bus, mp_bus_not_pci)) | |
973 | trigger = default_ISA_trigger(idx); | |
974 | else | |
975 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 976 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
977 | switch (mp_bus_id_to_type[bus]) { |
978 | case MP_BUS_ISA: /* ISA pin */ | |
979 | { | |
980 | /* set before the switch */ | |
981 | break; | |
982 | } | |
983 | case MP_BUS_EISA: /* EISA pin */ | |
984 | { | |
985 | trigger = default_EISA_trigger(idx); | |
986 | break; | |
987 | } | |
988 | case MP_BUS_PCI: /* PCI pin */ | |
989 | { | |
990 | /* set before the switch */ | |
991 | break; | |
992 | } | |
993 | case MP_BUS_MCA: /* MCA pin */ | |
994 | { | |
995 | trigger = default_MCA_trigger(idx); | |
996 | break; | |
997 | } | |
998 | default: | |
999 | { | |
1000 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1001 | trigger = 1; | |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | #endif | |
1da177e4 | 1006 | break; |
54168ed7 | 1007 | case 1: /* edge */ |
1da177e4 | 1008 | { |
54168ed7 | 1009 | trigger = 0; |
1da177e4 LT |
1010 | break; |
1011 | } | |
54168ed7 | 1012 | case 2: /* reserved */ |
1da177e4 | 1013 | { |
54168ed7 IM |
1014 | printk(KERN_WARNING "broken BIOS!!\n"); |
1015 | trigger = 1; | |
1da177e4 LT |
1016 | break; |
1017 | } | |
54168ed7 | 1018 | case 3: /* level */ |
1da177e4 | 1019 | { |
54168ed7 | 1020 | trigger = 1; |
1da177e4 LT |
1021 | break; |
1022 | } | |
54168ed7 | 1023 | default: /* invalid */ |
1da177e4 LT |
1024 | { |
1025 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1026 | trigger = 0; |
1da177e4 LT |
1027 | break; |
1028 | } | |
1029 | } | |
1030 | return trigger; | |
1031 | } | |
1032 | ||
1033 | static inline int irq_polarity(int idx) | |
1034 | { | |
1035 | return MPBIOS_polarity(idx); | |
1036 | } | |
1037 | ||
1038 | static inline int irq_trigger(int idx) | |
1039 | { | |
1040 | return MPBIOS_trigger(idx); | |
1041 | } | |
1042 | ||
efa2559f | 1043 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1044 | static int pin_2_irq(int idx, int apic, int pin) |
1045 | { | |
1046 | int irq, i; | |
c2c21745 | 1047 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1048 | |
1049 | /* | |
1050 | * Debugging check, we are in big trouble if this message pops up! | |
1051 | */ | |
c2c21745 | 1052 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1053 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1054 | ||
54168ed7 | 1055 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1056 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1057 | } else { |
643befed AS |
1058 | /* |
1059 | * PCI IRQs are mapped in order | |
1060 | */ | |
1061 | i = irq = 0; | |
1062 | while (i < apic) | |
1063 | irq += nr_ioapic_registers[i++]; | |
1064 | irq += pin; | |
d6c88a50 | 1065 | /* |
54168ed7 IM |
1066 | * For MPS mode, so far only needed by ES7000 platform |
1067 | */ | |
d6c88a50 TG |
1068 | if (ioapic_renumber_irq) |
1069 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1070 | } |
1071 | ||
54168ed7 | 1072 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1073 | /* |
1074 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1075 | */ | |
1076 | if ((pin >= 16) && (pin <= 23)) { | |
1077 | if (pirq_entries[pin-16] != -1) { | |
1078 | if (!pirq_entries[pin-16]) { | |
1079 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1080 | "disabling PIRQ%d\n", pin-16); | |
1081 | } else { | |
1082 | irq = pirq_entries[pin-16]; | |
1083 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1084 | "using PIRQ%d -> IRQ %d\n", | |
1085 | pin-16, irq); | |
1086 | } | |
1087 | } | |
1088 | } | |
54168ed7 IM |
1089 | #endif |
1090 | ||
1da177e4 LT |
1091 | return irq; |
1092 | } | |
1093 | ||
e20c06fd YL |
1094 | /* |
1095 | * Find a specific PCI IRQ entry. | |
1096 | * Not an __init, possibly needed by modules | |
1097 | */ | |
1098 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1099 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1100 | { |
1101 | int apic, i, best_guess = -1; | |
1102 | ||
1103 | apic_printk(APIC_DEBUG, | |
1104 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1105 | bus, slot, pin); | |
1106 | if (test_bit(bus, mp_bus_not_pci)) { | |
1107 | apic_printk(APIC_VERBOSE, | |
1108 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1109 | return -1; | |
1110 | } | |
1111 | for (i = 0; i < mp_irq_entries; i++) { | |
1112 | int lbus = mp_irqs[i].srcbus; | |
1113 | ||
1114 | for (apic = 0; apic < nr_ioapics; apic++) | |
1115 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1116 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1117 | break; | |
1118 | ||
1119 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1120 | !mp_irqs[i].irqtype && | |
1121 | (bus == lbus) && | |
1122 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1123 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1124 | ||
1125 | if (!(apic || IO_APIC_IRQ(irq))) | |
1126 | continue; | |
1127 | ||
1128 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1129 | set_io_apic_irq_attr(irq_attr, apic, |
1130 | mp_irqs[i].dstirq, | |
1131 | irq_trigger(i), | |
1132 | irq_polarity(i)); | |
e20c06fd YL |
1133 | return irq; |
1134 | } | |
1135 | /* | |
1136 | * Use the first all-but-pin matching entry as a | |
1137 | * best-guess fuzzy result for broken mptables. | |
1138 | */ | |
1139 | if (best_guess < 0) { | |
e5198075 YL |
1140 | set_io_apic_irq_attr(irq_attr, apic, |
1141 | mp_irqs[i].dstirq, | |
1142 | irq_trigger(i), | |
1143 | irq_polarity(i)); | |
e20c06fd YL |
1144 | best_guess = irq; |
1145 | } | |
1146 | } | |
1147 | } | |
1148 | return best_guess; | |
1149 | } | |
1150 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1151 | ||
497c9a19 YL |
1152 | void lock_vector_lock(void) |
1153 | { | |
1154 | /* Used to the online set of cpus does not change | |
1155 | * during assign_irq_vector. | |
1156 | */ | |
1157 | spin_lock(&vector_lock); | |
1158 | } | |
1da177e4 | 1159 | |
497c9a19 | 1160 | void unlock_vector_lock(void) |
1da177e4 | 1161 | { |
497c9a19 YL |
1162 | spin_unlock(&vector_lock); |
1163 | } | |
1da177e4 | 1164 | |
e7986739 MT |
1165 | static int |
1166 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1167 | { |
047c8fdb YL |
1168 | /* |
1169 | * NOTE! The local APIC isn't very good at handling | |
1170 | * multiple interrupts at the same interrupt level. | |
1171 | * As the interrupt level is determined by taking the | |
1172 | * vector number and shifting that right by 4, we | |
1173 | * want to spread these out a bit so that they don't | |
1174 | * all fall in the same interrupt level. | |
1175 | * | |
1176 | * Also, we've got to be careful not to trash gate | |
1177 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1178 | */ | |
54168ed7 IM |
1179 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1180 | unsigned int old_vector; | |
22f65d31 MT |
1181 | int cpu, err; |
1182 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1183 | |
54168ed7 IM |
1184 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1185 | return -EBUSY; | |
0a1ad60d | 1186 | |
22f65d31 MT |
1187 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1188 | return -ENOMEM; | |
ace80ab7 | 1189 | |
54168ed7 IM |
1190 | old_vector = cfg->vector; |
1191 | if (old_vector) { | |
22f65d31 MT |
1192 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1193 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1194 | if (!cpumask_empty(tmp_mask)) { | |
1195 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1196 | return 0; |
22f65d31 | 1197 | } |
54168ed7 | 1198 | } |
497c9a19 | 1199 | |
e7986739 | 1200 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1201 | err = -ENOSPC; |
1202 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1203 | int new_cpu; |
1204 | int vector, offset; | |
497c9a19 | 1205 | |
e2d40b18 | 1206 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1207 | |
54168ed7 IM |
1208 | vector = current_vector; |
1209 | offset = current_offset; | |
497c9a19 | 1210 | next: |
54168ed7 IM |
1211 | vector += 8; |
1212 | if (vector >= first_system_vector) { | |
e7986739 | 1213 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1214 | offset = (offset + 1) % 8; |
1215 | vector = FIRST_DEVICE_VECTOR + offset; | |
1216 | } | |
1217 | if (unlikely(current_vector == vector)) | |
1218 | continue; | |
b77b881f YL |
1219 | |
1220 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1221 | goto next; |
b77b881f | 1222 | |
22f65d31 | 1223 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1224 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1225 | goto next; | |
1226 | /* Found one! */ | |
1227 | current_vector = vector; | |
1228 | current_offset = offset; | |
1229 | if (old_vector) { | |
1230 | cfg->move_in_progress = 1; | |
22f65d31 | 1231 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1232 | } |
22f65d31 | 1233 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1234 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1235 | cfg->vector = vector; | |
22f65d31 MT |
1236 | cpumask_copy(cfg->domain, tmp_mask); |
1237 | err = 0; | |
1238 | break; | |
54168ed7 | 1239 | } |
22f65d31 MT |
1240 | free_cpumask_var(tmp_mask); |
1241 | return err; | |
497c9a19 YL |
1242 | } |
1243 | ||
e7986739 MT |
1244 | static int |
1245 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1246 | { |
1247 | int err; | |
ace80ab7 | 1248 | unsigned long flags; |
ace80ab7 EB |
1249 | |
1250 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1251 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1252 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1253 | return err; |
1254 | } | |
1255 | ||
3145e941 | 1256 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1257 | { |
497c9a19 YL |
1258 | int cpu, vector; |
1259 | ||
497c9a19 YL |
1260 | BUG_ON(!cfg->vector); |
1261 | ||
1262 | vector = cfg->vector; | |
22f65d31 | 1263 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1264 | per_cpu(vector_irq, cpu)[vector] = -1; |
1265 | ||
1266 | cfg->vector = 0; | |
22f65d31 | 1267 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1268 | |
1269 | if (likely(!cfg->move_in_progress)) | |
1270 | return; | |
22f65d31 | 1271 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1272 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1273 | vector++) { | |
1274 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1275 | continue; | |
1276 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1277 | break; | |
1278 | } | |
1279 | } | |
1280 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1281 | } |
1282 | ||
1283 | void __setup_vector_irq(int cpu) | |
1284 | { | |
1285 | /* Initialize vector_irq on a new cpu */ | |
1286 | /* This function must be called with vector_lock held */ | |
1287 | int irq, vector; | |
1288 | struct irq_cfg *cfg; | |
0b8f1efa | 1289 | struct irq_desc *desc; |
497c9a19 YL |
1290 | |
1291 | /* Mark the inuse vectors */ | |
0b8f1efa | 1292 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1293 | cfg = desc->chip_data; |
22f65d31 | 1294 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1295 | continue; |
1296 | vector = cfg->vector; | |
497c9a19 YL |
1297 | per_cpu(vector_irq, cpu)[vector] = irq; |
1298 | } | |
1299 | /* Mark the free vectors */ | |
1300 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1301 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1302 | if (irq < 0) | |
1303 | continue; | |
1304 | ||
1305 | cfg = irq_cfg(irq); | |
22f65d31 | 1306 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1307 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1308 | } |
1da177e4 | 1309 | } |
3fde6900 | 1310 | |
f5b9ed7a | 1311 | static struct irq_chip ioapic_chip; |
54168ed7 | 1312 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1313 | |
54168ed7 IM |
1314 | #define IOAPIC_AUTO -1 |
1315 | #define IOAPIC_EDGE 0 | |
1316 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1317 | |
047c8fdb | 1318 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1319 | static inline int IO_APIC_irq_trigger(int irq) |
1320 | { | |
d6c88a50 | 1321 | int apic, idx, pin; |
1d025192 | 1322 | |
d6c88a50 TG |
1323 | for (apic = 0; apic < nr_ioapics; apic++) { |
1324 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1325 | idx = find_irq_entry(apic, pin, mp_INT); | |
1326 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1327 | return irq_trigger(idx); | |
1328 | } | |
1329 | } | |
1330 | /* | |
54168ed7 IM |
1331 | * nonexistent IRQs are edge default |
1332 | */ | |
d6c88a50 | 1333 | return 0; |
1d025192 | 1334 | } |
047c8fdb YL |
1335 | #else |
1336 | static inline int IO_APIC_irq_trigger(int irq) | |
1337 | { | |
54168ed7 | 1338 | return 1; |
047c8fdb YL |
1339 | } |
1340 | #endif | |
1d025192 | 1341 | |
3145e941 | 1342 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1343 | { |
199751d7 | 1344 | |
6ebcc00e | 1345 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1346 | trigger == IOAPIC_LEVEL) |
08678b08 | 1347 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1348 | else |
1349 | desc->status &= ~IRQ_LEVEL; | |
1350 | ||
54168ed7 IM |
1351 | if (irq_remapped(irq)) { |
1352 | desc->status |= IRQ_MOVE_PCNTXT; | |
1353 | if (trigger) | |
1354 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1355 | handle_fasteoi_irq, | |
1356 | "fasteoi"); | |
1357 | else | |
1358 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1359 | handle_edge_irq, "edge"); | |
1360 | return; | |
1361 | } | |
29b61be6 | 1362 | |
047c8fdb YL |
1363 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1364 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1365 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1366 | handle_fasteoi_irq, |
1367 | "fasteoi"); | |
047c8fdb | 1368 | else |
a460e745 | 1369 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1370 | handle_edge_irq, "edge"); |
1da177e4 LT |
1371 | } |
1372 | ||
ca97ab90 JF |
1373 | int setup_ioapic_entry(int apic_id, int irq, |
1374 | struct IO_APIC_route_entry *entry, | |
1375 | unsigned int destination, int trigger, | |
0280f7c4 | 1376 | int polarity, int vector, int pin) |
1da177e4 | 1377 | { |
497c9a19 YL |
1378 | /* |
1379 | * add it to the IO-APIC irq-routing table: | |
1380 | */ | |
1381 | memset(entry,0,sizeof(*entry)); | |
1382 | ||
54168ed7 | 1383 | if (intr_remapping_enabled) { |
c8d46cf0 | 1384 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1385 | struct irte irte; |
1386 | struct IR_IO_APIC_route_entry *ir_entry = | |
1387 | (struct IR_IO_APIC_route_entry *) entry; | |
1388 | int index; | |
1389 | ||
1390 | if (!iommu) | |
c8d46cf0 | 1391 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1392 | |
1393 | index = alloc_irte(iommu, irq, 1); | |
1394 | if (index < 0) | |
c8d46cf0 | 1395 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1396 | |
1397 | memset(&irte, 0, sizeof(irte)); | |
1398 | ||
1399 | irte.present = 1; | |
9b5bc8dc | 1400 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1401 | /* |
1402 | * Trigger mode in the IRTE will always be edge, and the | |
1403 | * actual level or edge trigger will be setup in the IO-APIC | |
1404 | * RTE. This will help simplify level triggered irq migration. | |
1405 | * For more details, see the comments above explainig IO-APIC | |
1406 | * irq migration in the presence of interrupt-remapping. | |
1407 | */ | |
1408 | irte.trigger_mode = 0; | |
9b5bc8dc | 1409 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1410 | irte.vector = vector; |
1411 | irte.dest_id = IRTE_DEST(destination); | |
1412 | ||
1413 | modify_irte(irq, &irte); | |
1414 | ||
1415 | ir_entry->index2 = (index >> 15) & 0x1; | |
1416 | ir_entry->zero = 0; | |
1417 | ir_entry->format = 1; | |
1418 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1419 | /* |
1420 | * IO-APIC RTE will be configured with virtual vector. | |
1421 | * irq handler will do the explicit EOI to the io-apic. | |
1422 | */ | |
1423 | ir_entry->vector = pin; | |
29b61be6 | 1424 | } else { |
9b5bc8dc IM |
1425 | entry->delivery_mode = apic->irq_delivery_mode; |
1426 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1427 | entry->dest = destination; |
0280f7c4 | 1428 | entry->vector = vector; |
54168ed7 | 1429 | } |
497c9a19 | 1430 | |
54168ed7 | 1431 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1432 | entry->trigger = trigger; |
1433 | entry->polarity = polarity; | |
497c9a19 YL |
1434 | |
1435 | /* Mask level triggered irqs. | |
1436 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1437 | */ | |
1438 | if (trigger) | |
1439 | entry->mask = 1; | |
497c9a19 YL |
1440 | return 0; |
1441 | } | |
1442 | ||
c8d46cf0 | 1443 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1444 | int trigger, int polarity) |
497c9a19 YL |
1445 | { |
1446 | struct irq_cfg *cfg; | |
1da177e4 | 1447 | struct IO_APIC_route_entry entry; |
22f65d31 | 1448 | unsigned int dest; |
497c9a19 YL |
1449 | |
1450 | if (!IO_APIC_IRQ(irq)) | |
1451 | return; | |
1452 | ||
3145e941 | 1453 | cfg = desc->chip_data; |
497c9a19 | 1454 | |
fe402e1f | 1455 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1456 | return; |
1457 | ||
debccb3e | 1458 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1459 | |
1460 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1461 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1462 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1463 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1464 | irq, trigger, polarity); |
1465 | ||
1466 | ||
c8d46cf0 | 1467 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1468 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1469 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1470 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1471 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1472 | return; |
1473 | } | |
1474 | ||
3145e941 | 1475 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1476 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1477 | disable_8259A_irq(irq); |
1478 | ||
c8d46cf0 | 1479 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1480 | } |
1481 | ||
b9c61b70 YL |
1482 | static struct { |
1483 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1484 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1485 | ||
497c9a19 YL |
1486 | static void __init setup_IO_APIC_irqs(void) |
1487 | { | |
b9c61b70 | 1488 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1489 | int notcon = 0; |
0b8f1efa | 1490 | struct irq_desc *desc; |
3145e941 | 1491 | struct irq_cfg *cfg; |
85ac16d0 | 1492 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1493 | |
1494 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1495 | ||
b9c61b70 YL |
1496 | #ifdef CONFIG_ACPI |
1497 | if (!acpi_disabled && acpi_ioapic) { | |
1498 | apic_id = mp_find_ioapic(0); | |
1499 | if (apic_id < 0) | |
1500 | apic_id = 0; | |
1501 | } | |
1502 | #endif | |
3c2cbd24 | 1503 | |
b9c61b70 YL |
1504 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1505 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1506 | if (idx == -1) { | |
1507 | if (!notcon) { | |
1508 | notcon = 1; | |
1509 | apic_printk(APIC_VERBOSE, | |
1510 | KERN_DEBUG " %d-%d", | |
1511 | mp_ioapics[apic_id].apicid, pin); | |
1512 | } else | |
1513 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1514 | mp_ioapics[apic_id].apicid, pin); | |
1515 | continue; | |
1516 | } | |
1517 | if (notcon) { | |
1518 | apic_printk(APIC_VERBOSE, | |
1519 | " (apicid-pin) not connected\n"); | |
1520 | notcon = 0; | |
1521 | } | |
33a201fa | 1522 | |
b9c61b70 | 1523 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1524 | |
b9c61b70 YL |
1525 | /* |
1526 | * Skip the timer IRQ if there's a quirk handler | |
1527 | * installed and if it returns 1: | |
1528 | */ | |
1529 | if (apic->multi_timer_check && | |
1530 | apic->multi_timer_check(apic_id, irq)) | |
1531 | continue; | |
36062448 | 1532 | |
b9c61b70 YL |
1533 | desc = irq_to_desc_alloc_node(irq, node); |
1534 | if (!desc) { | |
1535 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1536 | continue; | |
3c2cbd24 | 1537 | } |
b9c61b70 YL |
1538 | cfg = desc->chip_data; |
1539 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1540 | /* |
1541 | * don't mark it in pin_programmed, so later acpi could | |
1542 | * set it correctly when irq < 16 | |
1543 | */ | |
b9c61b70 YL |
1544 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1545 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1546 | } |
1547 | ||
3c2cbd24 CG |
1548 | if (notcon) |
1549 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1550 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1551 | } |
1552 | ||
1553 | /* | |
f7633ce5 | 1554 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1555 | */ |
c8d46cf0 | 1556 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1557 | int vector) |
1da177e4 LT |
1558 | { |
1559 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1560 | |
54168ed7 IM |
1561 | if (intr_remapping_enabled) |
1562 | return; | |
54168ed7 | 1563 | |
36062448 | 1564 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1565 | |
1566 | /* | |
1567 | * We use logical delivery to get the timer IRQ | |
1568 | * to the first CPU. | |
1569 | */ | |
9b5bc8dc | 1570 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1571 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1572 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1573 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1574 | entry.polarity = 0; |
1575 | entry.trigger = 0; | |
1576 | entry.vector = vector; | |
1577 | ||
1578 | /* | |
1579 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1580 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1581 | */ |
54168ed7 | 1582 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1583 | |
1584 | /* | |
1585 | * Add it to the IO-APIC irq-routing table: | |
1586 | */ | |
c8d46cf0 | 1587 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1588 | } |
1589 | ||
32f71aff MR |
1590 | |
1591 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1592 | { |
1593 | int apic, i; | |
1594 | union IO_APIC_reg_00 reg_00; | |
1595 | union IO_APIC_reg_01 reg_01; | |
1596 | union IO_APIC_reg_02 reg_02; | |
1597 | union IO_APIC_reg_03 reg_03; | |
1598 | unsigned long flags; | |
0f978f45 | 1599 | struct irq_cfg *cfg; |
0b8f1efa | 1600 | struct irq_desc *desc; |
8f09cd20 | 1601 | unsigned int irq; |
1da177e4 LT |
1602 | |
1603 | if (apic_verbosity == APIC_QUIET) | |
1604 | return; | |
1605 | ||
36062448 | 1606 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1607 | for (i = 0; i < nr_ioapics; i++) |
1608 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1609 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1610 | |
1611 | /* | |
1612 | * We are a bit conservative about what we expect. We have to | |
1613 | * know about every hardware change ASAP. | |
1614 | */ | |
1615 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1616 | ||
1617 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1618 | ||
1619 | spin_lock_irqsave(&ioapic_lock, flags); | |
1620 | reg_00.raw = io_apic_read(apic, 0); | |
1621 | reg_01.raw = io_apic_read(apic, 1); | |
1622 | if (reg_01.bits.version >= 0x10) | |
1623 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1624 | if (reg_01.bits.version >= 0x20) |
1625 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1626 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1627 | ||
54168ed7 | 1628 | printk("\n"); |
b5ba7e6d | 1629 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1630 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1631 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1632 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1633 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1634 | |
54168ed7 | 1635 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1636 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1637 | |
1638 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1639 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1640 | |
1641 | /* | |
1642 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1643 | * but the value of reg_02 is read as the previous read register | |
1644 | * value, so ignore it if reg_02 == reg_01. | |
1645 | */ | |
1646 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1647 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1648 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1649 | } |
1650 | ||
1651 | /* | |
1652 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1653 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1654 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1655 | */ | |
1656 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1657 | reg_03.raw != reg_01.raw) { | |
1658 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1659 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1660 | } |
1661 | ||
1662 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1663 | ||
d83e94ac YL |
1664 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1665 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1666 | |
1667 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1668 | struct IO_APIC_route_entry entry; | |
1669 | ||
cf4c6a2f | 1670 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1671 | |
54168ed7 IM |
1672 | printk(KERN_DEBUG " %02x %03X ", |
1673 | i, | |
1674 | entry.dest | |
1675 | ); | |
1da177e4 LT |
1676 | |
1677 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1678 | entry.mask, | |
1679 | entry.trigger, | |
1680 | entry.irr, | |
1681 | entry.polarity, | |
1682 | entry.delivery_status, | |
1683 | entry.dest_mode, | |
1684 | entry.delivery_mode, | |
1685 | entry.vector | |
1686 | ); | |
1687 | } | |
1688 | } | |
1da177e4 | 1689 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1690 | for_each_irq_desc(irq, desc) { |
1691 | struct irq_pin_list *entry; | |
1692 | ||
0b8f1efa YL |
1693 | cfg = desc->chip_data; |
1694 | entry = cfg->irq_2_pin; | |
0f978f45 | 1695 | if (!entry) |
1da177e4 | 1696 | continue; |
8f09cd20 | 1697 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1698 | for (;;) { |
1699 | printk("-> %d:%d", entry->apic, entry->pin); | |
1700 | if (!entry->next) | |
1701 | break; | |
0f978f45 | 1702 | entry = entry->next; |
1da177e4 LT |
1703 | } |
1704 | printk("\n"); | |
1705 | } | |
1706 | ||
1707 | printk(KERN_INFO ".................................... done.\n"); | |
1708 | ||
1709 | return; | |
1710 | } | |
1711 | ||
32f71aff | 1712 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1713 | { |
1714 | unsigned int v; | |
1715 | int i, j; | |
1716 | ||
1717 | if (apic_verbosity == APIC_QUIET) | |
1718 | return; | |
1719 | ||
1720 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1721 | for (i = 0; i < 8; i++) { | |
1722 | v = apic_read(base + i*0x10); | |
1723 | for (j = 0; j < 32; j++) { | |
1724 | if (v & (1<<j)) | |
1725 | printk("1"); | |
1726 | else | |
1727 | printk("0"); | |
1728 | } | |
1729 | printk("\n"); | |
1730 | } | |
1731 | } | |
1732 | ||
32f71aff | 1733 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1734 | { |
97a52714 | 1735 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1736 | u64 icr; |
1da177e4 LT |
1737 | |
1738 | if (apic_verbosity == APIC_QUIET) | |
1739 | return; | |
1740 | ||
1741 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1742 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1743 | v = apic_read(APIC_ID); |
54168ed7 | 1744 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1745 | v = apic_read(APIC_LVR); |
1746 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1747 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1748 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1749 | |
1750 | v = apic_read(APIC_TASKPRI); | |
1751 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1752 | ||
54168ed7 | 1753 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1754 | if (!APIC_XAPIC(ver)) { |
1755 | v = apic_read(APIC_ARBPRI); | |
1756 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1757 | v & APIC_ARBPRI_MASK); | |
1758 | } | |
1da177e4 LT |
1759 | v = apic_read(APIC_PROCPRI); |
1760 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1761 | } | |
1762 | ||
a11b5abe YL |
1763 | /* |
1764 | * Remote read supported only in the 82489DX and local APIC for | |
1765 | * Pentium processors. | |
1766 | */ | |
1767 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1768 | v = apic_read(APIC_RRR); | |
1769 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1770 | } | |
1771 | ||
1da177e4 LT |
1772 | v = apic_read(APIC_LDR); |
1773 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1774 | if (!x2apic_enabled()) { |
1775 | v = apic_read(APIC_DFR); | |
1776 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1777 | } | |
1da177e4 LT |
1778 | v = apic_read(APIC_SPIV); |
1779 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1780 | ||
1781 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1782 | print_APIC_bitfield(APIC_ISR); | |
1783 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1784 | print_APIC_bitfield(APIC_TMR); | |
1785 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1786 | print_APIC_bitfield(APIC_IRR); | |
1787 | ||
54168ed7 IM |
1788 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1789 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1790 | apic_write(APIC_ESR, 0); |
54168ed7 | 1791 | |
1da177e4 LT |
1792 | v = apic_read(APIC_ESR); |
1793 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1794 | } | |
1795 | ||
7ab6af7a | 1796 | icr = apic_icr_read(); |
0c425cec IM |
1797 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1798 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1799 | |
1800 | v = apic_read(APIC_LVTT); | |
1801 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1802 | ||
1803 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1804 | v = apic_read(APIC_LVTPC); | |
1805 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1806 | } | |
1807 | v = apic_read(APIC_LVT0); | |
1808 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1809 | v = apic_read(APIC_LVT1); | |
1810 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1811 | ||
1812 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1813 | v = apic_read(APIC_LVTERR); | |
1814 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1815 | } | |
1816 | ||
1817 | v = apic_read(APIC_TMICT); | |
1818 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1819 | v = apic_read(APIC_TMCCT); | |
1820 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1821 | v = apic_read(APIC_TDCR); | |
1822 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1823 | |
1824 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1825 | v = apic_read(APIC_EFEAT); | |
1826 | maxlvt = (v >> 16) & 0xff; | |
1827 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1828 | v = apic_read(APIC_ECTRL); | |
1829 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1830 | for (i = 0; i < maxlvt; i++) { | |
1831 | v = apic_read(APIC_EILVTn(i)); | |
1832 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1833 | } | |
1834 | } | |
1da177e4 LT |
1835 | printk("\n"); |
1836 | } | |
1837 | ||
32f71aff | 1838 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1839 | { |
ffd5aae7 YL |
1840 | int cpu; |
1841 | ||
1842 | preempt_disable(); | |
1843 | for_each_online_cpu(cpu) | |
1844 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1845 | preempt_enable(); | |
1da177e4 LT |
1846 | } |
1847 | ||
32f71aff | 1848 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1849 | { |
1da177e4 LT |
1850 | unsigned int v; |
1851 | unsigned long flags; | |
1852 | ||
1853 | if (apic_verbosity == APIC_QUIET) | |
1854 | return; | |
1855 | ||
1856 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1857 | ||
1858 | spin_lock_irqsave(&i8259A_lock, flags); | |
1859 | ||
1860 | v = inb(0xa1) << 8 | inb(0x21); | |
1861 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1862 | ||
1863 | v = inb(0xa0) << 8 | inb(0x20); | |
1864 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1865 | ||
54168ed7 IM |
1866 | outb(0x0b,0xa0); |
1867 | outb(0x0b,0x20); | |
1da177e4 | 1868 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1869 | outb(0x0a,0xa0); |
1870 | outb(0x0a,0x20); | |
1da177e4 LT |
1871 | |
1872 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1873 | ||
1874 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1875 | ||
1876 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1877 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1878 | } | |
1879 | ||
32f71aff MR |
1880 | __apicdebuginit(int) print_all_ICs(void) |
1881 | { | |
1882 | print_PIC(); | |
4797f6b0 YL |
1883 | |
1884 | /* don't print out if apic is not there */ | |
1885 | if (!cpu_has_apic || disable_apic) | |
1886 | return 0; | |
1887 | ||
32f71aff MR |
1888 | print_all_local_APICs(); |
1889 | print_IO_APIC(); | |
1890 | ||
1891 | return 0; | |
1892 | } | |
1893 | ||
1894 | fs_initcall(print_all_ICs); | |
1895 | ||
1da177e4 | 1896 | |
efa2559f YL |
1897 | /* Where if anywhere is the i8259 connect in external int mode */ |
1898 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1899 | ||
54168ed7 | 1900 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1901 | { |
1902 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1903 | int i8259_apic, i8259_pin; |
54168ed7 | 1904 | int apic; |
1da177e4 LT |
1905 | unsigned long flags; |
1906 | ||
1da177e4 LT |
1907 | /* |
1908 | * The number of IO-APIC IRQ registers (== #pins): | |
1909 | */ | |
fcfd636a | 1910 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1911 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1912 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1913 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1914 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1915 | } | |
54168ed7 | 1916 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1917 | int pin; |
1918 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1919 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1920 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1921 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1922 | |
fcfd636a EB |
1923 | /* If the interrupt line is enabled and in ExtInt mode |
1924 | * I have found the pin where the i8259 is connected. | |
1925 | */ | |
1926 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1927 | ioapic_i8259.apic = apic; | |
1928 | ioapic_i8259.pin = pin; | |
1929 | goto found_i8259; | |
1930 | } | |
1931 | } | |
1932 | } | |
1933 | found_i8259: | |
1934 | /* Look to see what if the MP table has reported the ExtINT */ | |
1935 | /* If we could not find the appropriate pin by looking at the ioapic | |
1936 | * the i8259 probably is not connected the ioapic but give the | |
1937 | * mptable a chance anyway. | |
1938 | */ | |
1939 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1940 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1941 | /* Trust the MP table if nothing is setup in the hardware */ | |
1942 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1943 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1944 | ioapic_i8259.pin = i8259_pin; | |
1945 | ioapic_i8259.apic = i8259_apic; | |
1946 | } | |
1947 | /* Complain if the MP table and the hardware disagree */ | |
1948 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1949 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1950 | { | |
1951 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1952 | } |
1953 | ||
1954 | /* | |
1955 | * Do not trust the IO-APIC being empty at bootup | |
1956 | */ | |
1957 | clear_IO_APIC(); | |
1958 | } | |
1959 | ||
1960 | /* | |
1961 | * Not an __init, needed by the reboot code | |
1962 | */ | |
1963 | void disable_IO_APIC(void) | |
1964 | { | |
1965 | /* | |
1966 | * Clear the IO-APIC before rebooting: | |
1967 | */ | |
1968 | clear_IO_APIC(); | |
1969 | ||
650927ef | 1970 | /* |
0b968d23 | 1971 | * If the i8259 is routed through an IOAPIC |
650927ef | 1972 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1973 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1974 | * |
1975 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1976 | * as virtual wire B is little complex (need to configure both | |
1977 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1978 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1979 | */ |
7c6d9f97 | 1980 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1981 | struct IO_APIC_route_entry entry; |
650927ef EB |
1982 | |
1983 | memset(&entry, 0, sizeof(entry)); | |
1984 | entry.mask = 0; /* Enabled */ | |
1985 | entry.trigger = 0; /* Edge */ | |
1986 | entry.irr = 0; | |
1987 | entry.polarity = 0; /* High */ | |
1988 | entry.delivery_status = 0; | |
1989 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1990 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1991 | entry.vector = 0; |
54168ed7 | 1992 | entry.dest = read_apic_id(); |
650927ef EB |
1993 | |
1994 | /* | |
1995 | * Add it to the IO-APIC irq-routing table: | |
1996 | */ | |
cf4c6a2f | 1997 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1998 | } |
54168ed7 | 1999 | |
7c6d9f97 SS |
2000 | /* |
2001 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2002 | */ | |
2003 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
2004 | } |
2005 | ||
54168ed7 | 2006 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2007 | /* |
2008 | * function to set the IO-APIC physical IDs based on the | |
2009 | * values stored in the MPC table. | |
2010 | * | |
2011 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2012 | */ | |
2013 | ||
1da177e4 LT |
2014 | static void __init setup_ioapic_ids_from_mpc(void) |
2015 | { | |
2016 | union IO_APIC_reg_00 reg_00; | |
2017 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2018 | int apic_id; |
1da177e4 LT |
2019 | int i; |
2020 | unsigned char old_id; | |
2021 | unsigned long flags; | |
2022 | ||
a4dbc34d | 2023 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2024 | return; |
d49c4288 | 2025 | |
ca05fea6 NP |
2026 | /* |
2027 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2028 | * no meaning without the serial APIC bus. | |
2029 | */ | |
7c5c1e42 SL |
2030 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2031 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2032 | return; |
1da177e4 LT |
2033 | /* |
2034 | * This is broken; anything with a real cpu count has to | |
2035 | * circumvent this idiocy regardless. | |
2036 | */ | |
d190cb87 | 2037 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2038 | |
2039 | /* | |
2040 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2041 | */ | |
c8d46cf0 | 2042 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2043 | |
2044 | /* Read the register 0 value */ | |
2045 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2046 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2047 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2048 | |
c8d46cf0 | 2049 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2050 | |
c8d46cf0 | 2051 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2052 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2053 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2054 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2055 | reg_00.bits.ID); | |
c8d46cf0 | 2056 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2057 | } |
2058 | ||
1da177e4 LT |
2059 | /* |
2060 | * Sanity check, is the ID really free? Every APIC in a | |
2061 | * system must have a unique ID or we get lots of nice | |
2062 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2063 | */ | |
d1d7cae8 | 2064 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2065 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2066 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2067 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2068 | for (i = 0; i < get_physical_broadcast(); i++) |
2069 | if (!physid_isset(i, phys_id_present_map)) | |
2070 | break; | |
2071 | if (i >= get_physical_broadcast()) | |
2072 | panic("Max APIC ID exceeded!\n"); | |
2073 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2074 | i); | |
2075 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2076 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2077 | } else { |
2078 | physid_mask_t tmp; | |
8058714a | 2079 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2080 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2081 | "phys_id_present_map\n", | |
c8d46cf0 | 2082 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2083 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2084 | } | |
2085 | ||
2086 | ||
2087 | /* | |
2088 | * We need to adjust the IRQ routing table | |
2089 | * if the ID changed. | |
2090 | */ | |
c8d46cf0 | 2091 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2092 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2093 | if (mp_irqs[i].dstapic == old_id) |
2094 | mp_irqs[i].dstapic | |
c8d46cf0 | 2095 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2096 | |
2097 | /* | |
2098 | * Read the right value from the MPC table and | |
2099 | * write it into the ID register. | |
36062448 | 2100 | */ |
1da177e4 LT |
2101 | apic_printk(APIC_VERBOSE, KERN_INFO |
2102 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2103 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2104 | |
c8d46cf0 | 2105 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2106 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2107 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2108 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2109 | |
2110 | /* | |
2111 | * Sanity check | |
2112 | */ | |
2113 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2114 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2115 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2116 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2117 | printk("could not set ID!\n"); |
2118 | else | |
2119 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2120 | } | |
2121 | } | |
54168ed7 | 2122 | #endif |
1da177e4 | 2123 | |
7ce0bcfd | 2124 | int no_timer_check __initdata; |
8542b200 ZA |
2125 | |
2126 | static int __init notimercheck(char *s) | |
2127 | { | |
2128 | no_timer_check = 1; | |
2129 | return 1; | |
2130 | } | |
2131 | __setup("no_timer_check", notimercheck); | |
2132 | ||
1da177e4 LT |
2133 | /* |
2134 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2135 | * about the timer IRQ. We do the following to work around the situation: | |
2136 | * | |
2137 | * - timer IRQ defaults to IO-APIC IRQ | |
2138 | * - if this function detects that timer IRQs are defunct, then we fall | |
2139 | * back to ISA timer IRQs | |
2140 | */ | |
f0a7a5c9 | 2141 | static int __init timer_irq_works(void) |
1da177e4 LT |
2142 | { |
2143 | unsigned long t1 = jiffies; | |
4aae0702 | 2144 | unsigned long flags; |
1da177e4 | 2145 | |
8542b200 ZA |
2146 | if (no_timer_check) |
2147 | return 1; | |
2148 | ||
4aae0702 | 2149 | local_save_flags(flags); |
1da177e4 LT |
2150 | local_irq_enable(); |
2151 | /* Let ten ticks pass... */ | |
2152 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2153 | local_irq_restore(flags); |
1da177e4 LT |
2154 | |
2155 | /* | |
2156 | * Expect a few ticks at least, to be sure some possible | |
2157 | * glue logic does not lock up after one or two first | |
2158 | * ticks in a non-ExtINT mode. Also the local APIC | |
2159 | * might have cached one ExtINT interrupt. Finally, at | |
2160 | * least one tick may be lost due to delays. | |
2161 | */ | |
54168ed7 IM |
2162 | |
2163 | /* jiffies wrap? */ | |
1d16b53e | 2164 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2165 | return 1; |
1da177e4 LT |
2166 | return 0; |
2167 | } | |
2168 | ||
2169 | /* | |
2170 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2171 | * number of pending IRQ events unhandled. These cases are very rare, | |
2172 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2173 | * better to do it this way as thus we do not have to be aware of | |
2174 | * 'pending' interrupts in the IRQ path, except at this point. | |
2175 | */ | |
2176 | /* | |
2177 | * Edge triggered needs to resend any interrupt | |
2178 | * that was delayed but this is now handled in the device | |
2179 | * independent code. | |
2180 | */ | |
2181 | ||
2182 | /* | |
2183 | * Starting up a edge-triggered IO-APIC interrupt is | |
2184 | * nasty - we need to make sure that we get the edge. | |
2185 | * If it is already asserted for some reason, we need | |
2186 | * return 1 to indicate that is was pending. | |
2187 | * | |
2188 | * This is not complete - we should be able to fake | |
2189 | * an edge even if it isn't on the 8259A... | |
2190 | */ | |
54168ed7 | 2191 | |
f5b9ed7a | 2192 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2193 | { |
2194 | int was_pending = 0; | |
2195 | unsigned long flags; | |
0b8f1efa | 2196 | struct irq_cfg *cfg; |
1da177e4 LT |
2197 | |
2198 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2199 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2200 | disable_8259A_irq(irq); |
2201 | if (i8259A_irq_pending(irq)) | |
2202 | was_pending = 1; | |
2203 | } | |
0b8f1efa | 2204 | cfg = irq_cfg(irq); |
3145e941 | 2205 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2206 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2207 | ||
2208 | return was_pending; | |
2209 | } | |
2210 | ||
54168ed7 | 2211 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2212 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2213 | { |
54168ed7 IM |
2214 | |
2215 | struct irq_cfg *cfg = irq_cfg(irq); | |
2216 | unsigned long flags; | |
2217 | ||
2218 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2219 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2220 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2221 | |
2222 | return 1; | |
2223 | } | |
54168ed7 IM |
2224 | #else |
2225 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2226 | { |
dac5f412 | 2227 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2228 | |
d6c88a50 | 2229 | return 1; |
54168ed7 IM |
2230 | } |
2231 | #endif | |
497c9a19 | 2232 | |
54168ed7 IM |
2233 | /* |
2234 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2235 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2236 | * handled with the level-triggered descriptor, but that one has slightly | |
2237 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2238 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2239 | * races. | |
2240 | */ | |
497c9a19 | 2241 | |
54168ed7 | 2242 | #ifdef CONFIG_SMP |
e85abf8f GH |
2243 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2244 | { | |
2245 | cpumask_var_t cleanup_mask; | |
2246 | ||
2247 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2248 | unsigned int i; | |
2249 | cfg->move_cleanup_count = 0; | |
2250 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2251 | cfg->move_cleanup_count++; | |
2252 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2253 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2254 | } else { | |
2255 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2256 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2257 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2258 | free_cpumask_var(cleanup_mask); | |
2259 | } | |
2260 | cfg->move_in_progress = 0; | |
2261 | } | |
2262 | ||
4420471f | 2263 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2264 | { |
2265 | int apic, pin; | |
2266 | struct irq_pin_list *entry; | |
2267 | u8 vector = cfg->vector; | |
2268 | ||
2269 | entry = cfg->irq_2_pin; | |
2270 | for (;;) { | |
2271 | unsigned int reg; | |
2272 | ||
2273 | if (!entry) | |
2274 | break; | |
2275 | ||
2276 | apic = entry->apic; | |
2277 | pin = entry->pin; | |
2278 | /* | |
2279 | * With interrupt-remapping, destination information comes | |
2280 | * from interrupt-remapping table entry. | |
2281 | */ | |
2282 | if (!irq_remapped(irq)) | |
2283 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2284 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2285 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2286 | reg |= vector; | |
2287 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2288 | if (!entry->next) | |
2289 | break; | |
2290 | entry = entry->next; | |
2291 | } | |
2292 | } | |
2293 | ||
4420471f IM |
2294 | static int |
2295 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2296 | ||
e85abf8f GH |
2297 | /* |
2298 | * Either sets desc->affinity to a valid value, and returns | |
2299 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2300 | * leaves desc->affinity untouched. | |
2301 | */ | |
2302 | static unsigned int | |
2303 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2304 | { | |
2305 | struct irq_cfg *cfg; | |
2306 | unsigned int irq; | |
2307 | ||
2308 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2309 | return BAD_APICID; | |
2310 | ||
2311 | irq = desc->irq; | |
2312 | cfg = desc->chip_data; | |
2313 | if (assign_irq_vector(irq, cfg, mask)) | |
2314 | return BAD_APICID; | |
2315 | ||
e85abf8f GH |
2316 | cpumask_copy(desc->affinity, mask); |
2317 | ||
2318 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2319 | } | |
2320 | ||
4420471f | 2321 | static int |
e85abf8f GH |
2322 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2323 | { | |
2324 | struct irq_cfg *cfg; | |
2325 | unsigned long flags; | |
2326 | unsigned int dest; | |
2327 | unsigned int irq; | |
4420471f | 2328 | int ret = -1; |
e85abf8f GH |
2329 | |
2330 | irq = desc->irq; | |
2331 | cfg = desc->chip_data; | |
2332 | ||
2333 | spin_lock_irqsave(&ioapic_lock, flags); | |
2334 | dest = set_desc_affinity(desc, mask); | |
2335 | if (dest != BAD_APICID) { | |
2336 | /* Only the high 8 bits are valid. */ | |
2337 | dest = SET_APIC_LOGICAL_ID(dest); | |
2338 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2339 | ret = 0; |
e85abf8f GH |
2340 | } |
2341 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2342 | |
2343 | return ret; | |
e85abf8f GH |
2344 | } |
2345 | ||
4420471f | 2346 | static int |
e85abf8f GH |
2347 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2348 | { | |
2349 | struct irq_desc *desc; | |
2350 | ||
2351 | desc = irq_to_desc(irq); | |
2352 | ||
4420471f | 2353 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2354 | } |
497c9a19 | 2355 | |
54168ed7 | 2356 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2357 | |
54168ed7 IM |
2358 | /* |
2359 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2360 | * | |
0280f7c4 SS |
2361 | * For both level and edge triggered, irq migration is a simple atomic |
2362 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2363 | * |
0280f7c4 SS |
2364 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2365 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2366 | * Real vector that is used for interrupting cpu will be coming from | |
2367 | * the interrupt-remapping table entry. | |
54168ed7 | 2368 | */ |
d5dedd45 | 2369 | static int |
e7986739 | 2370 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2371 | { |
54168ed7 | 2372 | struct irq_cfg *cfg; |
54168ed7 | 2373 | struct irte irte; |
54168ed7 | 2374 | unsigned int dest; |
3145e941 | 2375 | unsigned int irq; |
d5dedd45 | 2376 | int ret = -1; |
497c9a19 | 2377 | |
22f65d31 | 2378 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2379 | return ret; |
497c9a19 | 2380 | |
3145e941 | 2381 | irq = desc->irq; |
54168ed7 | 2382 | if (get_irte(irq, &irte)) |
d5dedd45 | 2383 | return ret; |
497c9a19 | 2384 | |
3145e941 YL |
2385 | cfg = desc->chip_data; |
2386 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2387 | return ret; |
54168ed7 | 2388 | |
debccb3e | 2389 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2390 | |
54168ed7 IM |
2391 | irte.vector = cfg->vector; |
2392 | irte.dest_id = IRTE_DEST(dest); | |
2393 | ||
2394 | /* | |
2395 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2396 | */ | |
2397 | modify_irte(irq, &irte); | |
2398 | ||
22f65d31 MT |
2399 | if (cfg->move_in_progress) |
2400 | send_cleanup_vector(cfg); | |
54168ed7 | 2401 | |
7f7ace0c | 2402 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2403 | |
2404 | return 0; | |
54168ed7 IM |
2405 | } |
2406 | ||
54168ed7 IM |
2407 | /* |
2408 | * Migrates the IRQ destination in the process context. | |
2409 | */ | |
d5dedd45 | 2410 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2411 | const struct cpumask *mask) |
54168ed7 | 2412 | { |
d5dedd45 | 2413 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2414 | } |
d5dedd45 | 2415 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2416 | const struct cpumask *mask) |
3145e941 YL |
2417 | { |
2418 | struct irq_desc *desc = irq_to_desc(irq); | |
2419 | ||
d5dedd45 | 2420 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2421 | } |
29b61be6 | 2422 | #else |
d5dedd45 | 2423 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2424 | const struct cpumask *mask) |
2425 | { | |
d5dedd45 | 2426 | return 0; |
29b61be6 | 2427 | } |
54168ed7 IM |
2428 | #endif |
2429 | ||
2430 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2431 | { | |
2432 | unsigned vector, me; | |
8f2466f4 | 2433 | |
54168ed7 | 2434 | ack_APIC_irq(); |
54168ed7 | 2435 | exit_idle(); |
54168ed7 IM |
2436 | irq_enter(); |
2437 | ||
2438 | me = smp_processor_id(); | |
2439 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2440 | unsigned int irq; | |
68a8ca59 | 2441 | unsigned int irr; |
54168ed7 IM |
2442 | struct irq_desc *desc; |
2443 | struct irq_cfg *cfg; | |
2444 | irq = __get_cpu_var(vector_irq)[vector]; | |
2445 | ||
0b8f1efa YL |
2446 | if (irq == -1) |
2447 | continue; | |
2448 | ||
54168ed7 IM |
2449 | desc = irq_to_desc(irq); |
2450 | if (!desc) | |
2451 | continue; | |
2452 | ||
2453 | cfg = irq_cfg(irq); | |
2454 | spin_lock(&desc->lock); | |
2455 | if (!cfg->move_cleanup_count) | |
2456 | goto unlock; | |
2457 | ||
22f65d31 | 2458 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2459 | goto unlock; |
2460 | ||
68a8ca59 SS |
2461 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2462 | /* | |
2463 | * Check if the vector that needs to be cleanedup is | |
2464 | * registered at the cpu's IRR. If so, then this is not | |
2465 | * the best time to clean it up. Lets clean it up in the | |
2466 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2467 | * to myself. | |
2468 | */ | |
2469 | if (irr & (1 << (vector % 32))) { | |
2470 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2471 | goto unlock; | |
2472 | } | |
54168ed7 IM |
2473 | __get_cpu_var(vector_irq)[vector] = -1; |
2474 | cfg->move_cleanup_count--; | |
2475 | unlock: | |
2476 | spin_unlock(&desc->lock); | |
2477 | } | |
2478 | ||
2479 | irq_exit(); | |
2480 | } | |
2481 | ||
3145e941 | 2482 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2483 | { |
3145e941 YL |
2484 | struct irq_desc *desc = *descp; |
2485 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2486 | unsigned vector, me; |
2487 | ||
fcef5911 | 2488 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2489 | return; |
2490 | ||
2491 | vector = ~get_irq_regs()->orig_ax; | |
2492 | me = smp_processor_id(); | |
10b888d6 | 2493 | |
fcef5911 | 2494 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2495 | send_cleanup_vector(cfg); |
497c9a19 YL |
2496 | } |
2497 | #else | |
3145e941 | 2498 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2499 | #endif |
3145e941 | 2500 | |
1d025192 YL |
2501 | static void ack_apic_edge(unsigned int irq) |
2502 | { | |
3145e941 YL |
2503 | struct irq_desc *desc = irq_to_desc(irq); |
2504 | ||
2505 | irq_complete_move(&desc); | |
1d025192 YL |
2506 | move_native_irq(irq); |
2507 | ack_APIC_irq(); | |
2508 | } | |
2509 | ||
3eb2cce8 | 2510 | atomic_t irq_mis_count; |
3eb2cce8 | 2511 | |
047c8fdb YL |
2512 | static void ack_apic_level(unsigned int irq) |
2513 | { | |
3145e941 YL |
2514 | struct irq_desc *desc = irq_to_desc(irq); |
2515 | ||
3eb2cce8 YL |
2516 | #ifdef CONFIG_X86_32 |
2517 | unsigned long v; | |
2518 | int i; | |
2519 | #endif | |
3145e941 | 2520 | struct irq_cfg *cfg; |
54168ed7 | 2521 | int do_unmask_irq = 0; |
047c8fdb | 2522 | |
3145e941 | 2523 | irq_complete_move(&desc); |
047c8fdb | 2524 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2525 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2526 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2527 | do_unmask_irq = 1; |
3145e941 | 2528 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2529 | } |
047c8fdb YL |
2530 | #endif |
2531 | ||
3eb2cce8 YL |
2532 | #ifdef CONFIG_X86_32 |
2533 | /* | |
2534 | * It appears there is an erratum which affects at least version 0x11 | |
2535 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2536 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2537 | * erroneously delivered as edge-triggered one but the respective IRR | |
2538 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2539 | * message but it will never arrive and further interrupts are blocked | |
2540 | * from the source. The exact reason is so far unknown, but the | |
2541 | * phenomenon was observed when two consecutive interrupt requests | |
2542 | * from a given source get delivered to the same CPU and the source is | |
2543 | * temporarily disabled in between. | |
2544 | * | |
2545 | * A workaround is to simulate an EOI message manually. We achieve it | |
2546 | * by setting the trigger mode to edge and then to level when the edge | |
2547 | * trigger mode gets detected in the TMR of a local APIC for a | |
2548 | * level-triggered interrupt. We mask the source for the time of the | |
2549 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2550 | * The idea is from Manfred Spraul. --macro | |
2551 | */ | |
3145e941 YL |
2552 | cfg = desc->chip_data; |
2553 | i = cfg->vector; | |
3eb2cce8 YL |
2554 | |
2555 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2556 | #endif | |
2557 | ||
54168ed7 IM |
2558 | /* |
2559 | * We must acknowledge the irq before we move it or the acknowledge will | |
2560 | * not propagate properly. | |
2561 | */ | |
2562 | ack_APIC_irq(); | |
2563 | ||
2564 | /* Now we can move and renable the irq */ | |
2565 | if (unlikely(do_unmask_irq)) { | |
2566 | /* Only migrate the irq if the ack has been received. | |
2567 | * | |
2568 | * On rare occasions the broadcast level triggered ack gets | |
2569 | * delayed going to ioapics, and if we reprogram the | |
2570 | * vector while Remote IRR is still set the irq will never | |
2571 | * fire again. | |
2572 | * | |
2573 | * To prevent this scenario we read the Remote IRR bit | |
2574 | * of the ioapic. This has two effects. | |
2575 | * - On any sane system the read of the ioapic will | |
2576 | * flush writes (and acks) going to the ioapic from | |
2577 | * this cpu. | |
2578 | * - We get to see if the ACK has actually been delivered. | |
2579 | * | |
2580 | * Based on failed experiments of reprogramming the | |
2581 | * ioapic entry from outside of irq context starting | |
2582 | * with masking the ioapic entry and then polling until | |
2583 | * Remote IRR was clear before reprogramming the | |
2584 | * ioapic I don't trust the Remote IRR bit to be | |
2585 | * completey accurate. | |
2586 | * | |
2587 | * However there appears to be no other way to plug | |
2588 | * this race, so if the Remote IRR bit is not | |
2589 | * accurate and is causing problems then it is a hardware bug | |
2590 | * and you can go talk to the chipset vendor about it. | |
2591 | */ | |
3145e941 YL |
2592 | cfg = desc->chip_data; |
2593 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2594 | move_masked_irq(irq); |
3145e941 | 2595 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2596 | } |
1d025192 | 2597 | |
3eb2cce8 | 2598 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2599 | if (!(v & (1 << (i & 0x1f)))) { |
2600 | atomic_inc(&irq_mis_count); | |
2601 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2602 | __mask_and_edge_IO_APIC_irq(cfg); |
2603 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2604 | spin_unlock(&ioapic_lock); |
2605 | } | |
047c8fdb | 2606 | #endif |
3eb2cce8 | 2607 | } |
1d025192 | 2608 | |
d0b03bd1 | 2609 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2610 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2611 | { | |
2612 | int apic, pin; | |
2613 | struct irq_pin_list *entry; | |
2614 | ||
2615 | entry = cfg->irq_2_pin; | |
2616 | for (;;) { | |
2617 | ||
2618 | if (!entry) | |
2619 | break; | |
2620 | ||
2621 | apic = entry->apic; | |
2622 | pin = entry->pin; | |
2623 | io_apic_eoi(apic, pin); | |
2624 | entry = entry->next; | |
2625 | } | |
2626 | } | |
2627 | ||
2628 | static void | |
2629 | eoi_ioapic_irq(struct irq_desc *desc) | |
2630 | { | |
2631 | struct irq_cfg *cfg; | |
2632 | unsigned long flags; | |
2633 | unsigned int irq; | |
2634 | ||
2635 | irq = desc->irq; | |
2636 | cfg = desc->chip_data; | |
2637 | ||
2638 | spin_lock_irqsave(&ioapic_lock, flags); | |
2639 | __eoi_ioapic_irq(irq, cfg); | |
2640 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2641 | } | |
2642 | ||
d0b03bd1 HW |
2643 | static void ir_ack_apic_edge(unsigned int irq) |
2644 | { | |
5d0ae2db | 2645 | ack_APIC_irq(); |
d0b03bd1 HW |
2646 | } |
2647 | ||
2648 | static void ir_ack_apic_level(unsigned int irq) | |
2649 | { | |
5d0ae2db WH |
2650 | struct irq_desc *desc = irq_to_desc(irq); |
2651 | ||
2652 | ack_APIC_irq(); | |
2653 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2654 | } |
2655 | #endif /* CONFIG_INTR_REMAP */ | |
2656 | ||
f5b9ed7a | 2657 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2658 | .name = "IO-APIC", |
2659 | .startup = startup_ioapic_irq, | |
2660 | .mask = mask_IO_APIC_irq, | |
2661 | .unmask = unmask_IO_APIC_irq, | |
2662 | .ack = ack_apic_edge, | |
2663 | .eoi = ack_apic_level, | |
54d5d424 | 2664 | #ifdef CONFIG_SMP |
d6c88a50 | 2665 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2666 | #endif |
ace80ab7 | 2667 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2668 | }; |
2669 | ||
54168ed7 | 2670 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2671 | .name = "IR-IO-APIC", |
2672 | .startup = startup_ioapic_irq, | |
2673 | .mask = mask_IO_APIC_irq, | |
2674 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2675 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2676 | .ack = ir_ack_apic_edge, |
2677 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2678 | #ifdef CONFIG_SMP |
d6c88a50 | 2679 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2680 | #endif |
54168ed7 IM |
2681 | #endif |
2682 | .retrigger = ioapic_retrigger_irq, | |
2683 | }; | |
1da177e4 LT |
2684 | |
2685 | static inline void init_IO_APIC_traps(void) | |
2686 | { | |
2687 | int irq; | |
08678b08 | 2688 | struct irq_desc *desc; |
da51a821 | 2689 | struct irq_cfg *cfg; |
1da177e4 LT |
2690 | |
2691 | /* | |
2692 | * NOTE! The local APIC isn't very good at handling | |
2693 | * multiple interrupts at the same interrupt level. | |
2694 | * As the interrupt level is determined by taking the | |
2695 | * vector number and shifting that right by 4, we | |
2696 | * want to spread these out a bit so that they don't | |
2697 | * all fall in the same interrupt level. | |
2698 | * | |
2699 | * Also, we've got to be careful not to trash gate | |
2700 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2701 | */ | |
0b8f1efa | 2702 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2703 | cfg = desc->chip_data; |
2704 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2705 | /* |
2706 | * Hmm.. We don't have an entry for this, | |
2707 | * so default to an old-fashioned 8259 | |
2708 | * interrupt if we can.. | |
2709 | */ | |
99d093d1 | 2710 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2711 | make_8259A_irq(irq); |
0b8f1efa | 2712 | else |
1da177e4 | 2713 | /* Strange. Oh, well.. */ |
08678b08 | 2714 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2715 | } |
2716 | } | |
2717 | } | |
2718 | ||
f5b9ed7a IM |
2719 | /* |
2720 | * The local APIC irq-chip implementation: | |
2721 | */ | |
1da177e4 | 2722 | |
36062448 | 2723 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2724 | { |
2725 | unsigned long v; | |
2726 | ||
2727 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2728 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2729 | } |
2730 | ||
36062448 | 2731 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2732 | { |
f5b9ed7a | 2733 | unsigned long v; |
1da177e4 | 2734 | |
f5b9ed7a | 2735 | v = apic_read(APIC_LVT0); |
593f4a78 | 2736 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2737 | } |
1da177e4 | 2738 | |
3145e941 | 2739 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2740 | { |
2741 | ack_APIC_irq(); | |
2742 | } | |
2743 | ||
f5b9ed7a | 2744 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2745 | .name = "local-APIC", |
f5b9ed7a IM |
2746 | .mask = mask_lapic_irq, |
2747 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2748 | .ack = ack_lapic_irq, |
1da177e4 LT |
2749 | }; |
2750 | ||
3145e941 | 2751 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2752 | { |
08678b08 | 2753 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2754 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2755 | "edge"); | |
c88ac1df MR |
2756 | } |
2757 | ||
e9427101 | 2758 | static void __init setup_nmi(void) |
1da177e4 LT |
2759 | { |
2760 | /* | |
36062448 | 2761 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2762 | * We put the 8259A master into AEOI mode and |
2763 | * unmask on all local APICs LVT0 as NMI. | |
2764 | * | |
2765 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2766 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2767 | * the NMI handler or the timer interrupt. | |
36062448 | 2768 | */ |
1da177e4 LT |
2769 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2770 | ||
e9427101 | 2771 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2772 | |
2773 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2774 | } | |
2775 | ||
2776 | /* | |
2777 | * This looks a bit hackish but it's about the only one way of sending | |
2778 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2779 | * not support the ExtINT mode, unfortunately. We need to send these | |
2780 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2781 | * 8259A interrupt line asserted until INTA. --macro | |
2782 | */ | |
28acf285 | 2783 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2784 | { |
fcfd636a | 2785 | int apic, pin, i; |
1da177e4 LT |
2786 | struct IO_APIC_route_entry entry0, entry1; |
2787 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2788 | |
fcfd636a | 2789 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2790 | if (pin == -1) { |
2791 | WARN_ON_ONCE(1); | |
2792 | return; | |
2793 | } | |
fcfd636a | 2794 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2795 | if (apic == -1) { |
2796 | WARN_ON_ONCE(1); | |
1da177e4 | 2797 | return; |
956fb531 | 2798 | } |
1da177e4 | 2799 | |
cf4c6a2f | 2800 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2801 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2802 | |
2803 | memset(&entry1, 0, sizeof(entry1)); | |
2804 | ||
2805 | entry1.dest_mode = 0; /* physical delivery */ | |
2806 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2807 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2808 | entry1.delivery_mode = dest_ExtINT; |
2809 | entry1.polarity = entry0.polarity; | |
2810 | entry1.trigger = 0; | |
2811 | entry1.vector = 0; | |
2812 | ||
cf4c6a2f | 2813 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2814 | |
2815 | save_control = CMOS_READ(RTC_CONTROL); | |
2816 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2817 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2818 | RTC_FREQ_SELECT); | |
2819 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2820 | ||
2821 | i = 100; | |
2822 | while (i-- > 0) { | |
2823 | mdelay(10); | |
2824 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2825 | i -= 10; | |
2826 | } | |
2827 | ||
2828 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2829 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2830 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2831 | |
cf4c6a2f | 2832 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2833 | } |
2834 | ||
efa2559f | 2835 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2836 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2837 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2838 | { |
2839 | disable_timer_pin_1 = 1; | |
2840 | return 0; | |
2841 | } | |
54168ed7 | 2842 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2843 | |
2844 | int timer_through_8259 __initdata; | |
2845 | ||
1da177e4 LT |
2846 | /* |
2847 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2848 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2849 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2850 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2851 | * |
2852 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2853 | */ |
8542b200 | 2854 | static inline void __init check_timer(void) |
1da177e4 | 2855 | { |
3145e941 YL |
2856 | struct irq_desc *desc = irq_to_desc(0); |
2857 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2858 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2859 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2860 | unsigned long flags; |
047c8fdb | 2861 | int no_pin1 = 0; |
4aae0702 IM |
2862 | |
2863 | local_irq_save(flags); | |
d4d25dec | 2864 | |
1da177e4 LT |
2865 | /* |
2866 | * get/set the timer IRQ vector: | |
2867 | */ | |
2868 | disable_8259A_irq(0); | |
fe402e1f | 2869 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2870 | |
2871 | /* | |
d11d5794 MR |
2872 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2873 | * wire has to be disabled in the local APIC. Also | |
2874 | * timer interrupts need to be acknowledged manually in | |
2875 | * the 8259A for the i82489DX when using the NMI | |
2876 | * watchdog as that APIC treats NMIs as level-triggered. | |
2877 | * The AEOI mode will finish them in the 8259A | |
2878 | * automatically. | |
1da177e4 | 2879 | */ |
593f4a78 | 2880 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2881 | init_8259A(1); |
54168ed7 | 2882 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2883 | { |
2884 | unsigned int ver; | |
2885 | ||
2886 | ver = apic_read(APIC_LVR); | |
2887 | ver = GET_APIC_VERSION(ver); | |
2888 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2889 | } | |
54168ed7 | 2890 | #endif |
1da177e4 | 2891 | |
fcfd636a EB |
2892 | pin1 = find_isa_irq_pin(0, mp_INT); |
2893 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2894 | pin2 = ioapic_i8259.pin; | |
2895 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2896 | |
49a66a0b MR |
2897 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2898 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2899 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2900 | |
691874fa MR |
2901 | /* |
2902 | * Some BIOS writers are clueless and report the ExtINTA | |
2903 | * I/O APIC input from the cascaded 8259A as the timer | |
2904 | * interrupt input. So just in case, if only one pin | |
2905 | * was found above, try it both directly and through the | |
2906 | * 8259A. | |
2907 | */ | |
2908 | if (pin1 == -1) { | |
54168ed7 IM |
2909 | if (intr_remapping_enabled) |
2910 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2911 | pin1 = pin2; |
2912 | apic1 = apic2; | |
2913 | no_pin1 = 1; | |
2914 | } else if (pin2 == -1) { | |
2915 | pin2 = pin1; | |
2916 | apic2 = apic1; | |
2917 | } | |
2918 | ||
1da177e4 LT |
2919 | if (pin1 != -1) { |
2920 | /* | |
2921 | * Ok, does IRQ0 through the IOAPIC work? | |
2922 | */ | |
691874fa | 2923 | if (no_pin1) { |
85ac16d0 | 2924 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2925 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2926 | } else { |
2927 | /* for edge trigger, setup_IO_APIC_irq already | |
2928 | * leave it unmasked. | |
2929 | * so only need to unmask if it is level-trigger | |
2930 | * do we really have level trigger timer? | |
2931 | */ | |
2932 | int idx; | |
2933 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2934 | if (idx != -1 && irq_trigger(idx)) | |
2935 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2936 | } |
1da177e4 LT |
2937 | if (timer_irq_works()) { |
2938 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2939 | setup_nmi(); |
2940 | enable_8259A_irq(0); | |
1da177e4 | 2941 | } |
66759a01 CE |
2942 | if (disable_timer_pin_1 > 0) |
2943 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2944 | goto out; |
1da177e4 | 2945 | } |
54168ed7 IM |
2946 | if (intr_remapping_enabled) |
2947 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2948 | local_irq_disable(); |
fcfd636a | 2949 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2950 | if (!no_pin1) |
49a66a0b MR |
2951 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2952 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2953 | |
49a66a0b MR |
2954 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2955 | "(IRQ0) through the 8259A ...\n"); | |
2956 | apic_printk(APIC_QUIET, KERN_INFO | |
2957 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2958 | /* |
2959 | * legacy devices should be connected to IO APIC #0 | |
2960 | */ | |
85ac16d0 | 2961 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2962 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2963 | enable_8259A_irq(0); |
1da177e4 | 2964 | if (timer_irq_works()) { |
49a66a0b | 2965 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2966 | timer_through_8259 = 1; |
1da177e4 | 2967 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2968 | disable_8259A_irq(0); |
1da177e4 | 2969 | setup_nmi(); |
60134ebe | 2970 | enable_8259A_irq(0); |
1da177e4 | 2971 | } |
4aae0702 | 2972 | goto out; |
1da177e4 LT |
2973 | } |
2974 | /* | |
2975 | * Cleanup, just in case ... | |
2976 | */ | |
f72dccac | 2977 | local_irq_disable(); |
ecd29476 | 2978 | disable_8259A_irq(0); |
fcfd636a | 2979 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2980 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2981 | } |
1da177e4 LT |
2982 | |
2983 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2984 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2985 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2986 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2987 | } |
54168ed7 | 2988 | #ifdef CONFIG_X86_32 |
d11d5794 | 2989 | timer_ack = 0; |
54168ed7 | 2990 | #endif |
1da177e4 | 2991 | |
49a66a0b MR |
2992 | apic_printk(APIC_QUIET, KERN_INFO |
2993 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2994 | |
3145e941 | 2995 | lapic_register_intr(0, desc); |
497c9a19 | 2996 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2997 | enable_8259A_irq(0); |
2998 | ||
2999 | if (timer_irq_works()) { | |
49a66a0b | 3000 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3001 | goto out; |
1da177e4 | 3002 | } |
f72dccac | 3003 | local_irq_disable(); |
e67465f1 | 3004 | disable_8259A_irq(0); |
497c9a19 | 3005 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3006 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3007 | |
49a66a0b MR |
3008 | apic_printk(APIC_QUIET, KERN_INFO |
3009 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3010 | |
1da177e4 LT |
3011 | init_8259A(0); |
3012 | make_8259A_irq(0); | |
593f4a78 | 3013 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3014 | |
3015 | unlock_ExtINT_logic(); | |
3016 | ||
3017 | if (timer_irq_works()) { | |
49a66a0b | 3018 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3019 | goto out; |
1da177e4 | 3020 | } |
f72dccac | 3021 | local_irq_disable(); |
49a66a0b | 3022 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3023 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3024 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3025 | out: |
3026 | local_irq_restore(flags); | |
1da177e4 LT |
3027 | } |
3028 | ||
3029 | /* | |
af174783 MR |
3030 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3031 | * to devices. However there may be an I/O APIC pin available for | |
3032 | * this interrupt regardless. The pin may be left unconnected, but | |
3033 | * typically it will be reused as an ExtINT cascade interrupt for | |
3034 | * the master 8259A. In the MPS case such a pin will normally be | |
3035 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3036 | * there is no provision for ExtINT interrupts, and in the absence | |
3037 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3038 | * interrupt, that is edge-triggered and unmasked by default. We | |
3039 | * used to do this, but it caused problems on some systems because | |
3040 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3041 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3042 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3043 | * the I/O APIC in all cases now. No actual device should request | |
3044 | * it anyway. --macro | |
1da177e4 LT |
3045 | */ |
3046 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3047 | ||
3048 | void __init setup_IO_APIC(void) | |
3049 | { | |
54168ed7 | 3050 | |
54168ed7 IM |
3051 | /* |
3052 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3053 | */ | |
1da177e4 | 3054 | |
af174783 | 3055 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3056 | |
54168ed7 | 3057 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3058 | /* |
54168ed7 IM |
3059 | * Set up IO-APIC IRQ routing. |
3060 | */ | |
3061 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3062 | if (!acpi_ioapic) |
3063 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3064 | #endif |
1da177e4 LT |
3065 | sync_Arb_IDs(); |
3066 | setup_IO_APIC_irqs(); | |
3067 | init_IO_APIC_traps(); | |
1e4c85f9 | 3068 | check_timer(); |
1da177e4 LT |
3069 | } |
3070 | ||
3071 | /* | |
54168ed7 IM |
3072 | * Called after all the initialization is done. If we didnt find any |
3073 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3074 | */ |
36062448 | 3075 | |
1da177e4 LT |
3076 | static int __init io_apic_bug_finalize(void) |
3077 | { | |
d6c88a50 TG |
3078 | if (sis_apic_bug == -1) |
3079 | sis_apic_bug = 0; | |
3080 | return 0; | |
1da177e4 LT |
3081 | } |
3082 | ||
3083 | late_initcall(io_apic_bug_finalize); | |
3084 | ||
3085 | struct sysfs_ioapic_data { | |
3086 | struct sys_device dev; | |
3087 | struct IO_APIC_route_entry entry[0]; | |
3088 | }; | |
54168ed7 | 3089 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3090 | |
438510f6 | 3091 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3092 | { |
3093 | struct IO_APIC_route_entry *entry; | |
3094 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3095 | int i; |
36062448 | 3096 | |
1da177e4 LT |
3097 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3098 | entry = data->entry; | |
54168ed7 IM |
3099 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3100 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3101 | |
3102 | return 0; | |
3103 | } | |
3104 | ||
3105 | static int ioapic_resume(struct sys_device *dev) | |
3106 | { | |
3107 | struct IO_APIC_route_entry *entry; | |
3108 | struct sysfs_ioapic_data *data; | |
3109 | unsigned long flags; | |
3110 | union IO_APIC_reg_00 reg_00; | |
3111 | int i; | |
36062448 | 3112 | |
1da177e4 LT |
3113 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3114 | entry = data->entry; | |
3115 | ||
3116 | spin_lock_irqsave(&ioapic_lock, flags); | |
3117 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3118 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3119 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3120 | io_apic_write(dev->id, 0, reg_00.raw); |
3121 | } | |
1da177e4 | 3122 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3123 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3124 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3125 | |
3126 | return 0; | |
3127 | } | |
3128 | ||
3129 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3130 | .name = "ioapic", |
1da177e4 LT |
3131 | .suspend = ioapic_suspend, |
3132 | .resume = ioapic_resume, | |
3133 | }; | |
3134 | ||
3135 | static int __init ioapic_init_sysfs(void) | |
3136 | { | |
54168ed7 IM |
3137 | struct sys_device * dev; |
3138 | int i, size, error; | |
1da177e4 LT |
3139 | |
3140 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3141 | if (error) | |
3142 | return error; | |
3143 | ||
54168ed7 | 3144 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3145 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3146 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3147 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3148 | if (!mp_ioapic_data[i]) { |
3149 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3150 | continue; | |
3151 | } | |
1da177e4 | 3152 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3153 | dev->id = i; |
1da177e4 LT |
3154 | dev->cls = &ioapic_sysdev_class; |
3155 | error = sysdev_register(dev); | |
3156 | if (error) { | |
3157 | kfree(mp_ioapic_data[i]); | |
3158 | mp_ioapic_data[i] = NULL; | |
3159 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3160 | continue; | |
3161 | } | |
3162 | } | |
3163 | ||
3164 | return 0; | |
3165 | } | |
3166 | ||
3167 | device_initcall(ioapic_init_sysfs); | |
3168 | ||
abcaa2b8 | 3169 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3170 | /* |
95d77884 | 3171 | * Dynamic irq allocate and deallocation |
3fc471ed | 3172 | */ |
d047f53a | 3173 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3174 | { |
ace80ab7 | 3175 | /* Allocate an unused irq */ |
54168ed7 IM |
3176 | unsigned int irq; |
3177 | unsigned int new; | |
3fc471ed | 3178 | unsigned long flags; |
0b8f1efa | 3179 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3180 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3181 | |
3182 | irq = 0; | |
abcaa2b8 YL |
3183 | if (irq_want < nr_irqs_gsi) |
3184 | irq_want = nr_irqs_gsi; | |
3185 | ||
ace80ab7 | 3186 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3187 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3188 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3189 | if (!desc_new) { |
3190 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3191 | continue; |
0b8f1efa YL |
3192 | } |
3193 | cfg_new = desc_new->chip_data; | |
3194 | ||
3195 | if (cfg_new->vector != 0) | |
ace80ab7 | 3196 | continue; |
d047f53a | 3197 | |
15e957d0 | 3198 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3199 | |
fe402e1f | 3200 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3201 | irq = new; |
3202 | break; | |
3203 | } | |
3204 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3205 | |
199751d7 | 3206 | if (irq > 0) { |
3fc471ed | 3207 | dynamic_irq_init(irq); |
0b8f1efa YL |
3208 | /* restore it, in case dynamic_irq_init clear it */ |
3209 | if (desc_new) | |
3210 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3211 | } |
3212 | return irq; | |
3213 | } | |
3214 | ||
199751d7 YL |
3215 | int create_irq(void) |
3216 | { | |
d047f53a | 3217 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3218 | unsigned int irq_want; |
54168ed7 IM |
3219 | int irq; |
3220 | ||
be5d5350 | 3221 | irq_want = nr_irqs_gsi; |
d047f53a | 3222 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3223 | |
3224 | if (irq == 0) | |
3225 | irq = -1; | |
3226 | ||
3227 | return irq; | |
199751d7 YL |
3228 | } |
3229 | ||
3fc471ed EB |
3230 | void destroy_irq(unsigned int irq) |
3231 | { | |
3232 | unsigned long flags; | |
0b8f1efa YL |
3233 | struct irq_cfg *cfg; |
3234 | struct irq_desc *desc; | |
3fc471ed | 3235 | |
0b8f1efa YL |
3236 | /* store it, in case dynamic_irq_cleanup clear it */ |
3237 | desc = irq_to_desc(irq); | |
3238 | cfg = desc->chip_data; | |
3fc471ed | 3239 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3240 | /* connect back irq_cfg */ |
3241 | if (desc) | |
3242 | desc->chip_data = cfg; | |
3fc471ed | 3243 | |
54168ed7 | 3244 | free_irte(irq); |
3fc471ed | 3245 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3246 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3247 | spin_unlock_irqrestore(&vector_lock, flags); |
3248 | } | |
3fc471ed | 3249 | |
2d3fcc1c | 3250 | /* |
27b46d76 | 3251 | * MSI message composition |
2d3fcc1c EB |
3252 | */ |
3253 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3254 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3255 | { |
497c9a19 YL |
3256 | struct irq_cfg *cfg; |
3257 | int err; | |
2d3fcc1c EB |
3258 | unsigned dest; |
3259 | ||
f1182638 JB |
3260 | if (disable_apic) |
3261 | return -ENXIO; | |
3262 | ||
3145e941 | 3263 | cfg = irq_cfg(irq); |
fe402e1f | 3264 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3265 | if (err) |
3266 | return err; | |
2d3fcc1c | 3267 | |
debccb3e | 3268 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3269 | |
54168ed7 IM |
3270 | if (irq_remapped(irq)) { |
3271 | struct irte irte; | |
3272 | int ir_index; | |
3273 | u16 sub_handle; | |
3274 | ||
3275 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3276 | BUG_ON(ir_index == -1); | |
3277 | ||
3278 | memset (&irte, 0, sizeof(irte)); | |
3279 | ||
3280 | irte.present = 1; | |
9b5bc8dc | 3281 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3282 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3283 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3284 | irte.vector = cfg->vector; |
3285 | irte.dest_id = IRTE_DEST(dest); | |
3286 | ||
3287 | modify_irte(irq, &irte); | |
3288 | ||
3289 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3290 | msg->data = sub_handle; | |
3291 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3292 | MSI_ADDR_IR_SHV | | |
3293 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3294 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3295 | } else { |
9d783ba0 SS |
3296 | if (x2apic_enabled()) |
3297 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3298 | MSI_ADDR_EXT_DEST_ID(dest); | |
3299 | else | |
3300 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3301 | ||
54168ed7 IM |
3302 | msg->address_lo = |
3303 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3304 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3305 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3306 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3307 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3308 | MSI_ADDR_REDIRECTION_CPU: |
3309 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3310 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3311 | |
54168ed7 IM |
3312 | msg->data = |
3313 | MSI_DATA_TRIGGER_EDGE | | |
3314 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3315 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3316 | MSI_DATA_DELIVERY_FIXED: |
3317 | MSI_DATA_DELIVERY_LOWPRI) | | |
3318 | MSI_DATA_VECTOR(cfg->vector); | |
3319 | } | |
497c9a19 | 3320 | return err; |
2d3fcc1c EB |
3321 | } |
3322 | ||
3b7d1921 | 3323 | #ifdef CONFIG_SMP |
d5dedd45 | 3324 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3325 | { |
3145e941 | 3326 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3327 | struct irq_cfg *cfg; |
3b7d1921 EB |
3328 | struct msi_msg msg; |
3329 | unsigned int dest; | |
3b7d1921 | 3330 | |
22f65d31 MT |
3331 | dest = set_desc_affinity(desc, mask); |
3332 | if (dest == BAD_APICID) | |
d5dedd45 | 3333 | return -1; |
2d3fcc1c | 3334 | |
3145e941 | 3335 | cfg = desc->chip_data; |
2d3fcc1c | 3336 | |
3145e941 | 3337 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3338 | |
3339 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3340 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3341 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3342 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3343 | ||
3145e941 | 3344 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3345 | |
3346 | return 0; | |
2d3fcc1c | 3347 | } |
54168ed7 IM |
3348 | #ifdef CONFIG_INTR_REMAP |
3349 | /* | |
3350 | * Migrate the MSI irq to another cpumask. This migration is | |
3351 | * done in the process context using interrupt-remapping hardware. | |
3352 | */ | |
d5dedd45 | 3353 | static int |
e7986739 | 3354 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3355 | { |
3145e941 | 3356 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3357 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3358 | unsigned int dest; |
54168ed7 | 3359 | struct irte irte; |
54168ed7 IM |
3360 | |
3361 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3362 | return -1; |
54168ed7 | 3363 | |
22f65d31 MT |
3364 | dest = set_desc_affinity(desc, mask); |
3365 | if (dest == BAD_APICID) | |
d5dedd45 | 3366 | return -1; |
54168ed7 | 3367 | |
54168ed7 IM |
3368 | irte.vector = cfg->vector; |
3369 | irte.dest_id = IRTE_DEST(dest); | |
3370 | ||
3371 | /* | |
3372 | * atomically update the IRTE with the new destination and vector. | |
3373 | */ | |
3374 | modify_irte(irq, &irte); | |
3375 | ||
3376 | /* | |
3377 | * After this point, all the interrupts will start arriving | |
3378 | * at the new destination. So, time to cleanup the previous | |
3379 | * vector allocation. | |
3380 | */ | |
22f65d31 MT |
3381 | if (cfg->move_in_progress) |
3382 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3383 | |
3384 | return 0; | |
54168ed7 | 3385 | } |
3145e941 | 3386 | |
54168ed7 | 3387 | #endif |
3b7d1921 | 3388 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3389 | |
3b7d1921 EB |
3390 | /* |
3391 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3392 | * which implement the MSI or MSI-X Capability Structure. | |
3393 | */ | |
3394 | static struct irq_chip msi_chip = { | |
3395 | .name = "PCI-MSI", | |
3396 | .unmask = unmask_msi_irq, | |
3397 | .mask = mask_msi_irq, | |
1d025192 | 3398 | .ack = ack_apic_edge, |
3b7d1921 EB |
3399 | #ifdef CONFIG_SMP |
3400 | .set_affinity = set_msi_irq_affinity, | |
3401 | #endif | |
3402 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3403 | }; |
3404 | ||
54168ed7 IM |
3405 | static struct irq_chip msi_ir_chip = { |
3406 | .name = "IR-PCI-MSI", | |
3407 | .unmask = unmask_msi_irq, | |
3408 | .mask = mask_msi_irq, | |
a1e38ca5 | 3409 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3410 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3411 | #ifdef CONFIG_SMP |
3412 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3413 | #endif |
54168ed7 IM |
3414 | #endif |
3415 | .retrigger = ioapic_retrigger_irq, | |
3416 | }; | |
3417 | ||
3418 | /* | |
3419 | * Map the PCI dev to the corresponding remapping hardware unit | |
3420 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3421 | * in it. | |
3422 | */ | |
3423 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3424 | { | |
3425 | struct intel_iommu *iommu; | |
3426 | int index; | |
3427 | ||
3428 | iommu = map_dev_to_ir(dev); | |
3429 | if (!iommu) { | |
3430 | printk(KERN_ERR | |
3431 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3432 | return -ENOENT; | |
3433 | } | |
3434 | ||
3435 | index = alloc_irte(iommu, irq, nvec); | |
3436 | if (index < 0) { | |
3437 | printk(KERN_ERR | |
3438 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3439 | pci_name(dev)); |
54168ed7 IM |
3440 | return -ENOSPC; |
3441 | } | |
3442 | return index; | |
3443 | } | |
1d025192 | 3444 | |
3145e941 | 3445 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3446 | { |
3447 | int ret; | |
3448 | struct msi_msg msg; | |
3449 | ||
3450 | ret = msi_compose_msg(dev, irq, &msg); | |
3451 | if (ret < 0) | |
3452 | return ret; | |
3453 | ||
3145e941 | 3454 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3455 | write_msi_msg(irq, &msg); |
3456 | ||
54168ed7 IM |
3457 | if (irq_remapped(irq)) { |
3458 | struct irq_desc *desc = irq_to_desc(irq); | |
3459 | /* | |
3460 | * irq migration in process context | |
3461 | */ | |
3462 | desc->status |= IRQ_MOVE_PCNTXT; | |
3463 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3464 | } else | |
54168ed7 | 3465 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3466 | |
c81bba49 YL |
3467 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3468 | ||
1d025192 YL |
3469 | return 0; |
3470 | } | |
3471 | ||
047c8fdb YL |
3472 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3473 | { | |
54168ed7 IM |
3474 | unsigned int irq; |
3475 | int ret, sub_handle; | |
0b8f1efa | 3476 | struct msi_desc *msidesc; |
54168ed7 | 3477 | unsigned int irq_want; |
1cc18521 | 3478 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3479 | int index = 0; |
d047f53a | 3480 | int node; |
54168ed7 | 3481 | |
1c8d7b0a MW |
3482 | /* x86 doesn't support multiple MSI yet */ |
3483 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3484 | return 1; | |
3485 | ||
d047f53a | 3486 | node = dev_to_node(&dev->dev); |
be5d5350 | 3487 | irq_want = nr_irqs_gsi; |
54168ed7 | 3488 | sub_handle = 0; |
0b8f1efa | 3489 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3490 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3491 | if (irq == 0) |
3492 | return -1; | |
f1ee5548 | 3493 | irq_want = irq + 1; |
54168ed7 IM |
3494 | if (!intr_remapping_enabled) |
3495 | goto no_ir; | |
3496 | ||
3497 | if (!sub_handle) { | |
3498 | /* | |
3499 | * allocate the consecutive block of IRTE's | |
3500 | * for 'nvec' | |
3501 | */ | |
3502 | index = msi_alloc_irte(dev, irq, nvec); | |
3503 | if (index < 0) { | |
3504 | ret = index; | |
3505 | goto error; | |
3506 | } | |
3507 | } else { | |
3508 | iommu = map_dev_to_ir(dev); | |
3509 | if (!iommu) { | |
3510 | ret = -ENOENT; | |
3511 | goto error; | |
3512 | } | |
3513 | /* | |
3514 | * setup the mapping between the irq and the IRTE | |
3515 | * base index, the sub_handle pointing to the | |
3516 | * appropriate interrupt remap table entry. | |
3517 | */ | |
3518 | set_irte_irq(irq, iommu, index, sub_handle); | |
3519 | } | |
3520 | no_ir: | |
0b8f1efa | 3521 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3522 | if (ret < 0) |
3523 | goto error; | |
3524 | sub_handle++; | |
3525 | } | |
3526 | return 0; | |
047c8fdb YL |
3527 | |
3528 | error: | |
54168ed7 IM |
3529 | destroy_irq(irq); |
3530 | return ret; | |
047c8fdb YL |
3531 | } |
3532 | ||
3b7d1921 EB |
3533 | void arch_teardown_msi_irq(unsigned int irq) |
3534 | { | |
f7feaca7 | 3535 | destroy_irq(irq); |
3b7d1921 EB |
3536 | } |
3537 | ||
9d783ba0 | 3538 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3539 | #ifdef CONFIG_SMP |
d5dedd45 | 3540 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3541 | { |
3145e941 | 3542 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3543 | struct irq_cfg *cfg; |
3544 | struct msi_msg msg; | |
3545 | unsigned int dest; | |
54168ed7 | 3546 | |
22f65d31 MT |
3547 | dest = set_desc_affinity(desc, mask); |
3548 | if (dest == BAD_APICID) | |
d5dedd45 | 3549 | return -1; |
54168ed7 | 3550 | |
3145e941 | 3551 | cfg = desc->chip_data; |
54168ed7 IM |
3552 | |
3553 | dmar_msi_read(irq, &msg); | |
3554 | ||
3555 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3556 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3557 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3558 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3559 | ||
3560 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3561 | |
3562 | return 0; | |
54168ed7 | 3563 | } |
3145e941 | 3564 | |
54168ed7 IM |
3565 | #endif /* CONFIG_SMP */ |
3566 | ||
3567 | struct irq_chip dmar_msi_type = { | |
3568 | .name = "DMAR_MSI", | |
3569 | .unmask = dmar_msi_unmask, | |
3570 | .mask = dmar_msi_mask, | |
3571 | .ack = ack_apic_edge, | |
3572 | #ifdef CONFIG_SMP | |
3573 | .set_affinity = dmar_msi_set_affinity, | |
3574 | #endif | |
3575 | .retrigger = ioapic_retrigger_irq, | |
3576 | }; | |
3577 | ||
3578 | int arch_setup_dmar_msi(unsigned int irq) | |
3579 | { | |
3580 | int ret; | |
3581 | struct msi_msg msg; | |
2d3fcc1c | 3582 | |
54168ed7 IM |
3583 | ret = msi_compose_msg(NULL, irq, &msg); |
3584 | if (ret < 0) | |
3585 | return ret; | |
3586 | dmar_msi_write(irq, &msg); | |
3587 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3588 | "edge"); | |
3589 | return 0; | |
3590 | } | |
3591 | #endif | |
3592 | ||
58ac1e76 | 3593 | #ifdef CONFIG_HPET_TIMER |
3594 | ||
3595 | #ifdef CONFIG_SMP | |
d5dedd45 | 3596 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3597 | { |
3145e941 | 3598 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3599 | struct irq_cfg *cfg; |
58ac1e76 | 3600 | struct msi_msg msg; |
3601 | unsigned int dest; | |
58ac1e76 | 3602 | |
22f65d31 MT |
3603 | dest = set_desc_affinity(desc, mask); |
3604 | if (dest == BAD_APICID) | |
d5dedd45 | 3605 | return -1; |
58ac1e76 | 3606 | |
3145e941 | 3607 | cfg = desc->chip_data; |
58ac1e76 | 3608 | |
3609 | hpet_msi_read(irq, &msg); | |
3610 | ||
3611 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3612 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3613 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3614 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3615 | ||
3616 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3617 | |
3618 | return 0; | |
58ac1e76 | 3619 | } |
3145e941 | 3620 | |
58ac1e76 | 3621 | #endif /* CONFIG_SMP */ |
3622 | ||
1cc18521 | 3623 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3624 | .name = "HPET_MSI", |
3625 | .unmask = hpet_msi_unmask, | |
3626 | .mask = hpet_msi_mask, | |
3627 | .ack = ack_apic_edge, | |
3628 | #ifdef CONFIG_SMP | |
3629 | .set_affinity = hpet_msi_set_affinity, | |
3630 | #endif | |
3631 | .retrigger = ioapic_retrigger_irq, | |
3632 | }; | |
3633 | ||
3634 | int arch_setup_hpet_msi(unsigned int irq) | |
3635 | { | |
3636 | int ret; | |
3637 | struct msi_msg msg; | |
6ec3cfec | 3638 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3639 | |
3640 | ret = msi_compose_msg(NULL, irq, &msg); | |
3641 | if (ret < 0) | |
3642 | return ret; | |
3643 | ||
3644 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3645 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3646 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3647 | "edge"); | |
c81bba49 | 3648 | |
58ac1e76 | 3649 | return 0; |
3650 | } | |
3651 | #endif | |
3652 | ||
54168ed7 | 3653 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3654 | /* |
3655 | * Hypertransport interrupt support | |
3656 | */ | |
3657 | #ifdef CONFIG_HT_IRQ | |
3658 | ||
3659 | #ifdef CONFIG_SMP | |
3660 | ||
497c9a19 | 3661 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3662 | { |
ec68307c EB |
3663 | struct ht_irq_msg msg; |
3664 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3665 | |
497c9a19 | 3666 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3667 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3668 | |
497c9a19 | 3669 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3670 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3671 | |
ec68307c | 3672 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3673 | } |
3674 | ||
d5dedd45 | 3675 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3676 | { |
3145e941 | 3677 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3678 | struct irq_cfg *cfg; |
8b955b0d | 3679 | unsigned int dest; |
8b955b0d | 3680 | |
22f65d31 MT |
3681 | dest = set_desc_affinity(desc, mask); |
3682 | if (dest == BAD_APICID) | |
d5dedd45 | 3683 | return -1; |
8b955b0d | 3684 | |
3145e941 | 3685 | cfg = desc->chip_data; |
8b955b0d | 3686 | |
497c9a19 | 3687 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3688 | |
3689 | return 0; | |
8b955b0d | 3690 | } |
3145e941 | 3691 | |
8b955b0d EB |
3692 | #endif |
3693 | ||
c37e108d | 3694 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3695 | .name = "PCI-HT", |
3696 | .mask = mask_ht_irq, | |
3697 | .unmask = unmask_ht_irq, | |
1d025192 | 3698 | .ack = ack_apic_edge, |
8b955b0d EB |
3699 | #ifdef CONFIG_SMP |
3700 | .set_affinity = set_ht_irq_affinity, | |
3701 | #endif | |
3702 | .retrigger = ioapic_retrigger_irq, | |
3703 | }; | |
3704 | ||
3705 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3706 | { | |
497c9a19 YL |
3707 | struct irq_cfg *cfg; |
3708 | int err; | |
8b955b0d | 3709 | |
f1182638 JB |
3710 | if (disable_apic) |
3711 | return -ENXIO; | |
3712 | ||
3145e941 | 3713 | cfg = irq_cfg(irq); |
fe402e1f | 3714 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3715 | if (!err) { |
ec68307c | 3716 | struct ht_irq_msg msg; |
8b955b0d | 3717 | unsigned dest; |
8b955b0d | 3718 | |
debccb3e IM |
3719 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3720 | apic->target_cpus()); | |
8b955b0d | 3721 | |
ec68307c | 3722 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3723 | |
ec68307c EB |
3724 | msg.address_lo = |
3725 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3726 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3727 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3728 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3729 | HT_IRQ_LOW_DM_PHYSICAL : |
3730 | HT_IRQ_LOW_DM_LOGICAL) | | |
3731 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3732 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3733 | HT_IRQ_LOW_MT_FIXED : |
3734 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3735 | HT_IRQ_LOW_IRQ_MASKED; | |
3736 | ||
ec68307c | 3737 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3738 | |
a460e745 IM |
3739 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3740 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3741 | |
3742 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3743 | } |
497c9a19 | 3744 | return err; |
8b955b0d EB |
3745 | } |
3746 | #endif /* CONFIG_HT_IRQ */ | |
3747 | ||
03b48632 | 3748 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3749 | /* |
3750 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3751 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3752 | */ | |
3753 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3754 | unsigned long mmr_offset) | |
3755 | { | |
22f65d31 | 3756 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3757 | struct irq_cfg *cfg; |
3758 | int mmr_pnode; | |
3759 | unsigned long mmr_value; | |
3760 | struct uv_IO_APIC_route_entry *entry; | |
3761 | unsigned long flags; | |
3762 | int err; | |
3763 | ||
1cbac972 CG |
3764 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3765 | ||
3145e941 YL |
3766 | cfg = irq_cfg(irq); |
3767 | ||
e7986739 | 3768 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3769 | if (err != 0) |
3770 | return err; | |
3771 | ||
3772 | spin_lock_irqsave(&vector_lock, flags); | |
3773 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3774 | irq_name); | |
3775 | spin_unlock_irqrestore(&vector_lock, flags); | |
3776 | ||
4173a0e7 DN |
3777 | mmr_value = 0; |
3778 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3779 | entry->vector = cfg->vector; |
3780 | entry->delivery_mode = apic->irq_delivery_mode; | |
3781 | entry->dest_mode = apic->irq_dest_mode; | |
3782 | entry->polarity = 0; | |
3783 | entry->trigger = 0; | |
3784 | entry->mask = 0; | |
3785 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3786 | |
3787 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3788 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3789 | ||
3790 | return irq; | |
3791 | } | |
3792 | ||
3793 | /* | |
3794 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3795 | * longer allowed to be sent. | |
3796 | */ | |
3797 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3798 | { | |
3799 | unsigned long mmr_value; | |
3800 | struct uv_IO_APIC_route_entry *entry; | |
3801 | int mmr_pnode; | |
3802 | ||
1cbac972 CG |
3803 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3804 | ||
4173a0e7 DN |
3805 | mmr_value = 0; |
3806 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3807 | entry->mask = 1; |
3808 | ||
3809 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3810 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3811 | } | |
3812 | #endif /* CONFIG_X86_64 */ | |
3813 | ||
9d6a4d08 YL |
3814 | int __init io_apic_get_redir_entries (int ioapic) |
3815 | { | |
3816 | union IO_APIC_reg_01 reg_01; | |
3817 | unsigned long flags; | |
3818 | ||
3819 | spin_lock_irqsave(&ioapic_lock, flags); | |
3820 | reg_01.raw = io_apic_read(ioapic, 1); | |
3821 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3822 | ||
3823 | return reg_01.bits.entries; | |
3824 | } | |
3825 | ||
be5d5350 | 3826 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3827 | { |
be5d5350 YL |
3828 | int nr = 0; |
3829 | ||
cc6c5006 YL |
3830 | nr = acpi_probe_gsi(); |
3831 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3832 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3833 | } else { |
3834 | /* for acpi=off or acpi is not compiled in */ | |
3835 | int idx; | |
3836 | ||
3837 | nr = 0; | |
3838 | for (idx = 0; idx < nr_ioapics; idx++) | |
3839 | nr += io_apic_get_redir_entries(idx) + 1; | |
3840 | ||
3841 | if (nr > nr_irqs_gsi) | |
3842 | nr_irqs_gsi = nr; | |
3843 | } | |
3844 | ||
3845 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3846 | } |
3847 | ||
4a046d17 YL |
3848 | #ifdef CONFIG_SPARSE_IRQ |
3849 | int __init arch_probe_nr_irqs(void) | |
3850 | { | |
3851 | int nr; | |
3852 | ||
f1ee5548 YL |
3853 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3854 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3855 | |
f1ee5548 YL |
3856 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3857 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3858 | /* | |
3859 | * for MSI and HT dyn irq | |
3860 | */ | |
3861 | nr += nr_irqs_gsi * 16; | |
3862 | #endif | |
3863 | if (nr < nr_irqs) | |
4a046d17 YL |
3864 | nr_irqs = nr; |
3865 | ||
3866 | return 0; | |
3867 | } | |
3868 | #endif | |
3869 | ||
e5198075 YL |
3870 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3871 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3872 | { |
3873 | struct irq_desc *desc; | |
3874 | struct irq_cfg *cfg; | |
3875 | int node; | |
e5198075 YL |
3876 | int ioapic, pin; |
3877 | int trigger, polarity; | |
5ef21837 | 3878 | |
e5198075 | 3879 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3880 | if (!IO_APIC_IRQ(irq)) { |
3881 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3882 | ioapic); | |
3883 | return -EINVAL; | |
3884 | } | |
3885 | ||
3886 | if (dev) | |
3887 | node = dev_to_node(dev); | |
3888 | else | |
3889 | node = cpu_to_node(boot_cpu_id); | |
3890 | ||
3891 | desc = irq_to_desc_alloc_node(irq, node); | |
3892 | if (!desc) { | |
3893 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3894 | return 0; | |
3895 | } | |
3896 | ||
e5198075 YL |
3897 | pin = irq_attr->ioapic_pin; |
3898 | trigger = irq_attr->trigger; | |
3899 | polarity = irq_attr->polarity; | |
3900 | ||
5ef21837 YL |
3901 | /* |
3902 | * IRQs < 16 are already in the irq_2_pin[] map | |
3903 | */ | |
3904 | if (irq >= NR_IRQS_LEGACY) { | |
3905 | cfg = desc->chip_data; | |
3906 | add_pin_to_irq_node(cfg, node, ioapic, pin); | |
3907 | } | |
3908 | ||
e5198075 | 3909 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3910 | |
3911 | return 0; | |
3912 | } | |
3913 | ||
e5198075 YL |
3914 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3915 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3916 | { |
e5198075 | 3917 | int ioapic, pin; |
5ef21837 YL |
3918 | /* |
3919 | * Avoid pin reprogramming. PRTs typically include entries | |
3920 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3921 | * we only program the IOAPIC on the first. | |
3922 | */ | |
e5198075 YL |
3923 | ioapic = irq_attr->ioapic; |
3924 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3925 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3926 | pr_debug("Pin %d-%d already programmed\n", | |
3927 | mp_ioapics[ioapic].apicid, pin); | |
3928 | return 0; | |
3929 | } | |
3930 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3931 | ||
e5198075 | 3932 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3933 | } |
3934 | ||
1da177e4 | 3935 | /* -------------------------------------------------------------------------- |
54168ed7 | 3936 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3937 | -------------------------------------------------------------------------- */ |
3938 | ||
888ba6c6 | 3939 | #ifdef CONFIG_ACPI |
1da177e4 | 3940 | |
54168ed7 | 3941 | #ifdef CONFIG_X86_32 |
36062448 | 3942 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3943 | { |
3944 | union IO_APIC_reg_00 reg_00; | |
3945 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3946 | physid_mask_t tmp; | |
3947 | unsigned long flags; | |
3948 | int i = 0; | |
3949 | ||
3950 | /* | |
36062448 PC |
3951 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3952 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3953 | * supports up to 16 on one shared APIC bus. |
36062448 | 3954 | * |
1da177e4 LT |
3955 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3956 | * advantage of new APIC bus architecture. | |
3957 | */ | |
3958 | ||
3959 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3960 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3961 | |
3962 | spin_lock_irqsave(&ioapic_lock, flags); | |
3963 | reg_00.raw = io_apic_read(ioapic, 0); | |
3964 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3965 | ||
3966 | if (apic_id >= get_physical_broadcast()) { | |
3967 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3968 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3969 | apic_id = reg_00.bits.ID; | |
3970 | } | |
3971 | ||
3972 | /* | |
36062448 | 3973 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3974 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3975 | */ | |
d1d7cae8 | 3976 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3977 | |
3978 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3979 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3980 | break; |
3981 | } | |
3982 | ||
3983 | if (i == get_physical_broadcast()) | |
3984 | panic("Max apic_id exceeded!\n"); | |
3985 | ||
3986 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3987 | "trying %d\n", ioapic, apic_id, i); | |
3988 | ||
3989 | apic_id = i; | |
36062448 | 3990 | } |
1da177e4 | 3991 | |
8058714a | 3992 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3993 | physids_or(apic_id_map, apic_id_map, tmp); |
3994 | ||
3995 | if (reg_00.bits.ID != apic_id) { | |
3996 | reg_00.bits.ID = apic_id; | |
3997 | ||
3998 | spin_lock_irqsave(&ioapic_lock, flags); | |
3999 | io_apic_write(ioapic, 0, reg_00.raw); | |
4000 | reg_00.raw = io_apic_read(ioapic, 0); | |
4001 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4002 | ||
4003 | /* Sanity check */ | |
6070f9ec AD |
4004 | if (reg_00.bits.ID != apic_id) { |
4005 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4006 | return -1; | |
4007 | } | |
1da177e4 LT |
4008 | } |
4009 | ||
4010 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4011 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4012 | ||
4013 | return apic_id; | |
4014 | } | |
4015 | ||
36062448 | 4016 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4017 | { |
4018 | union IO_APIC_reg_01 reg_01; | |
4019 | unsigned long flags; | |
4020 | ||
4021 | spin_lock_irqsave(&ioapic_lock, flags); | |
4022 | reg_01.raw = io_apic_read(ioapic, 1); | |
4023 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4024 | ||
4025 | return reg_01.bits.version; | |
4026 | } | |
54168ed7 | 4027 | #endif |
1da177e4 | 4028 | |
61fd47e0 SL |
4029 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4030 | { | |
4031 | int i; | |
4032 | ||
4033 | if (skip_ioapic_setup) | |
4034 | return -1; | |
4035 | ||
4036 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4037 | if (mp_irqs[i].irqtype == mp_INT && |
4038 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4039 | break; |
4040 | if (i >= mp_irq_entries) | |
4041 | return -1; | |
4042 | ||
4043 | *trigger = irq_trigger(i); | |
4044 | *polarity = irq_polarity(i); | |
4045 | return 0; | |
4046 | } | |
4047 | ||
888ba6c6 | 4048 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4049 | |
497c9a19 YL |
4050 | /* |
4051 | * This function currently is only a helper for the i386 smp boot process where | |
4052 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4053 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4054 | */ |
4055 | #ifdef CONFIG_SMP | |
4056 | void __init setup_ioapic_dest(void) | |
4057 | { | |
b9c61b70 | 4058 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4059 | struct irq_desc *desc; |
22f65d31 | 4060 | const struct cpumask *mask; |
497c9a19 YL |
4061 | |
4062 | if (skip_ioapic_setup == 1) | |
4063 | return; | |
4064 | ||
b9c61b70 YL |
4065 | #ifdef CONFIG_ACPI |
4066 | if (!acpi_disabled && acpi_ioapic) { | |
4067 | ioapic = mp_find_ioapic(0); | |
4068 | if (ioapic < 0) | |
4069 | ioapic = 0; | |
4070 | } | |
4071 | #endif | |
6c2e9403 | 4072 | |
b9c61b70 YL |
4073 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4074 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4075 | if (irq_entry == -1) | |
4076 | continue; | |
4077 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4078 | |
b9c61b70 | 4079 | desc = irq_to_desc(irq); |
6c2e9403 | 4080 | |
b9c61b70 YL |
4081 | /* |
4082 | * Honour affinities which have been set in early boot | |
4083 | */ | |
4084 | if (desc->status & | |
4085 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4086 | mask = desc->affinity; | |
4087 | else | |
4088 | mask = apic->target_cpus(); | |
497c9a19 | 4089 | |
b9c61b70 YL |
4090 | if (intr_remapping_enabled) |
4091 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4092 | else | |
4093 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4094 | } |
b9c61b70 | 4095 | |
497c9a19 YL |
4096 | } |
4097 | #endif | |
4098 | ||
54168ed7 IM |
4099 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4100 | ||
4101 | static struct resource *ioapic_resources; | |
4102 | ||
4103 | static struct resource * __init ioapic_setup_resources(void) | |
4104 | { | |
4105 | unsigned long n; | |
4106 | struct resource *res; | |
4107 | char *mem; | |
4108 | int i; | |
4109 | ||
4110 | if (nr_ioapics <= 0) | |
4111 | return NULL; | |
4112 | ||
4113 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4114 | n *= nr_ioapics; | |
4115 | ||
4116 | mem = alloc_bootmem(n); | |
4117 | res = (void *)mem; | |
4118 | ||
4119 | if (mem != NULL) { | |
4120 | mem += sizeof(struct resource) * nr_ioapics; | |
4121 | ||
4122 | for (i = 0; i < nr_ioapics; i++) { | |
4123 | res[i].name = mem; | |
4124 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4125 | sprintf(mem, "IOAPIC %u", i); | |
4126 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4127 | } | |
4128 | } | |
4129 | ||
4130 | ioapic_resources = res; | |
4131 | ||
4132 | return res; | |
4133 | } | |
54168ed7 | 4134 | |
f3294a33 YL |
4135 | void __init ioapic_init_mappings(void) |
4136 | { | |
4137 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4138 | struct resource *ioapic_res; |
d6c88a50 | 4139 | int i; |
f3294a33 | 4140 | |
54168ed7 | 4141 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4142 | for (i = 0; i < nr_ioapics; i++) { |
4143 | if (smp_found_config) { | |
b5ba7e6d | 4144 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4145 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4146 | if (!ioapic_phys) { |
4147 | printk(KERN_ERR | |
4148 | "WARNING: bogus zero IO-APIC " | |
4149 | "address found in MPTABLE, " | |
4150 | "disabling IO/APIC support!\n"); | |
4151 | smp_found_config = 0; | |
4152 | skip_ioapic_setup = 1; | |
4153 | goto fake_ioapic_page; | |
4154 | } | |
54168ed7 | 4155 | #endif |
f3294a33 | 4156 | } else { |
54168ed7 | 4157 | #ifdef CONFIG_X86_32 |
f3294a33 | 4158 | fake_ioapic_page: |
54168ed7 | 4159 | #endif |
f3294a33 | 4160 | ioapic_phys = (unsigned long) |
54168ed7 | 4161 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4162 | ioapic_phys = __pa(ioapic_phys); |
4163 | } | |
4164 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4165 | apic_printk(APIC_VERBOSE, |
4166 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4167 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4168 | idx++; |
54168ed7 | 4169 | |
54168ed7 IM |
4170 | if (ioapic_res != NULL) { |
4171 | ioapic_res->start = ioapic_phys; | |
4172 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4173 | ioapic_res++; | |
4174 | } | |
f3294a33 YL |
4175 | } |
4176 | } | |
4177 | ||
54168ed7 IM |
4178 | static int __init ioapic_insert_resources(void) |
4179 | { | |
4180 | int i; | |
4181 | struct resource *r = ioapic_resources; | |
4182 | ||
4183 | if (!r) { | |
04c93ce4 BZ |
4184 | if (nr_ioapics > 0) { |
4185 | printk(KERN_ERR | |
4186 | "IO APIC resources couldn't be allocated.\n"); | |
4187 | return -1; | |
4188 | } | |
4189 | return 0; | |
54168ed7 IM |
4190 | } |
4191 | ||
4192 | for (i = 0; i < nr_ioapics; i++) { | |
4193 | insert_resource(&iomem_resource, r); | |
4194 | r++; | |
4195 | } | |
4196 | ||
4197 | return 0; | |
4198 | } | |
4199 | ||
4200 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4201 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4202 | late_initcall(ioapic_insert_resources); |