]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
5777372a EB |
92 | /* The last gsi number used */ |
93 | u32 gsi_end; | |
94 | ||
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 165 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
193 | cfg = desc->chip_data; | |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
0b8f1efa YL |
222 | cfg = desc->chip_data; |
223 | if (!cfg) { | |
85ac16d0 | 224 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
225 | if (!desc->chip_data) { |
226 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
227 | BUG_ON(1); | |
228 | } | |
229 | } | |
1da177e4 | 230 | |
13a0c3c2 | 231 | return 0; |
0b8f1efa | 232 | } |
0f978f45 | 233 | |
fcef5911 | 234 | /* for move_irq_desc */ |
48a1b10a | 235 | static void |
85ac16d0 | 236 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 237 | { |
48a1b10a YL |
238 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
239 | ||
240 | cfg->irq_2_pin = NULL; | |
241 | old_entry = old_cfg->irq_2_pin; | |
242 | if (!old_entry) | |
243 | return; | |
0f978f45 | 244 | |
85ac16d0 | 245 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
246 | if (!entry) |
247 | return; | |
0f978f45 | 248 | |
48a1b10a YL |
249 | entry->apic = old_entry->apic; |
250 | entry->pin = old_entry->pin; | |
251 | head = entry; | |
252 | tail = entry; | |
253 | old_entry = old_entry->next; | |
254 | while (old_entry) { | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) { |
257 | entry = head; | |
258 | while (entry) { | |
259 | head = entry->next; | |
260 | kfree(entry); | |
261 | entry = head; | |
262 | } | |
263 | /* still use the old one */ | |
264 | return; | |
265 | } | |
266 | entry->apic = old_entry->apic; | |
267 | entry->pin = old_entry->pin; | |
268 | tail->next = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | } | |
0f978f45 | 272 | |
48a1b10a YL |
273 | tail->next = NULL; |
274 | cfg->irq_2_pin = head; | |
0f978f45 | 275 | } |
0f978f45 | 276 | |
48a1b10a | 277 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 278 | { |
48a1b10a | 279 | struct irq_pin_list *entry, *next; |
0f978f45 | 280 | |
48a1b10a YL |
281 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
282 | return; | |
301e6190 | 283 | |
48a1b10a | 284 | entry = old_cfg->irq_2_pin; |
0f978f45 | 285 | |
48a1b10a YL |
286 | while (entry) { |
287 | next = entry->next; | |
288 | kfree(entry); | |
289 | entry = next; | |
290 | } | |
291 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 295 | struct irq_desc *desc, int node) |
0f978f45 | 296 | { |
48a1b10a YL |
297 | struct irq_cfg *cfg; |
298 | struct irq_cfg *old_cfg; | |
0f978f45 | 299 | |
85ac16d0 | 300 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 301 | |
48a1b10a YL |
302 | if (!cfg) |
303 | return; | |
304 | ||
305 | desc->chip_data = cfg; | |
306 | ||
307 | old_cfg = old_desc->chip_data; | |
308 | ||
309 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
310 | ||
85ac16d0 | 311 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 312 | } |
1da177e4 | 313 | |
48a1b10a YL |
314 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
315 | { | |
316 | kfree(old_cfg); | |
317 | } | |
318 | ||
319 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
320 | { | |
321 | struct irq_cfg *old_cfg, *cfg; | |
322 | ||
323 | old_cfg = old_desc->chip_data; | |
324 | cfg = desc->chip_data; | |
325 | ||
326 | if (old_cfg == cfg) | |
327 | return; | |
328 | ||
329 | if (old_cfg) { | |
330 | free_irq_2_pin(old_cfg, cfg); | |
331 | free_irq_cfg(old_cfg); | |
332 | old_desc->chip_data = NULL; | |
333 | } | |
334 | } | |
fcef5911 | 335 | /* end for move_irq_desc */ |
48a1b10a | 336 | |
0b8f1efa | 337 | #else |
9338ad6f | 338 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
339 | { |
340 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 341 | } |
1da177e4 | 342 | |
0b8f1efa YL |
343 | #endif |
344 | ||
130fe05d LT |
345 | struct io_apic { |
346 | unsigned int index; | |
347 | unsigned int unused[3]; | |
348 | unsigned int data; | |
0280f7c4 SS |
349 | unsigned int unused2[11]; |
350 | unsigned int eoi; | |
130fe05d LT |
351 | }; |
352 | ||
353 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
354 | { | |
355 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 356 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
357 | } |
358 | ||
0280f7c4 SS |
359 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
360 | { | |
361 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
362 | writel(vector, &io_apic->eoi); | |
363 | } | |
364 | ||
130fe05d LT |
365 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(reg, &io_apic->index); | |
369 | return readl(&io_apic->data); | |
370 | } | |
371 | ||
372 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
373 | { | |
374 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
375 | writel(reg, &io_apic->index); | |
376 | writel(value, &io_apic->data); | |
377 | } | |
378 | ||
379 | /* | |
380 | * Re-write a value: to be used for read-modify-write | |
381 | * cycles where the read already set up the index register. | |
382 | * | |
383 | * Older SiS APIC requires we rewrite the index register | |
384 | */ | |
385 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
386 | { | |
54168ed7 | 387 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
388 | |
389 | if (sis_apic_bug) | |
390 | writel(reg, &io_apic->index); | |
130fe05d LT |
391 | writel(value, &io_apic->data); |
392 | } | |
393 | ||
3145e941 | 394 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
395 | { |
396 | struct irq_pin_list *entry; | |
397 | unsigned long flags; | |
047c8fdb | 398 | |
dade7716 | 399 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 400 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
401 | unsigned int reg; |
402 | int pin; | |
403 | ||
047c8fdb YL |
404 | pin = entry->pin; |
405 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
406 | /* Is the remote IRR bit set? */ | |
407 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 408 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
409 | return true; |
410 | } | |
047c8fdb | 411 | } |
dade7716 | 412 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
413 | |
414 | return false; | |
415 | } | |
047c8fdb | 416 | |
cf4c6a2f AK |
417 | union entry_union { |
418 | struct { u32 w1, w2; }; | |
419 | struct IO_APIC_route_entry entry; | |
420 | }; | |
421 | ||
422 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
423 | { | |
424 | union entry_union eu; | |
425 | unsigned long flags; | |
dade7716 | 426 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
428 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
430 | return eu.entry; |
431 | } | |
432 | ||
f9dadfa7 LT |
433 | /* |
434 | * When we write a new IO APIC routing entry, we need to write the high | |
435 | * word first! If the mask bit in the low word is clear, we will enable | |
436 | * the interrupt, and we need to make sure the entry is fully populated | |
437 | * before that happens. | |
438 | */ | |
d15512f4 AK |
439 | static void |
440 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 441 | { |
50a8d4d2 F |
442 | union entry_union eu = {{0, 0}}; |
443 | ||
cf4c6a2f | 444 | eu.entry = e; |
f9dadfa7 LT |
445 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
446 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
447 | } |
448 | ||
ca97ab90 | 449 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
450 | { |
451 | unsigned long flags; | |
dade7716 | 452 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 453 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 454 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
455 | } |
456 | ||
457 | /* | |
458 | * When we mask an IO APIC routing entry, we need to write the low | |
459 | * word first, in order to set the mask bit before we change the | |
460 | * high bits! | |
461 | */ | |
462 | static void ioapic_mask_entry(int apic, int pin) | |
463 | { | |
464 | unsigned long flags; | |
465 | union entry_union eu = { .entry.mask = 1 }; | |
466 | ||
dade7716 | 467 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
468 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
469 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 470 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
471 | } |
472 | ||
1da177e4 LT |
473 | /* |
474 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
475 | * shared ISA-space IRQs, so we have to support them. We are super | |
476 | * fast in the common case, and fast for shared ISA-space IRQs. | |
477 | */ | |
f3d1915a CG |
478 | static int |
479 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 480 | { |
2977fb3f | 481 | struct irq_pin_list **last, *entry; |
0f978f45 | 482 | |
2977fb3f CG |
483 | /* don't allow duplicates */ |
484 | last = &cfg->irq_2_pin; | |
485 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 486 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 487 | return 0; |
2977fb3f | 488 | last = &entry->next; |
1da177e4 | 489 | } |
0f978f45 | 490 | |
875e68ec | 491 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 492 | if (!entry) { |
f3d1915a CG |
493 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
494 | node, apic, pin); | |
495 | return -ENOMEM; | |
a7428cd2 | 496 | } |
1da177e4 LT |
497 | entry->apic = apic; |
498 | entry->pin = pin; | |
875e68ec | 499 | |
2977fb3f | 500 | *last = entry; |
f3d1915a CG |
501 | return 0; |
502 | } | |
503 | ||
504 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
505 | { | |
506 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
507 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
508 | } |
509 | ||
510 | /* | |
511 | * Reroute an IRQ to a different pin. | |
512 | */ | |
85ac16d0 | 513 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
514 | int oldapic, int oldpin, |
515 | int newapic, int newpin) | |
1da177e4 | 516 | { |
535b6429 | 517 | struct irq_pin_list *entry; |
1da177e4 | 518 | |
2977fb3f | 519 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
520 | if (entry->apic == oldapic && entry->pin == oldpin) { |
521 | entry->apic = newapic; | |
522 | entry->pin = newpin; | |
0f978f45 | 523 | /* every one is different, right? */ |
4eea6fff | 524 | return; |
0f978f45 | 525 | } |
1da177e4 | 526 | } |
0f978f45 | 527 | |
4eea6fff JF |
528 | /* old apic/pin didn't exist, so just add new ones */ |
529 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
530 | } |
531 | ||
c29d9db3 SS |
532 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
533 | int mask_and, int mask_or, | |
534 | void (*final)(struct irq_pin_list *entry)) | |
535 | { | |
536 | unsigned int reg, pin; | |
537 | ||
538 | pin = entry->pin; | |
539 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
540 | reg &= mask_and; | |
541 | reg |= mask_or; | |
542 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
543 | if (final) | |
544 | final(entry); | |
545 | } | |
546 | ||
2f210deb JF |
547 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
548 | int mask_and, int mask_or, | |
549 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 550 | { |
87783be4 | 551 | struct irq_pin_list *entry; |
047c8fdb | 552 | |
c29d9db3 SS |
553 | for_each_irq_pin(entry, cfg->irq_2_pin) |
554 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
555 | } | |
556 | ||
557 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
558 | { | |
559 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
560 | IO_APIC_REDIR_MASKED, NULL); | |
561 | } | |
562 | ||
563 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
564 | { | |
565 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
566 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 567 | } |
047c8fdb | 568 | |
3145e941 | 569 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 570 | { |
3145e941 | 571 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 572 | } |
047c8fdb | 573 | |
7f3e632f | 574 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 575 | { |
87783be4 CG |
576 | /* |
577 | * Synchronize the IO-APIC and the CPU by doing | |
578 | * a dummy read from the IO-APIC | |
579 | */ | |
580 | struct io_apic __iomem *io_apic; | |
581 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 582 | readl(&io_apic->data); |
1da177e4 LT |
583 | } |
584 | ||
3145e941 | 585 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 586 | { |
3145e941 | 587 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 588 | } |
1da177e4 | 589 | |
3145e941 | 590 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 591 | { |
3145e941 | 592 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
593 | unsigned long flags; |
594 | ||
3145e941 YL |
595 | BUG_ON(!cfg); |
596 | ||
dade7716 | 597 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 598 | __mask_IO_APIC_irq(cfg); |
dade7716 | 599 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
600 | } |
601 | ||
3145e941 | 602 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 603 | { |
3145e941 | 604 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
605 | unsigned long flags; |
606 | ||
dade7716 | 607 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 608 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 609 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
610 | } |
611 | ||
3145e941 YL |
612 | static void mask_IO_APIC_irq(unsigned int irq) |
613 | { | |
614 | struct irq_desc *desc = irq_to_desc(irq); | |
615 | ||
616 | mask_IO_APIC_irq_desc(desc); | |
617 | } | |
618 | static void unmask_IO_APIC_irq(unsigned int irq) | |
619 | { | |
620 | struct irq_desc *desc = irq_to_desc(irq); | |
621 | ||
622 | unmask_IO_APIC_irq_desc(desc); | |
623 | } | |
624 | ||
1da177e4 LT |
625 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
626 | { | |
627 | struct IO_APIC_route_entry entry; | |
36062448 | 628 | |
1da177e4 | 629 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 630 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
631 | if (entry.delivery_mode == dest_SMI) |
632 | return; | |
1da177e4 LT |
633 | /* |
634 | * Disable it in the IO-APIC irq-routing table: | |
635 | */ | |
f9dadfa7 | 636 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
637 | } |
638 | ||
54168ed7 | 639 | static void clear_IO_APIC (void) |
1da177e4 LT |
640 | { |
641 | int apic, pin; | |
642 | ||
643 | for (apic = 0; apic < nr_ioapics; apic++) | |
644 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
645 | clear_IO_APIC_pin(apic, pin); | |
646 | } | |
647 | ||
54168ed7 | 648 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
649 | /* |
650 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
651 | * specific CPU-side IRQs. | |
652 | */ | |
653 | ||
654 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
655 | static int pirq_entries[MAX_PIRQS] = { |
656 | [0 ... MAX_PIRQS - 1] = -1 | |
657 | }; | |
1da177e4 | 658 | |
1da177e4 LT |
659 | static int __init ioapic_pirq_setup(char *str) |
660 | { | |
661 | int i, max; | |
662 | int ints[MAX_PIRQS+1]; | |
663 | ||
664 | get_options(str, ARRAY_SIZE(ints), ints); | |
665 | ||
1da177e4 LT |
666 | apic_printk(APIC_VERBOSE, KERN_INFO |
667 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
668 | max = MAX_PIRQS; | |
669 | if (ints[0] < MAX_PIRQS) | |
670 | max = ints[0]; | |
671 | ||
672 | for (i = 0; i < max; i++) { | |
673 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
674 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
675 | /* | |
676 | * PIRQs are mapped upside down, usually. | |
677 | */ | |
678 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
679 | } | |
680 | return 1; | |
681 | } | |
682 | ||
683 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
684 | #endif /* CONFIG_X86_32 */ |
685 | ||
b24696bc FY |
686 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
687 | { | |
688 | int apic; | |
689 | struct IO_APIC_route_entry **ioapic_entries; | |
690 | ||
691 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
692 | GFP_ATOMIC); | |
693 | if (!ioapic_entries) | |
694 | return 0; | |
695 | ||
696 | for (apic = 0; apic < nr_ioapics; apic++) { | |
697 | ioapic_entries[apic] = | |
698 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
699 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
700 | if (!ioapic_entries[apic]) | |
701 | goto nomem; | |
702 | } | |
703 | ||
704 | return ioapic_entries; | |
705 | ||
706 | nomem: | |
707 | while (--apic >= 0) | |
708 | kfree(ioapic_entries[apic]); | |
709 | kfree(ioapic_entries); | |
710 | ||
711 | return 0; | |
712 | } | |
54168ed7 IM |
713 | |
714 | /* | |
05c3dc2c | 715 | * Saves all the IO-APIC RTE's |
54168ed7 | 716 | */ |
b24696bc | 717 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 718 | { |
54168ed7 IM |
719 | int apic, pin; |
720 | ||
b24696bc FY |
721 | if (!ioapic_entries) |
722 | return -ENOMEM; | |
54168ed7 IM |
723 | |
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
725 | if (!ioapic_entries[apic]) |
726 | return -ENOMEM; | |
54168ed7 | 727 | |
05c3dc2c | 728 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 729 | ioapic_entries[apic][pin] = |
54168ed7 | 730 | ioapic_read_entry(apic, pin); |
b24696bc | 731 | } |
5ffa4eb2 | 732 | |
54168ed7 IM |
733 | return 0; |
734 | } | |
735 | ||
b24696bc FY |
736 | /* |
737 | * Mask all IO APIC entries. | |
738 | */ | |
739 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
740 | { |
741 | int apic, pin; | |
742 | ||
b24696bc FY |
743 | if (!ioapic_entries) |
744 | return; | |
745 | ||
05c3dc2c | 746 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 747 | if (!ioapic_entries[apic]) |
05c3dc2c | 748 | break; |
b24696bc | 749 | |
05c3dc2c SS |
750 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
751 | struct IO_APIC_route_entry entry; | |
752 | ||
b24696bc | 753 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
754 | if (!entry.mask) { |
755 | entry.mask = 1; | |
756 | ioapic_write_entry(apic, pin, entry); | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
b24696bc FY |
762 | /* |
763 | * Restore IO APIC entries which was saved in ioapic_entries. | |
764 | */ | |
765 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
766 | { |
767 | int apic, pin; | |
768 | ||
b24696bc FY |
769 | if (!ioapic_entries) |
770 | return -ENOMEM; | |
771 | ||
5ffa4eb2 | 772 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
773 | if (!ioapic_entries[apic]) |
774 | return -ENOMEM; | |
775 | ||
54168ed7 IM |
776 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
777 | ioapic_write_entry(apic, pin, | |
b24696bc | 778 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 779 | } |
b24696bc | 780 | return 0; |
54168ed7 IM |
781 | } |
782 | ||
b24696bc FY |
783 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
784 | { | |
785 | int apic; | |
786 | ||
787 | for (apic = 0; apic < nr_ioapics; apic++) | |
788 | kfree(ioapic_entries[apic]); | |
789 | ||
790 | kfree(ioapic_entries); | |
54168ed7 | 791 | } |
1da177e4 LT |
792 | |
793 | /* | |
794 | * Find the IRQ entry number of a certain pin. | |
795 | */ | |
796 | static int find_irq_entry(int apic, int pin, int type) | |
797 | { | |
798 | int i; | |
799 | ||
800 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
801 | if (mp_irqs[i].irqtype == type && |
802 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
803 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
804 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
805 | return i; |
806 | ||
807 | return -1; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Find the pin to which IRQ[irq] (ISA) is connected | |
812 | */ | |
fcfd636a | 813 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
814 | { |
815 | int i; | |
816 | ||
817 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 818 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 819 | |
d27e2b8e | 820 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
821 | (mp_irqs[i].irqtype == type) && |
822 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 823 | |
c2c21745 | 824 | return mp_irqs[i].dstirq; |
1da177e4 LT |
825 | } |
826 | return -1; | |
827 | } | |
828 | ||
fcfd636a EB |
829 | static int __init find_isa_irq_apic(int irq, int type) |
830 | { | |
831 | int i; | |
832 | ||
833 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 834 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 835 | |
73b2961b | 836 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
837 | (mp_irqs[i].irqtype == type) && |
838 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
839 | break; |
840 | } | |
841 | if (i < mp_irq_entries) { | |
842 | int apic; | |
54168ed7 | 843 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 844 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
845 | return apic; |
846 | } | |
847 | } | |
848 | ||
849 | return -1; | |
850 | } | |
851 | ||
c0a282c2 | 852 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
853 | /* |
854 | * EISA Edge/Level control register, ELCR | |
855 | */ | |
856 | static int EISA_ELCR(unsigned int irq) | |
857 | { | |
b81bb373 | 858 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
859 | unsigned int port = 0x4d0 + (irq >> 3); |
860 | return (inb(port) >> (irq & 7)) & 1; | |
861 | } | |
862 | apic_printk(APIC_VERBOSE, KERN_INFO | |
863 | "Broken MPtable reports ISA irq %d\n", irq); | |
864 | return 0; | |
865 | } | |
54168ed7 | 866 | |
c0a282c2 | 867 | #endif |
1da177e4 | 868 | |
6728801d AS |
869 | /* ISA interrupts are always polarity zero edge triggered, |
870 | * when listed as conforming in the MP table. */ | |
871 | ||
872 | #define default_ISA_trigger(idx) (0) | |
873 | #define default_ISA_polarity(idx) (0) | |
874 | ||
1da177e4 LT |
875 | /* EISA interrupts are always polarity zero and can be edge or level |
876 | * trigger depending on the ELCR value. If an interrupt is listed as | |
877 | * EISA conforming in the MP table, that means its trigger type must | |
878 | * be read in from the ELCR */ | |
879 | ||
c2c21745 | 880 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 881 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
882 | |
883 | /* PCI interrupts are always polarity one level triggered, | |
884 | * when listed as conforming in the MP table. */ | |
885 | ||
886 | #define default_PCI_trigger(idx) (1) | |
887 | #define default_PCI_polarity(idx) (1) | |
888 | ||
889 | /* MCA interrupts are always polarity zero level triggered, | |
890 | * when listed as conforming in the MP table. */ | |
891 | ||
892 | #define default_MCA_trigger(idx) (1) | |
6728801d | 893 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 894 | |
61fd47e0 | 895 | static int MPBIOS_polarity(int idx) |
1da177e4 | 896 | { |
c2c21745 | 897 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
898 | int polarity; |
899 | ||
900 | /* | |
901 | * Determine IRQ line polarity (high active or low active): | |
902 | */ | |
c2c21745 | 903 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 904 | { |
54168ed7 IM |
905 | case 0: /* conforms, ie. bus-type dependent polarity */ |
906 | if (test_bit(bus, mp_bus_not_pci)) | |
907 | polarity = default_ISA_polarity(idx); | |
908 | else | |
909 | polarity = default_PCI_polarity(idx); | |
910 | break; | |
911 | case 1: /* high active */ | |
912 | { | |
913 | polarity = 0; | |
914 | break; | |
915 | } | |
916 | case 2: /* reserved */ | |
917 | { | |
918 | printk(KERN_WARNING "broken BIOS!!\n"); | |
919 | polarity = 1; | |
920 | break; | |
921 | } | |
922 | case 3: /* low active */ | |
923 | { | |
924 | polarity = 1; | |
925 | break; | |
926 | } | |
927 | default: /* invalid */ | |
928 | { | |
929 | printk(KERN_WARNING "broken BIOS!!\n"); | |
930 | polarity = 1; | |
931 | break; | |
932 | } | |
1da177e4 LT |
933 | } |
934 | return polarity; | |
935 | } | |
936 | ||
937 | static int MPBIOS_trigger(int idx) | |
938 | { | |
c2c21745 | 939 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
940 | int trigger; |
941 | ||
942 | /* | |
943 | * Determine IRQ trigger mode (edge or level sensitive): | |
944 | */ | |
c2c21745 | 945 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 946 | { |
54168ed7 IM |
947 | case 0: /* conforms, ie. bus-type dependent */ |
948 | if (test_bit(bus, mp_bus_not_pci)) | |
949 | trigger = default_ISA_trigger(idx); | |
950 | else | |
951 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 952 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
953 | switch (mp_bus_id_to_type[bus]) { |
954 | case MP_BUS_ISA: /* ISA pin */ | |
955 | { | |
956 | /* set before the switch */ | |
957 | break; | |
958 | } | |
959 | case MP_BUS_EISA: /* EISA pin */ | |
960 | { | |
961 | trigger = default_EISA_trigger(idx); | |
962 | break; | |
963 | } | |
964 | case MP_BUS_PCI: /* PCI pin */ | |
965 | { | |
966 | /* set before the switch */ | |
967 | break; | |
968 | } | |
969 | case MP_BUS_MCA: /* MCA pin */ | |
970 | { | |
971 | trigger = default_MCA_trigger(idx); | |
972 | break; | |
973 | } | |
974 | default: | |
975 | { | |
976 | printk(KERN_WARNING "broken BIOS!!\n"); | |
977 | trigger = 1; | |
978 | break; | |
979 | } | |
980 | } | |
981 | #endif | |
1da177e4 | 982 | break; |
54168ed7 | 983 | case 1: /* edge */ |
1da177e4 | 984 | { |
54168ed7 | 985 | trigger = 0; |
1da177e4 LT |
986 | break; |
987 | } | |
54168ed7 | 988 | case 2: /* reserved */ |
1da177e4 | 989 | { |
54168ed7 IM |
990 | printk(KERN_WARNING "broken BIOS!!\n"); |
991 | trigger = 1; | |
1da177e4 LT |
992 | break; |
993 | } | |
54168ed7 | 994 | case 3: /* level */ |
1da177e4 | 995 | { |
54168ed7 | 996 | trigger = 1; |
1da177e4 LT |
997 | break; |
998 | } | |
54168ed7 | 999 | default: /* invalid */ |
1da177e4 LT |
1000 | { |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1002 | trigger = 0; |
1da177e4 LT |
1003 | break; |
1004 | } | |
1005 | } | |
1006 | return trigger; | |
1007 | } | |
1008 | ||
1009 | static inline int irq_polarity(int idx) | |
1010 | { | |
1011 | return MPBIOS_polarity(idx); | |
1012 | } | |
1013 | ||
1014 | static inline int irq_trigger(int idx) | |
1015 | { | |
1016 | return MPBIOS_trigger(idx); | |
1017 | } | |
1018 | ||
efa2559f | 1019 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1020 | static int pin_2_irq(int idx, int apic, int pin) |
1021 | { | |
d464207c | 1022 | int irq; |
c2c21745 | 1023 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1024 | |
1025 | /* | |
1026 | * Debugging check, we are in big trouble if this message pops up! | |
1027 | */ | |
c2c21745 | 1028 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1029 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1030 | ||
54168ed7 | 1031 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1032 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1033 | } else { |
d464207c | 1034 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
d6c88a50 | 1035 | /* |
54168ed7 IM |
1036 | * For MPS mode, so far only needed by ES7000 platform |
1037 | */ | |
d6c88a50 | 1038 | if (ioapic_renumber_irq) |
d464207c EB |
1039 | gsi = ioapic_renumber_irq(apic, gsi); |
1040 | irq = gsi; | |
1da177e4 LT |
1041 | } |
1042 | ||
54168ed7 | 1043 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1044 | /* |
1045 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1046 | */ | |
1047 | if ((pin >= 16) && (pin <= 23)) { | |
1048 | if (pirq_entries[pin-16] != -1) { | |
1049 | if (!pirq_entries[pin-16]) { | |
1050 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1051 | "disabling PIRQ%d\n", pin-16); | |
1052 | } else { | |
1053 | irq = pirq_entries[pin-16]; | |
1054 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1055 | "using PIRQ%d -> IRQ %d\n", | |
1056 | pin-16, irq); | |
1057 | } | |
1058 | } | |
1059 | } | |
54168ed7 IM |
1060 | #endif |
1061 | ||
1da177e4 LT |
1062 | return irq; |
1063 | } | |
1064 | ||
e20c06fd YL |
1065 | /* |
1066 | * Find a specific PCI IRQ entry. | |
1067 | * Not an __init, possibly needed by modules | |
1068 | */ | |
1069 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1070 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1071 | { |
1072 | int apic, i, best_guess = -1; | |
1073 | ||
1074 | apic_printk(APIC_DEBUG, | |
1075 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1076 | bus, slot, pin); | |
1077 | if (test_bit(bus, mp_bus_not_pci)) { | |
1078 | apic_printk(APIC_VERBOSE, | |
1079 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1080 | return -1; | |
1081 | } | |
1082 | for (i = 0; i < mp_irq_entries; i++) { | |
1083 | int lbus = mp_irqs[i].srcbus; | |
1084 | ||
1085 | for (apic = 0; apic < nr_ioapics; apic++) | |
1086 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1087 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1088 | break; | |
1089 | ||
1090 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1091 | !mp_irqs[i].irqtype && | |
1092 | (bus == lbus) && | |
1093 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1094 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1095 | ||
1096 | if (!(apic || IO_APIC_IRQ(irq))) | |
1097 | continue; | |
1098 | ||
1099 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1100 | set_io_apic_irq_attr(irq_attr, apic, |
1101 | mp_irqs[i].dstirq, | |
1102 | irq_trigger(i), | |
1103 | irq_polarity(i)); | |
e20c06fd YL |
1104 | return irq; |
1105 | } | |
1106 | /* | |
1107 | * Use the first all-but-pin matching entry as a | |
1108 | * best-guess fuzzy result for broken mptables. | |
1109 | */ | |
1110 | if (best_guess < 0) { | |
e5198075 YL |
1111 | set_io_apic_irq_attr(irq_attr, apic, |
1112 | mp_irqs[i].dstirq, | |
1113 | irq_trigger(i), | |
1114 | irq_polarity(i)); | |
e20c06fd YL |
1115 | best_guess = irq; |
1116 | } | |
1117 | } | |
1118 | } | |
1119 | return best_guess; | |
1120 | } | |
1121 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1122 | ||
497c9a19 YL |
1123 | void lock_vector_lock(void) |
1124 | { | |
1125 | /* Used to the online set of cpus does not change | |
1126 | * during assign_irq_vector. | |
1127 | */ | |
dade7716 | 1128 | raw_spin_lock(&vector_lock); |
497c9a19 | 1129 | } |
1da177e4 | 1130 | |
497c9a19 | 1131 | void unlock_vector_lock(void) |
1da177e4 | 1132 | { |
dade7716 | 1133 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1134 | } |
1da177e4 | 1135 | |
e7986739 MT |
1136 | static int |
1137 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1138 | { |
047c8fdb YL |
1139 | /* |
1140 | * NOTE! The local APIC isn't very good at handling | |
1141 | * multiple interrupts at the same interrupt level. | |
1142 | * As the interrupt level is determined by taking the | |
1143 | * vector number and shifting that right by 4, we | |
1144 | * want to spread these out a bit so that they don't | |
1145 | * all fall in the same interrupt level. | |
1146 | * | |
1147 | * Also, we've got to be careful not to trash gate | |
1148 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1149 | */ | |
6579b474 | 1150 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1151 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1152 | unsigned int old_vector; |
22f65d31 MT |
1153 | int cpu, err; |
1154 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1155 | |
23359a88 | 1156 | if (cfg->move_in_progress) |
54168ed7 | 1157 | return -EBUSY; |
0a1ad60d | 1158 | |
22f65d31 MT |
1159 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1160 | return -ENOMEM; | |
ace80ab7 | 1161 | |
54168ed7 IM |
1162 | old_vector = cfg->vector; |
1163 | if (old_vector) { | |
22f65d31 MT |
1164 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1165 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1166 | if (!cpumask_empty(tmp_mask)) { | |
1167 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1168 | return 0; |
22f65d31 | 1169 | } |
54168ed7 | 1170 | } |
497c9a19 | 1171 | |
e7986739 | 1172 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1173 | err = -ENOSPC; |
1174 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1175 | int new_cpu; |
1176 | int vector, offset; | |
497c9a19 | 1177 | |
e2d40b18 | 1178 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1179 | |
54168ed7 IM |
1180 | vector = current_vector; |
1181 | offset = current_offset; | |
497c9a19 | 1182 | next: |
54168ed7 IM |
1183 | vector += 8; |
1184 | if (vector >= first_system_vector) { | |
e7986739 | 1185 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1186 | offset = (offset + 1) % 8; |
6579b474 | 1187 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1188 | } |
1189 | if (unlikely(current_vector == vector)) | |
1190 | continue; | |
b77b881f YL |
1191 | |
1192 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1193 | goto next; |
b77b881f | 1194 | |
22f65d31 | 1195 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1196 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1197 | goto next; | |
1198 | /* Found one! */ | |
1199 | current_vector = vector; | |
1200 | current_offset = offset; | |
1201 | if (old_vector) { | |
1202 | cfg->move_in_progress = 1; | |
22f65d31 | 1203 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1204 | } |
22f65d31 | 1205 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1206 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1207 | cfg->vector = vector; | |
22f65d31 MT |
1208 | cpumask_copy(cfg->domain, tmp_mask); |
1209 | err = 0; | |
1210 | break; | |
54168ed7 | 1211 | } |
22f65d31 MT |
1212 | free_cpumask_var(tmp_mask); |
1213 | return err; | |
497c9a19 YL |
1214 | } |
1215 | ||
9338ad6f | 1216 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1217 | { |
1218 | int err; | |
ace80ab7 | 1219 | unsigned long flags; |
ace80ab7 | 1220 | |
dade7716 | 1221 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1222 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1223 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1224 | return err; |
1225 | } | |
1226 | ||
3145e941 | 1227 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1228 | { |
497c9a19 YL |
1229 | int cpu, vector; |
1230 | ||
497c9a19 YL |
1231 | BUG_ON(!cfg->vector); |
1232 | ||
1233 | vector = cfg->vector; | |
22f65d31 | 1234 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1235 | per_cpu(vector_irq, cpu)[vector] = -1; |
1236 | ||
1237 | cfg->vector = 0; | |
22f65d31 | 1238 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1239 | |
1240 | if (likely(!cfg->move_in_progress)) | |
1241 | return; | |
22f65d31 | 1242 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1243 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1244 | vector++) { | |
1245 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1246 | continue; | |
1247 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1248 | break; | |
1249 | } | |
1250 | } | |
1251 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1252 | } |
1253 | ||
1254 | void __setup_vector_irq(int cpu) | |
1255 | { | |
1256 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1257 | int irq, vector; |
1258 | struct irq_cfg *cfg; | |
0b8f1efa | 1259 | struct irq_desc *desc; |
497c9a19 | 1260 | |
9d133e5d SS |
1261 | /* |
1262 | * vector_lock will make sure that we don't run into irq vector | |
1263 | * assignments that might be happening on another cpu in parallel, | |
1264 | * while we setup our initial vector to irq mappings. | |
1265 | */ | |
dade7716 | 1266 | raw_spin_lock(&vector_lock); |
497c9a19 | 1267 | /* Mark the inuse vectors */ |
0b8f1efa | 1268 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1269 | cfg = desc->chip_data; |
36e9e1ea SS |
1270 | |
1271 | /* | |
1272 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1273 | * will be part of the irq_cfg's domain. | |
1274 | */ | |
1275 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1276 | cpumask_set_cpu(cpu, cfg->domain); | |
1277 | ||
22f65d31 | 1278 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1279 | continue; |
1280 | vector = cfg->vector; | |
497c9a19 YL |
1281 | per_cpu(vector_irq, cpu)[vector] = irq; |
1282 | } | |
1283 | /* Mark the free vectors */ | |
1284 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1285 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1286 | if (irq < 0) | |
1287 | continue; | |
1288 | ||
1289 | cfg = irq_cfg(irq); | |
22f65d31 | 1290 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1291 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1292 | } |
dade7716 | 1293 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1294 | } |
3fde6900 | 1295 | |
f5b9ed7a | 1296 | static struct irq_chip ioapic_chip; |
54168ed7 | 1297 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1298 | |
54168ed7 IM |
1299 | #define IOAPIC_AUTO -1 |
1300 | #define IOAPIC_EDGE 0 | |
1301 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1302 | |
047c8fdb | 1303 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1304 | static inline int IO_APIC_irq_trigger(int irq) |
1305 | { | |
d6c88a50 | 1306 | int apic, idx, pin; |
1d025192 | 1307 | |
d6c88a50 TG |
1308 | for (apic = 0; apic < nr_ioapics; apic++) { |
1309 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1310 | idx = find_irq_entry(apic, pin, mp_INT); | |
1311 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1312 | return irq_trigger(idx); | |
1313 | } | |
1314 | } | |
1315 | /* | |
54168ed7 IM |
1316 | * nonexistent IRQs are edge default |
1317 | */ | |
d6c88a50 | 1318 | return 0; |
1d025192 | 1319 | } |
047c8fdb YL |
1320 | #else |
1321 | static inline int IO_APIC_irq_trigger(int irq) | |
1322 | { | |
54168ed7 | 1323 | return 1; |
047c8fdb YL |
1324 | } |
1325 | #endif | |
1d025192 | 1326 | |
3145e941 | 1327 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1328 | { |
199751d7 | 1329 | |
6ebcc00e | 1330 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1331 | trigger == IOAPIC_LEVEL) |
08678b08 | 1332 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1333 | else |
1334 | desc->status &= ~IRQ_LEVEL; | |
1335 | ||
54168ed7 IM |
1336 | if (irq_remapped(irq)) { |
1337 | desc->status |= IRQ_MOVE_PCNTXT; | |
1338 | if (trigger) | |
1339 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1340 | handle_fasteoi_irq, | |
1341 | "fasteoi"); | |
1342 | else | |
1343 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1344 | handle_edge_irq, "edge"); | |
1345 | return; | |
1346 | } | |
29b61be6 | 1347 | |
047c8fdb YL |
1348 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1349 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1350 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1351 | handle_fasteoi_irq, |
1352 | "fasteoi"); | |
047c8fdb | 1353 | else |
a460e745 | 1354 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1355 | handle_edge_irq, "edge"); |
1da177e4 LT |
1356 | } |
1357 | ||
ca97ab90 JF |
1358 | int setup_ioapic_entry(int apic_id, int irq, |
1359 | struct IO_APIC_route_entry *entry, | |
1360 | unsigned int destination, int trigger, | |
0280f7c4 | 1361 | int polarity, int vector, int pin) |
1da177e4 | 1362 | { |
497c9a19 YL |
1363 | /* |
1364 | * add it to the IO-APIC irq-routing table: | |
1365 | */ | |
1366 | memset(entry,0,sizeof(*entry)); | |
1367 | ||
54168ed7 | 1368 | if (intr_remapping_enabled) { |
c8d46cf0 | 1369 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1370 | struct irte irte; |
1371 | struct IR_IO_APIC_route_entry *ir_entry = | |
1372 | (struct IR_IO_APIC_route_entry *) entry; | |
1373 | int index; | |
1374 | ||
1375 | if (!iommu) | |
c8d46cf0 | 1376 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1377 | |
1378 | index = alloc_irte(iommu, irq, 1); | |
1379 | if (index < 0) | |
c8d46cf0 | 1380 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1381 | |
1382 | memset(&irte, 0, sizeof(irte)); | |
1383 | ||
1384 | irte.present = 1; | |
9b5bc8dc | 1385 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1386 | /* |
1387 | * Trigger mode in the IRTE will always be edge, and the | |
1388 | * actual level or edge trigger will be setup in the IO-APIC | |
1389 | * RTE. This will help simplify level triggered irq migration. | |
1390 | * For more details, see the comments above explainig IO-APIC | |
1391 | * irq migration in the presence of interrupt-remapping. | |
1392 | */ | |
1393 | irte.trigger_mode = 0; | |
9b5bc8dc | 1394 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1395 | irte.vector = vector; |
1396 | irte.dest_id = IRTE_DEST(destination); | |
1397 | ||
f007e99c WH |
1398 | /* Set source-id of interrupt request */ |
1399 | set_ioapic_sid(&irte, apic_id); | |
1400 | ||
54168ed7 IM |
1401 | modify_irte(irq, &irte); |
1402 | ||
1403 | ir_entry->index2 = (index >> 15) & 0x1; | |
1404 | ir_entry->zero = 0; | |
1405 | ir_entry->format = 1; | |
1406 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1407 | /* |
1408 | * IO-APIC RTE will be configured with virtual vector. | |
1409 | * irq handler will do the explicit EOI to the io-apic. | |
1410 | */ | |
1411 | ir_entry->vector = pin; | |
29b61be6 | 1412 | } else { |
9b5bc8dc IM |
1413 | entry->delivery_mode = apic->irq_delivery_mode; |
1414 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1415 | entry->dest = destination; |
0280f7c4 | 1416 | entry->vector = vector; |
54168ed7 | 1417 | } |
497c9a19 | 1418 | |
54168ed7 | 1419 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1420 | entry->trigger = trigger; |
1421 | entry->polarity = polarity; | |
497c9a19 YL |
1422 | |
1423 | /* Mask level triggered irqs. | |
1424 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1425 | */ | |
1426 | if (trigger) | |
1427 | entry->mask = 1; | |
497c9a19 YL |
1428 | return 0; |
1429 | } | |
1430 | ||
c8d46cf0 | 1431 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1432 | int trigger, int polarity) |
497c9a19 YL |
1433 | { |
1434 | struct irq_cfg *cfg; | |
1da177e4 | 1435 | struct IO_APIC_route_entry entry; |
22f65d31 | 1436 | unsigned int dest; |
497c9a19 YL |
1437 | |
1438 | if (!IO_APIC_IRQ(irq)) | |
1439 | return; | |
1440 | ||
3145e941 | 1441 | cfg = desc->chip_data; |
497c9a19 | 1442 | |
69c89efb SS |
1443 | /* |
1444 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1445 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1446 | * the cfg->domain. | |
1447 | */ | |
28c6a0ba | 1448 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1449 | apic->vector_allocation_domain(0, cfg->domain); |
1450 | ||
fe402e1f | 1451 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1452 | return; |
1453 | ||
debccb3e | 1454 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1455 | |
1456 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1457 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1458 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1459 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1460 | irq, trigger, polarity); |
1461 | ||
1462 | ||
c8d46cf0 | 1463 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1464 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1465 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1466 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1467 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1468 | return; |
1469 | } | |
1470 | ||
3145e941 | 1471 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 JP |
1472 | if (irq < legacy_pic->nr_legacy_irqs) |
1473 | legacy_pic->chip->mask(irq); | |
497c9a19 | 1474 | |
c8d46cf0 | 1475 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1476 | } |
1477 | ||
b9c61b70 YL |
1478 | static struct { |
1479 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1480 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1481 | ||
497c9a19 YL |
1482 | static void __init setup_IO_APIC_irqs(void) |
1483 | { | |
fad53995 | 1484 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1485 | int notcon = 0; |
0b8f1efa | 1486 | struct irq_desc *desc; |
3145e941 | 1487 | struct irq_cfg *cfg; |
85ac16d0 | 1488 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1489 | |
1490 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1491 | ||
fad53995 | 1492 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1493 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1494 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1495 | if (idx == -1) { | |
1496 | if (!notcon) { | |
1497 | notcon = 1; | |
1498 | apic_printk(APIC_VERBOSE, | |
1499 | KERN_DEBUG " %d-%d", | |
1500 | mp_ioapics[apic_id].apicid, pin); | |
1501 | } else | |
1502 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1503 | mp_ioapics[apic_id].apicid, pin); | |
1504 | continue; | |
1505 | } | |
1506 | if (notcon) { | |
1507 | apic_printk(APIC_VERBOSE, | |
1508 | " (apicid-pin) not connected\n"); | |
1509 | notcon = 0; | |
1510 | } | |
33a201fa | 1511 | |
b9c61b70 | 1512 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1513 | |
fad53995 EB |
1514 | if ((apic_id > 0) && (irq > 16)) |
1515 | continue; | |
1516 | ||
b9c61b70 YL |
1517 | /* |
1518 | * Skip the timer IRQ if there's a quirk handler | |
1519 | * installed and if it returns 1: | |
1520 | */ | |
1521 | if (apic->multi_timer_check && | |
1522 | apic->multi_timer_check(apic_id, irq)) | |
1523 | continue; | |
36062448 | 1524 | |
b9c61b70 YL |
1525 | desc = irq_to_desc_alloc_node(irq, node); |
1526 | if (!desc) { | |
1527 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1528 | continue; | |
3c2cbd24 | 1529 | } |
b9c61b70 YL |
1530 | cfg = desc->chip_data; |
1531 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1532 | /* |
1533 | * don't mark it in pin_programmed, so later acpi could | |
1534 | * set it correctly when irq < 16 | |
1535 | */ | |
b9c61b70 YL |
1536 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1537 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1538 | } |
1539 | ||
3c2cbd24 CG |
1540 | if (notcon) |
1541 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1542 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1543 | } |
1544 | ||
18dce6ba YL |
1545 | /* |
1546 | * for the gsit that is not in first ioapic | |
1547 | * but could not use acpi_register_gsi() | |
1548 | * like some special sci in IBM x3330 | |
1549 | */ | |
1550 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1551 | { | |
1552 | int apic_id = 0, pin, idx, irq; | |
1553 | int node = cpu_to_node(boot_cpu_id); | |
1554 | struct irq_desc *desc; | |
1555 | struct irq_cfg *cfg; | |
1556 | ||
1557 | /* | |
1558 | * Convert 'gsi' to 'ioapic.pin'. | |
1559 | */ | |
1560 | apic_id = mp_find_ioapic(gsi); | |
1561 | if (apic_id < 0) | |
1562 | return; | |
1563 | ||
1564 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1565 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1566 | if (idx == -1) | |
1567 | return; | |
1568 | ||
1569 | irq = pin_2_irq(idx, apic_id, pin); | |
1570 | #ifdef CONFIG_SPARSE_IRQ | |
1571 | desc = irq_to_desc(irq); | |
1572 | if (desc) | |
1573 | return; | |
1574 | #endif | |
1575 | desc = irq_to_desc_alloc_node(irq, node); | |
1576 | if (!desc) { | |
1577 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1578 | return; | |
1579 | } | |
1580 | ||
1581 | cfg = desc->chip_data; | |
1582 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
1583 | ||
1584 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1585 | pr_debug("Pin %d-%d already programmed\n", | |
1586 | mp_ioapics[apic_id].apicid, pin); | |
1587 | return; | |
1588 | } | |
1589 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1590 | ||
1591 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1592 | irq_trigger(idx), irq_polarity(idx)); | |
1593 | } | |
1594 | ||
1da177e4 | 1595 | /* |
f7633ce5 | 1596 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1597 | */ |
c8d46cf0 | 1598 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1599 | int vector) |
1da177e4 LT |
1600 | { |
1601 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1602 | |
54168ed7 IM |
1603 | if (intr_remapping_enabled) |
1604 | return; | |
54168ed7 | 1605 | |
36062448 | 1606 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1607 | |
1608 | /* | |
1609 | * We use logical delivery to get the timer IRQ | |
1610 | * to the first CPU. | |
1611 | */ | |
9b5bc8dc | 1612 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1613 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1614 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1615 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1616 | entry.polarity = 0; |
1617 | entry.trigger = 0; | |
1618 | entry.vector = vector; | |
1619 | ||
1620 | /* | |
1621 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1622 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1623 | */ |
54168ed7 | 1624 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1625 | |
1626 | /* | |
1627 | * Add it to the IO-APIC irq-routing table: | |
1628 | */ | |
c8d46cf0 | 1629 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1630 | } |
1631 | ||
32f71aff MR |
1632 | |
1633 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1634 | { |
1635 | int apic, i; | |
1636 | union IO_APIC_reg_00 reg_00; | |
1637 | union IO_APIC_reg_01 reg_01; | |
1638 | union IO_APIC_reg_02 reg_02; | |
1639 | union IO_APIC_reg_03 reg_03; | |
1640 | unsigned long flags; | |
0f978f45 | 1641 | struct irq_cfg *cfg; |
0b8f1efa | 1642 | struct irq_desc *desc; |
8f09cd20 | 1643 | unsigned int irq; |
1da177e4 | 1644 | |
36062448 | 1645 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1646 | for (i = 0; i < nr_ioapics; i++) |
1647 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1648 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1649 | |
1650 | /* | |
1651 | * We are a bit conservative about what we expect. We have to | |
1652 | * know about every hardware change ASAP. | |
1653 | */ | |
1654 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1655 | ||
1656 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1657 | ||
dade7716 | 1658 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1659 | reg_00.raw = io_apic_read(apic, 0); |
1660 | reg_01.raw = io_apic_read(apic, 1); | |
1661 | if (reg_01.bits.version >= 0x10) | |
1662 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1663 | if (reg_01.bits.version >= 0x20) |
1664 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1665 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1666 | |
54168ed7 | 1667 | printk("\n"); |
b5ba7e6d | 1668 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1669 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1670 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1671 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1672 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1673 | |
54168ed7 | 1674 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1675 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1676 | |
1677 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1678 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1679 | |
1680 | /* | |
1681 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1682 | * but the value of reg_02 is read as the previous read register | |
1683 | * value, so ignore it if reg_02 == reg_01. | |
1684 | */ | |
1685 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1686 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1687 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1688 | } |
1689 | ||
1690 | /* | |
1691 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1692 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1693 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1694 | */ | |
1695 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1696 | reg_03.raw != reg_01.raw) { | |
1697 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1698 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1699 | } |
1700 | ||
1701 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1702 | ||
d83e94ac | 1703 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1704 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1705 | |
1706 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1707 | struct IO_APIC_route_entry entry; | |
1708 | ||
cf4c6a2f | 1709 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1710 | |
54168ed7 IM |
1711 | printk(KERN_DEBUG " %02x %03X ", |
1712 | i, | |
1713 | entry.dest | |
1714 | ); | |
1da177e4 LT |
1715 | |
1716 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1717 | entry.mask, | |
1718 | entry.trigger, | |
1719 | entry.irr, | |
1720 | entry.polarity, | |
1721 | entry.delivery_status, | |
1722 | entry.dest_mode, | |
1723 | entry.delivery_mode, | |
1724 | entry.vector | |
1725 | ); | |
1726 | } | |
1727 | } | |
1da177e4 | 1728 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1729 | for_each_irq_desc(irq, desc) { |
1730 | struct irq_pin_list *entry; | |
1731 | ||
0b8f1efa YL |
1732 | cfg = desc->chip_data; |
1733 | entry = cfg->irq_2_pin; | |
0f978f45 | 1734 | if (!entry) |
1da177e4 | 1735 | continue; |
8f09cd20 | 1736 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1737 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1738 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1739 | printk("\n"); |
1740 | } | |
1741 | ||
1742 | printk(KERN_INFO ".................................... done.\n"); | |
1743 | ||
1744 | return; | |
1745 | } | |
1746 | ||
251e1e44 | 1747 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1748 | { |
251e1e44 | 1749 | int i; |
1da177e4 | 1750 | |
251e1e44 IM |
1751 | printk(KERN_DEBUG); |
1752 | ||
1753 | for (i = 0; i < 8; i++) | |
1754 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1755 | ||
1756 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1757 | } |
1758 | ||
32f71aff | 1759 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1760 | { |
97a52714 | 1761 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1762 | u64 icr; |
1da177e4 | 1763 | |
251e1e44 | 1764 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1765 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1766 | v = apic_read(APIC_ID); |
54168ed7 | 1767 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1768 | v = apic_read(APIC_LVR); |
1769 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1770 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1771 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1772 | |
1773 | v = apic_read(APIC_TASKPRI); | |
1774 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1775 | ||
54168ed7 | 1776 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1777 | if (!APIC_XAPIC(ver)) { |
1778 | v = apic_read(APIC_ARBPRI); | |
1779 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1780 | v & APIC_ARBPRI_MASK); | |
1781 | } | |
1da177e4 LT |
1782 | v = apic_read(APIC_PROCPRI); |
1783 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1784 | } | |
1785 | ||
a11b5abe YL |
1786 | /* |
1787 | * Remote read supported only in the 82489DX and local APIC for | |
1788 | * Pentium processors. | |
1789 | */ | |
1790 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1791 | v = apic_read(APIC_RRR); | |
1792 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1793 | } | |
1794 | ||
1da177e4 LT |
1795 | v = apic_read(APIC_LDR); |
1796 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1797 | if (!x2apic_enabled()) { |
1798 | v = apic_read(APIC_DFR); | |
1799 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1800 | } | |
1da177e4 LT |
1801 | v = apic_read(APIC_SPIV); |
1802 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1803 | ||
1804 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1805 | print_APIC_field(APIC_ISR); |
1da177e4 | 1806 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1807 | print_APIC_field(APIC_TMR); |
1da177e4 | 1808 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1809 | print_APIC_field(APIC_IRR); |
1da177e4 | 1810 | |
54168ed7 IM |
1811 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1812 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1813 | apic_write(APIC_ESR, 0); |
54168ed7 | 1814 | |
1da177e4 LT |
1815 | v = apic_read(APIC_ESR); |
1816 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1817 | } | |
1818 | ||
7ab6af7a | 1819 | icr = apic_icr_read(); |
0c425cec IM |
1820 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1821 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1822 | |
1823 | v = apic_read(APIC_LVTT); | |
1824 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1825 | ||
1826 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1827 | v = apic_read(APIC_LVTPC); | |
1828 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1829 | } | |
1830 | v = apic_read(APIC_LVT0); | |
1831 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1832 | v = apic_read(APIC_LVT1); | |
1833 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1834 | ||
1835 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1836 | v = apic_read(APIC_LVTERR); | |
1837 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1838 | } | |
1839 | ||
1840 | v = apic_read(APIC_TMICT); | |
1841 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1842 | v = apic_read(APIC_TMCCT); | |
1843 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1844 | v = apic_read(APIC_TDCR); | |
1845 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1846 | |
1847 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1848 | v = apic_read(APIC_EFEAT); | |
1849 | maxlvt = (v >> 16) & 0xff; | |
1850 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1851 | v = apic_read(APIC_ECTRL); | |
1852 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1853 | for (i = 0; i < maxlvt; i++) { | |
1854 | v = apic_read(APIC_EILVTn(i)); | |
1855 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1856 | } | |
1857 | } | |
1da177e4 LT |
1858 | printk("\n"); |
1859 | } | |
1860 | ||
2626eb2b | 1861 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1862 | { |
ffd5aae7 YL |
1863 | int cpu; |
1864 | ||
2626eb2b CG |
1865 | if (!maxcpu) |
1866 | return; | |
1867 | ||
ffd5aae7 | 1868 | preempt_disable(); |
2626eb2b CG |
1869 | for_each_online_cpu(cpu) { |
1870 | if (cpu >= maxcpu) | |
1871 | break; | |
ffd5aae7 | 1872 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1873 | } |
ffd5aae7 | 1874 | preempt_enable(); |
1da177e4 LT |
1875 | } |
1876 | ||
32f71aff | 1877 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1878 | { |
1da177e4 LT |
1879 | unsigned int v; |
1880 | unsigned long flags; | |
1881 | ||
b81bb373 | 1882 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1883 | return; |
1884 | ||
1885 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1886 | ||
5619c280 | 1887 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1888 | |
1889 | v = inb(0xa1) << 8 | inb(0x21); | |
1890 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1891 | ||
1892 | v = inb(0xa0) << 8 | inb(0x20); | |
1893 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1894 | ||
54168ed7 IM |
1895 | outb(0x0b,0xa0); |
1896 | outb(0x0b,0x20); | |
1da177e4 | 1897 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1898 | outb(0x0a,0xa0); |
1899 | outb(0x0a,0x20); | |
1da177e4 | 1900 | |
5619c280 | 1901 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1902 | |
1903 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1904 | ||
1905 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1906 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1907 | } | |
1908 | ||
2626eb2b CG |
1909 | static int __initdata show_lapic = 1; |
1910 | static __init int setup_show_lapic(char *arg) | |
1911 | { | |
1912 | int num = -1; | |
1913 | ||
1914 | if (strcmp(arg, "all") == 0) { | |
1915 | show_lapic = CONFIG_NR_CPUS; | |
1916 | } else { | |
1917 | get_option(&arg, &num); | |
1918 | if (num >= 0) | |
1919 | show_lapic = num; | |
1920 | } | |
1921 | ||
1922 | return 1; | |
1923 | } | |
1924 | __setup("show_lapic=", setup_show_lapic); | |
1925 | ||
1926 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1927 | { |
2626eb2b CG |
1928 | if (apic_verbosity == APIC_QUIET) |
1929 | return 0; | |
1930 | ||
32f71aff | 1931 | print_PIC(); |
4797f6b0 YL |
1932 | |
1933 | /* don't print out if apic is not there */ | |
8312136f | 1934 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1935 | return 0; |
1936 | ||
2626eb2b | 1937 | print_local_APICs(show_lapic); |
32f71aff MR |
1938 | print_IO_APIC(); |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | ||
2626eb2b | 1943 | fs_initcall(print_ICs); |
32f71aff | 1944 | |
1da177e4 | 1945 | |
efa2559f YL |
1946 | /* Where if anywhere is the i8259 connect in external int mode */ |
1947 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1948 | ||
54168ed7 | 1949 | void __init enable_IO_APIC(void) |
1da177e4 | 1950 | { |
fcfd636a | 1951 | int i8259_apic, i8259_pin; |
54168ed7 | 1952 | int apic; |
bc07844a | 1953 | |
b81bb373 | 1954 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1955 | return; |
1956 | ||
54168ed7 | 1957 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1958 | int pin; |
1959 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1960 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1961 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1962 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1963 | |
fcfd636a EB |
1964 | /* If the interrupt line is enabled and in ExtInt mode |
1965 | * I have found the pin where the i8259 is connected. | |
1966 | */ | |
1967 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1968 | ioapic_i8259.apic = apic; | |
1969 | ioapic_i8259.pin = pin; | |
1970 | goto found_i8259; | |
1971 | } | |
1972 | } | |
1973 | } | |
1974 | found_i8259: | |
1975 | /* Look to see what if the MP table has reported the ExtINT */ | |
1976 | /* If we could not find the appropriate pin by looking at the ioapic | |
1977 | * the i8259 probably is not connected the ioapic but give the | |
1978 | * mptable a chance anyway. | |
1979 | */ | |
1980 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1981 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1982 | /* Trust the MP table if nothing is setup in the hardware */ | |
1983 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1984 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1985 | ioapic_i8259.pin = i8259_pin; | |
1986 | ioapic_i8259.apic = i8259_apic; | |
1987 | } | |
1988 | /* Complain if the MP table and the hardware disagree */ | |
1989 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1990 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1991 | { | |
1992 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1993 | } |
1994 | ||
1995 | /* | |
1996 | * Do not trust the IO-APIC being empty at bootup | |
1997 | */ | |
1998 | clear_IO_APIC(); | |
1999 | } | |
2000 | ||
2001 | /* | |
2002 | * Not an __init, needed by the reboot code | |
2003 | */ | |
2004 | void disable_IO_APIC(void) | |
2005 | { | |
2006 | /* | |
2007 | * Clear the IO-APIC before rebooting: | |
2008 | */ | |
2009 | clear_IO_APIC(); | |
2010 | ||
b81bb373 | 2011 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2012 | return; |
2013 | ||
650927ef | 2014 | /* |
0b968d23 | 2015 | * If the i8259 is routed through an IOAPIC |
650927ef | 2016 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2017 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2018 | * |
2019 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2020 | * as virtual wire B is little complex (need to configure both | |
2021 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2022 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2023 | */ |
7c6d9f97 | 2024 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2025 | struct IO_APIC_route_entry entry; |
650927ef EB |
2026 | |
2027 | memset(&entry, 0, sizeof(entry)); | |
2028 | entry.mask = 0; /* Enabled */ | |
2029 | entry.trigger = 0; /* Edge */ | |
2030 | entry.irr = 0; | |
2031 | entry.polarity = 0; /* High */ | |
2032 | entry.delivery_status = 0; | |
2033 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2034 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2035 | entry.vector = 0; |
54168ed7 | 2036 | entry.dest = read_apic_id(); |
650927ef EB |
2037 | |
2038 | /* | |
2039 | * Add it to the IO-APIC irq-routing table: | |
2040 | */ | |
cf4c6a2f | 2041 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2042 | } |
54168ed7 | 2043 | |
7c6d9f97 SS |
2044 | /* |
2045 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2046 | */ | |
8312136f | 2047 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2048 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2049 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2050 | } |
2051 | ||
54168ed7 | 2052 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2053 | /* |
2054 | * function to set the IO-APIC physical IDs based on the | |
2055 | * values stored in the MPC table. | |
2056 | * | |
2057 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2058 | */ | |
2059 | ||
de934103 | 2060 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2061 | { |
2062 | union IO_APIC_reg_00 reg_00; | |
2063 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2064 | int apic_id; |
1da177e4 LT |
2065 | int i; |
2066 | unsigned char old_id; | |
2067 | unsigned long flags; | |
2068 | ||
de934103 | 2069 | if (acpi_ioapic) |
d49c4288 | 2070 | return; |
ca05fea6 NP |
2071 | /* |
2072 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2073 | * no meaning without the serial APIC bus. | |
2074 | */ | |
7c5c1e42 SL |
2075 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2076 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2077 | return; |
1da177e4 LT |
2078 | /* |
2079 | * This is broken; anything with a real cpu count has to | |
2080 | * circumvent this idiocy regardless. | |
2081 | */ | |
7abc0753 | 2082 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2083 | |
2084 | /* | |
2085 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2086 | */ | |
c8d46cf0 | 2087 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2088 | |
2089 | /* Read the register 0 value */ | |
dade7716 | 2090 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2091 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2092 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2093 | |
c8d46cf0 | 2094 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2095 | |
c8d46cf0 | 2096 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2097 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2098 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2099 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2100 | reg_00.bits.ID); | |
c8d46cf0 | 2101 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2102 | } |
2103 | ||
1da177e4 LT |
2104 | /* |
2105 | * Sanity check, is the ID really free? Every APIC in a | |
2106 | * system must have a unique ID or we get lots of nice | |
2107 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2108 | */ | |
7abc0753 | 2109 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2110 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2111 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2112 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2113 | for (i = 0; i < get_physical_broadcast(); i++) |
2114 | if (!physid_isset(i, phys_id_present_map)) | |
2115 | break; | |
2116 | if (i >= get_physical_broadcast()) | |
2117 | panic("Max APIC ID exceeded!\n"); | |
2118 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2119 | i); | |
2120 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2121 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2122 | } else { |
2123 | physid_mask_t tmp; | |
7abc0753 | 2124 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2125 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2126 | "phys_id_present_map\n", | |
c8d46cf0 | 2127 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2128 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2129 | } | |
2130 | ||
2131 | ||
2132 | /* | |
2133 | * We need to adjust the IRQ routing table | |
2134 | * if the ID changed. | |
2135 | */ | |
c8d46cf0 | 2136 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2137 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2138 | if (mp_irqs[i].dstapic == old_id) |
2139 | mp_irqs[i].dstapic | |
c8d46cf0 | 2140 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2141 | |
2142 | /* | |
2143 | * Read the right value from the MPC table and | |
2144 | * write it into the ID register. | |
36062448 | 2145 | */ |
1da177e4 LT |
2146 | apic_printk(APIC_VERBOSE, KERN_INFO |
2147 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2148 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2149 | |
c8d46cf0 | 2150 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2151 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2152 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2153 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2154 | |
2155 | /* | |
2156 | * Sanity check | |
2157 | */ | |
dade7716 | 2158 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2159 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2160 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2161 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2162 | printk("could not set ID!\n"); |
2163 | else | |
2164 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2165 | } | |
2166 | } | |
54168ed7 | 2167 | #endif |
1da177e4 | 2168 | |
7ce0bcfd | 2169 | int no_timer_check __initdata; |
8542b200 ZA |
2170 | |
2171 | static int __init notimercheck(char *s) | |
2172 | { | |
2173 | no_timer_check = 1; | |
2174 | return 1; | |
2175 | } | |
2176 | __setup("no_timer_check", notimercheck); | |
2177 | ||
1da177e4 LT |
2178 | /* |
2179 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2180 | * about the timer IRQ. We do the following to work around the situation: | |
2181 | * | |
2182 | * - timer IRQ defaults to IO-APIC IRQ | |
2183 | * - if this function detects that timer IRQs are defunct, then we fall | |
2184 | * back to ISA timer IRQs | |
2185 | */ | |
f0a7a5c9 | 2186 | static int __init timer_irq_works(void) |
1da177e4 LT |
2187 | { |
2188 | unsigned long t1 = jiffies; | |
4aae0702 | 2189 | unsigned long flags; |
1da177e4 | 2190 | |
8542b200 ZA |
2191 | if (no_timer_check) |
2192 | return 1; | |
2193 | ||
4aae0702 | 2194 | local_save_flags(flags); |
1da177e4 LT |
2195 | local_irq_enable(); |
2196 | /* Let ten ticks pass... */ | |
2197 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2198 | local_irq_restore(flags); |
1da177e4 LT |
2199 | |
2200 | /* | |
2201 | * Expect a few ticks at least, to be sure some possible | |
2202 | * glue logic does not lock up after one or two first | |
2203 | * ticks in a non-ExtINT mode. Also the local APIC | |
2204 | * might have cached one ExtINT interrupt. Finally, at | |
2205 | * least one tick may be lost due to delays. | |
2206 | */ | |
54168ed7 IM |
2207 | |
2208 | /* jiffies wrap? */ | |
1d16b53e | 2209 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2210 | return 1; |
1da177e4 LT |
2211 | return 0; |
2212 | } | |
2213 | ||
2214 | /* | |
2215 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2216 | * number of pending IRQ events unhandled. These cases are very rare, | |
2217 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2218 | * better to do it this way as thus we do not have to be aware of | |
2219 | * 'pending' interrupts in the IRQ path, except at this point. | |
2220 | */ | |
2221 | /* | |
2222 | * Edge triggered needs to resend any interrupt | |
2223 | * that was delayed but this is now handled in the device | |
2224 | * independent code. | |
2225 | */ | |
2226 | ||
2227 | /* | |
2228 | * Starting up a edge-triggered IO-APIC interrupt is | |
2229 | * nasty - we need to make sure that we get the edge. | |
2230 | * If it is already asserted for some reason, we need | |
2231 | * return 1 to indicate that is was pending. | |
2232 | * | |
2233 | * This is not complete - we should be able to fake | |
2234 | * an edge even if it isn't on the 8259A... | |
2235 | */ | |
54168ed7 | 2236 | |
f5b9ed7a | 2237 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2238 | { |
2239 | int was_pending = 0; | |
2240 | unsigned long flags; | |
0b8f1efa | 2241 | struct irq_cfg *cfg; |
1da177e4 | 2242 | |
dade7716 | 2243 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 JP |
2244 | if (irq < legacy_pic->nr_legacy_irqs) { |
2245 | legacy_pic->chip->mask(irq); | |
2246 | if (legacy_pic->irq_pending(irq)) | |
1da177e4 LT |
2247 | was_pending = 1; |
2248 | } | |
0b8f1efa | 2249 | cfg = irq_cfg(irq); |
3145e941 | 2250 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 2251 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2252 | |
2253 | return was_pending; | |
2254 | } | |
2255 | ||
ace80ab7 | 2256 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2257 | { |
54168ed7 IM |
2258 | |
2259 | struct irq_cfg *cfg = irq_cfg(irq); | |
2260 | unsigned long flags; | |
2261 | ||
dade7716 | 2262 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2263 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2264 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2265 | |
2266 | return 1; | |
2267 | } | |
497c9a19 | 2268 | |
54168ed7 IM |
2269 | /* |
2270 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2271 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2272 | * handled with the level-triggered descriptor, but that one has slightly | |
2273 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2274 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2275 | * races. | |
2276 | */ | |
497c9a19 | 2277 | |
54168ed7 | 2278 | #ifdef CONFIG_SMP |
9338ad6f | 2279 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2280 | { |
2281 | cpumask_var_t cleanup_mask; | |
2282 | ||
2283 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2284 | unsigned int i; | |
e85abf8f GH |
2285 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2286 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2287 | } else { | |
2288 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2289 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2290 | free_cpumask_var(cleanup_mask); | |
2291 | } | |
2292 | cfg->move_in_progress = 0; | |
2293 | } | |
2294 | ||
4420471f | 2295 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2296 | { |
2297 | int apic, pin; | |
2298 | struct irq_pin_list *entry; | |
2299 | u8 vector = cfg->vector; | |
2300 | ||
2977fb3f | 2301 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2302 | unsigned int reg; |
2303 | ||
e85abf8f GH |
2304 | apic = entry->apic; |
2305 | pin = entry->pin; | |
2306 | /* | |
2307 | * With interrupt-remapping, destination information comes | |
2308 | * from interrupt-remapping table entry. | |
2309 | */ | |
2310 | if (!irq_remapped(irq)) | |
2311 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2312 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2313 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2314 | reg |= vector; | |
2315 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2316 | } |
2317 | } | |
2318 | ||
2319 | /* | |
2320 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2321 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2322 | * leaves desc->affinity untouched. |
2323 | */ | |
9338ad6f | 2324 | unsigned int |
18374d89 SS |
2325 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2326 | unsigned int *dest_id) | |
e85abf8f GH |
2327 | { |
2328 | struct irq_cfg *cfg; | |
2329 | unsigned int irq; | |
2330 | ||
2331 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2332 | return -1; |
e85abf8f GH |
2333 | |
2334 | irq = desc->irq; | |
2335 | cfg = desc->chip_data; | |
2336 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2337 | return -1; |
e85abf8f | 2338 | |
e85abf8f GH |
2339 | cpumask_copy(desc->affinity, mask); |
2340 | ||
18374d89 SS |
2341 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2342 | return 0; | |
e85abf8f GH |
2343 | } |
2344 | ||
4420471f | 2345 | static int |
e85abf8f GH |
2346 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2347 | { | |
2348 | struct irq_cfg *cfg; | |
2349 | unsigned long flags; | |
2350 | unsigned int dest; | |
2351 | unsigned int irq; | |
4420471f | 2352 | int ret = -1; |
e85abf8f GH |
2353 | |
2354 | irq = desc->irq; | |
2355 | cfg = desc->chip_data; | |
2356 | ||
dade7716 | 2357 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2358 | ret = set_desc_affinity(desc, mask, &dest); |
2359 | if (!ret) { | |
e85abf8f GH |
2360 | /* Only the high 8 bits are valid. */ |
2361 | dest = SET_APIC_LOGICAL_ID(dest); | |
2362 | __target_IO_APIC_irq(irq, dest, cfg); | |
2363 | } | |
dade7716 | 2364 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2365 | |
2366 | return ret; | |
e85abf8f GH |
2367 | } |
2368 | ||
4420471f | 2369 | static int |
e85abf8f GH |
2370 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2371 | { | |
2372 | struct irq_desc *desc; | |
2373 | ||
2374 | desc = irq_to_desc(irq); | |
2375 | ||
4420471f | 2376 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2377 | } |
497c9a19 | 2378 | |
54168ed7 | 2379 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2380 | |
54168ed7 IM |
2381 | /* |
2382 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2383 | * | |
0280f7c4 SS |
2384 | * For both level and edge triggered, irq migration is a simple atomic |
2385 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2386 | * |
0280f7c4 SS |
2387 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2388 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2389 | * Real vector that is used for interrupting cpu will be coming from | |
2390 | * the interrupt-remapping table entry. | |
54168ed7 | 2391 | */ |
d5dedd45 | 2392 | static int |
e7986739 | 2393 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2394 | { |
54168ed7 | 2395 | struct irq_cfg *cfg; |
54168ed7 | 2396 | struct irte irte; |
54168ed7 | 2397 | unsigned int dest; |
3145e941 | 2398 | unsigned int irq; |
d5dedd45 | 2399 | int ret = -1; |
497c9a19 | 2400 | |
22f65d31 | 2401 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2402 | return ret; |
497c9a19 | 2403 | |
3145e941 | 2404 | irq = desc->irq; |
54168ed7 | 2405 | if (get_irte(irq, &irte)) |
d5dedd45 | 2406 | return ret; |
497c9a19 | 2407 | |
3145e941 YL |
2408 | cfg = desc->chip_data; |
2409 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2410 | return ret; |
54168ed7 | 2411 | |
debccb3e | 2412 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2413 | |
54168ed7 IM |
2414 | irte.vector = cfg->vector; |
2415 | irte.dest_id = IRTE_DEST(dest); | |
2416 | ||
2417 | /* | |
2418 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2419 | */ | |
2420 | modify_irte(irq, &irte); | |
2421 | ||
22f65d31 MT |
2422 | if (cfg->move_in_progress) |
2423 | send_cleanup_vector(cfg); | |
54168ed7 | 2424 | |
7f7ace0c | 2425 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2426 | |
2427 | return 0; | |
54168ed7 IM |
2428 | } |
2429 | ||
54168ed7 IM |
2430 | /* |
2431 | * Migrates the IRQ destination in the process context. | |
2432 | */ | |
d5dedd45 | 2433 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2434 | const struct cpumask *mask) |
54168ed7 | 2435 | { |
d5dedd45 | 2436 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2437 | } |
d5dedd45 | 2438 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2439 | const struct cpumask *mask) |
3145e941 YL |
2440 | { |
2441 | struct irq_desc *desc = irq_to_desc(irq); | |
2442 | ||
d5dedd45 | 2443 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2444 | } |
29b61be6 | 2445 | #else |
d5dedd45 | 2446 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2447 | const struct cpumask *mask) |
2448 | { | |
d5dedd45 | 2449 | return 0; |
29b61be6 | 2450 | } |
54168ed7 IM |
2451 | #endif |
2452 | ||
2453 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2454 | { | |
2455 | unsigned vector, me; | |
8f2466f4 | 2456 | |
54168ed7 | 2457 | ack_APIC_irq(); |
54168ed7 | 2458 | exit_idle(); |
54168ed7 IM |
2459 | irq_enter(); |
2460 | ||
2461 | me = smp_processor_id(); | |
2462 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2463 | unsigned int irq; | |
68a8ca59 | 2464 | unsigned int irr; |
54168ed7 IM |
2465 | struct irq_desc *desc; |
2466 | struct irq_cfg *cfg; | |
2467 | irq = __get_cpu_var(vector_irq)[vector]; | |
2468 | ||
0b8f1efa YL |
2469 | if (irq == -1) |
2470 | continue; | |
2471 | ||
54168ed7 IM |
2472 | desc = irq_to_desc(irq); |
2473 | if (!desc) | |
2474 | continue; | |
2475 | ||
2476 | cfg = irq_cfg(irq); | |
239007b8 | 2477 | raw_spin_lock(&desc->lock); |
54168ed7 | 2478 | |
7f41c2e1 SS |
2479 | /* |
2480 | * Check if the irq migration is in progress. If so, we | |
2481 | * haven't received the cleanup request yet for this irq. | |
2482 | */ | |
2483 | if (cfg->move_in_progress) | |
2484 | goto unlock; | |
2485 | ||
22f65d31 | 2486 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2487 | goto unlock; |
2488 | ||
68a8ca59 SS |
2489 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2490 | /* | |
2491 | * Check if the vector that needs to be cleanedup is | |
2492 | * registered at the cpu's IRR. If so, then this is not | |
2493 | * the best time to clean it up. Lets clean it up in the | |
2494 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2495 | * to myself. | |
2496 | */ | |
2497 | if (irr & (1 << (vector % 32))) { | |
2498 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2499 | goto unlock; | |
2500 | } | |
54168ed7 | 2501 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2502 | unlock: |
239007b8 | 2503 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2504 | } |
2505 | ||
2506 | irq_exit(); | |
2507 | } | |
2508 | ||
a5e74b84 | 2509 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2510 | { |
3145e941 YL |
2511 | struct irq_desc *desc = *descp; |
2512 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2513 | unsigned me; |
54168ed7 | 2514 | |
fcef5911 | 2515 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2516 | return; |
2517 | ||
54168ed7 | 2518 | me = smp_processor_id(); |
10b888d6 | 2519 | |
fcef5911 | 2520 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2521 | send_cleanup_vector(cfg); |
497c9a19 | 2522 | } |
a5e74b84 SS |
2523 | |
2524 | static void irq_complete_move(struct irq_desc **descp) | |
2525 | { | |
2526 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2527 | } | |
2528 | ||
2529 | void irq_force_complete_move(int irq) | |
2530 | { | |
2531 | struct irq_desc *desc = irq_to_desc(irq); | |
2532 | struct irq_cfg *cfg = desc->chip_data; | |
2533 | ||
2534 | __irq_complete_move(&desc, cfg->vector); | |
2535 | } | |
497c9a19 | 2536 | #else |
3145e941 | 2537 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2538 | #endif |
3145e941 | 2539 | |
1d025192 YL |
2540 | static void ack_apic_edge(unsigned int irq) |
2541 | { | |
3145e941 YL |
2542 | struct irq_desc *desc = irq_to_desc(irq); |
2543 | ||
2544 | irq_complete_move(&desc); | |
1d025192 YL |
2545 | move_native_irq(irq); |
2546 | ack_APIC_irq(); | |
2547 | } | |
2548 | ||
3eb2cce8 | 2549 | atomic_t irq_mis_count; |
3eb2cce8 | 2550 | |
c29d9db3 SS |
2551 | /* |
2552 | * IO-APIC versions below 0x20 don't support EOI register. | |
2553 | * For the record, here is the information about various versions: | |
2554 | * 0Xh 82489DX | |
2555 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2556 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2557 | * 30h-FFh Reserved | |
2558 | * | |
2559 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2560 | * version as 0x2. This is an error with documentation and these ICH chips | |
2561 | * use io-apic's of version 0x20. | |
2562 | * | |
2563 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2564 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2565 | * mode to edge and then back to level, with RTE being masked during this. | |
2566 | */ | |
b3ec0a37 SS |
2567 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2568 | { | |
2569 | struct irq_pin_list *entry; | |
2570 | ||
2571 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2572 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2573 | /* | |
2574 | * Intr-remapping uses pin number as the virtual vector | |
2575 | * in the RTE. Actual vector is programmed in | |
2576 | * intr-remapping table entry. Hence for the io-apic | |
2577 | * EOI we use the pin number. | |
2578 | */ | |
2579 | if (irq_remapped(irq)) | |
2580 | io_apic_eoi(entry->apic, entry->pin); | |
2581 | else | |
2582 | io_apic_eoi(entry->apic, cfg->vector); | |
2583 | } else { | |
2584 | __mask_and_edge_IO_APIC_irq(entry); | |
2585 | __unmask_and_level_IO_APIC_irq(entry); | |
2586 | } | |
b3ec0a37 SS |
2587 | } |
2588 | } | |
2589 | ||
2590 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2591 | { | |
2592 | struct irq_cfg *cfg; | |
2593 | unsigned long flags; | |
2594 | unsigned int irq; | |
2595 | ||
2596 | irq = desc->irq; | |
2597 | cfg = desc->chip_data; | |
2598 | ||
dade7716 | 2599 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2600 | __eoi_ioapic_irq(irq, cfg); |
dade7716 | 2601 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2602 | } |
2603 | ||
047c8fdb YL |
2604 | static void ack_apic_level(unsigned int irq) |
2605 | { | |
3145e941 | 2606 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2607 | unsigned long v; |
2608 | int i; | |
3145e941 | 2609 | struct irq_cfg *cfg; |
54168ed7 | 2610 | int do_unmask_irq = 0; |
047c8fdb | 2611 | |
3145e941 | 2612 | irq_complete_move(&desc); |
047c8fdb | 2613 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2614 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2615 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2616 | do_unmask_irq = 1; |
3145e941 | 2617 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2618 | } |
047c8fdb YL |
2619 | #endif |
2620 | ||
3eb2cce8 | 2621 | /* |
916a0fe7 JF |
2622 | * It appears there is an erratum which affects at least version 0x11 |
2623 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2624 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2625 | * erroneously delivered as edge-triggered one but the respective IRR | |
2626 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2627 | * message but it will never arrive and further interrupts are blocked | |
2628 | * from the source. The exact reason is so far unknown, but the | |
2629 | * phenomenon was observed when two consecutive interrupt requests | |
2630 | * from a given source get delivered to the same CPU and the source is | |
2631 | * temporarily disabled in between. | |
2632 | * | |
2633 | * A workaround is to simulate an EOI message manually. We achieve it | |
2634 | * by setting the trigger mode to edge and then to level when the edge | |
2635 | * trigger mode gets detected in the TMR of a local APIC for a | |
2636 | * level-triggered interrupt. We mask the source for the time of the | |
2637 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2638 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2639 | * |
2640 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2641 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2642 | * destination that is handling the corresponding interrupt. This | |
2643 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2644 | * level-triggered io-apic interrupt will be seen as an edge | |
2645 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2646 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2647 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2648 | * supporting EOI register, we do an explicit EOI to clear the | |
2649 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2650 | * we use the above logic (mask+edge followed by unmask+level) from | |
2651 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2652 | */ |
3145e941 YL |
2653 | cfg = desc->chip_data; |
2654 | i = cfg->vector; | |
3eb2cce8 | 2655 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2656 | |
54168ed7 IM |
2657 | /* |
2658 | * We must acknowledge the irq before we move it or the acknowledge will | |
2659 | * not propagate properly. | |
2660 | */ | |
2661 | ack_APIC_irq(); | |
2662 | ||
1c83995b SS |
2663 | /* |
2664 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2665 | * message via io-apic EOI register write or simulating it using | |
2666 | * mask+edge followed by unnask+level logic) manually when the | |
2667 | * level triggered interrupt is seen as the edge triggered interrupt | |
2668 | * at the cpu. | |
2669 | */ | |
ca64c47c MR |
2670 | if (!(v & (1 << (i & 0x1f)))) { |
2671 | atomic_inc(&irq_mis_count); | |
2672 | ||
c29d9db3 | 2673 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2674 | } |
2675 | ||
54168ed7 IM |
2676 | /* Now we can move and renable the irq */ |
2677 | if (unlikely(do_unmask_irq)) { | |
2678 | /* Only migrate the irq if the ack has been received. | |
2679 | * | |
2680 | * On rare occasions the broadcast level triggered ack gets | |
2681 | * delayed going to ioapics, and if we reprogram the | |
2682 | * vector while Remote IRR is still set the irq will never | |
2683 | * fire again. | |
2684 | * | |
2685 | * To prevent this scenario we read the Remote IRR bit | |
2686 | * of the ioapic. This has two effects. | |
2687 | * - On any sane system the read of the ioapic will | |
2688 | * flush writes (and acks) going to the ioapic from | |
2689 | * this cpu. | |
2690 | * - We get to see if the ACK has actually been delivered. | |
2691 | * | |
2692 | * Based on failed experiments of reprogramming the | |
2693 | * ioapic entry from outside of irq context starting | |
2694 | * with masking the ioapic entry and then polling until | |
2695 | * Remote IRR was clear before reprogramming the | |
2696 | * ioapic I don't trust the Remote IRR bit to be | |
2697 | * completey accurate. | |
2698 | * | |
2699 | * However there appears to be no other way to plug | |
2700 | * this race, so if the Remote IRR bit is not | |
2701 | * accurate and is causing problems then it is a hardware bug | |
2702 | * and you can go talk to the chipset vendor about it. | |
2703 | */ | |
3145e941 YL |
2704 | cfg = desc->chip_data; |
2705 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2706 | move_masked_irq(irq); |
3145e941 | 2707 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2708 | } |
3eb2cce8 | 2709 | } |
1d025192 | 2710 | |
d0b03bd1 HW |
2711 | #ifdef CONFIG_INTR_REMAP |
2712 | static void ir_ack_apic_edge(unsigned int irq) | |
2713 | { | |
5d0ae2db | 2714 | ack_APIC_irq(); |
d0b03bd1 HW |
2715 | } |
2716 | ||
2717 | static void ir_ack_apic_level(unsigned int irq) | |
2718 | { | |
5d0ae2db WH |
2719 | struct irq_desc *desc = irq_to_desc(irq); |
2720 | ||
2721 | ack_APIC_irq(); | |
2722 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2723 | } |
2724 | #endif /* CONFIG_INTR_REMAP */ | |
2725 | ||
f5b9ed7a | 2726 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2727 | .name = "IO-APIC", |
2728 | .startup = startup_ioapic_irq, | |
2729 | .mask = mask_IO_APIC_irq, | |
2730 | .unmask = unmask_IO_APIC_irq, | |
2731 | .ack = ack_apic_edge, | |
2732 | .eoi = ack_apic_level, | |
54d5d424 | 2733 | #ifdef CONFIG_SMP |
d6c88a50 | 2734 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2735 | #endif |
ace80ab7 | 2736 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2737 | }; |
2738 | ||
54168ed7 | 2739 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2740 | .name = "IR-IO-APIC", |
2741 | .startup = startup_ioapic_irq, | |
2742 | .mask = mask_IO_APIC_irq, | |
2743 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2744 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2745 | .ack = ir_ack_apic_edge, |
2746 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2747 | #ifdef CONFIG_SMP |
d6c88a50 | 2748 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2749 | #endif |
54168ed7 IM |
2750 | #endif |
2751 | .retrigger = ioapic_retrigger_irq, | |
2752 | }; | |
1da177e4 LT |
2753 | |
2754 | static inline void init_IO_APIC_traps(void) | |
2755 | { | |
2756 | int irq; | |
08678b08 | 2757 | struct irq_desc *desc; |
da51a821 | 2758 | struct irq_cfg *cfg; |
1da177e4 LT |
2759 | |
2760 | /* | |
2761 | * NOTE! The local APIC isn't very good at handling | |
2762 | * multiple interrupts at the same interrupt level. | |
2763 | * As the interrupt level is determined by taking the | |
2764 | * vector number and shifting that right by 4, we | |
2765 | * want to spread these out a bit so that they don't | |
2766 | * all fall in the same interrupt level. | |
2767 | * | |
2768 | * Also, we've got to be careful not to trash gate | |
2769 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2770 | */ | |
0b8f1efa | 2771 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2772 | cfg = desc->chip_data; |
2773 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2774 | /* |
2775 | * Hmm.. We don't have an entry for this, | |
2776 | * so default to an old-fashioned 8259 | |
2777 | * interrupt if we can.. | |
2778 | */ | |
b81bb373 JP |
2779 | if (irq < legacy_pic->nr_legacy_irqs) |
2780 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2781 | else |
1da177e4 | 2782 | /* Strange. Oh, well.. */ |
08678b08 | 2783 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2784 | } |
2785 | } | |
2786 | } | |
2787 | ||
f5b9ed7a IM |
2788 | /* |
2789 | * The local APIC irq-chip implementation: | |
2790 | */ | |
1da177e4 | 2791 | |
36062448 | 2792 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2793 | { |
2794 | unsigned long v; | |
2795 | ||
2796 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2797 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2798 | } |
2799 | ||
36062448 | 2800 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2801 | { |
f5b9ed7a | 2802 | unsigned long v; |
1da177e4 | 2803 | |
f5b9ed7a | 2804 | v = apic_read(APIC_LVT0); |
593f4a78 | 2805 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2806 | } |
1da177e4 | 2807 | |
3145e941 | 2808 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2809 | { |
2810 | ack_APIC_irq(); | |
2811 | } | |
2812 | ||
f5b9ed7a | 2813 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2814 | .name = "local-APIC", |
f5b9ed7a IM |
2815 | .mask = mask_lapic_irq, |
2816 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2817 | .ack = ack_lapic_irq, |
1da177e4 LT |
2818 | }; |
2819 | ||
3145e941 | 2820 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2821 | { |
08678b08 | 2822 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2823 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2824 | "edge"); | |
c88ac1df MR |
2825 | } |
2826 | ||
e9427101 | 2827 | static void __init setup_nmi(void) |
1da177e4 LT |
2828 | { |
2829 | /* | |
36062448 | 2830 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2831 | * We put the 8259A master into AEOI mode and |
2832 | * unmask on all local APICs LVT0 as NMI. | |
2833 | * | |
2834 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2835 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2836 | * the NMI handler or the timer interrupt. | |
36062448 | 2837 | */ |
1da177e4 LT |
2838 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2839 | ||
e9427101 | 2840 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2841 | |
2842 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2843 | } | |
2844 | ||
2845 | /* | |
2846 | * This looks a bit hackish but it's about the only one way of sending | |
2847 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2848 | * not support the ExtINT mode, unfortunately. We need to send these | |
2849 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2850 | * 8259A interrupt line asserted until INTA. --macro | |
2851 | */ | |
28acf285 | 2852 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2853 | { |
fcfd636a | 2854 | int apic, pin, i; |
1da177e4 LT |
2855 | struct IO_APIC_route_entry entry0, entry1; |
2856 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2857 | |
fcfd636a | 2858 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2859 | if (pin == -1) { |
2860 | WARN_ON_ONCE(1); | |
2861 | return; | |
2862 | } | |
fcfd636a | 2863 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2864 | if (apic == -1) { |
2865 | WARN_ON_ONCE(1); | |
1da177e4 | 2866 | return; |
956fb531 | 2867 | } |
1da177e4 | 2868 | |
cf4c6a2f | 2869 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2870 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2871 | |
2872 | memset(&entry1, 0, sizeof(entry1)); | |
2873 | ||
2874 | entry1.dest_mode = 0; /* physical delivery */ | |
2875 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2876 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2877 | entry1.delivery_mode = dest_ExtINT; |
2878 | entry1.polarity = entry0.polarity; | |
2879 | entry1.trigger = 0; | |
2880 | entry1.vector = 0; | |
2881 | ||
cf4c6a2f | 2882 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2883 | |
2884 | save_control = CMOS_READ(RTC_CONTROL); | |
2885 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2886 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2887 | RTC_FREQ_SELECT); | |
2888 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2889 | ||
2890 | i = 100; | |
2891 | while (i-- > 0) { | |
2892 | mdelay(10); | |
2893 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2894 | i -= 10; | |
2895 | } | |
2896 | ||
2897 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2898 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2899 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2900 | |
cf4c6a2f | 2901 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2902 | } |
2903 | ||
efa2559f | 2904 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2905 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2906 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2907 | { |
2908 | disable_timer_pin_1 = 1; | |
2909 | return 0; | |
2910 | } | |
54168ed7 | 2911 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2912 | |
2913 | int timer_through_8259 __initdata; | |
2914 | ||
1da177e4 LT |
2915 | /* |
2916 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2917 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2918 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2919 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2920 | * |
2921 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2922 | */ |
8542b200 | 2923 | static inline void __init check_timer(void) |
1da177e4 | 2924 | { |
3145e941 YL |
2925 | struct irq_desc *desc = irq_to_desc(0); |
2926 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2927 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2928 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2929 | unsigned long flags; |
047c8fdb | 2930 | int no_pin1 = 0; |
4aae0702 IM |
2931 | |
2932 | local_irq_save(flags); | |
d4d25dec | 2933 | |
1da177e4 LT |
2934 | /* |
2935 | * get/set the timer IRQ vector: | |
2936 | */ | |
b81bb373 | 2937 | legacy_pic->chip->mask(0); |
fe402e1f | 2938 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2939 | |
2940 | /* | |
d11d5794 MR |
2941 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2942 | * wire has to be disabled in the local APIC. Also | |
2943 | * timer interrupts need to be acknowledged manually in | |
2944 | * the 8259A for the i82489DX when using the NMI | |
2945 | * watchdog as that APIC treats NMIs as level-triggered. | |
2946 | * The AEOI mode will finish them in the 8259A | |
2947 | * automatically. | |
1da177e4 | 2948 | */ |
593f4a78 | 2949 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2950 | legacy_pic->init(1); |
54168ed7 | 2951 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2952 | { |
2953 | unsigned int ver; | |
2954 | ||
2955 | ver = apic_read(APIC_LVR); | |
2956 | ver = GET_APIC_VERSION(ver); | |
2957 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2958 | } | |
54168ed7 | 2959 | #endif |
1da177e4 | 2960 | |
fcfd636a EB |
2961 | pin1 = find_isa_irq_pin(0, mp_INT); |
2962 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2963 | pin2 = ioapic_i8259.pin; | |
2964 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2965 | |
49a66a0b MR |
2966 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2967 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2968 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2969 | |
691874fa MR |
2970 | /* |
2971 | * Some BIOS writers are clueless and report the ExtINTA | |
2972 | * I/O APIC input from the cascaded 8259A as the timer | |
2973 | * interrupt input. So just in case, if only one pin | |
2974 | * was found above, try it both directly and through the | |
2975 | * 8259A. | |
2976 | */ | |
2977 | if (pin1 == -1) { | |
54168ed7 IM |
2978 | if (intr_remapping_enabled) |
2979 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2980 | pin1 = pin2; |
2981 | apic1 = apic2; | |
2982 | no_pin1 = 1; | |
2983 | } else if (pin2 == -1) { | |
2984 | pin2 = pin1; | |
2985 | apic2 = apic1; | |
2986 | } | |
2987 | ||
1da177e4 LT |
2988 | if (pin1 != -1) { |
2989 | /* | |
2990 | * Ok, does IRQ0 through the IOAPIC work? | |
2991 | */ | |
691874fa | 2992 | if (no_pin1) { |
85ac16d0 | 2993 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2994 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2995 | } else { |
2996 | /* for edge trigger, setup_IO_APIC_irq already | |
2997 | * leave it unmasked. | |
2998 | * so only need to unmask if it is level-trigger | |
2999 | * do we really have level trigger timer? | |
3000 | */ | |
3001 | int idx; | |
3002 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
3003 | if (idx != -1 && irq_trigger(idx)) | |
3004 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 3005 | } |
1da177e4 LT |
3006 | if (timer_irq_works()) { |
3007 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 3008 | setup_nmi(); |
b81bb373 | 3009 | legacy_pic->chip->unmask(0); |
1da177e4 | 3010 | } |
66759a01 CE |
3011 | if (disable_timer_pin_1 > 0) |
3012 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 3013 | goto out; |
1da177e4 | 3014 | } |
54168ed7 IM |
3015 | if (intr_remapping_enabled) |
3016 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 3017 | local_irq_disable(); |
fcfd636a | 3018 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 3019 | if (!no_pin1) |
49a66a0b MR |
3020 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
3021 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 3022 | |
49a66a0b MR |
3023 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3024 | "(IRQ0) through the 8259A ...\n"); | |
3025 | apic_printk(APIC_QUIET, KERN_INFO | |
3026 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3027 | /* |
3028 | * legacy devices should be connected to IO APIC #0 | |
3029 | */ | |
85ac16d0 | 3030 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3031 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
b81bb373 | 3032 | legacy_pic->chip->unmask(0); |
1da177e4 | 3033 | if (timer_irq_works()) { |
49a66a0b | 3034 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3035 | timer_through_8259 = 1; |
1da177e4 | 3036 | if (nmi_watchdog == NMI_IO_APIC) { |
b81bb373 | 3037 | legacy_pic->chip->mask(0); |
1da177e4 | 3038 | setup_nmi(); |
b81bb373 | 3039 | legacy_pic->chip->unmask(0); |
1da177e4 | 3040 | } |
4aae0702 | 3041 | goto out; |
1da177e4 LT |
3042 | } |
3043 | /* | |
3044 | * Cleanup, just in case ... | |
3045 | */ | |
f72dccac | 3046 | local_irq_disable(); |
b81bb373 | 3047 | legacy_pic->chip->mask(0); |
fcfd636a | 3048 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3049 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3050 | } |
1da177e4 LT |
3051 | |
3052 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3053 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3054 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3055 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3056 | } |
54168ed7 | 3057 | #ifdef CONFIG_X86_32 |
d11d5794 | 3058 | timer_ack = 0; |
54168ed7 | 3059 | #endif |
1da177e4 | 3060 | |
49a66a0b MR |
3061 | apic_printk(APIC_QUIET, KERN_INFO |
3062 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3063 | |
3145e941 | 3064 | lapic_register_intr(0, desc); |
497c9a19 | 3065 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
b81bb373 | 3066 | legacy_pic->chip->unmask(0); |
1da177e4 LT |
3067 | |
3068 | if (timer_irq_works()) { | |
49a66a0b | 3069 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3070 | goto out; |
1da177e4 | 3071 | } |
f72dccac | 3072 | local_irq_disable(); |
b81bb373 | 3073 | legacy_pic->chip->mask(0); |
497c9a19 | 3074 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3075 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3076 | |
49a66a0b MR |
3077 | apic_printk(APIC_QUIET, KERN_INFO |
3078 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3079 | |
b81bb373 JP |
3080 | legacy_pic->init(0); |
3081 | legacy_pic->make_irq(0); | |
593f4a78 | 3082 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3083 | |
3084 | unlock_ExtINT_logic(); | |
3085 | ||
3086 | if (timer_irq_works()) { | |
49a66a0b | 3087 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3088 | goto out; |
1da177e4 | 3089 | } |
f72dccac | 3090 | local_irq_disable(); |
49a66a0b | 3091 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3092 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3093 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3094 | out: |
3095 | local_irq_restore(flags); | |
1da177e4 LT |
3096 | } |
3097 | ||
3098 | /* | |
af174783 MR |
3099 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3100 | * to devices. However there may be an I/O APIC pin available for | |
3101 | * this interrupt regardless. The pin may be left unconnected, but | |
3102 | * typically it will be reused as an ExtINT cascade interrupt for | |
3103 | * the master 8259A. In the MPS case such a pin will normally be | |
3104 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3105 | * there is no provision for ExtINT interrupts, and in the absence | |
3106 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3107 | * interrupt, that is edge-triggered and unmasked by default. We | |
3108 | * used to do this, but it caused problems on some systems because | |
3109 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3110 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3111 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3112 | * the I/O APIC in all cases now. No actual device should request | |
3113 | * it anyway. --macro | |
1da177e4 | 3114 | */ |
bc07844a | 3115 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3116 | |
3117 | void __init setup_IO_APIC(void) | |
3118 | { | |
54168ed7 | 3119 | |
54168ed7 IM |
3120 | /* |
3121 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3122 | */ | |
b81bb373 | 3123 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3124 | |
54168ed7 | 3125 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3126 | /* |
54168ed7 IM |
3127 | * Set up IO-APIC IRQ routing. |
3128 | */ | |
de934103 TG |
3129 | x86_init.mpparse.setup_ioapic_ids(); |
3130 | ||
1da177e4 LT |
3131 | sync_Arb_IDs(); |
3132 | setup_IO_APIC_irqs(); | |
3133 | init_IO_APIC_traps(); | |
b81bb373 | 3134 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3135 | check_timer(); |
1da177e4 LT |
3136 | } |
3137 | ||
3138 | /* | |
54168ed7 IM |
3139 | * Called after all the initialization is done. If we didnt find any |
3140 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3141 | */ |
36062448 | 3142 | |
1da177e4 LT |
3143 | static int __init io_apic_bug_finalize(void) |
3144 | { | |
d6c88a50 TG |
3145 | if (sis_apic_bug == -1) |
3146 | sis_apic_bug = 0; | |
3147 | return 0; | |
1da177e4 LT |
3148 | } |
3149 | ||
3150 | late_initcall(io_apic_bug_finalize); | |
3151 | ||
3152 | struct sysfs_ioapic_data { | |
3153 | struct sys_device dev; | |
3154 | struct IO_APIC_route_entry entry[0]; | |
3155 | }; | |
54168ed7 | 3156 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3157 | |
438510f6 | 3158 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3159 | { |
3160 | struct IO_APIC_route_entry *entry; | |
3161 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3162 | int i; |
36062448 | 3163 | |
1da177e4 LT |
3164 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3165 | entry = data->entry; | |
54168ed7 IM |
3166 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3167 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3168 | |
3169 | return 0; | |
3170 | } | |
3171 | ||
3172 | static int ioapic_resume(struct sys_device *dev) | |
3173 | { | |
3174 | struct IO_APIC_route_entry *entry; | |
3175 | struct sysfs_ioapic_data *data; | |
3176 | unsigned long flags; | |
3177 | union IO_APIC_reg_00 reg_00; | |
3178 | int i; | |
36062448 | 3179 | |
1da177e4 LT |
3180 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3181 | entry = data->entry; | |
3182 | ||
dade7716 | 3183 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3184 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3185 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3186 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3187 | io_apic_write(dev->id, 0, reg_00.raw); |
3188 | } | |
dade7716 | 3189 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3190 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3191 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3192 | |
3193 | return 0; | |
3194 | } | |
3195 | ||
3196 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3197 | .name = "ioapic", |
1da177e4 LT |
3198 | .suspend = ioapic_suspend, |
3199 | .resume = ioapic_resume, | |
3200 | }; | |
3201 | ||
3202 | static int __init ioapic_init_sysfs(void) | |
3203 | { | |
54168ed7 IM |
3204 | struct sys_device * dev; |
3205 | int i, size, error; | |
1da177e4 LT |
3206 | |
3207 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3208 | if (error) | |
3209 | return error; | |
3210 | ||
54168ed7 | 3211 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3212 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3213 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3214 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3215 | if (!mp_ioapic_data[i]) { |
3216 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3217 | continue; | |
3218 | } | |
1da177e4 | 3219 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3220 | dev->id = i; |
1da177e4 LT |
3221 | dev->cls = &ioapic_sysdev_class; |
3222 | error = sysdev_register(dev); | |
3223 | if (error) { | |
3224 | kfree(mp_ioapic_data[i]); | |
3225 | mp_ioapic_data[i] = NULL; | |
3226 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3227 | continue; | |
3228 | } | |
3229 | } | |
3230 | ||
3231 | return 0; | |
3232 | } | |
3233 | ||
3234 | device_initcall(ioapic_init_sysfs); | |
3235 | ||
3fc471ed | 3236 | /* |
95d77884 | 3237 | * Dynamic irq allocate and deallocation |
3fc471ed | 3238 | */ |
d047f53a | 3239 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3240 | { |
ace80ab7 | 3241 | /* Allocate an unused irq */ |
54168ed7 IM |
3242 | unsigned int irq; |
3243 | unsigned int new; | |
3fc471ed | 3244 | unsigned long flags; |
0b8f1efa | 3245 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3246 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3247 | |
3248 | irq = 0; | |
abcaa2b8 YL |
3249 | if (irq_want < nr_irqs_gsi) |
3250 | irq_want = nr_irqs_gsi; | |
3251 | ||
dade7716 | 3252 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3253 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3254 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3255 | if (!desc_new) { |
3256 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3257 | continue; |
0b8f1efa YL |
3258 | } |
3259 | cfg_new = desc_new->chip_data; | |
3260 | ||
3261 | if (cfg_new->vector != 0) | |
ace80ab7 | 3262 | continue; |
d047f53a | 3263 | |
15e957d0 | 3264 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3265 | cfg_new = desc_new->chip_data; |
d047f53a | 3266 | |
fe402e1f | 3267 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3268 | irq = new; |
3269 | break; | |
3270 | } | |
dade7716 | 3271 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3272 | |
ced5b697 BP |
3273 | if (irq > 0) |
3274 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3275 | |
3fc471ed EB |
3276 | return irq; |
3277 | } | |
3278 | ||
199751d7 YL |
3279 | int create_irq(void) |
3280 | { | |
d047f53a | 3281 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3282 | unsigned int irq_want; |
54168ed7 IM |
3283 | int irq; |
3284 | ||
be5d5350 | 3285 | irq_want = nr_irqs_gsi; |
d047f53a | 3286 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3287 | |
3288 | if (irq == 0) | |
3289 | irq = -1; | |
3290 | ||
3291 | return irq; | |
199751d7 YL |
3292 | } |
3293 | ||
3fc471ed EB |
3294 | void destroy_irq(unsigned int irq) |
3295 | { | |
3296 | unsigned long flags; | |
3fc471ed | 3297 | |
ced5b697 | 3298 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3299 | |
54168ed7 | 3300 | free_irte(irq); |
dade7716 | 3301 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3302 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3303 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3304 | } |
3fc471ed | 3305 | |
2d3fcc1c | 3306 | /* |
27b46d76 | 3307 | * MSI message composition |
2d3fcc1c EB |
3308 | */ |
3309 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3310 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3311 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3312 | { |
497c9a19 YL |
3313 | struct irq_cfg *cfg; |
3314 | int err; | |
2d3fcc1c EB |
3315 | unsigned dest; |
3316 | ||
f1182638 JB |
3317 | if (disable_apic) |
3318 | return -ENXIO; | |
3319 | ||
3145e941 | 3320 | cfg = irq_cfg(irq); |
fe402e1f | 3321 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3322 | if (err) |
3323 | return err; | |
2d3fcc1c | 3324 | |
debccb3e | 3325 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3326 | |
54168ed7 IM |
3327 | if (irq_remapped(irq)) { |
3328 | struct irte irte; | |
3329 | int ir_index; | |
3330 | u16 sub_handle; | |
3331 | ||
3332 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3333 | BUG_ON(ir_index == -1); | |
3334 | ||
3335 | memset (&irte, 0, sizeof(irte)); | |
3336 | ||
3337 | irte.present = 1; | |
9b5bc8dc | 3338 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3339 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3340 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3341 | irte.vector = cfg->vector; |
3342 | irte.dest_id = IRTE_DEST(dest); | |
3343 | ||
f007e99c | 3344 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3345 | if (pdev) |
3346 | set_msi_sid(&irte, pdev); | |
3347 | else | |
3348 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3349 | |
54168ed7 IM |
3350 | modify_irte(irq, &irte); |
3351 | ||
3352 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3353 | msg->data = sub_handle; | |
3354 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3355 | MSI_ADDR_IR_SHV | | |
3356 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3357 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3358 | } else { |
9d783ba0 SS |
3359 | if (x2apic_enabled()) |
3360 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3361 | MSI_ADDR_EXT_DEST_ID(dest); | |
3362 | else | |
3363 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3364 | ||
54168ed7 IM |
3365 | msg->address_lo = |
3366 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3367 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3368 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3369 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3370 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3371 | MSI_ADDR_REDIRECTION_CPU: |
3372 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3373 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3374 | |
54168ed7 IM |
3375 | msg->data = |
3376 | MSI_DATA_TRIGGER_EDGE | | |
3377 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3378 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3379 | MSI_DATA_DELIVERY_FIXED: |
3380 | MSI_DATA_DELIVERY_LOWPRI) | | |
3381 | MSI_DATA_VECTOR(cfg->vector); | |
3382 | } | |
497c9a19 | 3383 | return err; |
2d3fcc1c EB |
3384 | } |
3385 | ||
3b7d1921 | 3386 | #ifdef CONFIG_SMP |
d5dedd45 | 3387 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3388 | { |
3145e941 | 3389 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3390 | struct irq_cfg *cfg; |
3b7d1921 EB |
3391 | struct msi_msg msg; |
3392 | unsigned int dest; | |
3b7d1921 | 3393 | |
18374d89 | 3394 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3395 | return -1; |
2d3fcc1c | 3396 | |
3145e941 | 3397 | cfg = desc->chip_data; |
2d3fcc1c | 3398 | |
3145e941 | 3399 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3400 | |
3401 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3402 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3403 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3404 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3405 | ||
3145e941 | 3406 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3407 | |
3408 | return 0; | |
2d3fcc1c | 3409 | } |
54168ed7 IM |
3410 | #ifdef CONFIG_INTR_REMAP |
3411 | /* | |
3412 | * Migrate the MSI irq to another cpumask. This migration is | |
3413 | * done in the process context using interrupt-remapping hardware. | |
3414 | */ | |
d5dedd45 | 3415 | static int |
e7986739 | 3416 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3417 | { |
3145e941 | 3418 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3419 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3420 | unsigned int dest; |
54168ed7 | 3421 | struct irte irte; |
54168ed7 IM |
3422 | |
3423 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3424 | return -1; |
54168ed7 | 3425 | |
18374d89 | 3426 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3427 | return -1; |
54168ed7 | 3428 | |
54168ed7 IM |
3429 | irte.vector = cfg->vector; |
3430 | irte.dest_id = IRTE_DEST(dest); | |
3431 | ||
3432 | /* | |
3433 | * atomically update the IRTE with the new destination and vector. | |
3434 | */ | |
3435 | modify_irte(irq, &irte); | |
3436 | ||
3437 | /* | |
3438 | * After this point, all the interrupts will start arriving | |
3439 | * at the new destination. So, time to cleanup the previous | |
3440 | * vector allocation. | |
3441 | */ | |
22f65d31 MT |
3442 | if (cfg->move_in_progress) |
3443 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3444 | |
3445 | return 0; | |
54168ed7 | 3446 | } |
3145e941 | 3447 | |
54168ed7 | 3448 | #endif |
3b7d1921 | 3449 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3450 | |
3b7d1921 EB |
3451 | /* |
3452 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3453 | * which implement the MSI or MSI-X Capability Structure. | |
3454 | */ | |
3455 | static struct irq_chip msi_chip = { | |
3456 | .name = "PCI-MSI", | |
3457 | .unmask = unmask_msi_irq, | |
3458 | .mask = mask_msi_irq, | |
1d025192 | 3459 | .ack = ack_apic_edge, |
3b7d1921 EB |
3460 | #ifdef CONFIG_SMP |
3461 | .set_affinity = set_msi_irq_affinity, | |
3462 | #endif | |
3463 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3464 | }; |
3465 | ||
54168ed7 IM |
3466 | static struct irq_chip msi_ir_chip = { |
3467 | .name = "IR-PCI-MSI", | |
3468 | .unmask = unmask_msi_irq, | |
3469 | .mask = mask_msi_irq, | |
a1e38ca5 | 3470 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3471 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3472 | #ifdef CONFIG_SMP |
3473 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3474 | #endif |
54168ed7 IM |
3475 | #endif |
3476 | .retrigger = ioapic_retrigger_irq, | |
3477 | }; | |
3478 | ||
3479 | /* | |
3480 | * Map the PCI dev to the corresponding remapping hardware unit | |
3481 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3482 | * in it. | |
3483 | */ | |
3484 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3485 | { | |
3486 | struct intel_iommu *iommu; | |
3487 | int index; | |
3488 | ||
3489 | iommu = map_dev_to_ir(dev); | |
3490 | if (!iommu) { | |
3491 | printk(KERN_ERR | |
3492 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3493 | return -ENOENT; | |
3494 | } | |
3495 | ||
3496 | index = alloc_irte(iommu, irq, nvec); | |
3497 | if (index < 0) { | |
3498 | printk(KERN_ERR | |
3499 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3500 | pci_name(dev)); |
54168ed7 IM |
3501 | return -ENOSPC; |
3502 | } | |
3503 | return index; | |
3504 | } | |
1d025192 | 3505 | |
3145e941 | 3506 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3507 | { |
3508 | int ret; | |
3509 | struct msi_msg msg; | |
3510 | ||
c8bc6f3c | 3511 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3512 | if (ret < 0) |
3513 | return ret; | |
3514 | ||
3145e941 | 3515 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3516 | write_msi_msg(irq, &msg); |
3517 | ||
54168ed7 IM |
3518 | if (irq_remapped(irq)) { |
3519 | struct irq_desc *desc = irq_to_desc(irq); | |
3520 | /* | |
3521 | * irq migration in process context | |
3522 | */ | |
3523 | desc->status |= IRQ_MOVE_PCNTXT; | |
3524 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3525 | } else | |
54168ed7 | 3526 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3527 | |
c81bba49 YL |
3528 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3529 | ||
1d025192 YL |
3530 | return 0; |
3531 | } | |
3532 | ||
047c8fdb YL |
3533 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3534 | { | |
54168ed7 IM |
3535 | unsigned int irq; |
3536 | int ret, sub_handle; | |
0b8f1efa | 3537 | struct msi_desc *msidesc; |
54168ed7 | 3538 | unsigned int irq_want; |
1cc18521 | 3539 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3540 | int index = 0; |
d047f53a | 3541 | int node; |
54168ed7 | 3542 | |
1c8d7b0a MW |
3543 | /* x86 doesn't support multiple MSI yet */ |
3544 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3545 | return 1; | |
3546 | ||
d047f53a | 3547 | node = dev_to_node(&dev->dev); |
be5d5350 | 3548 | irq_want = nr_irqs_gsi; |
54168ed7 | 3549 | sub_handle = 0; |
0b8f1efa | 3550 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3551 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3552 | if (irq == 0) |
3553 | return -1; | |
f1ee5548 | 3554 | irq_want = irq + 1; |
54168ed7 IM |
3555 | if (!intr_remapping_enabled) |
3556 | goto no_ir; | |
3557 | ||
3558 | if (!sub_handle) { | |
3559 | /* | |
3560 | * allocate the consecutive block of IRTE's | |
3561 | * for 'nvec' | |
3562 | */ | |
3563 | index = msi_alloc_irte(dev, irq, nvec); | |
3564 | if (index < 0) { | |
3565 | ret = index; | |
3566 | goto error; | |
3567 | } | |
3568 | } else { | |
3569 | iommu = map_dev_to_ir(dev); | |
3570 | if (!iommu) { | |
3571 | ret = -ENOENT; | |
3572 | goto error; | |
3573 | } | |
3574 | /* | |
3575 | * setup the mapping between the irq and the IRTE | |
3576 | * base index, the sub_handle pointing to the | |
3577 | * appropriate interrupt remap table entry. | |
3578 | */ | |
3579 | set_irte_irq(irq, iommu, index, sub_handle); | |
3580 | } | |
3581 | no_ir: | |
0b8f1efa | 3582 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3583 | if (ret < 0) |
3584 | goto error; | |
3585 | sub_handle++; | |
3586 | } | |
3587 | return 0; | |
047c8fdb YL |
3588 | |
3589 | error: | |
54168ed7 IM |
3590 | destroy_irq(irq); |
3591 | return ret; | |
047c8fdb YL |
3592 | } |
3593 | ||
3b7d1921 EB |
3594 | void arch_teardown_msi_irq(unsigned int irq) |
3595 | { | |
f7feaca7 | 3596 | destroy_irq(irq); |
3b7d1921 EB |
3597 | } |
3598 | ||
9d783ba0 | 3599 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3600 | #ifdef CONFIG_SMP |
d5dedd45 | 3601 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3602 | { |
3145e941 | 3603 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3604 | struct irq_cfg *cfg; |
3605 | struct msi_msg msg; | |
3606 | unsigned int dest; | |
54168ed7 | 3607 | |
18374d89 | 3608 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3609 | return -1; |
54168ed7 | 3610 | |
3145e941 | 3611 | cfg = desc->chip_data; |
54168ed7 IM |
3612 | |
3613 | dmar_msi_read(irq, &msg); | |
3614 | ||
3615 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3616 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3617 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3618 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3619 | ||
3620 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3621 | |
3622 | return 0; | |
54168ed7 | 3623 | } |
3145e941 | 3624 | |
54168ed7 IM |
3625 | #endif /* CONFIG_SMP */ |
3626 | ||
8f7007aa | 3627 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3628 | .name = "DMAR_MSI", |
3629 | .unmask = dmar_msi_unmask, | |
3630 | .mask = dmar_msi_mask, | |
3631 | .ack = ack_apic_edge, | |
3632 | #ifdef CONFIG_SMP | |
3633 | .set_affinity = dmar_msi_set_affinity, | |
3634 | #endif | |
3635 | .retrigger = ioapic_retrigger_irq, | |
3636 | }; | |
3637 | ||
3638 | int arch_setup_dmar_msi(unsigned int irq) | |
3639 | { | |
3640 | int ret; | |
3641 | struct msi_msg msg; | |
2d3fcc1c | 3642 | |
c8bc6f3c | 3643 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3644 | if (ret < 0) |
3645 | return ret; | |
3646 | dmar_msi_write(irq, &msg); | |
3647 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3648 | "edge"); | |
3649 | return 0; | |
3650 | } | |
3651 | #endif | |
3652 | ||
58ac1e76 | 3653 | #ifdef CONFIG_HPET_TIMER |
3654 | ||
3655 | #ifdef CONFIG_SMP | |
d5dedd45 | 3656 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3657 | { |
3145e941 | 3658 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3659 | struct irq_cfg *cfg; |
58ac1e76 | 3660 | struct msi_msg msg; |
3661 | unsigned int dest; | |
58ac1e76 | 3662 | |
18374d89 | 3663 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3664 | return -1; |
58ac1e76 | 3665 | |
3145e941 | 3666 | cfg = desc->chip_data; |
58ac1e76 | 3667 | |
3668 | hpet_msi_read(irq, &msg); | |
3669 | ||
3670 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3671 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3672 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3673 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3674 | ||
3675 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3676 | |
3677 | return 0; | |
58ac1e76 | 3678 | } |
3145e941 | 3679 | |
58ac1e76 | 3680 | #endif /* CONFIG_SMP */ |
3681 | ||
c8bc6f3c SS |
3682 | static struct irq_chip ir_hpet_msi_type = { |
3683 | .name = "IR-HPET_MSI", | |
3684 | .unmask = hpet_msi_unmask, | |
3685 | .mask = hpet_msi_mask, | |
3686 | #ifdef CONFIG_INTR_REMAP | |
3687 | .ack = ir_ack_apic_edge, | |
3688 | #ifdef CONFIG_SMP | |
3689 | .set_affinity = ir_set_msi_irq_affinity, | |
3690 | #endif | |
3691 | #endif | |
3692 | .retrigger = ioapic_retrigger_irq, | |
3693 | }; | |
3694 | ||
1cc18521 | 3695 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3696 | .name = "HPET_MSI", |
3697 | .unmask = hpet_msi_unmask, | |
3698 | .mask = hpet_msi_mask, | |
3699 | .ack = ack_apic_edge, | |
3700 | #ifdef CONFIG_SMP | |
3701 | .set_affinity = hpet_msi_set_affinity, | |
3702 | #endif | |
3703 | .retrigger = ioapic_retrigger_irq, | |
3704 | }; | |
3705 | ||
c8bc6f3c | 3706 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3707 | { |
3708 | int ret; | |
3709 | struct msi_msg msg; | |
6ec3cfec | 3710 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3711 | |
c8bc6f3c SS |
3712 | if (intr_remapping_enabled) { |
3713 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3714 | int index; | |
3715 | ||
3716 | if (!iommu) | |
3717 | return -1; | |
3718 | ||
3719 | index = alloc_irte(iommu, irq, 1); | |
3720 | if (index < 0) | |
3721 | return -1; | |
3722 | } | |
3723 | ||
3724 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3725 | if (ret < 0) |
3726 | return ret; | |
3727 | ||
3728 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3729 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3730 | if (irq_remapped(irq)) |
3731 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3732 | handle_edge_irq, "edge"); | |
3733 | else | |
3734 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3735 | handle_edge_irq, "edge"); | |
c81bba49 | 3736 | |
58ac1e76 | 3737 | return 0; |
3738 | } | |
3739 | #endif | |
3740 | ||
54168ed7 | 3741 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3742 | /* |
3743 | * Hypertransport interrupt support | |
3744 | */ | |
3745 | #ifdef CONFIG_HT_IRQ | |
3746 | ||
3747 | #ifdef CONFIG_SMP | |
3748 | ||
497c9a19 | 3749 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3750 | { |
ec68307c EB |
3751 | struct ht_irq_msg msg; |
3752 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3753 | |
497c9a19 | 3754 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3755 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3756 | |
497c9a19 | 3757 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3758 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3759 | |
ec68307c | 3760 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3761 | } |
3762 | ||
d5dedd45 | 3763 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3764 | { |
3145e941 | 3765 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3766 | struct irq_cfg *cfg; |
8b955b0d | 3767 | unsigned int dest; |
8b955b0d | 3768 | |
18374d89 | 3769 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3770 | return -1; |
8b955b0d | 3771 | |
3145e941 | 3772 | cfg = desc->chip_data; |
8b955b0d | 3773 | |
497c9a19 | 3774 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3775 | |
3776 | return 0; | |
8b955b0d | 3777 | } |
3145e941 | 3778 | |
8b955b0d EB |
3779 | #endif |
3780 | ||
c37e108d | 3781 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3782 | .name = "PCI-HT", |
3783 | .mask = mask_ht_irq, | |
3784 | .unmask = unmask_ht_irq, | |
1d025192 | 3785 | .ack = ack_apic_edge, |
8b955b0d EB |
3786 | #ifdef CONFIG_SMP |
3787 | .set_affinity = set_ht_irq_affinity, | |
3788 | #endif | |
3789 | .retrigger = ioapic_retrigger_irq, | |
3790 | }; | |
3791 | ||
3792 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3793 | { | |
497c9a19 YL |
3794 | struct irq_cfg *cfg; |
3795 | int err; | |
8b955b0d | 3796 | |
f1182638 JB |
3797 | if (disable_apic) |
3798 | return -ENXIO; | |
3799 | ||
3145e941 | 3800 | cfg = irq_cfg(irq); |
fe402e1f | 3801 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3802 | if (!err) { |
ec68307c | 3803 | struct ht_irq_msg msg; |
8b955b0d | 3804 | unsigned dest; |
8b955b0d | 3805 | |
debccb3e IM |
3806 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3807 | apic->target_cpus()); | |
8b955b0d | 3808 | |
ec68307c | 3809 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3810 | |
ec68307c EB |
3811 | msg.address_lo = |
3812 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3813 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3814 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3815 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3816 | HT_IRQ_LOW_DM_PHYSICAL : |
3817 | HT_IRQ_LOW_DM_LOGICAL) | | |
3818 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3819 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3820 | HT_IRQ_LOW_MT_FIXED : |
3821 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3822 | HT_IRQ_LOW_IRQ_MASKED; | |
3823 | ||
ec68307c | 3824 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3825 | |
a460e745 IM |
3826 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3827 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3828 | |
3829 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3830 | } |
497c9a19 | 3831 | return err; |
8b955b0d EB |
3832 | } |
3833 | #endif /* CONFIG_HT_IRQ */ | |
3834 | ||
9d6a4d08 YL |
3835 | int __init io_apic_get_redir_entries (int ioapic) |
3836 | { | |
3837 | union IO_APIC_reg_01 reg_01; | |
3838 | unsigned long flags; | |
3839 | ||
dade7716 | 3840 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3841 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3842 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3843 | |
4b6b19a1 EB |
3844 | /* The register returns the maximum index redir index |
3845 | * supported, which is one less than the total number of redir | |
3846 | * entries. | |
3847 | */ | |
3848 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3849 | } |
3850 | ||
be5d5350 | 3851 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3852 | { |
be5d5350 YL |
3853 | int nr = 0; |
3854 | ||
cc6c5006 YL |
3855 | nr = acpi_probe_gsi(); |
3856 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3857 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3858 | } else { |
3859 | /* for acpi=off or acpi is not compiled in */ | |
3860 | int idx; | |
3861 | ||
3862 | nr = 0; | |
3863 | for (idx = 0; idx < nr_ioapics; idx++) | |
4b6b19a1 | 3864 | nr += io_apic_get_redir_entries(idx); |
cc6c5006 YL |
3865 | |
3866 | if (nr > nr_irqs_gsi) | |
3867 | nr_irqs_gsi = nr; | |
3868 | } | |
3869 | ||
3870 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3871 | } |
3872 | ||
4a046d17 YL |
3873 | #ifdef CONFIG_SPARSE_IRQ |
3874 | int __init arch_probe_nr_irqs(void) | |
3875 | { | |
3876 | int nr; | |
3877 | ||
f1ee5548 YL |
3878 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3879 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3880 | |
f1ee5548 YL |
3881 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3882 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3883 | /* | |
3884 | * for MSI and HT dyn irq | |
3885 | */ | |
3886 | nr += nr_irqs_gsi * 16; | |
3887 | #endif | |
3888 | if (nr < nr_irqs) | |
4a046d17 YL |
3889 | nr_irqs = nr; |
3890 | ||
3891 | return 0; | |
3892 | } | |
3893 | #endif | |
3894 | ||
e5198075 YL |
3895 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3896 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3897 | { |
3898 | struct irq_desc *desc; | |
3899 | struct irq_cfg *cfg; | |
3900 | int node; | |
e5198075 YL |
3901 | int ioapic, pin; |
3902 | int trigger, polarity; | |
5ef21837 | 3903 | |
e5198075 | 3904 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3905 | if (!IO_APIC_IRQ(irq)) { |
3906 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3907 | ioapic); | |
3908 | return -EINVAL; | |
3909 | } | |
3910 | ||
3911 | if (dev) | |
3912 | node = dev_to_node(dev); | |
3913 | else | |
3914 | node = cpu_to_node(boot_cpu_id); | |
3915 | ||
3916 | desc = irq_to_desc_alloc_node(irq, node); | |
3917 | if (!desc) { | |
3918 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3919 | return 0; | |
3920 | } | |
3921 | ||
e5198075 YL |
3922 | pin = irq_attr->ioapic_pin; |
3923 | trigger = irq_attr->trigger; | |
3924 | polarity = irq_attr->polarity; | |
3925 | ||
5ef21837 YL |
3926 | /* |
3927 | * IRQs < 16 are already in the irq_2_pin[] map | |
3928 | */ | |
b81bb373 | 3929 | if (irq >= legacy_pic->nr_legacy_irqs) { |
5ef21837 | 3930 | cfg = desc->chip_data; |
f3d1915a CG |
3931 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3932 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3933 | pin, irq); | |
3934 | return 0; | |
3935 | } | |
5ef21837 YL |
3936 | } |
3937 | ||
e5198075 | 3938 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3939 | |
3940 | return 0; | |
3941 | } | |
3942 | ||
e5198075 YL |
3943 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3944 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3945 | { |
e5198075 | 3946 | int ioapic, pin; |
5ef21837 YL |
3947 | /* |
3948 | * Avoid pin reprogramming. PRTs typically include entries | |
3949 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3950 | * we only program the IOAPIC on the first. | |
3951 | */ | |
e5198075 YL |
3952 | ioapic = irq_attr->ioapic; |
3953 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3954 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3955 | pr_debug("Pin %d-%d already programmed\n", | |
3956 | mp_ioapics[ioapic].apicid, pin); | |
3957 | return 0; | |
3958 | } | |
3959 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3960 | ||
e5198075 | 3961 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3962 | } |
3963 | ||
2a4ab640 FT |
3964 | u8 __init io_apic_unique_id(u8 id) |
3965 | { | |
3966 | #ifdef CONFIG_X86_32 | |
3967 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3968 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3969 | return io_apic_get_unique_id(nr_ioapics, id); | |
3970 | else | |
3971 | return id; | |
3972 | #else | |
3973 | int i; | |
3974 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3975 | |
2a4ab640 FT |
3976 | bitmap_zero(used, 256); |
3977 | for (i = 0; i < nr_ioapics; i++) { | |
3978 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3979 | __set_bit(ia->apicid, used); | |
3980 | } | |
3981 | if (!test_bit(id, used)) | |
3982 | return id; | |
3983 | return find_first_zero_bit(used, 256); | |
3984 | #endif | |
3985 | } | |
1da177e4 | 3986 | |
54168ed7 | 3987 | #ifdef CONFIG_X86_32 |
36062448 | 3988 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3989 | { |
3990 | union IO_APIC_reg_00 reg_00; | |
3991 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3992 | physid_mask_t tmp; | |
3993 | unsigned long flags; | |
3994 | int i = 0; | |
3995 | ||
3996 | /* | |
36062448 PC |
3997 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3998 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3999 | * supports up to 16 on one shared APIC bus. |
36062448 | 4000 | * |
1da177e4 LT |
4001 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
4002 | * advantage of new APIC bus architecture. | |
4003 | */ | |
4004 | ||
4005 | if (physids_empty(apic_id_map)) | |
7abc0753 | 4006 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 4007 | |
dade7716 | 4008 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4009 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 4010 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4011 | |
4012 | if (apic_id >= get_physical_broadcast()) { | |
4013 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
4014 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
4015 | apic_id = reg_00.bits.ID; | |
4016 | } | |
4017 | ||
4018 | /* | |
36062448 | 4019 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
4020 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
4021 | */ | |
7abc0753 | 4022 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
4023 | |
4024 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 4025 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
4026 | break; |
4027 | } | |
4028 | ||
4029 | if (i == get_physical_broadcast()) | |
4030 | panic("Max apic_id exceeded!\n"); | |
4031 | ||
4032 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
4033 | "trying %d\n", ioapic, apic_id, i); | |
4034 | ||
4035 | apic_id = i; | |
36062448 | 4036 | } |
1da177e4 | 4037 | |
7abc0753 | 4038 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
4039 | physids_or(apic_id_map, apic_id_map, tmp); |
4040 | ||
4041 | if (reg_00.bits.ID != apic_id) { | |
4042 | reg_00.bits.ID = apic_id; | |
4043 | ||
dade7716 | 4044 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
4045 | io_apic_write(ioapic, 0, reg_00.raw); |
4046 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 4047 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4048 | |
4049 | /* Sanity check */ | |
6070f9ec AD |
4050 | if (reg_00.bits.ID != apic_id) { |
4051 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4052 | return -1; | |
4053 | } | |
1da177e4 LT |
4054 | } |
4055 | ||
4056 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4057 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4058 | ||
4059 | return apic_id; | |
4060 | } | |
58f892e0 | 4061 | #endif |
1da177e4 | 4062 | |
36062448 | 4063 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4064 | { |
4065 | union IO_APIC_reg_01 reg_01; | |
4066 | unsigned long flags; | |
4067 | ||
dade7716 | 4068 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4069 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4070 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4071 | |
4072 | return reg_01.bits.version; | |
4073 | } | |
4074 | ||
9a0a91bb | 4075 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4076 | { |
9a0a91bb | 4077 | int ioapic, pin, idx; |
61fd47e0 SL |
4078 | |
4079 | if (skip_ioapic_setup) | |
4080 | return -1; | |
4081 | ||
9a0a91bb EB |
4082 | ioapic = mp_find_ioapic(gsi); |
4083 | if (ioapic < 0) | |
4084 | return -1; | |
4085 | ||
4086 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
4087 | if (pin < 0) | |
4088 | return -1; | |
4089 | ||
4090 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4091 | if (idx < 0) | |
61fd47e0 SL |
4092 | return -1; |
4093 | ||
9a0a91bb EB |
4094 | *trigger = irq_trigger(idx); |
4095 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4096 | return 0; |
4097 | } | |
4098 | ||
497c9a19 YL |
4099 | /* |
4100 | * This function currently is only a helper for the i386 smp boot process where | |
4101 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4102 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4103 | */ |
4104 | #ifdef CONFIG_SMP | |
4105 | void __init setup_ioapic_dest(void) | |
4106 | { | |
fad53995 | 4107 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4108 | struct irq_desc *desc; |
22f65d31 | 4109 | const struct cpumask *mask; |
497c9a19 YL |
4110 | |
4111 | if (skip_ioapic_setup == 1) | |
4112 | return; | |
4113 | ||
fad53995 | 4114 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4115 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4116 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4117 | if (irq_entry == -1) | |
4118 | continue; | |
4119 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4120 | |
fad53995 EB |
4121 | if ((ioapic > 0) && (irq > 16)) |
4122 | continue; | |
4123 | ||
b9c61b70 | 4124 | desc = irq_to_desc(irq); |
6c2e9403 | 4125 | |
b9c61b70 YL |
4126 | /* |
4127 | * Honour affinities which have been set in early boot | |
4128 | */ | |
4129 | if (desc->status & | |
4130 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4131 | mask = desc->affinity; | |
4132 | else | |
4133 | mask = apic->target_cpus(); | |
497c9a19 | 4134 | |
b9c61b70 YL |
4135 | if (intr_remapping_enabled) |
4136 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4137 | else | |
4138 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4139 | } |
b9c61b70 | 4140 | |
497c9a19 YL |
4141 | } |
4142 | #endif | |
4143 | ||
54168ed7 IM |
4144 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4145 | ||
4146 | static struct resource *ioapic_resources; | |
4147 | ||
ffc43836 | 4148 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4149 | { |
4150 | unsigned long n; | |
4151 | struct resource *res; | |
4152 | char *mem; | |
4153 | int i; | |
4154 | ||
4155 | if (nr_ioapics <= 0) | |
4156 | return NULL; | |
4157 | ||
4158 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4159 | n *= nr_ioapics; | |
4160 | ||
4161 | mem = alloc_bootmem(n); | |
4162 | res = (void *)mem; | |
4163 | ||
ffc43836 | 4164 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4165 | |
ffc43836 CG |
4166 | for (i = 0; i < nr_ioapics; i++) { |
4167 | res[i].name = mem; | |
4168 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4169 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4170 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4171 | } |
4172 | ||
4173 | ioapic_resources = res; | |
4174 | ||
4175 | return res; | |
4176 | } | |
54168ed7 | 4177 | |
f3294a33 YL |
4178 | void __init ioapic_init_mappings(void) |
4179 | { | |
4180 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4181 | struct resource *ioapic_res; |
d6c88a50 | 4182 | int i; |
f3294a33 | 4183 | |
ffc43836 | 4184 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4185 | for (i = 0; i < nr_ioapics; i++) { |
4186 | if (smp_found_config) { | |
b5ba7e6d | 4187 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4188 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4189 | if (!ioapic_phys) { |
4190 | printk(KERN_ERR | |
4191 | "WARNING: bogus zero IO-APIC " | |
4192 | "address found in MPTABLE, " | |
4193 | "disabling IO/APIC support!\n"); | |
4194 | smp_found_config = 0; | |
4195 | skip_ioapic_setup = 1; | |
4196 | goto fake_ioapic_page; | |
4197 | } | |
54168ed7 | 4198 | #endif |
f3294a33 | 4199 | } else { |
54168ed7 | 4200 | #ifdef CONFIG_X86_32 |
f3294a33 | 4201 | fake_ioapic_page: |
54168ed7 | 4202 | #endif |
e79c65a9 | 4203 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4204 | ioapic_phys = __pa(ioapic_phys); |
4205 | } | |
4206 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4207 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4208 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4209 | ioapic_phys); | |
f3294a33 | 4210 | idx++; |
54168ed7 | 4211 | |
ffc43836 | 4212 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4213 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4214 | ioapic_res++; |
f3294a33 YL |
4215 | } |
4216 | } | |
4217 | ||
857fdc53 | 4218 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4219 | { |
4220 | int i; | |
4221 | struct resource *r = ioapic_resources; | |
4222 | ||
4223 | if (!r) { | |
857fdc53 | 4224 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4225 | printk(KERN_ERR |
4226 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4227 | return; |
54168ed7 IM |
4228 | } |
4229 | ||
4230 | for (i = 0; i < nr_ioapics; i++) { | |
4231 | insert_resource(&iomem_resource, r); | |
4232 | r++; | |
4233 | } | |
54168ed7 | 4234 | } |
2a4ab640 | 4235 | |
eddb0c55 | 4236 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4237 | { |
4238 | int i = 0; | |
4239 | ||
4240 | /* Find the IOAPIC that manages this GSI. */ | |
4241 | for (i = 0; i < nr_ioapics; i++) { | |
4242 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4243 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4244 | return i; | |
4245 | } | |
54168ed7 | 4246 | |
2a4ab640 FT |
4247 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4248 | return -1; | |
4249 | } | |
4250 | ||
eddb0c55 | 4251 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4252 | { |
4253 | if (WARN_ON(ioapic == -1)) | |
4254 | return -1; | |
4255 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4256 | return -1; | |
4257 | ||
4258 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4259 | } | |
4260 | ||
4261 | static int bad_ioapic(unsigned long address) | |
4262 | { | |
4263 | if (nr_ioapics >= MAX_IO_APICS) { | |
4264 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4265 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4266 | return 1; | |
4267 | } | |
4268 | if (!address) { | |
4269 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4270 | " found in table, skipping!\n"); | |
4271 | return 1; | |
4272 | } | |
54168ed7 IM |
4273 | return 0; |
4274 | } | |
4275 | ||
2a4ab640 FT |
4276 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4277 | { | |
4278 | int idx = 0; | |
7716a5c4 | 4279 | int entries; |
2a4ab640 FT |
4280 | |
4281 | if (bad_ioapic(address)) | |
4282 | return; | |
4283 | ||
4284 | idx = nr_ioapics; | |
4285 | ||
4286 | mp_ioapics[idx].type = MP_IOAPIC; | |
4287 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4288 | mp_ioapics[idx].apicaddr = address; | |
4289 | ||
4290 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4291 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4292 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4293 | ||
4294 | /* | |
4295 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4296 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4297 | */ | |
7716a5c4 | 4298 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4299 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4300 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4301 | ||
4302 | /* | |
4303 | * The number of IO-APIC IRQ registers (== #pins): | |
4304 | */ | |
4305 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4306 | |
5777372a EB |
4307 | if (mp_gsi_routing[idx].gsi_end > gsi_end) |
4308 | gsi_end = mp_gsi_routing[idx].gsi_end; | |
4309 | ||
2a4ab640 FT |
4310 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
4311 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4312 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4313 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4314 | ||
4315 | nr_ioapics++; | |
4316 | } | |
05ddafb1 JP |
4317 | |
4318 | /* Enable IOAPIC early just for system timer */ | |
4319 | void __init pre_init_apic_IRQ0(void) | |
4320 | { | |
4321 | struct irq_cfg *cfg; | |
4322 | struct irq_desc *desc; | |
4323 | ||
4324 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4325 | #ifndef CONFIG_SMP | |
4326 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4327 | #endif | |
4328 | desc = irq_to_desc_alloc_node(0, 0); | |
4329 | ||
4330 | setup_local_APIC(); | |
4331 | ||
4332 | cfg = irq_cfg(0); | |
4333 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4334 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4335 | ||
4336 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4337 | } |