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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 165 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
193 | cfg = desc->chip_data; | |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
0b8f1efa YL |
222 | cfg = desc->chip_data; |
223 | if (!cfg) { | |
85ac16d0 | 224 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
225 | if (!desc->chip_data) { |
226 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
227 | BUG_ON(1); | |
228 | } | |
229 | } | |
1da177e4 | 230 | |
13a0c3c2 | 231 | return 0; |
0b8f1efa | 232 | } |
0f978f45 | 233 | |
fcef5911 | 234 | /* for move_irq_desc */ |
48a1b10a | 235 | static void |
85ac16d0 | 236 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 237 | { |
48a1b10a YL |
238 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
239 | ||
240 | cfg->irq_2_pin = NULL; | |
241 | old_entry = old_cfg->irq_2_pin; | |
242 | if (!old_entry) | |
243 | return; | |
0f978f45 | 244 | |
85ac16d0 | 245 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
246 | if (!entry) |
247 | return; | |
0f978f45 | 248 | |
48a1b10a YL |
249 | entry->apic = old_entry->apic; |
250 | entry->pin = old_entry->pin; | |
251 | head = entry; | |
252 | tail = entry; | |
253 | old_entry = old_entry->next; | |
254 | while (old_entry) { | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) { |
257 | entry = head; | |
258 | while (entry) { | |
259 | head = entry->next; | |
260 | kfree(entry); | |
261 | entry = head; | |
262 | } | |
263 | /* still use the old one */ | |
264 | return; | |
265 | } | |
266 | entry->apic = old_entry->apic; | |
267 | entry->pin = old_entry->pin; | |
268 | tail->next = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | } | |
0f978f45 | 272 | |
48a1b10a YL |
273 | tail->next = NULL; |
274 | cfg->irq_2_pin = head; | |
0f978f45 | 275 | } |
0f978f45 | 276 | |
48a1b10a | 277 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 278 | { |
48a1b10a | 279 | struct irq_pin_list *entry, *next; |
0f978f45 | 280 | |
48a1b10a YL |
281 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
282 | return; | |
301e6190 | 283 | |
48a1b10a | 284 | entry = old_cfg->irq_2_pin; |
0f978f45 | 285 | |
48a1b10a YL |
286 | while (entry) { |
287 | next = entry->next; | |
288 | kfree(entry); | |
289 | entry = next; | |
290 | } | |
291 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 295 | struct irq_desc *desc, int node) |
0f978f45 | 296 | { |
48a1b10a YL |
297 | struct irq_cfg *cfg; |
298 | struct irq_cfg *old_cfg; | |
0f978f45 | 299 | |
85ac16d0 | 300 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 301 | |
48a1b10a YL |
302 | if (!cfg) |
303 | return; | |
304 | ||
305 | desc->chip_data = cfg; | |
306 | ||
307 | old_cfg = old_desc->chip_data; | |
308 | ||
1cf180c9 TG |
309 | cfg->vector = old_cfg->vector; |
310 | cfg->move_in_progress = old_cfg->move_in_progress; | |
311 | cpumask_copy(cfg->domain, old_cfg->domain); | |
312 | cpumask_copy(cfg->old_domain, old_cfg->old_domain); | |
48a1b10a | 313 | |
85ac16d0 | 314 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 315 | } |
1da177e4 | 316 | |
1cf180c9 | 317 | static void free_irq_cfg(struct irq_cfg *cfg) |
48a1b10a | 318 | { |
1cf180c9 TG |
319 | free_cpumask_var(cfg->domain); |
320 | free_cpumask_var(cfg->old_domain); | |
321 | kfree(cfg); | |
48a1b10a YL |
322 | } |
323 | ||
324 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
325 | { | |
326 | struct irq_cfg *old_cfg, *cfg; | |
327 | ||
328 | old_cfg = old_desc->chip_data; | |
329 | cfg = desc->chip_data; | |
330 | ||
331 | if (old_cfg == cfg) | |
332 | return; | |
333 | ||
334 | if (old_cfg) { | |
335 | free_irq_2_pin(old_cfg, cfg); | |
336 | free_irq_cfg(old_cfg); | |
337 | old_desc->chip_data = NULL; | |
338 | } | |
339 | } | |
fcef5911 | 340 | /* end for move_irq_desc */ |
48a1b10a | 341 | |
0b8f1efa | 342 | #else |
9338ad6f | 343 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
344 | { |
345 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 346 | } |
1da177e4 | 347 | |
0b8f1efa YL |
348 | #endif |
349 | ||
130fe05d LT |
350 | struct io_apic { |
351 | unsigned int index; | |
352 | unsigned int unused[3]; | |
353 | unsigned int data; | |
0280f7c4 SS |
354 | unsigned int unused2[11]; |
355 | unsigned int eoi; | |
130fe05d LT |
356 | }; |
357 | ||
358 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
359 | { | |
360 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 361 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
362 | } |
363 | ||
0280f7c4 SS |
364 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
365 | { | |
366 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
367 | writel(vector, &io_apic->eoi); | |
368 | } | |
369 | ||
130fe05d LT |
370 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
371 | { | |
372 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
373 | writel(reg, &io_apic->index); | |
374 | return readl(&io_apic->data); | |
375 | } | |
376 | ||
377 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
378 | { | |
379 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
380 | writel(reg, &io_apic->index); | |
381 | writel(value, &io_apic->data); | |
382 | } | |
383 | ||
384 | /* | |
385 | * Re-write a value: to be used for read-modify-write | |
386 | * cycles where the read already set up the index register. | |
387 | * | |
388 | * Older SiS APIC requires we rewrite the index register | |
389 | */ | |
390 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
391 | { | |
54168ed7 | 392 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
393 | |
394 | if (sis_apic_bug) | |
395 | writel(reg, &io_apic->index); | |
130fe05d LT |
396 | writel(value, &io_apic->data); |
397 | } | |
398 | ||
3145e941 | 399 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
400 | { |
401 | struct irq_pin_list *entry; | |
402 | unsigned long flags; | |
047c8fdb | 403 | |
dade7716 | 404 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 405 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
406 | unsigned int reg; |
407 | int pin; | |
408 | ||
047c8fdb YL |
409 | pin = entry->pin; |
410 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
411 | /* Is the remote IRR bit set? */ | |
412 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 413 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
414 | return true; |
415 | } | |
047c8fdb | 416 | } |
dade7716 | 417 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
418 | |
419 | return false; | |
420 | } | |
047c8fdb | 421 | |
cf4c6a2f AK |
422 | union entry_union { |
423 | struct { u32 w1, w2; }; | |
424 | struct IO_APIC_route_entry entry; | |
425 | }; | |
426 | ||
427 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
428 | { | |
429 | union entry_union eu; | |
430 | unsigned long flags; | |
dade7716 | 431 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
432 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
433 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 434 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
435 | return eu.entry; |
436 | } | |
437 | ||
f9dadfa7 LT |
438 | /* |
439 | * When we write a new IO APIC routing entry, we need to write the high | |
440 | * word first! If the mask bit in the low word is clear, we will enable | |
441 | * the interrupt, and we need to make sure the entry is fully populated | |
442 | * before that happens. | |
443 | */ | |
d15512f4 AK |
444 | static void |
445 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 446 | { |
50a8d4d2 F |
447 | union entry_union eu = {{0, 0}}; |
448 | ||
cf4c6a2f | 449 | eu.entry = e; |
f9dadfa7 LT |
450 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
451 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
452 | } |
453 | ||
ca97ab90 | 454 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
455 | { |
456 | unsigned long flags; | |
dade7716 | 457 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 458 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 459 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
460 | } |
461 | ||
462 | /* | |
463 | * When we mask an IO APIC routing entry, we need to write the low | |
464 | * word first, in order to set the mask bit before we change the | |
465 | * high bits! | |
466 | */ | |
467 | static void ioapic_mask_entry(int apic, int pin) | |
468 | { | |
469 | unsigned long flags; | |
470 | union entry_union eu = { .entry.mask = 1 }; | |
471 | ||
dade7716 | 472 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
473 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
474 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 475 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
476 | } |
477 | ||
1da177e4 LT |
478 | /* |
479 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
480 | * shared ISA-space IRQs, so we have to support them. We are super | |
481 | * fast in the common case, and fast for shared ISA-space IRQs. | |
482 | */ | |
f3d1915a CG |
483 | static int |
484 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 485 | { |
2977fb3f | 486 | struct irq_pin_list **last, *entry; |
0f978f45 | 487 | |
2977fb3f CG |
488 | /* don't allow duplicates */ |
489 | last = &cfg->irq_2_pin; | |
490 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 491 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 492 | return 0; |
2977fb3f | 493 | last = &entry->next; |
1da177e4 | 494 | } |
0f978f45 | 495 | |
875e68ec | 496 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 497 | if (!entry) { |
f3d1915a CG |
498 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
499 | node, apic, pin); | |
500 | return -ENOMEM; | |
a7428cd2 | 501 | } |
1da177e4 LT |
502 | entry->apic = apic; |
503 | entry->pin = pin; | |
875e68ec | 504 | |
2977fb3f | 505 | *last = entry; |
f3d1915a CG |
506 | return 0; |
507 | } | |
508 | ||
509 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
510 | { | |
511 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
512 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
513 | } |
514 | ||
515 | /* | |
516 | * Reroute an IRQ to a different pin. | |
517 | */ | |
85ac16d0 | 518 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
519 | int oldapic, int oldpin, |
520 | int newapic, int newpin) | |
1da177e4 | 521 | { |
535b6429 | 522 | struct irq_pin_list *entry; |
1da177e4 | 523 | |
2977fb3f | 524 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
525 | if (entry->apic == oldapic && entry->pin == oldpin) { |
526 | entry->apic = newapic; | |
527 | entry->pin = newpin; | |
0f978f45 | 528 | /* every one is different, right? */ |
4eea6fff | 529 | return; |
0f978f45 | 530 | } |
1da177e4 | 531 | } |
0f978f45 | 532 | |
4eea6fff JF |
533 | /* old apic/pin didn't exist, so just add new ones */ |
534 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
535 | } |
536 | ||
c29d9db3 SS |
537 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
538 | int mask_and, int mask_or, | |
539 | void (*final)(struct irq_pin_list *entry)) | |
540 | { | |
541 | unsigned int reg, pin; | |
542 | ||
543 | pin = entry->pin; | |
544 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
545 | reg &= mask_and; | |
546 | reg |= mask_or; | |
547 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
548 | if (final) | |
549 | final(entry); | |
550 | } | |
551 | ||
2f210deb JF |
552 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
553 | int mask_and, int mask_or, | |
554 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 555 | { |
87783be4 | 556 | struct irq_pin_list *entry; |
047c8fdb | 557 | |
c29d9db3 SS |
558 | for_each_irq_pin(entry, cfg->irq_2_pin) |
559 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
560 | } | |
561 | ||
562 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
563 | { | |
564 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
565 | IO_APIC_REDIR_MASKED, NULL); | |
566 | } | |
567 | ||
568 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
569 | { | |
570 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
571 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 572 | } |
047c8fdb | 573 | |
3145e941 | 574 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 575 | { |
3145e941 | 576 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 577 | } |
047c8fdb | 578 | |
7f3e632f | 579 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 580 | { |
87783be4 CG |
581 | /* |
582 | * Synchronize the IO-APIC and the CPU by doing | |
583 | * a dummy read from the IO-APIC | |
584 | */ | |
585 | struct io_apic __iomem *io_apic; | |
586 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 587 | readl(&io_apic->data); |
1da177e4 LT |
588 | } |
589 | ||
3145e941 | 590 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 591 | { |
3145e941 | 592 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 593 | } |
1da177e4 | 594 | |
3145e941 | 595 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 596 | { |
3145e941 | 597 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
598 | unsigned long flags; |
599 | ||
3145e941 YL |
600 | BUG_ON(!cfg); |
601 | ||
dade7716 | 602 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 603 | __mask_IO_APIC_irq(cfg); |
dade7716 | 604 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
605 | } |
606 | ||
3145e941 | 607 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 608 | { |
3145e941 | 609 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
610 | unsigned long flags; |
611 | ||
dade7716 | 612 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 613 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 614 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
615 | } |
616 | ||
3145e941 YL |
617 | static void mask_IO_APIC_irq(unsigned int irq) |
618 | { | |
619 | struct irq_desc *desc = irq_to_desc(irq); | |
620 | ||
621 | mask_IO_APIC_irq_desc(desc); | |
622 | } | |
623 | static void unmask_IO_APIC_irq(unsigned int irq) | |
624 | { | |
625 | struct irq_desc *desc = irq_to_desc(irq); | |
626 | ||
627 | unmask_IO_APIC_irq_desc(desc); | |
628 | } | |
629 | ||
1da177e4 LT |
630 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
631 | { | |
632 | struct IO_APIC_route_entry entry; | |
36062448 | 633 | |
1da177e4 | 634 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 635 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
636 | if (entry.delivery_mode == dest_SMI) |
637 | return; | |
1da177e4 LT |
638 | /* |
639 | * Disable it in the IO-APIC irq-routing table: | |
640 | */ | |
f9dadfa7 | 641 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
642 | } |
643 | ||
54168ed7 | 644 | static void clear_IO_APIC (void) |
1da177e4 LT |
645 | { |
646 | int apic, pin; | |
647 | ||
648 | for (apic = 0; apic < nr_ioapics; apic++) | |
649 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
650 | clear_IO_APIC_pin(apic, pin); | |
651 | } | |
652 | ||
54168ed7 | 653 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
654 | /* |
655 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
656 | * specific CPU-side IRQs. | |
657 | */ | |
658 | ||
659 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
660 | static int pirq_entries[MAX_PIRQS] = { |
661 | [0 ... MAX_PIRQS - 1] = -1 | |
662 | }; | |
1da177e4 | 663 | |
1da177e4 LT |
664 | static int __init ioapic_pirq_setup(char *str) |
665 | { | |
666 | int i, max; | |
667 | int ints[MAX_PIRQS+1]; | |
668 | ||
669 | get_options(str, ARRAY_SIZE(ints), ints); | |
670 | ||
1da177e4 LT |
671 | apic_printk(APIC_VERBOSE, KERN_INFO |
672 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
673 | max = MAX_PIRQS; | |
674 | if (ints[0] < MAX_PIRQS) | |
675 | max = ints[0]; | |
676 | ||
677 | for (i = 0; i < max; i++) { | |
678 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
679 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
680 | /* | |
681 | * PIRQs are mapped upside down, usually. | |
682 | */ | |
683 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
684 | } | |
685 | return 1; | |
686 | } | |
687 | ||
688 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
689 | #endif /* CONFIG_X86_32 */ |
690 | ||
b24696bc FY |
691 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
692 | { | |
693 | int apic; | |
694 | struct IO_APIC_route_entry **ioapic_entries; | |
695 | ||
696 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
697 | GFP_ATOMIC); | |
698 | if (!ioapic_entries) | |
699 | return 0; | |
700 | ||
701 | for (apic = 0; apic < nr_ioapics; apic++) { | |
702 | ioapic_entries[apic] = | |
703 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
704 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
705 | if (!ioapic_entries[apic]) | |
706 | goto nomem; | |
707 | } | |
708 | ||
709 | return ioapic_entries; | |
710 | ||
711 | nomem: | |
712 | while (--apic >= 0) | |
713 | kfree(ioapic_entries[apic]); | |
714 | kfree(ioapic_entries); | |
715 | ||
716 | return 0; | |
717 | } | |
54168ed7 IM |
718 | |
719 | /* | |
05c3dc2c | 720 | * Saves all the IO-APIC RTE's |
54168ed7 | 721 | */ |
b24696bc | 722 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 723 | { |
54168ed7 IM |
724 | int apic, pin; |
725 | ||
b24696bc FY |
726 | if (!ioapic_entries) |
727 | return -ENOMEM; | |
54168ed7 IM |
728 | |
729 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
730 | if (!ioapic_entries[apic]) |
731 | return -ENOMEM; | |
54168ed7 | 732 | |
05c3dc2c | 733 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 734 | ioapic_entries[apic][pin] = |
54168ed7 | 735 | ioapic_read_entry(apic, pin); |
b24696bc | 736 | } |
5ffa4eb2 | 737 | |
54168ed7 IM |
738 | return 0; |
739 | } | |
740 | ||
b24696bc FY |
741 | /* |
742 | * Mask all IO APIC entries. | |
743 | */ | |
744 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
745 | { |
746 | int apic, pin; | |
747 | ||
b24696bc FY |
748 | if (!ioapic_entries) |
749 | return; | |
750 | ||
05c3dc2c | 751 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 752 | if (!ioapic_entries[apic]) |
05c3dc2c | 753 | break; |
b24696bc | 754 | |
05c3dc2c SS |
755 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
756 | struct IO_APIC_route_entry entry; | |
757 | ||
b24696bc | 758 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
759 | if (!entry.mask) { |
760 | entry.mask = 1; | |
761 | ioapic_write_entry(apic, pin, entry); | |
762 | } | |
763 | } | |
764 | } | |
765 | } | |
766 | ||
b24696bc FY |
767 | /* |
768 | * Restore IO APIC entries which was saved in ioapic_entries. | |
769 | */ | |
770 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
771 | { |
772 | int apic, pin; | |
773 | ||
b24696bc FY |
774 | if (!ioapic_entries) |
775 | return -ENOMEM; | |
776 | ||
5ffa4eb2 | 777 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
778 | if (!ioapic_entries[apic]) |
779 | return -ENOMEM; | |
780 | ||
54168ed7 IM |
781 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
782 | ioapic_write_entry(apic, pin, | |
b24696bc | 783 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 784 | } |
b24696bc | 785 | return 0; |
54168ed7 IM |
786 | } |
787 | ||
b24696bc FY |
788 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
789 | { | |
790 | int apic; | |
791 | ||
792 | for (apic = 0; apic < nr_ioapics; apic++) | |
793 | kfree(ioapic_entries[apic]); | |
794 | ||
795 | kfree(ioapic_entries); | |
54168ed7 | 796 | } |
1da177e4 LT |
797 | |
798 | /* | |
799 | * Find the IRQ entry number of a certain pin. | |
800 | */ | |
801 | static int find_irq_entry(int apic, int pin, int type) | |
802 | { | |
803 | int i; | |
804 | ||
805 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
806 | if (mp_irqs[i].irqtype == type && |
807 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
808 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
809 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
810 | return i; |
811 | ||
812 | return -1; | |
813 | } | |
814 | ||
815 | /* | |
816 | * Find the pin to which IRQ[irq] (ISA) is connected | |
817 | */ | |
fcfd636a | 818 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
819 | { |
820 | int i; | |
821 | ||
822 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 823 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 824 | |
d27e2b8e | 825 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
826 | (mp_irqs[i].irqtype == type) && |
827 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 828 | |
c2c21745 | 829 | return mp_irqs[i].dstirq; |
1da177e4 LT |
830 | } |
831 | return -1; | |
832 | } | |
833 | ||
fcfd636a EB |
834 | static int __init find_isa_irq_apic(int irq, int type) |
835 | { | |
836 | int i; | |
837 | ||
838 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 839 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 840 | |
73b2961b | 841 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
842 | (mp_irqs[i].irqtype == type) && |
843 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
844 | break; |
845 | } | |
846 | if (i < mp_irq_entries) { | |
847 | int apic; | |
54168ed7 | 848 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 849 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
850 | return apic; |
851 | } | |
852 | } | |
853 | ||
854 | return -1; | |
855 | } | |
856 | ||
c0a282c2 | 857 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
858 | /* |
859 | * EISA Edge/Level control register, ELCR | |
860 | */ | |
861 | static int EISA_ELCR(unsigned int irq) | |
862 | { | |
b81bb373 | 863 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
864 | unsigned int port = 0x4d0 + (irq >> 3); |
865 | return (inb(port) >> (irq & 7)) & 1; | |
866 | } | |
867 | apic_printk(APIC_VERBOSE, KERN_INFO | |
868 | "Broken MPtable reports ISA irq %d\n", irq); | |
869 | return 0; | |
870 | } | |
54168ed7 | 871 | |
c0a282c2 | 872 | #endif |
1da177e4 | 873 | |
6728801d AS |
874 | /* ISA interrupts are always polarity zero edge triggered, |
875 | * when listed as conforming in the MP table. */ | |
876 | ||
877 | #define default_ISA_trigger(idx) (0) | |
878 | #define default_ISA_polarity(idx) (0) | |
879 | ||
1da177e4 LT |
880 | /* EISA interrupts are always polarity zero and can be edge or level |
881 | * trigger depending on the ELCR value. If an interrupt is listed as | |
882 | * EISA conforming in the MP table, that means its trigger type must | |
883 | * be read in from the ELCR */ | |
884 | ||
c2c21745 | 885 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 886 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
887 | |
888 | /* PCI interrupts are always polarity one level triggered, | |
889 | * when listed as conforming in the MP table. */ | |
890 | ||
891 | #define default_PCI_trigger(idx) (1) | |
892 | #define default_PCI_polarity(idx) (1) | |
893 | ||
894 | /* MCA interrupts are always polarity zero level triggered, | |
895 | * when listed as conforming in the MP table. */ | |
896 | ||
897 | #define default_MCA_trigger(idx) (1) | |
6728801d | 898 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 899 | |
61fd47e0 | 900 | static int MPBIOS_polarity(int idx) |
1da177e4 | 901 | { |
c2c21745 | 902 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
903 | int polarity; |
904 | ||
905 | /* | |
906 | * Determine IRQ line polarity (high active or low active): | |
907 | */ | |
c2c21745 | 908 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 909 | { |
54168ed7 IM |
910 | case 0: /* conforms, ie. bus-type dependent polarity */ |
911 | if (test_bit(bus, mp_bus_not_pci)) | |
912 | polarity = default_ISA_polarity(idx); | |
913 | else | |
914 | polarity = default_PCI_polarity(idx); | |
915 | break; | |
916 | case 1: /* high active */ | |
917 | { | |
918 | polarity = 0; | |
919 | break; | |
920 | } | |
921 | case 2: /* reserved */ | |
922 | { | |
923 | printk(KERN_WARNING "broken BIOS!!\n"); | |
924 | polarity = 1; | |
925 | break; | |
926 | } | |
927 | case 3: /* low active */ | |
928 | { | |
929 | polarity = 1; | |
930 | break; | |
931 | } | |
932 | default: /* invalid */ | |
933 | { | |
934 | printk(KERN_WARNING "broken BIOS!!\n"); | |
935 | polarity = 1; | |
936 | break; | |
937 | } | |
1da177e4 LT |
938 | } |
939 | return polarity; | |
940 | } | |
941 | ||
942 | static int MPBIOS_trigger(int idx) | |
943 | { | |
c2c21745 | 944 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
945 | int trigger; |
946 | ||
947 | /* | |
948 | * Determine IRQ trigger mode (edge or level sensitive): | |
949 | */ | |
c2c21745 | 950 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 951 | { |
54168ed7 IM |
952 | case 0: /* conforms, ie. bus-type dependent */ |
953 | if (test_bit(bus, mp_bus_not_pci)) | |
954 | trigger = default_ISA_trigger(idx); | |
955 | else | |
956 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 957 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
958 | switch (mp_bus_id_to_type[bus]) { |
959 | case MP_BUS_ISA: /* ISA pin */ | |
960 | { | |
961 | /* set before the switch */ | |
962 | break; | |
963 | } | |
964 | case MP_BUS_EISA: /* EISA pin */ | |
965 | { | |
966 | trigger = default_EISA_trigger(idx); | |
967 | break; | |
968 | } | |
969 | case MP_BUS_PCI: /* PCI pin */ | |
970 | { | |
971 | /* set before the switch */ | |
972 | break; | |
973 | } | |
974 | case MP_BUS_MCA: /* MCA pin */ | |
975 | { | |
976 | trigger = default_MCA_trigger(idx); | |
977 | break; | |
978 | } | |
979 | default: | |
980 | { | |
981 | printk(KERN_WARNING "broken BIOS!!\n"); | |
982 | trigger = 1; | |
983 | break; | |
984 | } | |
985 | } | |
986 | #endif | |
1da177e4 | 987 | break; |
54168ed7 | 988 | case 1: /* edge */ |
1da177e4 | 989 | { |
54168ed7 | 990 | trigger = 0; |
1da177e4 LT |
991 | break; |
992 | } | |
54168ed7 | 993 | case 2: /* reserved */ |
1da177e4 | 994 | { |
54168ed7 IM |
995 | printk(KERN_WARNING "broken BIOS!!\n"); |
996 | trigger = 1; | |
1da177e4 LT |
997 | break; |
998 | } | |
54168ed7 | 999 | case 3: /* level */ |
1da177e4 | 1000 | { |
54168ed7 | 1001 | trigger = 1; |
1da177e4 LT |
1002 | break; |
1003 | } | |
54168ed7 | 1004 | default: /* invalid */ |
1da177e4 LT |
1005 | { |
1006 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1007 | trigger = 0; |
1da177e4 LT |
1008 | break; |
1009 | } | |
1010 | } | |
1011 | return trigger; | |
1012 | } | |
1013 | ||
1014 | static inline int irq_polarity(int idx) | |
1015 | { | |
1016 | return MPBIOS_polarity(idx); | |
1017 | } | |
1018 | ||
1019 | static inline int irq_trigger(int idx) | |
1020 | { | |
1021 | return MPBIOS_trigger(idx); | |
1022 | } | |
1023 | ||
1024 | static int pin_2_irq(int idx, int apic, int pin) | |
1025 | { | |
d464207c | 1026 | int irq; |
c2c21745 | 1027 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1028 | |
1029 | /* | |
1030 | * Debugging check, we are in big trouble if this message pops up! | |
1031 | */ | |
c2c21745 | 1032 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1033 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1034 | ||
54168ed7 | 1035 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1036 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1037 | } else { |
d464207c | 1038 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
1039 | |
1040 | if (gsi >= NR_IRQS_LEGACY) | |
1041 | irq = gsi; | |
1042 | else | |
a4384df3 | 1043 | irq = gsi_top + gsi; |
1da177e4 LT |
1044 | } |
1045 | ||
54168ed7 | 1046 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1047 | /* |
1048 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1049 | */ | |
1050 | if ((pin >= 16) && (pin <= 23)) { | |
1051 | if (pirq_entries[pin-16] != -1) { | |
1052 | if (!pirq_entries[pin-16]) { | |
1053 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1054 | "disabling PIRQ%d\n", pin-16); | |
1055 | } else { | |
1056 | irq = pirq_entries[pin-16]; | |
1057 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1058 | "using PIRQ%d -> IRQ %d\n", | |
1059 | pin-16, irq); | |
1060 | } | |
1061 | } | |
1062 | } | |
54168ed7 IM |
1063 | #endif |
1064 | ||
1da177e4 LT |
1065 | return irq; |
1066 | } | |
1067 | ||
e20c06fd YL |
1068 | /* |
1069 | * Find a specific PCI IRQ entry. | |
1070 | * Not an __init, possibly needed by modules | |
1071 | */ | |
1072 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1073 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1074 | { |
1075 | int apic, i, best_guess = -1; | |
1076 | ||
1077 | apic_printk(APIC_DEBUG, | |
1078 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1079 | bus, slot, pin); | |
1080 | if (test_bit(bus, mp_bus_not_pci)) { | |
1081 | apic_printk(APIC_VERBOSE, | |
1082 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1083 | return -1; | |
1084 | } | |
1085 | for (i = 0; i < mp_irq_entries; i++) { | |
1086 | int lbus = mp_irqs[i].srcbus; | |
1087 | ||
1088 | for (apic = 0; apic < nr_ioapics; apic++) | |
1089 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1090 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1091 | break; | |
1092 | ||
1093 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1094 | !mp_irqs[i].irqtype && | |
1095 | (bus == lbus) && | |
1096 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1097 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1098 | ||
1099 | if (!(apic || IO_APIC_IRQ(irq))) | |
1100 | continue; | |
1101 | ||
1102 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1103 | set_io_apic_irq_attr(irq_attr, apic, |
1104 | mp_irqs[i].dstirq, | |
1105 | irq_trigger(i), | |
1106 | irq_polarity(i)); | |
e20c06fd YL |
1107 | return irq; |
1108 | } | |
1109 | /* | |
1110 | * Use the first all-but-pin matching entry as a | |
1111 | * best-guess fuzzy result for broken mptables. | |
1112 | */ | |
1113 | if (best_guess < 0) { | |
e5198075 YL |
1114 | set_io_apic_irq_attr(irq_attr, apic, |
1115 | mp_irqs[i].dstirq, | |
1116 | irq_trigger(i), | |
1117 | irq_polarity(i)); | |
e20c06fd YL |
1118 | best_guess = irq; |
1119 | } | |
1120 | } | |
1121 | } | |
1122 | return best_guess; | |
1123 | } | |
1124 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1125 | ||
497c9a19 YL |
1126 | void lock_vector_lock(void) |
1127 | { | |
1128 | /* Used to the online set of cpus does not change | |
1129 | * during assign_irq_vector. | |
1130 | */ | |
dade7716 | 1131 | raw_spin_lock(&vector_lock); |
497c9a19 | 1132 | } |
1da177e4 | 1133 | |
497c9a19 | 1134 | void unlock_vector_lock(void) |
1da177e4 | 1135 | { |
dade7716 | 1136 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1137 | } |
1da177e4 | 1138 | |
e7986739 MT |
1139 | static int |
1140 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1141 | { |
047c8fdb YL |
1142 | /* |
1143 | * NOTE! The local APIC isn't very good at handling | |
1144 | * multiple interrupts at the same interrupt level. | |
1145 | * As the interrupt level is determined by taking the | |
1146 | * vector number and shifting that right by 4, we | |
1147 | * want to spread these out a bit so that they don't | |
1148 | * all fall in the same interrupt level. | |
1149 | * | |
1150 | * Also, we've got to be careful not to trash gate | |
1151 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1152 | */ | |
6579b474 | 1153 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1154 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1155 | unsigned int old_vector; |
22f65d31 MT |
1156 | int cpu, err; |
1157 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1158 | |
23359a88 | 1159 | if (cfg->move_in_progress) |
54168ed7 | 1160 | return -EBUSY; |
0a1ad60d | 1161 | |
22f65d31 MT |
1162 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1163 | return -ENOMEM; | |
ace80ab7 | 1164 | |
54168ed7 IM |
1165 | old_vector = cfg->vector; |
1166 | if (old_vector) { | |
22f65d31 MT |
1167 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1168 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1169 | if (!cpumask_empty(tmp_mask)) { | |
1170 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1171 | return 0; |
22f65d31 | 1172 | } |
54168ed7 | 1173 | } |
497c9a19 | 1174 | |
e7986739 | 1175 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1176 | err = -ENOSPC; |
1177 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1178 | int new_cpu; |
1179 | int vector, offset; | |
497c9a19 | 1180 | |
e2d40b18 | 1181 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1182 | |
54168ed7 IM |
1183 | vector = current_vector; |
1184 | offset = current_offset; | |
497c9a19 | 1185 | next: |
54168ed7 IM |
1186 | vector += 8; |
1187 | if (vector >= first_system_vector) { | |
e7986739 | 1188 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1189 | offset = (offset + 1) % 8; |
6579b474 | 1190 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1191 | } |
1192 | if (unlikely(current_vector == vector)) | |
1193 | continue; | |
b77b881f YL |
1194 | |
1195 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1196 | goto next; |
b77b881f | 1197 | |
22f65d31 | 1198 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1199 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1200 | goto next; | |
1201 | /* Found one! */ | |
1202 | current_vector = vector; | |
1203 | current_offset = offset; | |
1204 | if (old_vector) { | |
1205 | cfg->move_in_progress = 1; | |
22f65d31 | 1206 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1207 | } |
22f65d31 | 1208 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1209 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1210 | cfg->vector = vector; | |
22f65d31 MT |
1211 | cpumask_copy(cfg->domain, tmp_mask); |
1212 | err = 0; | |
1213 | break; | |
54168ed7 | 1214 | } |
22f65d31 MT |
1215 | free_cpumask_var(tmp_mask); |
1216 | return err; | |
497c9a19 YL |
1217 | } |
1218 | ||
9338ad6f | 1219 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1220 | { |
1221 | int err; | |
ace80ab7 | 1222 | unsigned long flags; |
ace80ab7 | 1223 | |
dade7716 | 1224 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1225 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1226 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1227 | return err; |
1228 | } | |
1229 | ||
3145e941 | 1230 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1231 | { |
497c9a19 YL |
1232 | int cpu, vector; |
1233 | ||
497c9a19 YL |
1234 | BUG_ON(!cfg->vector); |
1235 | ||
1236 | vector = cfg->vector; | |
22f65d31 | 1237 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1238 | per_cpu(vector_irq, cpu)[vector] = -1; |
1239 | ||
1240 | cfg->vector = 0; | |
22f65d31 | 1241 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1242 | |
1243 | if (likely(!cfg->move_in_progress)) | |
1244 | return; | |
22f65d31 | 1245 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1246 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1247 | vector++) { | |
1248 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1249 | continue; | |
1250 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1255 | } |
1256 | ||
1257 | void __setup_vector_irq(int cpu) | |
1258 | { | |
1259 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1260 | int irq, vector; |
1261 | struct irq_cfg *cfg; | |
0b8f1efa | 1262 | struct irq_desc *desc; |
497c9a19 | 1263 | |
9d133e5d SS |
1264 | /* |
1265 | * vector_lock will make sure that we don't run into irq vector | |
1266 | * assignments that might be happening on another cpu in parallel, | |
1267 | * while we setup our initial vector to irq mappings. | |
1268 | */ | |
dade7716 | 1269 | raw_spin_lock(&vector_lock); |
497c9a19 | 1270 | /* Mark the inuse vectors */ |
0b8f1efa | 1271 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1272 | cfg = desc->chip_data; |
36e9e1ea SS |
1273 | |
1274 | /* | |
1275 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1276 | * will be part of the irq_cfg's domain. | |
1277 | */ | |
1278 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1279 | cpumask_set_cpu(cpu, cfg->domain); | |
1280 | ||
22f65d31 | 1281 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1282 | continue; |
1283 | vector = cfg->vector; | |
497c9a19 YL |
1284 | per_cpu(vector_irq, cpu)[vector] = irq; |
1285 | } | |
1286 | /* Mark the free vectors */ | |
1287 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1288 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1289 | if (irq < 0) | |
1290 | continue; | |
1291 | ||
1292 | cfg = irq_cfg(irq); | |
22f65d31 | 1293 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1294 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1295 | } |
dade7716 | 1296 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1297 | } |
3fde6900 | 1298 | |
f5b9ed7a | 1299 | static struct irq_chip ioapic_chip; |
54168ed7 | 1300 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1301 | |
54168ed7 IM |
1302 | #define IOAPIC_AUTO -1 |
1303 | #define IOAPIC_EDGE 0 | |
1304 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1305 | |
047c8fdb | 1306 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1307 | static inline int IO_APIC_irq_trigger(int irq) |
1308 | { | |
d6c88a50 | 1309 | int apic, idx, pin; |
1d025192 | 1310 | |
d6c88a50 TG |
1311 | for (apic = 0; apic < nr_ioapics; apic++) { |
1312 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1313 | idx = find_irq_entry(apic, pin, mp_INT); | |
1314 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1315 | return irq_trigger(idx); | |
1316 | } | |
1317 | } | |
1318 | /* | |
54168ed7 IM |
1319 | * nonexistent IRQs are edge default |
1320 | */ | |
d6c88a50 | 1321 | return 0; |
1d025192 | 1322 | } |
047c8fdb YL |
1323 | #else |
1324 | static inline int IO_APIC_irq_trigger(int irq) | |
1325 | { | |
54168ed7 | 1326 | return 1; |
047c8fdb YL |
1327 | } |
1328 | #endif | |
1d025192 | 1329 | |
3145e941 | 1330 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1331 | { |
199751d7 | 1332 | |
6ebcc00e | 1333 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1334 | trigger == IOAPIC_LEVEL) |
08678b08 | 1335 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1336 | else |
1337 | desc->status &= ~IRQ_LEVEL; | |
1338 | ||
54168ed7 IM |
1339 | if (irq_remapped(irq)) { |
1340 | desc->status |= IRQ_MOVE_PCNTXT; | |
1341 | if (trigger) | |
1342 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1343 | handle_fasteoi_irq, | |
1344 | "fasteoi"); | |
1345 | else | |
1346 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1347 | handle_edge_irq, "edge"); | |
1348 | return; | |
1349 | } | |
29b61be6 | 1350 | |
047c8fdb YL |
1351 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1352 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1353 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1354 | handle_fasteoi_irq, |
1355 | "fasteoi"); | |
047c8fdb | 1356 | else |
a460e745 | 1357 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1358 | handle_edge_irq, "edge"); |
1da177e4 LT |
1359 | } |
1360 | ||
ca97ab90 JF |
1361 | int setup_ioapic_entry(int apic_id, int irq, |
1362 | struct IO_APIC_route_entry *entry, | |
1363 | unsigned int destination, int trigger, | |
0280f7c4 | 1364 | int polarity, int vector, int pin) |
1da177e4 | 1365 | { |
497c9a19 YL |
1366 | /* |
1367 | * add it to the IO-APIC irq-routing table: | |
1368 | */ | |
1369 | memset(entry,0,sizeof(*entry)); | |
1370 | ||
54168ed7 | 1371 | if (intr_remapping_enabled) { |
c8d46cf0 | 1372 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1373 | struct irte irte; |
1374 | struct IR_IO_APIC_route_entry *ir_entry = | |
1375 | (struct IR_IO_APIC_route_entry *) entry; | |
1376 | int index; | |
1377 | ||
1378 | if (!iommu) | |
c8d46cf0 | 1379 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1380 | |
1381 | index = alloc_irte(iommu, irq, 1); | |
1382 | if (index < 0) | |
c8d46cf0 | 1383 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1384 | |
1385 | memset(&irte, 0, sizeof(irte)); | |
1386 | ||
1387 | irte.present = 1; | |
9b5bc8dc | 1388 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1389 | /* |
1390 | * Trigger mode in the IRTE will always be edge, and the | |
1391 | * actual level or edge trigger will be setup in the IO-APIC | |
1392 | * RTE. This will help simplify level triggered irq migration. | |
1393 | * For more details, see the comments above explainig IO-APIC | |
1394 | * irq migration in the presence of interrupt-remapping. | |
1395 | */ | |
1396 | irte.trigger_mode = 0; | |
9b5bc8dc | 1397 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1398 | irte.vector = vector; |
1399 | irte.dest_id = IRTE_DEST(destination); | |
1400 | ||
f007e99c WH |
1401 | /* Set source-id of interrupt request */ |
1402 | set_ioapic_sid(&irte, apic_id); | |
1403 | ||
54168ed7 IM |
1404 | modify_irte(irq, &irte); |
1405 | ||
1406 | ir_entry->index2 = (index >> 15) & 0x1; | |
1407 | ir_entry->zero = 0; | |
1408 | ir_entry->format = 1; | |
1409 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1410 | /* |
1411 | * IO-APIC RTE will be configured with virtual vector. | |
1412 | * irq handler will do the explicit EOI to the io-apic. | |
1413 | */ | |
1414 | ir_entry->vector = pin; | |
29b61be6 | 1415 | } else { |
9b5bc8dc IM |
1416 | entry->delivery_mode = apic->irq_delivery_mode; |
1417 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1418 | entry->dest = destination; |
0280f7c4 | 1419 | entry->vector = vector; |
54168ed7 | 1420 | } |
497c9a19 | 1421 | |
54168ed7 | 1422 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1423 | entry->trigger = trigger; |
1424 | entry->polarity = polarity; | |
497c9a19 YL |
1425 | |
1426 | /* Mask level triggered irqs. | |
1427 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1428 | */ | |
1429 | if (trigger) | |
1430 | entry->mask = 1; | |
497c9a19 YL |
1431 | return 0; |
1432 | } | |
1433 | ||
c8d46cf0 | 1434 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1435 | int trigger, int polarity) |
497c9a19 YL |
1436 | { |
1437 | struct irq_cfg *cfg; | |
1da177e4 | 1438 | struct IO_APIC_route_entry entry; |
22f65d31 | 1439 | unsigned int dest; |
497c9a19 YL |
1440 | |
1441 | if (!IO_APIC_IRQ(irq)) | |
1442 | return; | |
1443 | ||
3145e941 | 1444 | cfg = desc->chip_data; |
497c9a19 | 1445 | |
69c89efb SS |
1446 | /* |
1447 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1448 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1449 | * the cfg->domain. | |
1450 | */ | |
28c6a0ba | 1451 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1452 | apic->vector_allocation_domain(0, cfg->domain); |
1453 | ||
fe402e1f | 1454 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1455 | return; |
1456 | ||
debccb3e | 1457 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1458 | |
1459 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1460 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1461 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1462 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1463 | irq, trigger, polarity); |
1464 | ||
1465 | ||
c8d46cf0 | 1466 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1467 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1468 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1469 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1470 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1471 | return; |
1472 | } | |
1473 | ||
3145e941 | 1474 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 JP |
1475 | if (irq < legacy_pic->nr_legacy_irqs) |
1476 | legacy_pic->chip->mask(irq); | |
497c9a19 | 1477 | |
c8d46cf0 | 1478 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1479 | } |
1480 | ||
b9c61b70 YL |
1481 | static struct { |
1482 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1483 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1484 | ||
497c9a19 YL |
1485 | static void __init setup_IO_APIC_irqs(void) |
1486 | { | |
fad53995 | 1487 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1488 | int notcon = 0; |
0b8f1efa | 1489 | struct irq_desc *desc; |
3145e941 | 1490 | struct irq_cfg *cfg; |
85ac16d0 | 1491 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1492 | |
1493 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1494 | ||
fad53995 | 1495 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1496 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1497 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1498 | if (idx == -1) { | |
1499 | if (!notcon) { | |
1500 | notcon = 1; | |
1501 | apic_printk(APIC_VERBOSE, | |
1502 | KERN_DEBUG " %d-%d", | |
1503 | mp_ioapics[apic_id].apicid, pin); | |
1504 | } else | |
1505 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1506 | mp_ioapics[apic_id].apicid, pin); | |
1507 | continue; | |
1508 | } | |
1509 | if (notcon) { | |
1510 | apic_printk(APIC_VERBOSE, | |
1511 | " (apicid-pin) not connected\n"); | |
1512 | notcon = 0; | |
1513 | } | |
33a201fa | 1514 | |
b9c61b70 | 1515 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1516 | |
fad53995 EB |
1517 | if ((apic_id > 0) && (irq > 16)) |
1518 | continue; | |
1519 | ||
b9c61b70 YL |
1520 | /* |
1521 | * Skip the timer IRQ if there's a quirk handler | |
1522 | * installed and if it returns 1: | |
1523 | */ | |
1524 | if (apic->multi_timer_check && | |
1525 | apic->multi_timer_check(apic_id, irq)) | |
1526 | continue; | |
36062448 | 1527 | |
b9c61b70 YL |
1528 | desc = irq_to_desc_alloc_node(irq, node); |
1529 | if (!desc) { | |
1530 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1531 | continue; | |
3c2cbd24 | 1532 | } |
b9c61b70 YL |
1533 | cfg = desc->chip_data; |
1534 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1535 | /* |
1536 | * don't mark it in pin_programmed, so later acpi could | |
1537 | * set it correctly when irq < 16 | |
1538 | */ | |
b9c61b70 YL |
1539 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1540 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1541 | } |
1542 | ||
3c2cbd24 CG |
1543 | if (notcon) |
1544 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1545 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1546 | } |
1547 | ||
18dce6ba YL |
1548 | /* |
1549 | * for the gsit that is not in first ioapic | |
1550 | * but could not use acpi_register_gsi() | |
1551 | * like some special sci in IBM x3330 | |
1552 | */ | |
1553 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1554 | { | |
1555 | int apic_id = 0, pin, idx, irq; | |
1556 | int node = cpu_to_node(boot_cpu_id); | |
1557 | struct irq_desc *desc; | |
1558 | struct irq_cfg *cfg; | |
1559 | ||
1560 | /* | |
1561 | * Convert 'gsi' to 'ioapic.pin'. | |
1562 | */ | |
1563 | apic_id = mp_find_ioapic(gsi); | |
1564 | if (apic_id < 0) | |
1565 | return; | |
1566 | ||
1567 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1568 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1569 | if (idx == -1) | |
1570 | return; | |
1571 | ||
1572 | irq = pin_2_irq(idx, apic_id, pin); | |
1573 | #ifdef CONFIG_SPARSE_IRQ | |
1574 | desc = irq_to_desc(irq); | |
1575 | if (desc) | |
1576 | return; | |
1577 | #endif | |
1578 | desc = irq_to_desc_alloc_node(irq, node); | |
1579 | if (!desc) { | |
1580 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1581 | return; | |
1582 | } | |
1583 | ||
1584 | cfg = desc->chip_data; | |
1585 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
1586 | ||
1587 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1588 | pr_debug("Pin %d-%d already programmed\n", | |
1589 | mp_ioapics[apic_id].apicid, pin); | |
1590 | return; | |
1591 | } | |
1592 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1593 | ||
1594 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1595 | irq_trigger(idx), irq_polarity(idx)); | |
1596 | } | |
1597 | ||
1da177e4 | 1598 | /* |
f7633ce5 | 1599 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1600 | */ |
c8d46cf0 | 1601 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1602 | int vector) |
1da177e4 LT |
1603 | { |
1604 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1605 | |
54168ed7 IM |
1606 | if (intr_remapping_enabled) |
1607 | return; | |
54168ed7 | 1608 | |
36062448 | 1609 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1610 | |
1611 | /* | |
1612 | * We use logical delivery to get the timer IRQ | |
1613 | * to the first CPU. | |
1614 | */ | |
9b5bc8dc | 1615 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1616 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1617 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1618 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1619 | entry.polarity = 0; |
1620 | entry.trigger = 0; | |
1621 | entry.vector = vector; | |
1622 | ||
1623 | /* | |
1624 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1625 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1626 | */ |
54168ed7 | 1627 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1628 | |
1629 | /* | |
1630 | * Add it to the IO-APIC irq-routing table: | |
1631 | */ | |
c8d46cf0 | 1632 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1633 | } |
1634 | ||
32f71aff MR |
1635 | |
1636 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1637 | { |
1638 | int apic, i; | |
1639 | union IO_APIC_reg_00 reg_00; | |
1640 | union IO_APIC_reg_01 reg_01; | |
1641 | union IO_APIC_reg_02 reg_02; | |
1642 | union IO_APIC_reg_03 reg_03; | |
1643 | unsigned long flags; | |
0f978f45 | 1644 | struct irq_cfg *cfg; |
0b8f1efa | 1645 | struct irq_desc *desc; |
8f09cd20 | 1646 | unsigned int irq; |
1da177e4 | 1647 | |
36062448 | 1648 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1649 | for (i = 0; i < nr_ioapics; i++) |
1650 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1651 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1652 | |
1653 | /* | |
1654 | * We are a bit conservative about what we expect. We have to | |
1655 | * know about every hardware change ASAP. | |
1656 | */ | |
1657 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1658 | ||
1659 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1660 | ||
dade7716 | 1661 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1662 | reg_00.raw = io_apic_read(apic, 0); |
1663 | reg_01.raw = io_apic_read(apic, 1); | |
1664 | if (reg_01.bits.version >= 0x10) | |
1665 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1666 | if (reg_01.bits.version >= 0x20) |
1667 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1668 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1669 | |
54168ed7 | 1670 | printk("\n"); |
b5ba7e6d | 1671 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1672 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1673 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1674 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1675 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1676 | |
54168ed7 | 1677 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1678 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1679 | |
1680 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1681 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1682 | |
1683 | /* | |
1684 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1685 | * but the value of reg_02 is read as the previous read register | |
1686 | * value, so ignore it if reg_02 == reg_01. | |
1687 | */ | |
1688 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1689 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1690 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1691 | } |
1692 | ||
1693 | /* | |
1694 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1695 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1696 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1697 | */ | |
1698 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1699 | reg_03.raw != reg_01.raw) { | |
1700 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1701 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1702 | } |
1703 | ||
1704 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1705 | ||
d83e94ac | 1706 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1707 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1708 | |
1709 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1710 | struct IO_APIC_route_entry entry; | |
1711 | ||
cf4c6a2f | 1712 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1713 | |
54168ed7 IM |
1714 | printk(KERN_DEBUG " %02x %03X ", |
1715 | i, | |
1716 | entry.dest | |
1717 | ); | |
1da177e4 LT |
1718 | |
1719 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1720 | entry.mask, | |
1721 | entry.trigger, | |
1722 | entry.irr, | |
1723 | entry.polarity, | |
1724 | entry.delivery_status, | |
1725 | entry.dest_mode, | |
1726 | entry.delivery_mode, | |
1727 | entry.vector | |
1728 | ); | |
1729 | } | |
1730 | } | |
1da177e4 | 1731 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1732 | for_each_irq_desc(irq, desc) { |
1733 | struct irq_pin_list *entry; | |
1734 | ||
0b8f1efa | 1735 | cfg = desc->chip_data; |
05e40760 DK |
1736 | if (!cfg) |
1737 | continue; | |
0b8f1efa | 1738 | entry = cfg->irq_2_pin; |
0f978f45 | 1739 | if (!entry) |
1da177e4 | 1740 | continue; |
8f09cd20 | 1741 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1742 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1743 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1744 | printk("\n"); |
1745 | } | |
1746 | ||
1747 | printk(KERN_INFO ".................................... done.\n"); | |
1748 | ||
1749 | return; | |
1750 | } | |
1751 | ||
251e1e44 | 1752 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1753 | { |
251e1e44 | 1754 | int i; |
1da177e4 | 1755 | |
251e1e44 IM |
1756 | printk(KERN_DEBUG); |
1757 | ||
1758 | for (i = 0; i < 8; i++) | |
1759 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1760 | ||
1761 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1762 | } |
1763 | ||
32f71aff | 1764 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1765 | { |
97a52714 | 1766 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1767 | u64 icr; |
1da177e4 | 1768 | |
251e1e44 | 1769 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1770 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1771 | v = apic_read(APIC_ID); |
54168ed7 | 1772 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1773 | v = apic_read(APIC_LVR); |
1774 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1775 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1776 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1777 | |
1778 | v = apic_read(APIC_TASKPRI); | |
1779 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1780 | ||
54168ed7 | 1781 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1782 | if (!APIC_XAPIC(ver)) { |
1783 | v = apic_read(APIC_ARBPRI); | |
1784 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1785 | v & APIC_ARBPRI_MASK); | |
1786 | } | |
1da177e4 LT |
1787 | v = apic_read(APIC_PROCPRI); |
1788 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1789 | } | |
1790 | ||
a11b5abe YL |
1791 | /* |
1792 | * Remote read supported only in the 82489DX and local APIC for | |
1793 | * Pentium processors. | |
1794 | */ | |
1795 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1796 | v = apic_read(APIC_RRR); | |
1797 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1798 | } | |
1799 | ||
1da177e4 LT |
1800 | v = apic_read(APIC_LDR); |
1801 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1802 | if (!x2apic_enabled()) { |
1803 | v = apic_read(APIC_DFR); | |
1804 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1805 | } | |
1da177e4 LT |
1806 | v = apic_read(APIC_SPIV); |
1807 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1808 | ||
1809 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1810 | print_APIC_field(APIC_ISR); |
1da177e4 | 1811 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1812 | print_APIC_field(APIC_TMR); |
1da177e4 | 1813 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1814 | print_APIC_field(APIC_IRR); |
1da177e4 | 1815 | |
54168ed7 IM |
1816 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1817 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1818 | apic_write(APIC_ESR, 0); |
54168ed7 | 1819 | |
1da177e4 LT |
1820 | v = apic_read(APIC_ESR); |
1821 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1822 | } | |
1823 | ||
7ab6af7a | 1824 | icr = apic_icr_read(); |
0c425cec IM |
1825 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1826 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1827 | |
1828 | v = apic_read(APIC_LVTT); | |
1829 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1830 | ||
1831 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1832 | v = apic_read(APIC_LVTPC); | |
1833 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1834 | } | |
1835 | v = apic_read(APIC_LVT0); | |
1836 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1837 | v = apic_read(APIC_LVT1); | |
1838 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1839 | ||
1840 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1841 | v = apic_read(APIC_LVTERR); | |
1842 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1843 | } | |
1844 | ||
1845 | v = apic_read(APIC_TMICT); | |
1846 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1847 | v = apic_read(APIC_TMCCT); | |
1848 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1849 | v = apic_read(APIC_TDCR); | |
1850 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1851 | |
1852 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1853 | v = apic_read(APIC_EFEAT); | |
1854 | maxlvt = (v >> 16) & 0xff; | |
1855 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1856 | v = apic_read(APIC_ECTRL); | |
1857 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1858 | for (i = 0; i < maxlvt; i++) { | |
1859 | v = apic_read(APIC_EILVTn(i)); | |
1860 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1861 | } | |
1862 | } | |
1da177e4 LT |
1863 | printk("\n"); |
1864 | } | |
1865 | ||
2626eb2b | 1866 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1867 | { |
ffd5aae7 YL |
1868 | int cpu; |
1869 | ||
2626eb2b CG |
1870 | if (!maxcpu) |
1871 | return; | |
1872 | ||
ffd5aae7 | 1873 | preempt_disable(); |
2626eb2b CG |
1874 | for_each_online_cpu(cpu) { |
1875 | if (cpu >= maxcpu) | |
1876 | break; | |
ffd5aae7 | 1877 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1878 | } |
ffd5aae7 | 1879 | preempt_enable(); |
1da177e4 LT |
1880 | } |
1881 | ||
32f71aff | 1882 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1883 | { |
1da177e4 LT |
1884 | unsigned int v; |
1885 | unsigned long flags; | |
1886 | ||
b81bb373 | 1887 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1888 | return; |
1889 | ||
1890 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1891 | ||
5619c280 | 1892 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1893 | |
1894 | v = inb(0xa1) << 8 | inb(0x21); | |
1895 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1896 | ||
1897 | v = inb(0xa0) << 8 | inb(0x20); | |
1898 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1899 | ||
54168ed7 IM |
1900 | outb(0x0b,0xa0); |
1901 | outb(0x0b,0x20); | |
1da177e4 | 1902 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1903 | outb(0x0a,0xa0); |
1904 | outb(0x0a,0x20); | |
1da177e4 | 1905 | |
5619c280 | 1906 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1907 | |
1908 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1909 | ||
1910 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1911 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1912 | } | |
1913 | ||
2626eb2b CG |
1914 | static int __initdata show_lapic = 1; |
1915 | static __init int setup_show_lapic(char *arg) | |
1916 | { | |
1917 | int num = -1; | |
1918 | ||
1919 | if (strcmp(arg, "all") == 0) { | |
1920 | show_lapic = CONFIG_NR_CPUS; | |
1921 | } else { | |
1922 | get_option(&arg, &num); | |
1923 | if (num >= 0) | |
1924 | show_lapic = num; | |
1925 | } | |
1926 | ||
1927 | return 1; | |
1928 | } | |
1929 | __setup("show_lapic=", setup_show_lapic); | |
1930 | ||
1931 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1932 | { |
2626eb2b CG |
1933 | if (apic_verbosity == APIC_QUIET) |
1934 | return 0; | |
1935 | ||
32f71aff | 1936 | print_PIC(); |
4797f6b0 YL |
1937 | |
1938 | /* don't print out if apic is not there */ | |
8312136f | 1939 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1940 | return 0; |
1941 | ||
2626eb2b | 1942 | print_local_APICs(show_lapic); |
32f71aff MR |
1943 | print_IO_APIC(); |
1944 | ||
1945 | return 0; | |
1946 | } | |
1947 | ||
2626eb2b | 1948 | fs_initcall(print_ICs); |
32f71aff | 1949 | |
1da177e4 | 1950 | |
efa2559f YL |
1951 | /* Where if anywhere is the i8259 connect in external int mode */ |
1952 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1953 | ||
54168ed7 | 1954 | void __init enable_IO_APIC(void) |
1da177e4 | 1955 | { |
fcfd636a | 1956 | int i8259_apic, i8259_pin; |
54168ed7 | 1957 | int apic; |
bc07844a | 1958 | |
b81bb373 | 1959 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1960 | return; |
1961 | ||
54168ed7 | 1962 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1963 | int pin; |
1964 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1965 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1966 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1967 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1968 | |
fcfd636a EB |
1969 | /* If the interrupt line is enabled and in ExtInt mode |
1970 | * I have found the pin where the i8259 is connected. | |
1971 | */ | |
1972 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1973 | ioapic_i8259.apic = apic; | |
1974 | ioapic_i8259.pin = pin; | |
1975 | goto found_i8259; | |
1976 | } | |
1977 | } | |
1978 | } | |
1979 | found_i8259: | |
1980 | /* Look to see what if the MP table has reported the ExtINT */ | |
1981 | /* If we could not find the appropriate pin by looking at the ioapic | |
1982 | * the i8259 probably is not connected the ioapic but give the | |
1983 | * mptable a chance anyway. | |
1984 | */ | |
1985 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1986 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1987 | /* Trust the MP table if nothing is setup in the hardware */ | |
1988 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1989 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1990 | ioapic_i8259.pin = i8259_pin; | |
1991 | ioapic_i8259.apic = i8259_apic; | |
1992 | } | |
1993 | /* Complain if the MP table and the hardware disagree */ | |
1994 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1995 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1996 | { | |
1997 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1998 | } |
1999 | ||
2000 | /* | |
2001 | * Do not trust the IO-APIC being empty at bootup | |
2002 | */ | |
2003 | clear_IO_APIC(); | |
2004 | } | |
2005 | ||
2006 | /* | |
2007 | * Not an __init, needed by the reboot code | |
2008 | */ | |
2009 | void disable_IO_APIC(void) | |
2010 | { | |
2011 | /* | |
2012 | * Clear the IO-APIC before rebooting: | |
2013 | */ | |
2014 | clear_IO_APIC(); | |
2015 | ||
b81bb373 | 2016 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2017 | return; |
2018 | ||
650927ef | 2019 | /* |
0b968d23 | 2020 | * If the i8259 is routed through an IOAPIC |
650927ef | 2021 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2022 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2023 | * |
2024 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2025 | * as virtual wire B is little complex (need to configure both | |
2026 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2027 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2028 | */ |
7c6d9f97 | 2029 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2030 | struct IO_APIC_route_entry entry; |
650927ef EB |
2031 | |
2032 | memset(&entry, 0, sizeof(entry)); | |
2033 | entry.mask = 0; /* Enabled */ | |
2034 | entry.trigger = 0; /* Edge */ | |
2035 | entry.irr = 0; | |
2036 | entry.polarity = 0; /* High */ | |
2037 | entry.delivery_status = 0; | |
2038 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2039 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2040 | entry.vector = 0; |
54168ed7 | 2041 | entry.dest = read_apic_id(); |
650927ef EB |
2042 | |
2043 | /* | |
2044 | * Add it to the IO-APIC irq-routing table: | |
2045 | */ | |
cf4c6a2f | 2046 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2047 | } |
54168ed7 | 2048 | |
7c6d9f97 SS |
2049 | /* |
2050 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2051 | */ | |
8312136f | 2052 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2053 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2054 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2055 | } |
2056 | ||
54168ed7 | 2057 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2058 | /* |
2059 | * function to set the IO-APIC physical IDs based on the | |
2060 | * values stored in the MPC table. | |
2061 | * | |
2062 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2063 | */ | |
2064 | ||
de934103 | 2065 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2066 | { |
2067 | union IO_APIC_reg_00 reg_00; | |
2068 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2069 | int apic_id; |
1da177e4 LT |
2070 | int i; |
2071 | unsigned char old_id; | |
2072 | unsigned long flags; | |
2073 | ||
de934103 | 2074 | if (acpi_ioapic) |
d49c4288 | 2075 | return; |
ca05fea6 NP |
2076 | /* |
2077 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2078 | * no meaning without the serial APIC bus. | |
2079 | */ | |
7c5c1e42 SL |
2080 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2081 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2082 | return; |
1da177e4 LT |
2083 | /* |
2084 | * This is broken; anything with a real cpu count has to | |
2085 | * circumvent this idiocy regardless. | |
2086 | */ | |
7abc0753 | 2087 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2088 | |
2089 | /* | |
2090 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2091 | */ | |
c8d46cf0 | 2092 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2093 | |
2094 | /* Read the register 0 value */ | |
dade7716 | 2095 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2096 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2097 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2098 | |
c8d46cf0 | 2099 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2100 | |
c8d46cf0 | 2101 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2102 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2103 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2104 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2105 | reg_00.bits.ID); | |
c8d46cf0 | 2106 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2107 | } |
2108 | ||
1da177e4 LT |
2109 | /* |
2110 | * Sanity check, is the ID really free? Every APIC in a | |
2111 | * system must have a unique ID or we get lots of nice | |
2112 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2113 | */ | |
7abc0753 | 2114 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2115 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2116 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2117 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2118 | for (i = 0; i < get_physical_broadcast(); i++) |
2119 | if (!physid_isset(i, phys_id_present_map)) | |
2120 | break; | |
2121 | if (i >= get_physical_broadcast()) | |
2122 | panic("Max APIC ID exceeded!\n"); | |
2123 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2124 | i); | |
2125 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2126 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2127 | } else { |
2128 | physid_mask_t tmp; | |
7abc0753 | 2129 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2130 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2131 | "phys_id_present_map\n", | |
c8d46cf0 | 2132 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2133 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2134 | } | |
2135 | ||
2136 | ||
2137 | /* | |
2138 | * We need to adjust the IRQ routing table | |
2139 | * if the ID changed. | |
2140 | */ | |
c8d46cf0 | 2141 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2142 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2143 | if (mp_irqs[i].dstapic == old_id) |
2144 | mp_irqs[i].dstapic | |
c8d46cf0 | 2145 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2146 | |
2147 | /* | |
2148 | * Read the right value from the MPC table and | |
2149 | * write it into the ID register. | |
36062448 | 2150 | */ |
1da177e4 LT |
2151 | apic_printk(APIC_VERBOSE, KERN_INFO |
2152 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2153 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2154 | |
c8d46cf0 | 2155 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2156 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2157 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2158 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2159 | |
2160 | /* | |
2161 | * Sanity check | |
2162 | */ | |
dade7716 | 2163 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2164 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2165 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2166 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2167 | printk("could not set ID!\n"); |
2168 | else | |
2169 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2170 | } | |
2171 | } | |
54168ed7 | 2172 | #endif |
1da177e4 | 2173 | |
7ce0bcfd | 2174 | int no_timer_check __initdata; |
8542b200 ZA |
2175 | |
2176 | static int __init notimercheck(char *s) | |
2177 | { | |
2178 | no_timer_check = 1; | |
2179 | return 1; | |
2180 | } | |
2181 | __setup("no_timer_check", notimercheck); | |
2182 | ||
1da177e4 LT |
2183 | /* |
2184 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2185 | * about the timer IRQ. We do the following to work around the situation: | |
2186 | * | |
2187 | * - timer IRQ defaults to IO-APIC IRQ | |
2188 | * - if this function detects that timer IRQs are defunct, then we fall | |
2189 | * back to ISA timer IRQs | |
2190 | */ | |
f0a7a5c9 | 2191 | static int __init timer_irq_works(void) |
1da177e4 LT |
2192 | { |
2193 | unsigned long t1 = jiffies; | |
4aae0702 | 2194 | unsigned long flags; |
1da177e4 | 2195 | |
8542b200 ZA |
2196 | if (no_timer_check) |
2197 | return 1; | |
2198 | ||
4aae0702 | 2199 | local_save_flags(flags); |
1da177e4 LT |
2200 | local_irq_enable(); |
2201 | /* Let ten ticks pass... */ | |
2202 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2203 | local_irq_restore(flags); |
1da177e4 LT |
2204 | |
2205 | /* | |
2206 | * Expect a few ticks at least, to be sure some possible | |
2207 | * glue logic does not lock up after one or two first | |
2208 | * ticks in a non-ExtINT mode. Also the local APIC | |
2209 | * might have cached one ExtINT interrupt. Finally, at | |
2210 | * least one tick may be lost due to delays. | |
2211 | */ | |
54168ed7 IM |
2212 | |
2213 | /* jiffies wrap? */ | |
1d16b53e | 2214 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2215 | return 1; |
1da177e4 LT |
2216 | return 0; |
2217 | } | |
2218 | ||
2219 | /* | |
2220 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2221 | * number of pending IRQ events unhandled. These cases are very rare, | |
2222 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2223 | * better to do it this way as thus we do not have to be aware of | |
2224 | * 'pending' interrupts in the IRQ path, except at this point. | |
2225 | */ | |
2226 | /* | |
2227 | * Edge triggered needs to resend any interrupt | |
2228 | * that was delayed but this is now handled in the device | |
2229 | * independent code. | |
2230 | */ | |
2231 | ||
2232 | /* | |
2233 | * Starting up a edge-triggered IO-APIC interrupt is | |
2234 | * nasty - we need to make sure that we get the edge. | |
2235 | * If it is already asserted for some reason, we need | |
2236 | * return 1 to indicate that is was pending. | |
2237 | * | |
2238 | * This is not complete - we should be able to fake | |
2239 | * an edge even if it isn't on the 8259A... | |
2240 | */ | |
54168ed7 | 2241 | |
f5b9ed7a | 2242 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2243 | { |
2244 | int was_pending = 0; | |
2245 | unsigned long flags; | |
0b8f1efa | 2246 | struct irq_cfg *cfg; |
1da177e4 | 2247 | |
dade7716 | 2248 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 JP |
2249 | if (irq < legacy_pic->nr_legacy_irqs) { |
2250 | legacy_pic->chip->mask(irq); | |
2251 | if (legacy_pic->irq_pending(irq)) | |
1da177e4 LT |
2252 | was_pending = 1; |
2253 | } | |
0b8f1efa | 2254 | cfg = irq_cfg(irq); |
3145e941 | 2255 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 2256 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2257 | |
2258 | return was_pending; | |
2259 | } | |
2260 | ||
ace80ab7 | 2261 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2262 | { |
54168ed7 IM |
2263 | |
2264 | struct irq_cfg *cfg = irq_cfg(irq); | |
2265 | unsigned long flags; | |
2266 | ||
dade7716 | 2267 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2268 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2269 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2270 | |
2271 | return 1; | |
2272 | } | |
497c9a19 | 2273 | |
54168ed7 IM |
2274 | /* |
2275 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2276 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2277 | * handled with the level-triggered descriptor, but that one has slightly | |
2278 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2279 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2280 | * races. | |
2281 | */ | |
497c9a19 | 2282 | |
54168ed7 | 2283 | #ifdef CONFIG_SMP |
9338ad6f | 2284 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2285 | { |
2286 | cpumask_var_t cleanup_mask; | |
2287 | ||
2288 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2289 | unsigned int i; | |
e85abf8f GH |
2290 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2291 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2292 | } else { | |
2293 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2294 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2295 | free_cpumask_var(cleanup_mask); | |
2296 | } | |
2297 | cfg->move_in_progress = 0; | |
2298 | } | |
2299 | ||
4420471f | 2300 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2301 | { |
2302 | int apic, pin; | |
2303 | struct irq_pin_list *entry; | |
2304 | u8 vector = cfg->vector; | |
2305 | ||
2977fb3f | 2306 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2307 | unsigned int reg; |
2308 | ||
e85abf8f GH |
2309 | apic = entry->apic; |
2310 | pin = entry->pin; | |
2311 | /* | |
2312 | * With interrupt-remapping, destination information comes | |
2313 | * from interrupt-remapping table entry. | |
2314 | */ | |
2315 | if (!irq_remapped(irq)) | |
2316 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2317 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2318 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2319 | reg |= vector; | |
2320 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2321 | } |
2322 | } | |
2323 | ||
2324 | /* | |
2325 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2326 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2327 | * leaves desc->affinity untouched. |
2328 | */ | |
9338ad6f | 2329 | unsigned int |
18374d89 SS |
2330 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2331 | unsigned int *dest_id) | |
e85abf8f GH |
2332 | { |
2333 | struct irq_cfg *cfg; | |
2334 | unsigned int irq; | |
2335 | ||
2336 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2337 | return -1; |
e85abf8f GH |
2338 | |
2339 | irq = desc->irq; | |
2340 | cfg = desc->chip_data; | |
2341 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2342 | return -1; |
e85abf8f | 2343 | |
e85abf8f GH |
2344 | cpumask_copy(desc->affinity, mask); |
2345 | ||
18374d89 SS |
2346 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2347 | return 0; | |
e85abf8f GH |
2348 | } |
2349 | ||
4420471f | 2350 | static int |
e85abf8f GH |
2351 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2352 | { | |
2353 | struct irq_cfg *cfg; | |
2354 | unsigned long flags; | |
2355 | unsigned int dest; | |
2356 | unsigned int irq; | |
4420471f | 2357 | int ret = -1; |
e85abf8f GH |
2358 | |
2359 | irq = desc->irq; | |
2360 | cfg = desc->chip_data; | |
2361 | ||
dade7716 | 2362 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2363 | ret = set_desc_affinity(desc, mask, &dest); |
2364 | if (!ret) { | |
e85abf8f GH |
2365 | /* Only the high 8 bits are valid. */ |
2366 | dest = SET_APIC_LOGICAL_ID(dest); | |
2367 | __target_IO_APIC_irq(irq, dest, cfg); | |
2368 | } | |
dade7716 | 2369 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2370 | |
2371 | return ret; | |
e85abf8f GH |
2372 | } |
2373 | ||
4420471f | 2374 | static int |
e85abf8f GH |
2375 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2376 | { | |
2377 | struct irq_desc *desc; | |
2378 | ||
2379 | desc = irq_to_desc(irq); | |
2380 | ||
4420471f | 2381 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2382 | } |
497c9a19 | 2383 | |
54168ed7 | 2384 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2385 | |
54168ed7 IM |
2386 | /* |
2387 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2388 | * | |
0280f7c4 SS |
2389 | * For both level and edge triggered, irq migration is a simple atomic |
2390 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2391 | * |
0280f7c4 SS |
2392 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2393 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2394 | * Real vector that is used for interrupting cpu will be coming from | |
2395 | * the interrupt-remapping table entry. | |
54168ed7 | 2396 | */ |
d5dedd45 | 2397 | static int |
e7986739 | 2398 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2399 | { |
54168ed7 | 2400 | struct irq_cfg *cfg; |
54168ed7 | 2401 | struct irte irte; |
54168ed7 | 2402 | unsigned int dest; |
3145e941 | 2403 | unsigned int irq; |
d5dedd45 | 2404 | int ret = -1; |
497c9a19 | 2405 | |
22f65d31 | 2406 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2407 | return ret; |
497c9a19 | 2408 | |
3145e941 | 2409 | irq = desc->irq; |
54168ed7 | 2410 | if (get_irte(irq, &irte)) |
d5dedd45 | 2411 | return ret; |
497c9a19 | 2412 | |
3145e941 YL |
2413 | cfg = desc->chip_data; |
2414 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2415 | return ret; |
54168ed7 | 2416 | |
debccb3e | 2417 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2418 | |
54168ed7 IM |
2419 | irte.vector = cfg->vector; |
2420 | irte.dest_id = IRTE_DEST(dest); | |
2421 | ||
2422 | /* | |
2423 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2424 | */ | |
2425 | modify_irte(irq, &irte); | |
2426 | ||
22f65d31 MT |
2427 | if (cfg->move_in_progress) |
2428 | send_cleanup_vector(cfg); | |
54168ed7 | 2429 | |
7f7ace0c | 2430 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2431 | |
2432 | return 0; | |
54168ed7 IM |
2433 | } |
2434 | ||
54168ed7 IM |
2435 | /* |
2436 | * Migrates the IRQ destination in the process context. | |
2437 | */ | |
d5dedd45 | 2438 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2439 | const struct cpumask *mask) |
54168ed7 | 2440 | { |
d5dedd45 | 2441 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2442 | } |
d5dedd45 | 2443 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2444 | const struct cpumask *mask) |
3145e941 YL |
2445 | { |
2446 | struct irq_desc *desc = irq_to_desc(irq); | |
2447 | ||
d5dedd45 | 2448 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2449 | } |
29b61be6 | 2450 | #else |
d5dedd45 | 2451 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2452 | const struct cpumask *mask) |
2453 | { | |
d5dedd45 | 2454 | return 0; |
29b61be6 | 2455 | } |
54168ed7 IM |
2456 | #endif |
2457 | ||
2458 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2459 | { | |
2460 | unsigned vector, me; | |
8f2466f4 | 2461 | |
54168ed7 | 2462 | ack_APIC_irq(); |
54168ed7 | 2463 | exit_idle(); |
54168ed7 IM |
2464 | irq_enter(); |
2465 | ||
2466 | me = smp_processor_id(); | |
2467 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2468 | unsigned int irq; | |
68a8ca59 | 2469 | unsigned int irr; |
54168ed7 IM |
2470 | struct irq_desc *desc; |
2471 | struct irq_cfg *cfg; | |
2472 | irq = __get_cpu_var(vector_irq)[vector]; | |
2473 | ||
0b8f1efa YL |
2474 | if (irq == -1) |
2475 | continue; | |
2476 | ||
54168ed7 IM |
2477 | desc = irq_to_desc(irq); |
2478 | if (!desc) | |
2479 | continue; | |
2480 | ||
2481 | cfg = irq_cfg(irq); | |
239007b8 | 2482 | raw_spin_lock(&desc->lock); |
54168ed7 | 2483 | |
7f41c2e1 SS |
2484 | /* |
2485 | * Check if the irq migration is in progress. If so, we | |
2486 | * haven't received the cleanup request yet for this irq. | |
2487 | */ | |
2488 | if (cfg->move_in_progress) | |
2489 | goto unlock; | |
2490 | ||
22f65d31 | 2491 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2492 | goto unlock; |
2493 | ||
68a8ca59 SS |
2494 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2495 | /* | |
2496 | * Check if the vector that needs to be cleanedup is | |
2497 | * registered at the cpu's IRR. If so, then this is not | |
2498 | * the best time to clean it up. Lets clean it up in the | |
2499 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2500 | * to myself. | |
2501 | */ | |
2502 | if (irr & (1 << (vector % 32))) { | |
2503 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2504 | goto unlock; | |
2505 | } | |
54168ed7 | 2506 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2507 | unlock: |
239007b8 | 2508 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2509 | } |
2510 | ||
2511 | irq_exit(); | |
2512 | } | |
2513 | ||
a5e74b84 | 2514 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2515 | { |
3145e941 YL |
2516 | struct irq_desc *desc = *descp; |
2517 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2518 | unsigned me; |
54168ed7 | 2519 | |
fcef5911 | 2520 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2521 | return; |
2522 | ||
54168ed7 | 2523 | me = smp_processor_id(); |
10b888d6 | 2524 | |
fcef5911 | 2525 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2526 | send_cleanup_vector(cfg); |
497c9a19 | 2527 | } |
a5e74b84 SS |
2528 | |
2529 | static void irq_complete_move(struct irq_desc **descp) | |
2530 | { | |
2531 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2532 | } | |
2533 | ||
2534 | void irq_force_complete_move(int irq) | |
2535 | { | |
2536 | struct irq_desc *desc = irq_to_desc(irq); | |
2537 | struct irq_cfg *cfg = desc->chip_data; | |
2538 | ||
bbd391a1 PB |
2539 | if (!cfg) |
2540 | return; | |
2541 | ||
a5e74b84 SS |
2542 | __irq_complete_move(&desc, cfg->vector); |
2543 | } | |
497c9a19 | 2544 | #else |
3145e941 | 2545 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2546 | #endif |
3145e941 | 2547 | |
1d025192 YL |
2548 | static void ack_apic_edge(unsigned int irq) |
2549 | { | |
3145e941 YL |
2550 | struct irq_desc *desc = irq_to_desc(irq); |
2551 | ||
2552 | irq_complete_move(&desc); | |
1d025192 YL |
2553 | move_native_irq(irq); |
2554 | ack_APIC_irq(); | |
2555 | } | |
2556 | ||
3eb2cce8 | 2557 | atomic_t irq_mis_count; |
3eb2cce8 | 2558 | |
c29d9db3 SS |
2559 | /* |
2560 | * IO-APIC versions below 0x20 don't support EOI register. | |
2561 | * For the record, here is the information about various versions: | |
2562 | * 0Xh 82489DX | |
2563 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2564 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2565 | * 30h-FFh Reserved | |
2566 | * | |
2567 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2568 | * version as 0x2. This is an error with documentation and these ICH chips | |
2569 | * use io-apic's of version 0x20. | |
2570 | * | |
2571 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2572 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2573 | * mode to edge and then back to level, with RTE being masked during this. | |
2574 | */ | |
b3ec0a37 SS |
2575 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2576 | { | |
2577 | struct irq_pin_list *entry; | |
2578 | ||
2579 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2580 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2581 | /* | |
2582 | * Intr-remapping uses pin number as the virtual vector | |
2583 | * in the RTE. Actual vector is programmed in | |
2584 | * intr-remapping table entry. Hence for the io-apic | |
2585 | * EOI we use the pin number. | |
2586 | */ | |
2587 | if (irq_remapped(irq)) | |
2588 | io_apic_eoi(entry->apic, entry->pin); | |
2589 | else | |
2590 | io_apic_eoi(entry->apic, cfg->vector); | |
2591 | } else { | |
2592 | __mask_and_edge_IO_APIC_irq(entry); | |
2593 | __unmask_and_level_IO_APIC_irq(entry); | |
2594 | } | |
b3ec0a37 SS |
2595 | } |
2596 | } | |
2597 | ||
2598 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2599 | { | |
2600 | struct irq_cfg *cfg; | |
2601 | unsigned long flags; | |
2602 | unsigned int irq; | |
2603 | ||
2604 | irq = desc->irq; | |
2605 | cfg = desc->chip_data; | |
2606 | ||
dade7716 | 2607 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2608 | __eoi_ioapic_irq(irq, cfg); |
dade7716 | 2609 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2610 | } |
2611 | ||
047c8fdb YL |
2612 | static void ack_apic_level(unsigned int irq) |
2613 | { | |
3145e941 | 2614 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2615 | unsigned long v; |
2616 | int i; | |
3145e941 | 2617 | struct irq_cfg *cfg; |
54168ed7 | 2618 | int do_unmask_irq = 0; |
047c8fdb | 2619 | |
3145e941 | 2620 | irq_complete_move(&desc); |
047c8fdb | 2621 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2622 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2623 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2624 | do_unmask_irq = 1; |
3145e941 | 2625 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2626 | } |
047c8fdb YL |
2627 | #endif |
2628 | ||
3eb2cce8 | 2629 | /* |
916a0fe7 JF |
2630 | * It appears there is an erratum which affects at least version 0x11 |
2631 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2632 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2633 | * erroneously delivered as edge-triggered one but the respective IRR | |
2634 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2635 | * message but it will never arrive and further interrupts are blocked | |
2636 | * from the source. The exact reason is so far unknown, but the | |
2637 | * phenomenon was observed when two consecutive interrupt requests | |
2638 | * from a given source get delivered to the same CPU and the source is | |
2639 | * temporarily disabled in between. | |
2640 | * | |
2641 | * A workaround is to simulate an EOI message manually. We achieve it | |
2642 | * by setting the trigger mode to edge and then to level when the edge | |
2643 | * trigger mode gets detected in the TMR of a local APIC for a | |
2644 | * level-triggered interrupt. We mask the source for the time of the | |
2645 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2646 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2647 | * |
2648 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2649 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2650 | * destination that is handling the corresponding interrupt. This | |
2651 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2652 | * level-triggered io-apic interrupt will be seen as an edge | |
2653 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2654 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2655 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2656 | * supporting EOI register, we do an explicit EOI to clear the | |
2657 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2658 | * we use the above logic (mask+edge followed by unmask+level) from | |
2659 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2660 | */ |
3145e941 YL |
2661 | cfg = desc->chip_data; |
2662 | i = cfg->vector; | |
3eb2cce8 | 2663 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2664 | |
54168ed7 IM |
2665 | /* |
2666 | * We must acknowledge the irq before we move it or the acknowledge will | |
2667 | * not propagate properly. | |
2668 | */ | |
2669 | ack_APIC_irq(); | |
2670 | ||
1c83995b SS |
2671 | /* |
2672 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2673 | * message via io-apic EOI register write or simulating it using | |
2674 | * mask+edge followed by unnask+level logic) manually when the | |
2675 | * level triggered interrupt is seen as the edge triggered interrupt | |
2676 | * at the cpu. | |
2677 | */ | |
ca64c47c MR |
2678 | if (!(v & (1 << (i & 0x1f)))) { |
2679 | atomic_inc(&irq_mis_count); | |
2680 | ||
c29d9db3 | 2681 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2682 | } |
2683 | ||
54168ed7 IM |
2684 | /* Now we can move and renable the irq */ |
2685 | if (unlikely(do_unmask_irq)) { | |
2686 | /* Only migrate the irq if the ack has been received. | |
2687 | * | |
2688 | * On rare occasions the broadcast level triggered ack gets | |
2689 | * delayed going to ioapics, and if we reprogram the | |
2690 | * vector while Remote IRR is still set the irq will never | |
2691 | * fire again. | |
2692 | * | |
2693 | * To prevent this scenario we read the Remote IRR bit | |
2694 | * of the ioapic. This has two effects. | |
2695 | * - On any sane system the read of the ioapic will | |
2696 | * flush writes (and acks) going to the ioapic from | |
2697 | * this cpu. | |
2698 | * - We get to see if the ACK has actually been delivered. | |
2699 | * | |
2700 | * Based on failed experiments of reprogramming the | |
2701 | * ioapic entry from outside of irq context starting | |
2702 | * with masking the ioapic entry and then polling until | |
2703 | * Remote IRR was clear before reprogramming the | |
2704 | * ioapic I don't trust the Remote IRR bit to be | |
2705 | * completey accurate. | |
2706 | * | |
2707 | * However there appears to be no other way to plug | |
2708 | * this race, so if the Remote IRR bit is not | |
2709 | * accurate and is causing problems then it is a hardware bug | |
2710 | * and you can go talk to the chipset vendor about it. | |
2711 | */ | |
3145e941 YL |
2712 | cfg = desc->chip_data; |
2713 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2714 | move_masked_irq(irq); |
3145e941 | 2715 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2716 | } |
3eb2cce8 | 2717 | } |
1d025192 | 2718 | |
d0b03bd1 HW |
2719 | #ifdef CONFIG_INTR_REMAP |
2720 | static void ir_ack_apic_edge(unsigned int irq) | |
2721 | { | |
5d0ae2db | 2722 | ack_APIC_irq(); |
d0b03bd1 HW |
2723 | } |
2724 | ||
2725 | static void ir_ack_apic_level(unsigned int irq) | |
2726 | { | |
5d0ae2db WH |
2727 | struct irq_desc *desc = irq_to_desc(irq); |
2728 | ||
2729 | ack_APIC_irq(); | |
2730 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2731 | } |
2732 | #endif /* CONFIG_INTR_REMAP */ | |
2733 | ||
f5b9ed7a | 2734 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2735 | .name = "IO-APIC", |
2736 | .startup = startup_ioapic_irq, | |
2737 | .mask = mask_IO_APIC_irq, | |
2738 | .unmask = unmask_IO_APIC_irq, | |
2739 | .ack = ack_apic_edge, | |
2740 | .eoi = ack_apic_level, | |
54d5d424 | 2741 | #ifdef CONFIG_SMP |
d6c88a50 | 2742 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2743 | #endif |
ace80ab7 | 2744 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2745 | }; |
2746 | ||
54168ed7 | 2747 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2748 | .name = "IR-IO-APIC", |
2749 | .startup = startup_ioapic_irq, | |
2750 | .mask = mask_IO_APIC_irq, | |
2751 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2752 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2753 | .ack = ir_ack_apic_edge, |
2754 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2755 | #ifdef CONFIG_SMP |
d6c88a50 | 2756 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2757 | #endif |
54168ed7 IM |
2758 | #endif |
2759 | .retrigger = ioapic_retrigger_irq, | |
2760 | }; | |
1da177e4 LT |
2761 | |
2762 | static inline void init_IO_APIC_traps(void) | |
2763 | { | |
2764 | int irq; | |
08678b08 | 2765 | struct irq_desc *desc; |
da51a821 | 2766 | struct irq_cfg *cfg; |
1da177e4 LT |
2767 | |
2768 | /* | |
2769 | * NOTE! The local APIC isn't very good at handling | |
2770 | * multiple interrupts at the same interrupt level. | |
2771 | * As the interrupt level is determined by taking the | |
2772 | * vector number and shifting that right by 4, we | |
2773 | * want to spread these out a bit so that they don't | |
2774 | * all fall in the same interrupt level. | |
2775 | * | |
2776 | * Also, we've got to be careful not to trash gate | |
2777 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2778 | */ | |
0b8f1efa | 2779 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2780 | cfg = desc->chip_data; |
2781 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2782 | /* |
2783 | * Hmm.. We don't have an entry for this, | |
2784 | * so default to an old-fashioned 8259 | |
2785 | * interrupt if we can.. | |
2786 | */ | |
b81bb373 JP |
2787 | if (irq < legacy_pic->nr_legacy_irqs) |
2788 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2789 | else |
1da177e4 | 2790 | /* Strange. Oh, well.. */ |
08678b08 | 2791 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2792 | } |
2793 | } | |
2794 | } | |
2795 | ||
f5b9ed7a IM |
2796 | /* |
2797 | * The local APIC irq-chip implementation: | |
2798 | */ | |
1da177e4 | 2799 | |
36062448 | 2800 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2801 | { |
2802 | unsigned long v; | |
2803 | ||
2804 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2805 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2806 | } |
2807 | ||
36062448 | 2808 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2809 | { |
f5b9ed7a | 2810 | unsigned long v; |
1da177e4 | 2811 | |
f5b9ed7a | 2812 | v = apic_read(APIC_LVT0); |
593f4a78 | 2813 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2814 | } |
1da177e4 | 2815 | |
3145e941 | 2816 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2817 | { |
2818 | ack_APIC_irq(); | |
2819 | } | |
2820 | ||
f5b9ed7a | 2821 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2822 | .name = "local-APIC", |
f5b9ed7a IM |
2823 | .mask = mask_lapic_irq, |
2824 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2825 | .ack = ack_lapic_irq, |
1da177e4 LT |
2826 | }; |
2827 | ||
3145e941 | 2828 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2829 | { |
08678b08 | 2830 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2831 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2832 | "edge"); | |
c88ac1df MR |
2833 | } |
2834 | ||
e9427101 | 2835 | static void __init setup_nmi(void) |
1da177e4 LT |
2836 | { |
2837 | /* | |
36062448 | 2838 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2839 | * We put the 8259A master into AEOI mode and |
2840 | * unmask on all local APICs LVT0 as NMI. | |
2841 | * | |
2842 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2843 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2844 | * the NMI handler or the timer interrupt. | |
36062448 | 2845 | */ |
1da177e4 LT |
2846 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2847 | ||
e9427101 | 2848 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2849 | |
2850 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2851 | } | |
2852 | ||
2853 | /* | |
2854 | * This looks a bit hackish but it's about the only one way of sending | |
2855 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2856 | * not support the ExtINT mode, unfortunately. We need to send these | |
2857 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2858 | * 8259A interrupt line asserted until INTA. --macro | |
2859 | */ | |
28acf285 | 2860 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2861 | { |
fcfd636a | 2862 | int apic, pin, i; |
1da177e4 LT |
2863 | struct IO_APIC_route_entry entry0, entry1; |
2864 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2865 | |
fcfd636a | 2866 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2867 | if (pin == -1) { |
2868 | WARN_ON_ONCE(1); | |
2869 | return; | |
2870 | } | |
fcfd636a | 2871 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2872 | if (apic == -1) { |
2873 | WARN_ON_ONCE(1); | |
1da177e4 | 2874 | return; |
956fb531 | 2875 | } |
1da177e4 | 2876 | |
cf4c6a2f | 2877 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2878 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2879 | |
2880 | memset(&entry1, 0, sizeof(entry1)); | |
2881 | ||
2882 | entry1.dest_mode = 0; /* physical delivery */ | |
2883 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2884 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2885 | entry1.delivery_mode = dest_ExtINT; |
2886 | entry1.polarity = entry0.polarity; | |
2887 | entry1.trigger = 0; | |
2888 | entry1.vector = 0; | |
2889 | ||
cf4c6a2f | 2890 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2891 | |
2892 | save_control = CMOS_READ(RTC_CONTROL); | |
2893 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2894 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2895 | RTC_FREQ_SELECT); | |
2896 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2897 | ||
2898 | i = 100; | |
2899 | while (i-- > 0) { | |
2900 | mdelay(10); | |
2901 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2902 | i -= 10; | |
2903 | } | |
2904 | ||
2905 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2906 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2907 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2908 | |
cf4c6a2f | 2909 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2910 | } |
2911 | ||
efa2559f | 2912 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2913 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2914 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2915 | { |
2916 | disable_timer_pin_1 = 1; | |
2917 | return 0; | |
2918 | } | |
54168ed7 | 2919 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2920 | |
2921 | int timer_through_8259 __initdata; | |
2922 | ||
1da177e4 LT |
2923 | /* |
2924 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2925 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2926 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2927 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2928 | * |
2929 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2930 | */ |
8542b200 | 2931 | static inline void __init check_timer(void) |
1da177e4 | 2932 | { |
3145e941 YL |
2933 | struct irq_desc *desc = irq_to_desc(0); |
2934 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2935 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2936 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2937 | unsigned long flags; |
047c8fdb | 2938 | int no_pin1 = 0; |
4aae0702 IM |
2939 | |
2940 | local_irq_save(flags); | |
d4d25dec | 2941 | |
1da177e4 LT |
2942 | /* |
2943 | * get/set the timer IRQ vector: | |
2944 | */ | |
b81bb373 | 2945 | legacy_pic->chip->mask(0); |
fe402e1f | 2946 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2947 | |
2948 | /* | |
d11d5794 MR |
2949 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2950 | * wire has to be disabled in the local APIC. Also | |
2951 | * timer interrupts need to be acknowledged manually in | |
2952 | * the 8259A for the i82489DX when using the NMI | |
2953 | * watchdog as that APIC treats NMIs as level-triggered. | |
2954 | * The AEOI mode will finish them in the 8259A | |
2955 | * automatically. | |
1da177e4 | 2956 | */ |
593f4a78 | 2957 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2958 | legacy_pic->init(1); |
54168ed7 | 2959 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2960 | { |
2961 | unsigned int ver; | |
2962 | ||
2963 | ver = apic_read(APIC_LVR); | |
2964 | ver = GET_APIC_VERSION(ver); | |
2965 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2966 | } | |
54168ed7 | 2967 | #endif |
1da177e4 | 2968 | |
fcfd636a EB |
2969 | pin1 = find_isa_irq_pin(0, mp_INT); |
2970 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2971 | pin2 = ioapic_i8259.pin; | |
2972 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2973 | |
49a66a0b MR |
2974 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2975 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2976 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2977 | |
691874fa MR |
2978 | /* |
2979 | * Some BIOS writers are clueless and report the ExtINTA | |
2980 | * I/O APIC input from the cascaded 8259A as the timer | |
2981 | * interrupt input. So just in case, if only one pin | |
2982 | * was found above, try it both directly and through the | |
2983 | * 8259A. | |
2984 | */ | |
2985 | if (pin1 == -1) { | |
54168ed7 IM |
2986 | if (intr_remapping_enabled) |
2987 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2988 | pin1 = pin2; |
2989 | apic1 = apic2; | |
2990 | no_pin1 = 1; | |
2991 | } else if (pin2 == -1) { | |
2992 | pin2 = pin1; | |
2993 | apic2 = apic1; | |
2994 | } | |
2995 | ||
1da177e4 LT |
2996 | if (pin1 != -1) { |
2997 | /* | |
2998 | * Ok, does IRQ0 through the IOAPIC work? | |
2999 | */ | |
691874fa | 3000 | if (no_pin1) { |
85ac16d0 | 3001 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 3002 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
3003 | } else { |
3004 | /* for edge trigger, setup_IO_APIC_irq already | |
3005 | * leave it unmasked. | |
3006 | * so only need to unmask if it is level-trigger | |
3007 | * do we really have level trigger timer? | |
3008 | */ | |
3009 | int idx; | |
3010 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
3011 | if (idx != -1 && irq_trigger(idx)) | |
3012 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 3013 | } |
1da177e4 LT |
3014 | if (timer_irq_works()) { |
3015 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 3016 | setup_nmi(); |
b81bb373 | 3017 | legacy_pic->chip->unmask(0); |
1da177e4 | 3018 | } |
66759a01 CE |
3019 | if (disable_timer_pin_1 > 0) |
3020 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 3021 | goto out; |
1da177e4 | 3022 | } |
54168ed7 IM |
3023 | if (intr_remapping_enabled) |
3024 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 3025 | local_irq_disable(); |
fcfd636a | 3026 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 3027 | if (!no_pin1) |
49a66a0b MR |
3028 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
3029 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 3030 | |
49a66a0b MR |
3031 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3032 | "(IRQ0) through the 8259A ...\n"); | |
3033 | apic_printk(APIC_QUIET, KERN_INFO | |
3034 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3035 | /* |
3036 | * legacy devices should be connected to IO APIC #0 | |
3037 | */ | |
85ac16d0 | 3038 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3039 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
b81bb373 | 3040 | legacy_pic->chip->unmask(0); |
1da177e4 | 3041 | if (timer_irq_works()) { |
49a66a0b | 3042 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3043 | timer_through_8259 = 1; |
1da177e4 | 3044 | if (nmi_watchdog == NMI_IO_APIC) { |
b81bb373 | 3045 | legacy_pic->chip->mask(0); |
1da177e4 | 3046 | setup_nmi(); |
b81bb373 | 3047 | legacy_pic->chip->unmask(0); |
1da177e4 | 3048 | } |
4aae0702 | 3049 | goto out; |
1da177e4 LT |
3050 | } |
3051 | /* | |
3052 | * Cleanup, just in case ... | |
3053 | */ | |
f72dccac | 3054 | local_irq_disable(); |
b81bb373 | 3055 | legacy_pic->chip->mask(0); |
fcfd636a | 3056 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3057 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3058 | } |
1da177e4 LT |
3059 | |
3060 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3061 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3062 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3063 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3064 | } |
54168ed7 | 3065 | #ifdef CONFIG_X86_32 |
d11d5794 | 3066 | timer_ack = 0; |
54168ed7 | 3067 | #endif |
1da177e4 | 3068 | |
49a66a0b MR |
3069 | apic_printk(APIC_QUIET, KERN_INFO |
3070 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3071 | |
3145e941 | 3072 | lapic_register_intr(0, desc); |
497c9a19 | 3073 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
b81bb373 | 3074 | legacy_pic->chip->unmask(0); |
1da177e4 LT |
3075 | |
3076 | if (timer_irq_works()) { | |
49a66a0b | 3077 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3078 | goto out; |
1da177e4 | 3079 | } |
f72dccac | 3080 | local_irq_disable(); |
b81bb373 | 3081 | legacy_pic->chip->mask(0); |
497c9a19 | 3082 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3083 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3084 | |
49a66a0b MR |
3085 | apic_printk(APIC_QUIET, KERN_INFO |
3086 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3087 | |
b81bb373 JP |
3088 | legacy_pic->init(0); |
3089 | legacy_pic->make_irq(0); | |
593f4a78 | 3090 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3091 | |
3092 | unlock_ExtINT_logic(); | |
3093 | ||
3094 | if (timer_irq_works()) { | |
49a66a0b | 3095 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3096 | goto out; |
1da177e4 | 3097 | } |
f72dccac | 3098 | local_irq_disable(); |
49a66a0b | 3099 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3100 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3101 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3102 | out: |
3103 | local_irq_restore(flags); | |
1da177e4 LT |
3104 | } |
3105 | ||
3106 | /* | |
af174783 MR |
3107 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3108 | * to devices. However there may be an I/O APIC pin available for | |
3109 | * this interrupt regardless. The pin may be left unconnected, but | |
3110 | * typically it will be reused as an ExtINT cascade interrupt for | |
3111 | * the master 8259A. In the MPS case such a pin will normally be | |
3112 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3113 | * there is no provision for ExtINT interrupts, and in the absence | |
3114 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3115 | * interrupt, that is edge-triggered and unmasked by default. We | |
3116 | * used to do this, but it caused problems on some systems because | |
3117 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3118 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3119 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3120 | * the I/O APIC in all cases now. No actual device should request | |
3121 | * it anyway. --macro | |
1da177e4 | 3122 | */ |
bc07844a | 3123 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3124 | |
3125 | void __init setup_IO_APIC(void) | |
3126 | { | |
54168ed7 | 3127 | |
54168ed7 IM |
3128 | /* |
3129 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3130 | */ | |
b81bb373 | 3131 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3132 | |
54168ed7 | 3133 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3134 | /* |
54168ed7 IM |
3135 | * Set up IO-APIC IRQ routing. |
3136 | */ | |
de934103 TG |
3137 | x86_init.mpparse.setup_ioapic_ids(); |
3138 | ||
1da177e4 LT |
3139 | sync_Arb_IDs(); |
3140 | setup_IO_APIC_irqs(); | |
3141 | init_IO_APIC_traps(); | |
b81bb373 | 3142 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3143 | check_timer(); |
1da177e4 LT |
3144 | } |
3145 | ||
3146 | /* | |
54168ed7 IM |
3147 | * Called after all the initialization is done. If we didnt find any |
3148 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3149 | */ |
36062448 | 3150 | |
1da177e4 LT |
3151 | static int __init io_apic_bug_finalize(void) |
3152 | { | |
d6c88a50 TG |
3153 | if (sis_apic_bug == -1) |
3154 | sis_apic_bug = 0; | |
3155 | return 0; | |
1da177e4 LT |
3156 | } |
3157 | ||
3158 | late_initcall(io_apic_bug_finalize); | |
3159 | ||
3160 | struct sysfs_ioapic_data { | |
3161 | struct sys_device dev; | |
3162 | struct IO_APIC_route_entry entry[0]; | |
3163 | }; | |
54168ed7 | 3164 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3165 | |
438510f6 | 3166 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3167 | { |
3168 | struct IO_APIC_route_entry *entry; | |
3169 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3170 | int i; |
36062448 | 3171 | |
1da177e4 LT |
3172 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3173 | entry = data->entry; | |
54168ed7 IM |
3174 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3175 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3176 | |
3177 | return 0; | |
3178 | } | |
3179 | ||
3180 | static int ioapic_resume(struct sys_device *dev) | |
3181 | { | |
3182 | struct IO_APIC_route_entry *entry; | |
3183 | struct sysfs_ioapic_data *data; | |
3184 | unsigned long flags; | |
3185 | union IO_APIC_reg_00 reg_00; | |
3186 | int i; | |
36062448 | 3187 | |
1da177e4 LT |
3188 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3189 | entry = data->entry; | |
3190 | ||
dade7716 | 3191 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3192 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3193 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3194 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3195 | io_apic_write(dev->id, 0, reg_00.raw); |
3196 | } | |
dade7716 | 3197 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3198 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3199 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3200 | |
3201 | return 0; | |
3202 | } | |
3203 | ||
3204 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3205 | .name = "ioapic", |
1da177e4 LT |
3206 | .suspend = ioapic_suspend, |
3207 | .resume = ioapic_resume, | |
3208 | }; | |
3209 | ||
3210 | static int __init ioapic_init_sysfs(void) | |
3211 | { | |
54168ed7 IM |
3212 | struct sys_device * dev; |
3213 | int i, size, error; | |
1da177e4 LT |
3214 | |
3215 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3216 | if (error) | |
3217 | return error; | |
3218 | ||
54168ed7 | 3219 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3220 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3221 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3222 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3223 | if (!mp_ioapic_data[i]) { |
3224 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3225 | continue; | |
3226 | } | |
1da177e4 | 3227 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3228 | dev->id = i; |
1da177e4 LT |
3229 | dev->cls = &ioapic_sysdev_class; |
3230 | error = sysdev_register(dev); | |
3231 | if (error) { | |
3232 | kfree(mp_ioapic_data[i]); | |
3233 | mp_ioapic_data[i] = NULL; | |
3234 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3235 | continue; | |
3236 | } | |
3237 | } | |
3238 | ||
3239 | return 0; | |
3240 | } | |
3241 | ||
3242 | device_initcall(ioapic_init_sysfs); | |
3243 | ||
3fc471ed | 3244 | /* |
95d77884 | 3245 | * Dynamic irq allocate and deallocation |
3fc471ed | 3246 | */ |
d047f53a | 3247 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3248 | { |
ace80ab7 | 3249 | /* Allocate an unused irq */ |
54168ed7 IM |
3250 | unsigned int irq; |
3251 | unsigned int new; | |
3fc471ed | 3252 | unsigned long flags; |
0b8f1efa | 3253 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3254 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3255 | |
3256 | irq = 0; | |
abcaa2b8 YL |
3257 | if (irq_want < nr_irqs_gsi) |
3258 | irq_want = nr_irqs_gsi; | |
3259 | ||
dade7716 | 3260 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3261 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3262 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3263 | if (!desc_new) { |
3264 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3265 | continue; |
0b8f1efa YL |
3266 | } |
3267 | cfg_new = desc_new->chip_data; | |
3268 | ||
3269 | if (cfg_new->vector != 0) | |
ace80ab7 | 3270 | continue; |
d047f53a | 3271 | |
15e957d0 | 3272 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3273 | cfg_new = desc_new->chip_data; |
d047f53a | 3274 | |
fe402e1f | 3275 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3276 | irq = new; |
3277 | break; | |
3278 | } | |
dade7716 | 3279 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3280 | |
ced5b697 BP |
3281 | if (irq > 0) |
3282 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3283 | |
3fc471ed EB |
3284 | return irq; |
3285 | } | |
3286 | ||
199751d7 YL |
3287 | int create_irq(void) |
3288 | { | |
d047f53a | 3289 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3290 | unsigned int irq_want; |
54168ed7 IM |
3291 | int irq; |
3292 | ||
be5d5350 | 3293 | irq_want = nr_irqs_gsi; |
d047f53a | 3294 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3295 | |
3296 | if (irq == 0) | |
3297 | irq = -1; | |
3298 | ||
3299 | return irq; | |
199751d7 YL |
3300 | } |
3301 | ||
3fc471ed EB |
3302 | void destroy_irq(unsigned int irq) |
3303 | { | |
3304 | unsigned long flags; | |
3fc471ed | 3305 | |
ced5b697 | 3306 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3307 | |
54168ed7 | 3308 | free_irte(irq); |
dade7716 | 3309 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3310 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3311 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3312 | } |
3fc471ed | 3313 | |
2d3fcc1c | 3314 | /* |
27b46d76 | 3315 | * MSI message composition |
2d3fcc1c EB |
3316 | */ |
3317 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3318 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3319 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3320 | { |
497c9a19 YL |
3321 | struct irq_cfg *cfg; |
3322 | int err; | |
2d3fcc1c EB |
3323 | unsigned dest; |
3324 | ||
f1182638 JB |
3325 | if (disable_apic) |
3326 | return -ENXIO; | |
3327 | ||
3145e941 | 3328 | cfg = irq_cfg(irq); |
fe402e1f | 3329 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3330 | if (err) |
3331 | return err; | |
2d3fcc1c | 3332 | |
debccb3e | 3333 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3334 | |
54168ed7 IM |
3335 | if (irq_remapped(irq)) { |
3336 | struct irte irte; | |
3337 | int ir_index; | |
3338 | u16 sub_handle; | |
3339 | ||
3340 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3341 | BUG_ON(ir_index == -1); | |
3342 | ||
3343 | memset (&irte, 0, sizeof(irte)); | |
3344 | ||
3345 | irte.present = 1; | |
9b5bc8dc | 3346 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3347 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3348 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3349 | irte.vector = cfg->vector; |
3350 | irte.dest_id = IRTE_DEST(dest); | |
3351 | ||
f007e99c | 3352 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3353 | if (pdev) |
3354 | set_msi_sid(&irte, pdev); | |
3355 | else | |
3356 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3357 | |
54168ed7 IM |
3358 | modify_irte(irq, &irte); |
3359 | ||
3360 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3361 | msg->data = sub_handle; | |
3362 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3363 | MSI_ADDR_IR_SHV | | |
3364 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3365 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3366 | } else { |
9d783ba0 SS |
3367 | if (x2apic_enabled()) |
3368 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3369 | MSI_ADDR_EXT_DEST_ID(dest); | |
3370 | else | |
3371 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3372 | ||
54168ed7 IM |
3373 | msg->address_lo = |
3374 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3375 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3376 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3377 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3378 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3379 | MSI_ADDR_REDIRECTION_CPU: |
3380 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3381 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3382 | |
54168ed7 IM |
3383 | msg->data = |
3384 | MSI_DATA_TRIGGER_EDGE | | |
3385 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3386 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3387 | MSI_DATA_DELIVERY_FIXED: |
3388 | MSI_DATA_DELIVERY_LOWPRI) | | |
3389 | MSI_DATA_VECTOR(cfg->vector); | |
3390 | } | |
497c9a19 | 3391 | return err; |
2d3fcc1c EB |
3392 | } |
3393 | ||
3b7d1921 | 3394 | #ifdef CONFIG_SMP |
d5dedd45 | 3395 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3396 | { |
3145e941 | 3397 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3398 | struct irq_cfg *cfg; |
3b7d1921 EB |
3399 | struct msi_msg msg; |
3400 | unsigned int dest; | |
3b7d1921 | 3401 | |
18374d89 | 3402 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3403 | return -1; |
2d3fcc1c | 3404 | |
3145e941 | 3405 | cfg = desc->chip_data; |
2d3fcc1c | 3406 | |
30da5524 | 3407 | get_cached_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3408 | |
3409 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3410 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3411 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3412 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3413 | ||
3145e941 | 3414 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3415 | |
3416 | return 0; | |
2d3fcc1c | 3417 | } |
54168ed7 IM |
3418 | #ifdef CONFIG_INTR_REMAP |
3419 | /* | |
3420 | * Migrate the MSI irq to another cpumask. This migration is | |
3421 | * done in the process context using interrupt-remapping hardware. | |
3422 | */ | |
d5dedd45 | 3423 | static int |
e7986739 | 3424 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3425 | { |
3145e941 | 3426 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3427 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3428 | unsigned int dest; |
54168ed7 | 3429 | struct irte irte; |
54168ed7 IM |
3430 | |
3431 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3432 | return -1; |
54168ed7 | 3433 | |
18374d89 | 3434 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3435 | return -1; |
54168ed7 | 3436 | |
54168ed7 IM |
3437 | irte.vector = cfg->vector; |
3438 | irte.dest_id = IRTE_DEST(dest); | |
3439 | ||
3440 | /* | |
3441 | * atomically update the IRTE with the new destination and vector. | |
3442 | */ | |
3443 | modify_irte(irq, &irte); | |
3444 | ||
3445 | /* | |
3446 | * After this point, all the interrupts will start arriving | |
3447 | * at the new destination. So, time to cleanup the previous | |
3448 | * vector allocation. | |
3449 | */ | |
22f65d31 MT |
3450 | if (cfg->move_in_progress) |
3451 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3452 | |
3453 | return 0; | |
54168ed7 | 3454 | } |
3145e941 | 3455 | |
54168ed7 | 3456 | #endif |
3b7d1921 | 3457 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3458 | |
3b7d1921 EB |
3459 | /* |
3460 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3461 | * which implement the MSI or MSI-X Capability Structure. | |
3462 | */ | |
3463 | static struct irq_chip msi_chip = { | |
3464 | .name = "PCI-MSI", | |
3465 | .unmask = unmask_msi_irq, | |
3466 | .mask = mask_msi_irq, | |
1d025192 | 3467 | .ack = ack_apic_edge, |
3b7d1921 EB |
3468 | #ifdef CONFIG_SMP |
3469 | .set_affinity = set_msi_irq_affinity, | |
3470 | #endif | |
3471 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3472 | }; |
3473 | ||
54168ed7 IM |
3474 | static struct irq_chip msi_ir_chip = { |
3475 | .name = "IR-PCI-MSI", | |
3476 | .unmask = unmask_msi_irq, | |
3477 | .mask = mask_msi_irq, | |
a1e38ca5 | 3478 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3479 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3480 | #ifdef CONFIG_SMP |
3481 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3482 | #endif |
54168ed7 IM |
3483 | #endif |
3484 | .retrigger = ioapic_retrigger_irq, | |
3485 | }; | |
3486 | ||
3487 | /* | |
3488 | * Map the PCI dev to the corresponding remapping hardware unit | |
3489 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3490 | * in it. | |
3491 | */ | |
3492 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3493 | { | |
3494 | struct intel_iommu *iommu; | |
3495 | int index; | |
3496 | ||
3497 | iommu = map_dev_to_ir(dev); | |
3498 | if (!iommu) { | |
3499 | printk(KERN_ERR | |
3500 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3501 | return -ENOENT; | |
3502 | } | |
3503 | ||
3504 | index = alloc_irte(iommu, irq, nvec); | |
3505 | if (index < 0) { | |
3506 | printk(KERN_ERR | |
3507 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3508 | pci_name(dev)); |
54168ed7 IM |
3509 | return -ENOSPC; |
3510 | } | |
3511 | return index; | |
3512 | } | |
1d025192 | 3513 | |
3145e941 | 3514 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3515 | { |
3516 | int ret; | |
3517 | struct msi_msg msg; | |
3518 | ||
c8bc6f3c | 3519 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3520 | if (ret < 0) |
3521 | return ret; | |
3522 | ||
3145e941 | 3523 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3524 | write_msi_msg(irq, &msg); |
3525 | ||
54168ed7 IM |
3526 | if (irq_remapped(irq)) { |
3527 | struct irq_desc *desc = irq_to_desc(irq); | |
3528 | /* | |
3529 | * irq migration in process context | |
3530 | */ | |
3531 | desc->status |= IRQ_MOVE_PCNTXT; | |
3532 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3533 | } else | |
54168ed7 | 3534 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3535 | |
c81bba49 YL |
3536 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3537 | ||
1d025192 YL |
3538 | return 0; |
3539 | } | |
3540 | ||
047c8fdb YL |
3541 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3542 | { | |
54168ed7 IM |
3543 | unsigned int irq; |
3544 | int ret, sub_handle; | |
0b8f1efa | 3545 | struct msi_desc *msidesc; |
54168ed7 | 3546 | unsigned int irq_want; |
1cc18521 | 3547 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3548 | int index = 0; |
d047f53a | 3549 | int node; |
54168ed7 | 3550 | |
1c8d7b0a MW |
3551 | /* x86 doesn't support multiple MSI yet */ |
3552 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3553 | return 1; | |
3554 | ||
d047f53a | 3555 | node = dev_to_node(&dev->dev); |
be5d5350 | 3556 | irq_want = nr_irqs_gsi; |
54168ed7 | 3557 | sub_handle = 0; |
0b8f1efa | 3558 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3559 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3560 | if (irq == 0) |
3561 | return -1; | |
f1ee5548 | 3562 | irq_want = irq + 1; |
54168ed7 IM |
3563 | if (!intr_remapping_enabled) |
3564 | goto no_ir; | |
3565 | ||
3566 | if (!sub_handle) { | |
3567 | /* | |
3568 | * allocate the consecutive block of IRTE's | |
3569 | * for 'nvec' | |
3570 | */ | |
3571 | index = msi_alloc_irte(dev, irq, nvec); | |
3572 | if (index < 0) { | |
3573 | ret = index; | |
3574 | goto error; | |
3575 | } | |
3576 | } else { | |
3577 | iommu = map_dev_to_ir(dev); | |
3578 | if (!iommu) { | |
3579 | ret = -ENOENT; | |
3580 | goto error; | |
3581 | } | |
3582 | /* | |
3583 | * setup the mapping between the irq and the IRTE | |
3584 | * base index, the sub_handle pointing to the | |
3585 | * appropriate interrupt remap table entry. | |
3586 | */ | |
3587 | set_irte_irq(irq, iommu, index, sub_handle); | |
3588 | } | |
3589 | no_ir: | |
0b8f1efa | 3590 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3591 | if (ret < 0) |
3592 | goto error; | |
3593 | sub_handle++; | |
3594 | } | |
3595 | return 0; | |
047c8fdb YL |
3596 | |
3597 | error: | |
54168ed7 IM |
3598 | destroy_irq(irq); |
3599 | return ret; | |
047c8fdb YL |
3600 | } |
3601 | ||
3b7d1921 EB |
3602 | void arch_teardown_msi_irq(unsigned int irq) |
3603 | { | |
f7feaca7 | 3604 | destroy_irq(irq); |
3b7d1921 EB |
3605 | } |
3606 | ||
9d783ba0 | 3607 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3608 | #ifdef CONFIG_SMP |
d5dedd45 | 3609 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3610 | { |
3145e941 | 3611 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3612 | struct irq_cfg *cfg; |
3613 | struct msi_msg msg; | |
3614 | unsigned int dest; | |
54168ed7 | 3615 | |
18374d89 | 3616 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3617 | return -1; |
54168ed7 | 3618 | |
3145e941 | 3619 | cfg = desc->chip_data; |
54168ed7 IM |
3620 | |
3621 | dmar_msi_read(irq, &msg); | |
3622 | ||
3623 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3624 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3625 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3626 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3627 | ||
3628 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3629 | |
3630 | return 0; | |
54168ed7 | 3631 | } |
3145e941 | 3632 | |
54168ed7 IM |
3633 | #endif /* CONFIG_SMP */ |
3634 | ||
8f7007aa | 3635 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3636 | .name = "DMAR_MSI", |
3637 | .unmask = dmar_msi_unmask, | |
3638 | .mask = dmar_msi_mask, | |
3639 | .ack = ack_apic_edge, | |
3640 | #ifdef CONFIG_SMP | |
3641 | .set_affinity = dmar_msi_set_affinity, | |
3642 | #endif | |
3643 | .retrigger = ioapic_retrigger_irq, | |
3644 | }; | |
3645 | ||
3646 | int arch_setup_dmar_msi(unsigned int irq) | |
3647 | { | |
3648 | int ret; | |
3649 | struct msi_msg msg; | |
2d3fcc1c | 3650 | |
c8bc6f3c | 3651 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3652 | if (ret < 0) |
3653 | return ret; | |
3654 | dmar_msi_write(irq, &msg); | |
3655 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3656 | "edge"); | |
3657 | return 0; | |
3658 | } | |
3659 | #endif | |
3660 | ||
58ac1e76 | 3661 | #ifdef CONFIG_HPET_TIMER |
3662 | ||
3663 | #ifdef CONFIG_SMP | |
d5dedd45 | 3664 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3665 | { |
3145e941 | 3666 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3667 | struct irq_cfg *cfg; |
58ac1e76 | 3668 | struct msi_msg msg; |
3669 | unsigned int dest; | |
58ac1e76 | 3670 | |
18374d89 | 3671 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3672 | return -1; |
58ac1e76 | 3673 | |
3145e941 | 3674 | cfg = desc->chip_data; |
58ac1e76 | 3675 | |
3676 | hpet_msi_read(irq, &msg); | |
3677 | ||
3678 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3679 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3680 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3681 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3682 | ||
3683 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3684 | |
3685 | return 0; | |
58ac1e76 | 3686 | } |
3145e941 | 3687 | |
58ac1e76 | 3688 | #endif /* CONFIG_SMP */ |
3689 | ||
c8bc6f3c SS |
3690 | static struct irq_chip ir_hpet_msi_type = { |
3691 | .name = "IR-HPET_MSI", | |
3692 | .unmask = hpet_msi_unmask, | |
3693 | .mask = hpet_msi_mask, | |
3694 | #ifdef CONFIG_INTR_REMAP | |
3695 | .ack = ir_ack_apic_edge, | |
3696 | #ifdef CONFIG_SMP | |
3697 | .set_affinity = ir_set_msi_irq_affinity, | |
3698 | #endif | |
3699 | #endif | |
3700 | .retrigger = ioapic_retrigger_irq, | |
3701 | }; | |
3702 | ||
1cc18521 | 3703 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3704 | .name = "HPET_MSI", |
3705 | .unmask = hpet_msi_unmask, | |
3706 | .mask = hpet_msi_mask, | |
3707 | .ack = ack_apic_edge, | |
3708 | #ifdef CONFIG_SMP | |
3709 | .set_affinity = hpet_msi_set_affinity, | |
3710 | #endif | |
3711 | .retrigger = ioapic_retrigger_irq, | |
3712 | }; | |
3713 | ||
c8bc6f3c | 3714 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3715 | { |
3716 | int ret; | |
3717 | struct msi_msg msg; | |
6ec3cfec | 3718 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3719 | |
c8bc6f3c SS |
3720 | if (intr_remapping_enabled) { |
3721 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3722 | int index; | |
3723 | ||
3724 | if (!iommu) | |
3725 | return -1; | |
3726 | ||
3727 | index = alloc_irte(iommu, irq, 1); | |
3728 | if (index < 0) | |
3729 | return -1; | |
3730 | } | |
3731 | ||
3732 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3733 | if (ret < 0) |
3734 | return ret; | |
3735 | ||
3736 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3737 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3738 | if (irq_remapped(irq)) |
3739 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3740 | handle_edge_irq, "edge"); | |
3741 | else | |
3742 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3743 | handle_edge_irq, "edge"); | |
c81bba49 | 3744 | |
58ac1e76 | 3745 | return 0; |
3746 | } | |
3747 | #endif | |
3748 | ||
54168ed7 | 3749 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3750 | /* |
3751 | * Hypertransport interrupt support | |
3752 | */ | |
3753 | #ifdef CONFIG_HT_IRQ | |
3754 | ||
3755 | #ifdef CONFIG_SMP | |
3756 | ||
497c9a19 | 3757 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3758 | { |
ec68307c EB |
3759 | struct ht_irq_msg msg; |
3760 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3761 | |
497c9a19 | 3762 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3763 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3764 | |
497c9a19 | 3765 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3766 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3767 | |
ec68307c | 3768 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3769 | } |
3770 | ||
d5dedd45 | 3771 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3772 | { |
3145e941 | 3773 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3774 | struct irq_cfg *cfg; |
8b955b0d | 3775 | unsigned int dest; |
8b955b0d | 3776 | |
18374d89 | 3777 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3778 | return -1; |
8b955b0d | 3779 | |
3145e941 | 3780 | cfg = desc->chip_data; |
8b955b0d | 3781 | |
497c9a19 | 3782 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3783 | |
3784 | return 0; | |
8b955b0d | 3785 | } |
3145e941 | 3786 | |
8b955b0d EB |
3787 | #endif |
3788 | ||
c37e108d | 3789 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3790 | .name = "PCI-HT", |
3791 | .mask = mask_ht_irq, | |
3792 | .unmask = unmask_ht_irq, | |
1d025192 | 3793 | .ack = ack_apic_edge, |
8b955b0d EB |
3794 | #ifdef CONFIG_SMP |
3795 | .set_affinity = set_ht_irq_affinity, | |
3796 | #endif | |
3797 | .retrigger = ioapic_retrigger_irq, | |
3798 | }; | |
3799 | ||
3800 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3801 | { | |
497c9a19 YL |
3802 | struct irq_cfg *cfg; |
3803 | int err; | |
8b955b0d | 3804 | |
f1182638 JB |
3805 | if (disable_apic) |
3806 | return -ENXIO; | |
3807 | ||
3145e941 | 3808 | cfg = irq_cfg(irq); |
fe402e1f | 3809 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3810 | if (!err) { |
ec68307c | 3811 | struct ht_irq_msg msg; |
8b955b0d | 3812 | unsigned dest; |
8b955b0d | 3813 | |
debccb3e IM |
3814 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3815 | apic->target_cpus()); | |
8b955b0d | 3816 | |
ec68307c | 3817 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3818 | |
ec68307c EB |
3819 | msg.address_lo = |
3820 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3821 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3822 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3823 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3824 | HT_IRQ_LOW_DM_PHYSICAL : |
3825 | HT_IRQ_LOW_DM_LOGICAL) | | |
3826 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3827 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3828 | HT_IRQ_LOW_MT_FIXED : |
3829 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3830 | HT_IRQ_LOW_IRQ_MASKED; | |
3831 | ||
ec68307c | 3832 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3833 | |
a460e745 IM |
3834 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3835 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3836 | |
3837 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3838 | } |
497c9a19 | 3839 | return err; |
8b955b0d EB |
3840 | } |
3841 | #endif /* CONFIG_HT_IRQ */ | |
3842 | ||
9d6a4d08 YL |
3843 | int __init io_apic_get_redir_entries (int ioapic) |
3844 | { | |
3845 | union IO_APIC_reg_01 reg_01; | |
3846 | unsigned long flags; | |
3847 | ||
dade7716 | 3848 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3849 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3850 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3851 | |
4b6b19a1 EB |
3852 | /* The register returns the maximum index redir index |
3853 | * supported, which is one less than the total number of redir | |
3854 | * entries. | |
3855 | */ | |
3856 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3857 | } |
3858 | ||
be5d5350 | 3859 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3860 | { |
4afc51a8 | 3861 | int nr; |
be5d5350 | 3862 | |
a4384df3 | 3863 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3864 | if (nr > nr_irqs_gsi) |
be5d5350 | 3865 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3866 | |
3867 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3868 | } |
3869 | ||
4a046d17 YL |
3870 | #ifdef CONFIG_SPARSE_IRQ |
3871 | int __init arch_probe_nr_irqs(void) | |
3872 | { | |
3873 | int nr; | |
3874 | ||
f1ee5548 YL |
3875 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3876 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3877 | |
f1ee5548 YL |
3878 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3879 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3880 | /* | |
3881 | * for MSI and HT dyn irq | |
3882 | */ | |
3883 | nr += nr_irqs_gsi * 16; | |
3884 | #endif | |
3885 | if (nr < nr_irqs) | |
4a046d17 YL |
3886 | nr_irqs = nr; |
3887 | ||
3888 | return 0; | |
3889 | } | |
3890 | #endif | |
3891 | ||
e5198075 YL |
3892 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3893 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3894 | { |
3895 | struct irq_desc *desc; | |
3896 | struct irq_cfg *cfg; | |
3897 | int node; | |
e5198075 YL |
3898 | int ioapic, pin; |
3899 | int trigger, polarity; | |
5ef21837 | 3900 | |
e5198075 | 3901 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3902 | if (!IO_APIC_IRQ(irq)) { |
3903 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3904 | ioapic); | |
3905 | return -EINVAL; | |
3906 | } | |
3907 | ||
3908 | if (dev) | |
3909 | node = dev_to_node(dev); | |
3910 | else | |
3911 | node = cpu_to_node(boot_cpu_id); | |
3912 | ||
3913 | desc = irq_to_desc_alloc_node(irq, node); | |
3914 | if (!desc) { | |
3915 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3916 | return 0; | |
3917 | } | |
3918 | ||
e5198075 YL |
3919 | pin = irq_attr->ioapic_pin; |
3920 | trigger = irq_attr->trigger; | |
3921 | polarity = irq_attr->polarity; | |
3922 | ||
5ef21837 YL |
3923 | /* |
3924 | * IRQs < 16 are already in the irq_2_pin[] map | |
3925 | */ | |
b81bb373 | 3926 | if (irq >= legacy_pic->nr_legacy_irqs) { |
5ef21837 | 3927 | cfg = desc->chip_data; |
f3d1915a CG |
3928 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3929 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3930 | pin, irq); | |
3931 | return 0; | |
3932 | } | |
5ef21837 YL |
3933 | } |
3934 | ||
e5198075 | 3935 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3936 | |
3937 | return 0; | |
3938 | } | |
3939 | ||
e5198075 YL |
3940 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3941 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3942 | { |
e5198075 | 3943 | int ioapic, pin; |
5ef21837 YL |
3944 | /* |
3945 | * Avoid pin reprogramming. PRTs typically include entries | |
3946 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3947 | * we only program the IOAPIC on the first. | |
3948 | */ | |
e5198075 YL |
3949 | ioapic = irq_attr->ioapic; |
3950 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3951 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3952 | pr_debug("Pin %d-%d already programmed\n", | |
3953 | mp_ioapics[ioapic].apicid, pin); | |
3954 | return 0; | |
3955 | } | |
3956 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3957 | ||
e5198075 | 3958 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3959 | } |
3960 | ||
2a4ab640 FT |
3961 | u8 __init io_apic_unique_id(u8 id) |
3962 | { | |
3963 | #ifdef CONFIG_X86_32 | |
3964 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3965 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3966 | return io_apic_get_unique_id(nr_ioapics, id); | |
3967 | else | |
3968 | return id; | |
3969 | #else | |
3970 | int i; | |
3971 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3972 | |
2a4ab640 FT |
3973 | bitmap_zero(used, 256); |
3974 | for (i = 0; i < nr_ioapics; i++) { | |
3975 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3976 | __set_bit(ia->apicid, used); | |
3977 | } | |
3978 | if (!test_bit(id, used)) | |
3979 | return id; | |
3980 | return find_first_zero_bit(used, 256); | |
3981 | #endif | |
3982 | } | |
1da177e4 | 3983 | |
54168ed7 | 3984 | #ifdef CONFIG_X86_32 |
36062448 | 3985 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3986 | { |
3987 | union IO_APIC_reg_00 reg_00; | |
3988 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3989 | physid_mask_t tmp; | |
3990 | unsigned long flags; | |
3991 | int i = 0; | |
3992 | ||
3993 | /* | |
36062448 PC |
3994 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3995 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3996 | * supports up to 16 on one shared APIC bus. |
36062448 | 3997 | * |
1da177e4 LT |
3998 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3999 | * advantage of new APIC bus architecture. | |
4000 | */ | |
4001 | ||
4002 | if (physids_empty(apic_id_map)) | |
7abc0753 | 4003 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 4004 | |
dade7716 | 4005 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4006 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 4007 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4008 | |
4009 | if (apic_id >= get_physical_broadcast()) { | |
4010 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
4011 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
4012 | apic_id = reg_00.bits.ID; | |
4013 | } | |
4014 | ||
4015 | /* | |
36062448 | 4016 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
4017 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
4018 | */ | |
7abc0753 | 4019 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
4020 | |
4021 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 4022 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
4023 | break; |
4024 | } | |
4025 | ||
4026 | if (i == get_physical_broadcast()) | |
4027 | panic("Max apic_id exceeded!\n"); | |
4028 | ||
4029 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
4030 | "trying %d\n", ioapic, apic_id, i); | |
4031 | ||
4032 | apic_id = i; | |
36062448 | 4033 | } |
1da177e4 | 4034 | |
7abc0753 | 4035 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
4036 | physids_or(apic_id_map, apic_id_map, tmp); |
4037 | ||
4038 | if (reg_00.bits.ID != apic_id) { | |
4039 | reg_00.bits.ID = apic_id; | |
4040 | ||
dade7716 | 4041 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
4042 | io_apic_write(ioapic, 0, reg_00.raw); |
4043 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 4044 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4045 | |
4046 | /* Sanity check */ | |
6070f9ec AD |
4047 | if (reg_00.bits.ID != apic_id) { |
4048 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4049 | return -1; | |
4050 | } | |
1da177e4 LT |
4051 | } |
4052 | ||
4053 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4054 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4055 | ||
4056 | return apic_id; | |
4057 | } | |
58f892e0 | 4058 | #endif |
1da177e4 | 4059 | |
36062448 | 4060 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4061 | { |
4062 | union IO_APIC_reg_01 reg_01; | |
4063 | unsigned long flags; | |
4064 | ||
dade7716 | 4065 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4066 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4067 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4068 | |
4069 | return reg_01.bits.version; | |
4070 | } | |
4071 | ||
9a0a91bb | 4072 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4073 | { |
9a0a91bb | 4074 | int ioapic, pin, idx; |
61fd47e0 SL |
4075 | |
4076 | if (skip_ioapic_setup) | |
4077 | return -1; | |
4078 | ||
9a0a91bb EB |
4079 | ioapic = mp_find_ioapic(gsi); |
4080 | if (ioapic < 0) | |
61fd47e0 SL |
4081 | return -1; |
4082 | ||
9a0a91bb EB |
4083 | pin = mp_find_ioapic_pin(ioapic, gsi); |
4084 | if (pin < 0) | |
4085 | return -1; | |
4086 | ||
4087 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4088 | if (idx < 0) | |
61fd47e0 SL |
4089 | return -1; |
4090 | ||
9a0a91bb EB |
4091 | *trigger = irq_trigger(idx); |
4092 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4093 | return 0; |
4094 | } | |
4095 | ||
497c9a19 YL |
4096 | /* |
4097 | * This function currently is only a helper for the i386 smp boot process where | |
4098 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4099 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4100 | */ |
4101 | #ifdef CONFIG_SMP | |
4102 | void __init setup_ioapic_dest(void) | |
4103 | { | |
fad53995 | 4104 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4105 | struct irq_desc *desc; |
22f65d31 | 4106 | const struct cpumask *mask; |
497c9a19 YL |
4107 | |
4108 | if (skip_ioapic_setup == 1) | |
4109 | return; | |
4110 | ||
fad53995 | 4111 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4112 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4113 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4114 | if (irq_entry == -1) | |
4115 | continue; | |
4116 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4117 | |
fad53995 EB |
4118 | if ((ioapic > 0) && (irq > 16)) |
4119 | continue; | |
4120 | ||
b9c61b70 | 4121 | desc = irq_to_desc(irq); |
6c2e9403 | 4122 | |
b9c61b70 YL |
4123 | /* |
4124 | * Honour affinities which have been set in early boot | |
4125 | */ | |
4126 | if (desc->status & | |
4127 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4128 | mask = desc->affinity; | |
4129 | else | |
4130 | mask = apic->target_cpus(); | |
497c9a19 | 4131 | |
b9c61b70 YL |
4132 | if (intr_remapping_enabled) |
4133 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4134 | else | |
4135 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4136 | } |
b9c61b70 | 4137 | |
497c9a19 YL |
4138 | } |
4139 | #endif | |
4140 | ||
54168ed7 IM |
4141 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4142 | ||
4143 | static struct resource *ioapic_resources; | |
4144 | ||
ffc43836 | 4145 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4146 | { |
4147 | unsigned long n; | |
4148 | struct resource *res; | |
4149 | char *mem; | |
4150 | int i; | |
4151 | ||
4152 | if (nr_ioapics <= 0) | |
4153 | return NULL; | |
4154 | ||
4155 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4156 | n *= nr_ioapics; | |
4157 | ||
4158 | mem = alloc_bootmem(n); | |
4159 | res = (void *)mem; | |
4160 | ||
ffc43836 | 4161 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4162 | |
ffc43836 CG |
4163 | for (i = 0; i < nr_ioapics; i++) { |
4164 | res[i].name = mem; | |
4165 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4166 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4167 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4168 | } |
4169 | ||
4170 | ioapic_resources = res; | |
4171 | ||
4172 | return res; | |
4173 | } | |
54168ed7 | 4174 | |
f3294a33 YL |
4175 | void __init ioapic_init_mappings(void) |
4176 | { | |
4177 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4178 | struct resource *ioapic_res; |
d6c88a50 | 4179 | int i; |
f3294a33 | 4180 | |
ffc43836 | 4181 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4182 | for (i = 0; i < nr_ioapics; i++) { |
4183 | if (smp_found_config) { | |
b5ba7e6d | 4184 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4185 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4186 | if (!ioapic_phys) { |
4187 | printk(KERN_ERR | |
4188 | "WARNING: bogus zero IO-APIC " | |
4189 | "address found in MPTABLE, " | |
4190 | "disabling IO/APIC support!\n"); | |
4191 | smp_found_config = 0; | |
4192 | skip_ioapic_setup = 1; | |
4193 | goto fake_ioapic_page; | |
4194 | } | |
54168ed7 | 4195 | #endif |
f3294a33 | 4196 | } else { |
54168ed7 | 4197 | #ifdef CONFIG_X86_32 |
f3294a33 | 4198 | fake_ioapic_page: |
54168ed7 | 4199 | #endif |
e79c65a9 | 4200 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4201 | ioapic_phys = __pa(ioapic_phys); |
4202 | } | |
4203 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4204 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4205 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4206 | ioapic_phys); | |
f3294a33 | 4207 | idx++; |
54168ed7 | 4208 | |
ffc43836 | 4209 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4210 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4211 | ioapic_res++; |
f3294a33 YL |
4212 | } |
4213 | } | |
4214 | ||
857fdc53 | 4215 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4216 | { |
4217 | int i; | |
4218 | struct resource *r = ioapic_resources; | |
4219 | ||
4220 | if (!r) { | |
857fdc53 | 4221 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4222 | printk(KERN_ERR |
4223 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4224 | return; |
54168ed7 IM |
4225 | } |
4226 | ||
4227 | for (i = 0; i < nr_ioapics; i++) { | |
4228 | insert_resource(&iomem_resource, r); | |
4229 | r++; | |
4230 | } | |
54168ed7 | 4231 | } |
2a4ab640 | 4232 | |
eddb0c55 | 4233 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4234 | { |
4235 | int i = 0; | |
4236 | ||
4237 | /* Find the IOAPIC that manages this GSI. */ | |
4238 | for (i = 0; i < nr_ioapics; i++) { | |
4239 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4240 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4241 | return i; | |
4242 | } | |
54168ed7 | 4243 | |
2a4ab640 FT |
4244 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4245 | return -1; | |
4246 | } | |
4247 | ||
eddb0c55 | 4248 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4249 | { |
4250 | if (WARN_ON(ioapic == -1)) | |
4251 | return -1; | |
4252 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4253 | return -1; | |
4254 | ||
4255 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4256 | } | |
4257 | ||
4258 | static int bad_ioapic(unsigned long address) | |
4259 | { | |
4260 | if (nr_ioapics >= MAX_IO_APICS) { | |
4261 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4262 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4263 | return 1; | |
4264 | } | |
4265 | if (!address) { | |
4266 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4267 | " found in table, skipping!\n"); | |
4268 | return 1; | |
4269 | } | |
54168ed7 IM |
4270 | return 0; |
4271 | } | |
4272 | ||
2a4ab640 FT |
4273 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4274 | { | |
4275 | int idx = 0; | |
7716a5c4 | 4276 | int entries; |
2a4ab640 FT |
4277 | |
4278 | if (bad_ioapic(address)) | |
4279 | return; | |
4280 | ||
4281 | idx = nr_ioapics; | |
4282 | ||
4283 | mp_ioapics[idx].type = MP_IOAPIC; | |
4284 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4285 | mp_ioapics[idx].apicaddr = address; | |
4286 | ||
4287 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4288 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4289 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4290 | ||
4291 | /* | |
4292 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4293 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4294 | */ | |
7716a5c4 | 4295 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4296 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4297 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4298 | ||
4299 | /* | |
4300 | * The number of IO-APIC IRQ registers (== #pins): | |
4301 | */ | |
4302 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4303 | |
a4384df3 EB |
4304 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4305 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4306 | |
4307 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4308 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4309 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4310 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4311 | ||
4312 | nr_ioapics++; | |
4313 | } | |
05ddafb1 JP |
4314 | |
4315 | /* Enable IOAPIC early just for system timer */ | |
4316 | void __init pre_init_apic_IRQ0(void) | |
4317 | { | |
4318 | struct irq_cfg *cfg; | |
4319 | struct irq_desc *desc; | |
4320 | ||
4321 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4322 | #ifndef CONFIG_SMP | |
4323 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4324 | #endif | |
4325 | desc = irq_to_desc_alloc_node(0, 0); | |
4326 | ||
4327 | setup_local_APIC(); | |
4328 | ||
4329 | cfg = irq_cfg(0); | |
4330 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4331 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4332 | ||
4333 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4334 | } |