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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
4173a0e7 DN |
63 | #include <asm/uv/uv_hub.h> |
64 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 65 | |
7b6aa335 | 66 | #include <asm/apic.h> |
1da177e4 | 67 | |
32f71aff | 68 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
69 | #define for_each_irq_pin(entry, head) \ |
70 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 71 | |
1da177e4 | 72 | /* |
54168ed7 IM |
73 | * Is the SiS APIC rmw bug present ? |
74 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
75 | */ |
76 | int sis_apic_bug = -1; | |
77 | ||
efa2559f YL |
78 | static DEFINE_SPINLOCK(ioapic_lock); |
79 | static DEFINE_SPINLOCK(vector_lock); | |
80 | ||
1da177e4 LT |
81 | /* |
82 | * # of IRQ routing registers | |
83 | */ | |
84 | int nr_ioapic_registers[MAX_IO_APICS]; | |
85 | ||
9f640ccb | 86 | /* I/O APIC entries */ |
b5ba7e6d | 87 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
88 | int nr_ioapics; |
89 | ||
584f734d | 90 | /* MP IRQ source entries */ |
c2c21745 | 91 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
92 | |
93 | /* # of MP IRQ source entries */ | |
94 | int mp_irq_entries; | |
95 | ||
8732fc4b AS |
96 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
97 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
98 | #endif | |
99 | ||
100 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
101 | ||
efa2559f YL |
102 | int skip_ioapic_setup; |
103 | ||
65a4e574 IM |
104 | void arch_disable_smp_support(void) |
105 | { | |
106 | #ifdef CONFIG_PCI | |
107 | noioapicquirk = 1; | |
108 | noioapicreroute = -1; | |
109 | #endif | |
110 | skip_ioapic_setup = 1; | |
111 | } | |
112 | ||
54168ed7 | 113 | static int __init parse_noapic(char *str) |
efa2559f YL |
114 | { |
115 | /* disable IO-APIC */ | |
65a4e574 | 116 | arch_disable_smp_support(); |
efa2559f YL |
117 | return 0; |
118 | } | |
119 | early_param("noapic", parse_noapic); | |
66759a01 | 120 | |
0b8f1efa YL |
121 | struct irq_pin_list { |
122 | int apic, pin; | |
123 | struct irq_pin_list *next; | |
124 | }; | |
125 | ||
85ac16d0 | 126 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
127 | { |
128 | struct irq_pin_list *pin; | |
0b8f1efa YL |
129 | |
130 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
131 | |
132 | return pin; | |
133 | } | |
134 | ||
8e13d697 JF |
135 | /* |
136 | * This is performance-critical, we want to do it O(1) | |
137 | * | |
138 | * Most irqs are mapped 1:1 with pins. | |
139 | */ | |
a1420f39 | 140 | struct irq_cfg { |
0f978f45 | 141 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
142 | cpumask_var_t domain; |
143 | cpumask_var_t old_domain; | |
497c9a19 | 144 | unsigned move_cleanup_count; |
a1420f39 | 145 | u8 vector; |
497c9a19 | 146 | u8 move_in_progress : 1; |
a1420f39 YL |
147 | }; |
148 | ||
a1420f39 | 149 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
150 | #ifdef CONFIG_SPARSE_IRQ |
151 | static struct irq_cfg irq_cfgx[] = { | |
152 | #else | |
d6c88a50 | 153 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 154 | #endif |
22f65d31 MT |
155 | [0] = { .vector = IRQ0_VECTOR, }, |
156 | [1] = { .vector = IRQ1_VECTOR, }, | |
157 | [2] = { .vector = IRQ2_VECTOR, }, | |
158 | [3] = { .vector = IRQ3_VECTOR, }, | |
159 | [4] = { .vector = IRQ4_VECTOR, }, | |
160 | [5] = { .vector = IRQ5_VECTOR, }, | |
161 | [6] = { .vector = IRQ6_VECTOR, }, | |
162 | [7] = { .vector = IRQ7_VECTOR, }, | |
163 | [8] = { .vector = IRQ8_VECTOR, }, | |
164 | [9] = { .vector = IRQ9_VECTOR, }, | |
165 | [10] = { .vector = IRQ10_VECTOR, }, | |
166 | [11] = { .vector = IRQ11_VECTOR, }, | |
167 | [12] = { .vector = IRQ12_VECTOR, }, | |
168 | [13] = { .vector = IRQ13_VECTOR, }, | |
169 | [14] = { .vector = IRQ14_VECTOR, }, | |
170 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
171 | }; |
172 | ||
13a0c3c2 | 173 | int __init arch_early_irq_init(void) |
8f09cd20 | 174 | { |
0b8f1efa YL |
175 | struct irq_cfg *cfg; |
176 | struct irq_desc *desc; | |
177 | int count; | |
dad213ae | 178 | int node; |
0b8f1efa | 179 | int i; |
d6c88a50 | 180 | |
0b8f1efa YL |
181 | cfg = irq_cfgx; |
182 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 183 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 184 | |
0b8f1efa YL |
185 | for (i = 0; i < count; i++) { |
186 | desc = irq_to_desc(i); | |
187 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
188 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
189 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
22f65d31 MT |
190 | if (i < NR_IRQS_LEGACY) |
191 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 192 | } |
13a0c3c2 YL |
193 | |
194 | return 0; | |
0b8f1efa | 195 | } |
8f09cd20 | 196 | |
0b8f1efa | 197 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 198 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 199 | { |
0b8f1efa YL |
200 | struct irq_cfg *cfg = NULL; |
201 | struct irq_desc *desc; | |
1da177e4 | 202 | |
0b8f1efa YL |
203 | desc = irq_to_desc(irq); |
204 | if (desc) | |
205 | cfg = desc->chip_data; | |
0f978f45 | 206 | |
0b8f1efa | 207 | return cfg; |
8f09cd20 | 208 | } |
d6c88a50 | 209 | |
85ac16d0 | 210 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 211 | { |
0b8f1efa | 212 | struct irq_cfg *cfg; |
0f978f45 | 213 | |
0b8f1efa | 214 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 215 | if (cfg) { |
80855f73 | 216 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
217 | kfree(cfg); |
218 | cfg = NULL; | |
80855f73 MT |
219 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
220 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
221 | free_cpumask_var(cfg->domain); |
222 | kfree(cfg); | |
223 | cfg = NULL; | |
224 | } else { | |
225 | cpumask_clear(cfg->domain); | |
226 | cpumask_clear(cfg->old_domain); | |
227 | } | |
228 | } | |
0f978f45 | 229 | |
0b8f1efa | 230 | return cfg; |
8f09cd20 YL |
231 | } |
232 | ||
85ac16d0 | 233 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 234 | { |
0b8f1efa | 235 | struct irq_cfg *cfg; |
d6c88a50 | 236 | |
0b8f1efa YL |
237 | cfg = desc->chip_data; |
238 | if (!cfg) { | |
85ac16d0 | 239 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
240 | if (!desc->chip_data) { |
241 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
242 | BUG_ON(1); | |
243 | } | |
244 | } | |
1da177e4 | 245 | |
13a0c3c2 | 246 | return 0; |
0b8f1efa | 247 | } |
0f978f45 | 248 | |
fcef5911 | 249 | /* for move_irq_desc */ |
48a1b10a | 250 | static void |
85ac16d0 | 251 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 252 | { |
48a1b10a YL |
253 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
254 | ||
255 | cfg->irq_2_pin = NULL; | |
256 | old_entry = old_cfg->irq_2_pin; | |
257 | if (!old_entry) | |
258 | return; | |
0f978f45 | 259 | |
85ac16d0 | 260 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
261 | if (!entry) |
262 | return; | |
0f978f45 | 263 | |
48a1b10a YL |
264 | entry->apic = old_entry->apic; |
265 | entry->pin = old_entry->pin; | |
266 | head = entry; | |
267 | tail = entry; | |
268 | old_entry = old_entry->next; | |
269 | while (old_entry) { | |
85ac16d0 | 270 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
271 | if (!entry) { |
272 | entry = head; | |
273 | while (entry) { | |
274 | head = entry->next; | |
275 | kfree(entry); | |
276 | entry = head; | |
277 | } | |
278 | /* still use the old one */ | |
279 | return; | |
280 | } | |
281 | entry->apic = old_entry->apic; | |
282 | entry->pin = old_entry->pin; | |
283 | tail->next = entry; | |
284 | tail = entry; | |
285 | old_entry = old_entry->next; | |
286 | } | |
0f978f45 | 287 | |
48a1b10a YL |
288 | tail->next = NULL; |
289 | cfg->irq_2_pin = head; | |
0f978f45 | 290 | } |
0f978f45 | 291 | |
48a1b10a | 292 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 293 | { |
48a1b10a | 294 | struct irq_pin_list *entry, *next; |
0f978f45 | 295 | |
48a1b10a YL |
296 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
297 | return; | |
301e6190 | 298 | |
48a1b10a | 299 | entry = old_cfg->irq_2_pin; |
0f978f45 | 300 | |
48a1b10a YL |
301 | while (entry) { |
302 | next = entry->next; | |
303 | kfree(entry); | |
304 | entry = next; | |
305 | } | |
306 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 307 | } |
0f978f45 | 308 | |
48a1b10a | 309 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 310 | struct irq_desc *desc, int node) |
0f978f45 | 311 | { |
48a1b10a YL |
312 | struct irq_cfg *cfg; |
313 | struct irq_cfg *old_cfg; | |
0f978f45 | 314 | |
85ac16d0 | 315 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 316 | |
48a1b10a YL |
317 | if (!cfg) |
318 | return; | |
319 | ||
320 | desc->chip_data = cfg; | |
321 | ||
322 | old_cfg = old_desc->chip_data; | |
323 | ||
324 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
325 | ||
85ac16d0 | 326 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 327 | } |
1da177e4 | 328 | |
48a1b10a YL |
329 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
330 | { | |
331 | kfree(old_cfg); | |
332 | } | |
333 | ||
334 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
335 | { | |
336 | struct irq_cfg *old_cfg, *cfg; | |
337 | ||
338 | old_cfg = old_desc->chip_data; | |
339 | cfg = desc->chip_data; | |
340 | ||
341 | if (old_cfg == cfg) | |
342 | return; | |
343 | ||
344 | if (old_cfg) { | |
345 | free_irq_2_pin(old_cfg, cfg); | |
346 | free_irq_cfg(old_cfg); | |
347 | old_desc->chip_data = NULL; | |
348 | } | |
349 | } | |
fcef5911 | 350 | /* end for move_irq_desc */ |
48a1b10a | 351 | |
0b8f1efa YL |
352 | #else |
353 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
354 | { | |
355 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 356 | } |
1da177e4 | 357 | |
0b8f1efa YL |
358 | #endif |
359 | ||
130fe05d LT |
360 | struct io_apic { |
361 | unsigned int index; | |
362 | unsigned int unused[3]; | |
363 | unsigned int data; | |
0280f7c4 SS |
364 | unsigned int unused2[11]; |
365 | unsigned int eoi; | |
130fe05d LT |
366 | }; |
367 | ||
368 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
369 | { | |
370 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 371 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
372 | } |
373 | ||
0280f7c4 SS |
374 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
375 | { | |
376 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
377 | writel(vector, &io_apic->eoi); | |
378 | } | |
379 | ||
130fe05d LT |
380 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
381 | { | |
382 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
383 | writel(reg, &io_apic->index); | |
384 | return readl(&io_apic->data); | |
385 | } | |
386 | ||
387 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
388 | { | |
389 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
390 | writel(reg, &io_apic->index); | |
391 | writel(value, &io_apic->data); | |
392 | } | |
393 | ||
394 | /* | |
395 | * Re-write a value: to be used for read-modify-write | |
396 | * cycles where the read already set up the index register. | |
397 | * | |
398 | * Older SiS APIC requires we rewrite the index register | |
399 | */ | |
400 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
401 | { | |
54168ed7 | 402 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
403 | |
404 | if (sis_apic_bug) | |
405 | writel(reg, &io_apic->index); | |
130fe05d LT |
406 | writel(value, &io_apic->data); |
407 | } | |
408 | ||
3145e941 | 409 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
410 | { |
411 | struct irq_pin_list *entry; | |
412 | unsigned long flags; | |
047c8fdb YL |
413 | |
414 | spin_lock_irqsave(&ioapic_lock, flags); | |
2977fb3f | 415 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
416 | unsigned int reg; |
417 | int pin; | |
418 | ||
047c8fdb YL |
419 | pin = entry->pin; |
420 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
421 | /* Is the remote IRR bit set? */ | |
422 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
423 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
424 | return true; | |
425 | } | |
047c8fdb YL |
426 | } |
427 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
428 | ||
429 | return false; | |
430 | } | |
047c8fdb | 431 | |
cf4c6a2f AK |
432 | union entry_union { |
433 | struct { u32 w1, w2; }; | |
434 | struct IO_APIC_route_entry entry; | |
435 | }; | |
436 | ||
437 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
438 | { | |
439 | union entry_union eu; | |
440 | unsigned long flags; | |
441 | spin_lock_irqsave(&ioapic_lock, flags); | |
442 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
443 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
444 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
445 | return eu.entry; | |
446 | } | |
447 | ||
f9dadfa7 LT |
448 | /* |
449 | * When we write a new IO APIC routing entry, we need to write the high | |
450 | * word first! If the mask bit in the low word is clear, we will enable | |
451 | * the interrupt, and we need to make sure the entry is fully populated | |
452 | * before that happens. | |
453 | */ | |
d15512f4 AK |
454 | static void |
455 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 456 | { |
50a8d4d2 F |
457 | union entry_union eu = {{0, 0}}; |
458 | ||
cf4c6a2f | 459 | eu.entry = e; |
f9dadfa7 LT |
460 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
461 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
462 | } |
463 | ||
ca97ab90 | 464 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
465 | { |
466 | unsigned long flags; | |
467 | spin_lock_irqsave(&ioapic_lock, flags); | |
468 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
469 | spin_unlock_irqrestore(&ioapic_lock, flags); |
470 | } | |
471 | ||
472 | /* | |
473 | * When we mask an IO APIC routing entry, we need to write the low | |
474 | * word first, in order to set the mask bit before we change the | |
475 | * high bits! | |
476 | */ | |
477 | static void ioapic_mask_entry(int apic, int pin) | |
478 | { | |
479 | unsigned long flags; | |
480 | union entry_union eu = { .entry.mask = 1 }; | |
481 | ||
cf4c6a2f AK |
482 | spin_lock_irqsave(&ioapic_lock, flags); |
483 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
484 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
485 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
486 | } | |
487 | ||
1da177e4 LT |
488 | /* |
489 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
490 | * shared ISA-space IRQs, so we have to support them. We are super | |
491 | * fast in the common case, and fast for shared ISA-space IRQs. | |
492 | */ | |
f3d1915a CG |
493 | static int |
494 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 495 | { |
2977fb3f | 496 | struct irq_pin_list **last, *entry; |
0f978f45 | 497 | |
2977fb3f CG |
498 | /* don't allow duplicates */ |
499 | last = &cfg->irq_2_pin; | |
500 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 501 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 502 | return 0; |
2977fb3f | 503 | last = &entry->next; |
1da177e4 | 504 | } |
0f978f45 | 505 | |
875e68ec | 506 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 507 | if (!entry) { |
f3d1915a CG |
508 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
509 | node, apic, pin); | |
510 | return -ENOMEM; | |
a7428cd2 | 511 | } |
1da177e4 LT |
512 | entry->apic = apic; |
513 | entry->pin = pin; | |
875e68ec | 514 | |
2977fb3f | 515 | *last = entry; |
f3d1915a CG |
516 | return 0; |
517 | } | |
518 | ||
519 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
520 | { | |
521 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
522 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
523 | } |
524 | ||
525 | /* | |
526 | * Reroute an IRQ to a different pin. | |
527 | */ | |
85ac16d0 | 528 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
529 | int oldapic, int oldpin, |
530 | int newapic, int newpin) | |
1da177e4 | 531 | { |
535b6429 | 532 | struct irq_pin_list *entry; |
1da177e4 | 533 | |
2977fb3f | 534 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
535 | if (entry->apic == oldapic && entry->pin == oldpin) { |
536 | entry->apic = newapic; | |
537 | entry->pin = newpin; | |
0f978f45 | 538 | /* every one is different, right? */ |
4eea6fff | 539 | return; |
0f978f45 | 540 | } |
1da177e4 | 541 | } |
0f978f45 | 542 | |
4eea6fff JF |
543 | /* old apic/pin didn't exist, so just add new ones */ |
544 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
545 | } |
546 | ||
2f210deb JF |
547 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
548 | int mask_and, int mask_or, | |
549 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 CG |
550 | { |
551 | int pin; | |
87783be4 | 552 | struct irq_pin_list *entry; |
047c8fdb | 553 | |
2977fb3f | 554 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
87783be4 CG |
555 | unsigned int reg; |
556 | pin = entry->pin; | |
557 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
558 | reg &= mask_and; | |
559 | reg |= mask_or; | |
560 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
561 | if (final) | |
562 | final(entry); | |
563 | } | |
564 | } | |
047c8fdb | 565 | |
3145e941 | 566 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 567 | { |
3145e941 | 568 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 569 | } |
047c8fdb | 570 | |
7f3e632f | 571 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 572 | { |
87783be4 CG |
573 | /* |
574 | * Synchronize the IO-APIC and the CPU by doing | |
575 | * a dummy read from the IO-APIC | |
576 | */ | |
577 | struct io_apic __iomem *io_apic; | |
578 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 579 | readl(&io_apic->data); |
1da177e4 LT |
580 | } |
581 | ||
3145e941 | 582 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 583 | { |
3145e941 | 584 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 585 | } |
1da177e4 | 586 | |
3145e941 | 587 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 588 | { |
3145e941 | 589 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
590 | IO_APIC_REDIR_MASKED, NULL); |
591 | } | |
1da177e4 | 592 | |
3145e941 | 593 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 594 | { |
3145e941 | 595 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
596 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
597 | } | |
047c8fdb | 598 | |
3145e941 | 599 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 600 | { |
3145e941 | 601 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
602 | unsigned long flags; |
603 | ||
3145e941 YL |
604 | BUG_ON(!cfg); |
605 | ||
1da177e4 | 606 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 607 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
608 | spin_unlock_irqrestore(&ioapic_lock, flags); |
609 | } | |
610 | ||
3145e941 | 611 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 612 | { |
3145e941 | 613 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
614 | unsigned long flags; |
615 | ||
616 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 617 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
618 | spin_unlock_irqrestore(&ioapic_lock, flags); |
619 | } | |
620 | ||
3145e941 YL |
621 | static void mask_IO_APIC_irq(unsigned int irq) |
622 | { | |
623 | struct irq_desc *desc = irq_to_desc(irq); | |
624 | ||
625 | mask_IO_APIC_irq_desc(desc); | |
626 | } | |
627 | static void unmask_IO_APIC_irq(unsigned int irq) | |
628 | { | |
629 | struct irq_desc *desc = irq_to_desc(irq); | |
630 | ||
631 | unmask_IO_APIC_irq_desc(desc); | |
632 | } | |
633 | ||
1da177e4 LT |
634 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
635 | { | |
636 | struct IO_APIC_route_entry entry; | |
36062448 | 637 | |
1da177e4 | 638 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 639 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
640 | if (entry.delivery_mode == dest_SMI) |
641 | return; | |
1da177e4 LT |
642 | /* |
643 | * Disable it in the IO-APIC irq-routing table: | |
644 | */ | |
f9dadfa7 | 645 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
646 | } |
647 | ||
54168ed7 | 648 | static void clear_IO_APIC (void) |
1da177e4 LT |
649 | { |
650 | int apic, pin; | |
651 | ||
652 | for (apic = 0; apic < nr_ioapics; apic++) | |
653 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
654 | clear_IO_APIC_pin(apic, pin); | |
655 | } | |
656 | ||
54168ed7 | 657 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
658 | /* |
659 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
660 | * specific CPU-side IRQs. | |
661 | */ | |
662 | ||
663 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
664 | static int pirq_entries[MAX_PIRQS] = { |
665 | [0 ... MAX_PIRQS - 1] = -1 | |
666 | }; | |
1da177e4 | 667 | |
1da177e4 LT |
668 | static int __init ioapic_pirq_setup(char *str) |
669 | { | |
670 | int i, max; | |
671 | int ints[MAX_PIRQS+1]; | |
672 | ||
673 | get_options(str, ARRAY_SIZE(ints), ints); | |
674 | ||
1da177e4 LT |
675 | apic_printk(APIC_VERBOSE, KERN_INFO |
676 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
677 | max = MAX_PIRQS; | |
678 | if (ints[0] < MAX_PIRQS) | |
679 | max = ints[0]; | |
680 | ||
681 | for (i = 0; i < max; i++) { | |
682 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
683 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
684 | /* | |
685 | * PIRQs are mapped upside down, usually. | |
686 | */ | |
687 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
688 | } | |
689 | return 1; | |
690 | } | |
691 | ||
692 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
693 | #endif /* CONFIG_X86_32 */ |
694 | ||
b24696bc FY |
695 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
696 | { | |
697 | int apic; | |
698 | struct IO_APIC_route_entry **ioapic_entries; | |
699 | ||
700 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
701 | GFP_ATOMIC); | |
702 | if (!ioapic_entries) | |
703 | return 0; | |
704 | ||
705 | for (apic = 0; apic < nr_ioapics; apic++) { | |
706 | ioapic_entries[apic] = | |
707 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
708 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
709 | if (!ioapic_entries[apic]) | |
710 | goto nomem; | |
711 | } | |
712 | ||
713 | return ioapic_entries; | |
714 | ||
715 | nomem: | |
716 | while (--apic >= 0) | |
717 | kfree(ioapic_entries[apic]); | |
718 | kfree(ioapic_entries); | |
719 | ||
720 | return 0; | |
721 | } | |
54168ed7 IM |
722 | |
723 | /* | |
05c3dc2c | 724 | * Saves all the IO-APIC RTE's |
54168ed7 | 725 | */ |
b24696bc | 726 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 727 | { |
54168ed7 IM |
728 | int apic, pin; |
729 | ||
b24696bc FY |
730 | if (!ioapic_entries) |
731 | return -ENOMEM; | |
54168ed7 IM |
732 | |
733 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
734 | if (!ioapic_entries[apic]) |
735 | return -ENOMEM; | |
54168ed7 | 736 | |
05c3dc2c | 737 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 738 | ioapic_entries[apic][pin] = |
54168ed7 | 739 | ioapic_read_entry(apic, pin); |
b24696bc | 740 | } |
5ffa4eb2 | 741 | |
54168ed7 IM |
742 | return 0; |
743 | } | |
744 | ||
b24696bc FY |
745 | /* |
746 | * Mask all IO APIC entries. | |
747 | */ | |
748 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
749 | { |
750 | int apic, pin; | |
751 | ||
b24696bc FY |
752 | if (!ioapic_entries) |
753 | return; | |
754 | ||
05c3dc2c | 755 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 756 | if (!ioapic_entries[apic]) |
05c3dc2c | 757 | break; |
b24696bc | 758 | |
05c3dc2c SS |
759 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
760 | struct IO_APIC_route_entry entry; | |
761 | ||
b24696bc | 762 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
763 | if (!entry.mask) { |
764 | entry.mask = 1; | |
765 | ioapic_write_entry(apic, pin, entry); | |
766 | } | |
767 | } | |
768 | } | |
769 | } | |
770 | ||
b24696bc FY |
771 | /* |
772 | * Restore IO APIC entries which was saved in ioapic_entries. | |
773 | */ | |
774 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
775 | { |
776 | int apic, pin; | |
777 | ||
b24696bc FY |
778 | if (!ioapic_entries) |
779 | return -ENOMEM; | |
780 | ||
5ffa4eb2 | 781 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
782 | if (!ioapic_entries[apic]) |
783 | return -ENOMEM; | |
784 | ||
54168ed7 IM |
785 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
786 | ioapic_write_entry(apic, pin, | |
b24696bc | 787 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 788 | } |
b24696bc | 789 | return 0; |
54168ed7 IM |
790 | } |
791 | ||
b24696bc FY |
792 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
793 | { | |
794 | int apic; | |
795 | ||
796 | for (apic = 0; apic < nr_ioapics; apic++) | |
797 | kfree(ioapic_entries[apic]); | |
798 | ||
799 | kfree(ioapic_entries); | |
54168ed7 | 800 | } |
1da177e4 LT |
801 | |
802 | /* | |
803 | * Find the IRQ entry number of a certain pin. | |
804 | */ | |
805 | static int find_irq_entry(int apic, int pin, int type) | |
806 | { | |
807 | int i; | |
808 | ||
809 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
810 | if (mp_irqs[i].irqtype == type && |
811 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
812 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
813 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
814 | return i; |
815 | ||
816 | return -1; | |
817 | } | |
818 | ||
819 | /* | |
820 | * Find the pin to which IRQ[irq] (ISA) is connected | |
821 | */ | |
fcfd636a | 822 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
823 | { |
824 | int i; | |
825 | ||
826 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 827 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 828 | |
d27e2b8e | 829 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
830 | (mp_irqs[i].irqtype == type) && |
831 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 832 | |
c2c21745 | 833 | return mp_irqs[i].dstirq; |
1da177e4 LT |
834 | } |
835 | return -1; | |
836 | } | |
837 | ||
fcfd636a EB |
838 | static int __init find_isa_irq_apic(int irq, int type) |
839 | { | |
840 | int i; | |
841 | ||
842 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 843 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 844 | |
73b2961b | 845 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
846 | (mp_irqs[i].irqtype == type) && |
847 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
848 | break; |
849 | } | |
850 | if (i < mp_irq_entries) { | |
851 | int apic; | |
54168ed7 | 852 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 853 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
854 | return apic; |
855 | } | |
856 | } | |
857 | ||
858 | return -1; | |
859 | } | |
860 | ||
c0a282c2 | 861 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
862 | /* |
863 | * EISA Edge/Level control register, ELCR | |
864 | */ | |
865 | static int EISA_ELCR(unsigned int irq) | |
866 | { | |
99d093d1 | 867 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
868 | unsigned int port = 0x4d0 + (irq >> 3); |
869 | return (inb(port) >> (irq & 7)) & 1; | |
870 | } | |
871 | apic_printk(APIC_VERBOSE, KERN_INFO | |
872 | "Broken MPtable reports ISA irq %d\n", irq); | |
873 | return 0; | |
874 | } | |
54168ed7 | 875 | |
c0a282c2 | 876 | #endif |
1da177e4 | 877 | |
6728801d AS |
878 | /* ISA interrupts are always polarity zero edge triggered, |
879 | * when listed as conforming in the MP table. */ | |
880 | ||
881 | #define default_ISA_trigger(idx) (0) | |
882 | #define default_ISA_polarity(idx) (0) | |
883 | ||
1da177e4 LT |
884 | /* EISA interrupts are always polarity zero and can be edge or level |
885 | * trigger depending on the ELCR value. If an interrupt is listed as | |
886 | * EISA conforming in the MP table, that means its trigger type must | |
887 | * be read in from the ELCR */ | |
888 | ||
c2c21745 | 889 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 890 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
891 | |
892 | /* PCI interrupts are always polarity one level triggered, | |
893 | * when listed as conforming in the MP table. */ | |
894 | ||
895 | #define default_PCI_trigger(idx) (1) | |
896 | #define default_PCI_polarity(idx) (1) | |
897 | ||
898 | /* MCA interrupts are always polarity zero level triggered, | |
899 | * when listed as conforming in the MP table. */ | |
900 | ||
901 | #define default_MCA_trigger(idx) (1) | |
6728801d | 902 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 903 | |
61fd47e0 | 904 | static int MPBIOS_polarity(int idx) |
1da177e4 | 905 | { |
c2c21745 | 906 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
907 | int polarity; |
908 | ||
909 | /* | |
910 | * Determine IRQ line polarity (high active or low active): | |
911 | */ | |
c2c21745 | 912 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 913 | { |
54168ed7 IM |
914 | case 0: /* conforms, ie. bus-type dependent polarity */ |
915 | if (test_bit(bus, mp_bus_not_pci)) | |
916 | polarity = default_ISA_polarity(idx); | |
917 | else | |
918 | polarity = default_PCI_polarity(idx); | |
919 | break; | |
920 | case 1: /* high active */ | |
921 | { | |
922 | polarity = 0; | |
923 | break; | |
924 | } | |
925 | case 2: /* reserved */ | |
926 | { | |
927 | printk(KERN_WARNING "broken BIOS!!\n"); | |
928 | polarity = 1; | |
929 | break; | |
930 | } | |
931 | case 3: /* low active */ | |
932 | { | |
933 | polarity = 1; | |
934 | break; | |
935 | } | |
936 | default: /* invalid */ | |
937 | { | |
938 | printk(KERN_WARNING "broken BIOS!!\n"); | |
939 | polarity = 1; | |
940 | break; | |
941 | } | |
1da177e4 LT |
942 | } |
943 | return polarity; | |
944 | } | |
945 | ||
946 | static int MPBIOS_trigger(int idx) | |
947 | { | |
c2c21745 | 948 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
949 | int trigger; |
950 | ||
951 | /* | |
952 | * Determine IRQ trigger mode (edge or level sensitive): | |
953 | */ | |
c2c21745 | 954 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 955 | { |
54168ed7 IM |
956 | case 0: /* conforms, ie. bus-type dependent */ |
957 | if (test_bit(bus, mp_bus_not_pci)) | |
958 | trigger = default_ISA_trigger(idx); | |
959 | else | |
960 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 961 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
962 | switch (mp_bus_id_to_type[bus]) { |
963 | case MP_BUS_ISA: /* ISA pin */ | |
964 | { | |
965 | /* set before the switch */ | |
966 | break; | |
967 | } | |
968 | case MP_BUS_EISA: /* EISA pin */ | |
969 | { | |
970 | trigger = default_EISA_trigger(idx); | |
971 | break; | |
972 | } | |
973 | case MP_BUS_PCI: /* PCI pin */ | |
974 | { | |
975 | /* set before the switch */ | |
976 | break; | |
977 | } | |
978 | case MP_BUS_MCA: /* MCA pin */ | |
979 | { | |
980 | trigger = default_MCA_trigger(idx); | |
981 | break; | |
982 | } | |
983 | default: | |
984 | { | |
985 | printk(KERN_WARNING "broken BIOS!!\n"); | |
986 | trigger = 1; | |
987 | break; | |
988 | } | |
989 | } | |
990 | #endif | |
1da177e4 | 991 | break; |
54168ed7 | 992 | case 1: /* edge */ |
1da177e4 | 993 | { |
54168ed7 | 994 | trigger = 0; |
1da177e4 LT |
995 | break; |
996 | } | |
54168ed7 | 997 | case 2: /* reserved */ |
1da177e4 | 998 | { |
54168ed7 IM |
999 | printk(KERN_WARNING "broken BIOS!!\n"); |
1000 | trigger = 1; | |
1da177e4 LT |
1001 | break; |
1002 | } | |
54168ed7 | 1003 | case 3: /* level */ |
1da177e4 | 1004 | { |
54168ed7 | 1005 | trigger = 1; |
1da177e4 LT |
1006 | break; |
1007 | } | |
54168ed7 | 1008 | default: /* invalid */ |
1da177e4 LT |
1009 | { |
1010 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1011 | trigger = 0; |
1da177e4 LT |
1012 | break; |
1013 | } | |
1014 | } | |
1015 | return trigger; | |
1016 | } | |
1017 | ||
1018 | static inline int irq_polarity(int idx) | |
1019 | { | |
1020 | return MPBIOS_polarity(idx); | |
1021 | } | |
1022 | ||
1023 | static inline int irq_trigger(int idx) | |
1024 | { | |
1025 | return MPBIOS_trigger(idx); | |
1026 | } | |
1027 | ||
efa2559f | 1028 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1029 | static int pin_2_irq(int idx, int apic, int pin) |
1030 | { | |
1031 | int irq, i; | |
c2c21745 | 1032 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1033 | |
1034 | /* | |
1035 | * Debugging check, we are in big trouble if this message pops up! | |
1036 | */ | |
c2c21745 | 1037 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1038 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1039 | ||
54168ed7 | 1040 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1041 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1042 | } else { |
643befed AS |
1043 | /* |
1044 | * PCI IRQs are mapped in order | |
1045 | */ | |
1046 | i = irq = 0; | |
1047 | while (i < apic) | |
1048 | irq += nr_ioapic_registers[i++]; | |
1049 | irq += pin; | |
d6c88a50 | 1050 | /* |
54168ed7 IM |
1051 | * For MPS mode, so far only needed by ES7000 platform |
1052 | */ | |
d6c88a50 TG |
1053 | if (ioapic_renumber_irq) |
1054 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1055 | } |
1056 | ||
54168ed7 | 1057 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1058 | /* |
1059 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1060 | */ | |
1061 | if ((pin >= 16) && (pin <= 23)) { | |
1062 | if (pirq_entries[pin-16] != -1) { | |
1063 | if (!pirq_entries[pin-16]) { | |
1064 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1065 | "disabling PIRQ%d\n", pin-16); | |
1066 | } else { | |
1067 | irq = pirq_entries[pin-16]; | |
1068 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1069 | "using PIRQ%d -> IRQ %d\n", | |
1070 | pin-16, irq); | |
1071 | } | |
1072 | } | |
1073 | } | |
54168ed7 IM |
1074 | #endif |
1075 | ||
1da177e4 LT |
1076 | return irq; |
1077 | } | |
1078 | ||
e20c06fd YL |
1079 | /* |
1080 | * Find a specific PCI IRQ entry. | |
1081 | * Not an __init, possibly needed by modules | |
1082 | */ | |
1083 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1084 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1085 | { |
1086 | int apic, i, best_guess = -1; | |
1087 | ||
1088 | apic_printk(APIC_DEBUG, | |
1089 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1090 | bus, slot, pin); | |
1091 | if (test_bit(bus, mp_bus_not_pci)) { | |
1092 | apic_printk(APIC_VERBOSE, | |
1093 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1094 | return -1; | |
1095 | } | |
1096 | for (i = 0; i < mp_irq_entries; i++) { | |
1097 | int lbus = mp_irqs[i].srcbus; | |
1098 | ||
1099 | for (apic = 0; apic < nr_ioapics; apic++) | |
1100 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1101 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1102 | break; | |
1103 | ||
1104 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1105 | !mp_irqs[i].irqtype && | |
1106 | (bus == lbus) && | |
1107 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1108 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1109 | ||
1110 | if (!(apic || IO_APIC_IRQ(irq))) | |
1111 | continue; | |
1112 | ||
1113 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1114 | set_io_apic_irq_attr(irq_attr, apic, |
1115 | mp_irqs[i].dstirq, | |
1116 | irq_trigger(i), | |
1117 | irq_polarity(i)); | |
e20c06fd YL |
1118 | return irq; |
1119 | } | |
1120 | /* | |
1121 | * Use the first all-but-pin matching entry as a | |
1122 | * best-guess fuzzy result for broken mptables. | |
1123 | */ | |
1124 | if (best_guess < 0) { | |
e5198075 YL |
1125 | set_io_apic_irq_attr(irq_attr, apic, |
1126 | mp_irqs[i].dstirq, | |
1127 | irq_trigger(i), | |
1128 | irq_polarity(i)); | |
e20c06fd YL |
1129 | best_guess = irq; |
1130 | } | |
1131 | } | |
1132 | } | |
1133 | return best_guess; | |
1134 | } | |
1135 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1136 | ||
497c9a19 YL |
1137 | void lock_vector_lock(void) |
1138 | { | |
1139 | /* Used to the online set of cpus does not change | |
1140 | * during assign_irq_vector. | |
1141 | */ | |
1142 | spin_lock(&vector_lock); | |
1143 | } | |
1da177e4 | 1144 | |
497c9a19 | 1145 | void unlock_vector_lock(void) |
1da177e4 | 1146 | { |
497c9a19 YL |
1147 | spin_unlock(&vector_lock); |
1148 | } | |
1da177e4 | 1149 | |
e7986739 MT |
1150 | static int |
1151 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1152 | { |
047c8fdb YL |
1153 | /* |
1154 | * NOTE! The local APIC isn't very good at handling | |
1155 | * multiple interrupts at the same interrupt level. | |
1156 | * As the interrupt level is determined by taking the | |
1157 | * vector number and shifting that right by 4, we | |
1158 | * want to spread these out a bit so that they don't | |
1159 | * all fall in the same interrupt level. | |
1160 | * | |
1161 | * Also, we've got to be careful not to trash gate | |
1162 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1163 | */ | |
54168ed7 IM |
1164 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1165 | unsigned int old_vector; | |
22f65d31 MT |
1166 | int cpu, err; |
1167 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1168 | |
54168ed7 IM |
1169 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1170 | return -EBUSY; | |
0a1ad60d | 1171 | |
22f65d31 MT |
1172 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1173 | return -ENOMEM; | |
ace80ab7 | 1174 | |
54168ed7 IM |
1175 | old_vector = cfg->vector; |
1176 | if (old_vector) { | |
22f65d31 MT |
1177 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1178 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1179 | if (!cpumask_empty(tmp_mask)) { | |
1180 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1181 | return 0; |
22f65d31 | 1182 | } |
54168ed7 | 1183 | } |
497c9a19 | 1184 | |
e7986739 | 1185 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1186 | err = -ENOSPC; |
1187 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1188 | int new_cpu; |
1189 | int vector, offset; | |
497c9a19 | 1190 | |
e2d40b18 | 1191 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1192 | |
54168ed7 IM |
1193 | vector = current_vector; |
1194 | offset = current_offset; | |
497c9a19 | 1195 | next: |
54168ed7 IM |
1196 | vector += 8; |
1197 | if (vector >= first_system_vector) { | |
e7986739 | 1198 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1199 | offset = (offset + 1) % 8; |
1200 | vector = FIRST_DEVICE_VECTOR + offset; | |
1201 | } | |
1202 | if (unlikely(current_vector == vector)) | |
1203 | continue; | |
b77b881f YL |
1204 | |
1205 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1206 | goto next; |
b77b881f | 1207 | |
22f65d31 | 1208 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1209 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1210 | goto next; | |
1211 | /* Found one! */ | |
1212 | current_vector = vector; | |
1213 | current_offset = offset; | |
1214 | if (old_vector) { | |
1215 | cfg->move_in_progress = 1; | |
22f65d31 | 1216 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1217 | } |
22f65d31 | 1218 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1219 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1220 | cfg->vector = vector; | |
22f65d31 MT |
1221 | cpumask_copy(cfg->domain, tmp_mask); |
1222 | err = 0; | |
1223 | break; | |
54168ed7 | 1224 | } |
22f65d31 MT |
1225 | free_cpumask_var(tmp_mask); |
1226 | return err; | |
497c9a19 YL |
1227 | } |
1228 | ||
e7986739 MT |
1229 | static int |
1230 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1231 | { |
1232 | int err; | |
ace80ab7 | 1233 | unsigned long flags; |
ace80ab7 EB |
1234 | |
1235 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1236 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1237 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1238 | return err; |
1239 | } | |
1240 | ||
3145e941 | 1241 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1242 | { |
497c9a19 YL |
1243 | int cpu, vector; |
1244 | ||
497c9a19 YL |
1245 | BUG_ON(!cfg->vector); |
1246 | ||
1247 | vector = cfg->vector; | |
22f65d31 | 1248 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1249 | per_cpu(vector_irq, cpu)[vector] = -1; |
1250 | ||
1251 | cfg->vector = 0; | |
22f65d31 | 1252 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1253 | |
1254 | if (likely(!cfg->move_in_progress)) | |
1255 | return; | |
22f65d31 | 1256 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1257 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1258 | vector++) { | |
1259 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1260 | continue; | |
1261 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1262 | break; | |
1263 | } | |
1264 | } | |
1265 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1266 | } |
1267 | ||
1268 | void __setup_vector_irq(int cpu) | |
1269 | { | |
1270 | /* Initialize vector_irq on a new cpu */ | |
1271 | /* This function must be called with vector_lock held */ | |
1272 | int irq, vector; | |
1273 | struct irq_cfg *cfg; | |
0b8f1efa | 1274 | struct irq_desc *desc; |
497c9a19 YL |
1275 | |
1276 | /* Mark the inuse vectors */ | |
0b8f1efa | 1277 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1278 | cfg = desc->chip_data; |
22f65d31 | 1279 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1280 | continue; |
1281 | vector = cfg->vector; | |
497c9a19 YL |
1282 | per_cpu(vector_irq, cpu)[vector] = irq; |
1283 | } | |
1284 | /* Mark the free vectors */ | |
1285 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1286 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1287 | if (irq < 0) | |
1288 | continue; | |
1289 | ||
1290 | cfg = irq_cfg(irq); | |
22f65d31 | 1291 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1292 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1293 | } |
1da177e4 | 1294 | } |
3fde6900 | 1295 | |
f5b9ed7a | 1296 | static struct irq_chip ioapic_chip; |
54168ed7 | 1297 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1298 | |
54168ed7 IM |
1299 | #define IOAPIC_AUTO -1 |
1300 | #define IOAPIC_EDGE 0 | |
1301 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1302 | |
047c8fdb | 1303 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1304 | static inline int IO_APIC_irq_trigger(int irq) |
1305 | { | |
d6c88a50 | 1306 | int apic, idx, pin; |
1d025192 | 1307 | |
d6c88a50 TG |
1308 | for (apic = 0; apic < nr_ioapics; apic++) { |
1309 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1310 | idx = find_irq_entry(apic, pin, mp_INT); | |
1311 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1312 | return irq_trigger(idx); | |
1313 | } | |
1314 | } | |
1315 | /* | |
54168ed7 IM |
1316 | * nonexistent IRQs are edge default |
1317 | */ | |
d6c88a50 | 1318 | return 0; |
1d025192 | 1319 | } |
047c8fdb YL |
1320 | #else |
1321 | static inline int IO_APIC_irq_trigger(int irq) | |
1322 | { | |
54168ed7 | 1323 | return 1; |
047c8fdb YL |
1324 | } |
1325 | #endif | |
1d025192 | 1326 | |
3145e941 | 1327 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1328 | { |
199751d7 | 1329 | |
6ebcc00e | 1330 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1331 | trigger == IOAPIC_LEVEL) |
08678b08 | 1332 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1333 | else |
1334 | desc->status &= ~IRQ_LEVEL; | |
1335 | ||
54168ed7 IM |
1336 | if (irq_remapped(irq)) { |
1337 | desc->status |= IRQ_MOVE_PCNTXT; | |
1338 | if (trigger) | |
1339 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1340 | handle_fasteoi_irq, | |
1341 | "fasteoi"); | |
1342 | else | |
1343 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1344 | handle_edge_irq, "edge"); | |
1345 | return; | |
1346 | } | |
29b61be6 | 1347 | |
047c8fdb YL |
1348 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1349 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1350 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1351 | handle_fasteoi_irq, |
1352 | "fasteoi"); | |
047c8fdb | 1353 | else |
a460e745 | 1354 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1355 | handle_edge_irq, "edge"); |
1da177e4 LT |
1356 | } |
1357 | ||
ca97ab90 JF |
1358 | int setup_ioapic_entry(int apic_id, int irq, |
1359 | struct IO_APIC_route_entry *entry, | |
1360 | unsigned int destination, int trigger, | |
0280f7c4 | 1361 | int polarity, int vector, int pin) |
1da177e4 | 1362 | { |
497c9a19 YL |
1363 | /* |
1364 | * add it to the IO-APIC irq-routing table: | |
1365 | */ | |
1366 | memset(entry,0,sizeof(*entry)); | |
1367 | ||
54168ed7 | 1368 | if (intr_remapping_enabled) { |
c8d46cf0 | 1369 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1370 | struct irte irte; |
1371 | struct IR_IO_APIC_route_entry *ir_entry = | |
1372 | (struct IR_IO_APIC_route_entry *) entry; | |
1373 | int index; | |
1374 | ||
1375 | if (!iommu) | |
c8d46cf0 | 1376 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1377 | |
1378 | index = alloc_irte(iommu, irq, 1); | |
1379 | if (index < 0) | |
c8d46cf0 | 1380 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1381 | |
1382 | memset(&irte, 0, sizeof(irte)); | |
1383 | ||
1384 | irte.present = 1; | |
9b5bc8dc | 1385 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1386 | /* |
1387 | * Trigger mode in the IRTE will always be edge, and the | |
1388 | * actual level or edge trigger will be setup in the IO-APIC | |
1389 | * RTE. This will help simplify level triggered irq migration. | |
1390 | * For more details, see the comments above explainig IO-APIC | |
1391 | * irq migration in the presence of interrupt-remapping. | |
1392 | */ | |
1393 | irte.trigger_mode = 0; | |
9b5bc8dc | 1394 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1395 | irte.vector = vector; |
1396 | irte.dest_id = IRTE_DEST(destination); | |
1397 | ||
f007e99c WH |
1398 | /* Set source-id of interrupt request */ |
1399 | set_ioapic_sid(&irte, apic_id); | |
1400 | ||
54168ed7 IM |
1401 | modify_irte(irq, &irte); |
1402 | ||
1403 | ir_entry->index2 = (index >> 15) & 0x1; | |
1404 | ir_entry->zero = 0; | |
1405 | ir_entry->format = 1; | |
1406 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1407 | /* |
1408 | * IO-APIC RTE will be configured with virtual vector. | |
1409 | * irq handler will do the explicit EOI to the io-apic. | |
1410 | */ | |
1411 | ir_entry->vector = pin; | |
29b61be6 | 1412 | } else { |
9b5bc8dc IM |
1413 | entry->delivery_mode = apic->irq_delivery_mode; |
1414 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1415 | entry->dest = destination; |
0280f7c4 | 1416 | entry->vector = vector; |
54168ed7 | 1417 | } |
497c9a19 | 1418 | |
54168ed7 | 1419 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1420 | entry->trigger = trigger; |
1421 | entry->polarity = polarity; | |
497c9a19 YL |
1422 | |
1423 | /* Mask level triggered irqs. | |
1424 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1425 | */ | |
1426 | if (trigger) | |
1427 | entry->mask = 1; | |
497c9a19 YL |
1428 | return 0; |
1429 | } | |
1430 | ||
c8d46cf0 | 1431 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1432 | int trigger, int polarity) |
497c9a19 YL |
1433 | { |
1434 | struct irq_cfg *cfg; | |
1da177e4 | 1435 | struct IO_APIC_route_entry entry; |
22f65d31 | 1436 | unsigned int dest; |
497c9a19 YL |
1437 | |
1438 | if (!IO_APIC_IRQ(irq)) | |
1439 | return; | |
1440 | ||
3145e941 | 1441 | cfg = desc->chip_data; |
497c9a19 | 1442 | |
fe402e1f | 1443 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1444 | return; |
1445 | ||
debccb3e | 1446 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1447 | |
1448 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1449 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1450 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1451 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1452 | irq, trigger, polarity); |
1453 | ||
1454 | ||
c8d46cf0 | 1455 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1456 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1457 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1458 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1459 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1460 | return; |
1461 | } | |
1462 | ||
3145e941 | 1463 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1464 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1465 | disable_8259A_irq(irq); |
1466 | ||
c8d46cf0 | 1467 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1468 | } |
1469 | ||
b9c61b70 YL |
1470 | static struct { |
1471 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1472 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1473 | ||
497c9a19 YL |
1474 | static void __init setup_IO_APIC_irqs(void) |
1475 | { | |
b9c61b70 | 1476 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1477 | int notcon = 0; |
0b8f1efa | 1478 | struct irq_desc *desc; |
3145e941 | 1479 | struct irq_cfg *cfg; |
85ac16d0 | 1480 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1481 | |
1482 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1483 | ||
b9c61b70 YL |
1484 | #ifdef CONFIG_ACPI |
1485 | if (!acpi_disabled && acpi_ioapic) { | |
1486 | apic_id = mp_find_ioapic(0); | |
1487 | if (apic_id < 0) | |
1488 | apic_id = 0; | |
1489 | } | |
1490 | #endif | |
3c2cbd24 | 1491 | |
b9c61b70 YL |
1492 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1493 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1494 | if (idx == -1) { | |
1495 | if (!notcon) { | |
1496 | notcon = 1; | |
1497 | apic_printk(APIC_VERBOSE, | |
1498 | KERN_DEBUG " %d-%d", | |
1499 | mp_ioapics[apic_id].apicid, pin); | |
1500 | } else | |
1501 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1502 | mp_ioapics[apic_id].apicid, pin); | |
1503 | continue; | |
1504 | } | |
1505 | if (notcon) { | |
1506 | apic_printk(APIC_VERBOSE, | |
1507 | " (apicid-pin) not connected\n"); | |
1508 | notcon = 0; | |
1509 | } | |
33a201fa | 1510 | |
b9c61b70 | 1511 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1512 | |
b9c61b70 YL |
1513 | /* |
1514 | * Skip the timer IRQ if there's a quirk handler | |
1515 | * installed and if it returns 1: | |
1516 | */ | |
1517 | if (apic->multi_timer_check && | |
1518 | apic->multi_timer_check(apic_id, irq)) | |
1519 | continue; | |
36062448 | 1520 | |
b9c61b70 YL |
1521 | desc = irq_to_desc_alloc_node(irq, node); |
1522 | if (!desc) { | |
1523 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1524 | continue; | |
3c2cbd24 | 1525 | } |
b9c61b70 YL |
1526 | cfg = desc->chip_data; |
1527 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1528 | /* |
1529 | * don't mark it in pin_programmed, so later acpi could | |
1530 | * set it correctly when irq < 16 | |
1531 | */ | |
b9c61b70 YL |
1532 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1533 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1534 | } |
1535 | ||
3c2cbd24 CG |
1536 | if (notcon) |
1537 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1538 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1539 | } |
1540 | ||
1541 | /* | |
f7633ce5 | 1542 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1543 | */ |
c8d46cf0 | 1544 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1545 | int vector) |
1da177e4 LT |
1546 | { |
1547 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1548 | |
54168ed7 IM |
1549 | if (intr_remapping_enabled) |
1550 | return; | |
54168ed7 | 1551 | |
36062448 | 1552 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1553 | |
1554 | /* | |
1555 | * We use logical delivery to get the timer IRQ | |
1556 | * to the first CPU. | |
1557 | */ | |
9b5bc8dc | 1558 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1559 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1560 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1561 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1562 | entry.polarity = 0; |
1563 | entry.trigger = 0; | |
1564 | entry.vector = vector; | |
1565 | ||
1566 | /* | |
1567 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1568 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1569 | */ |
54168ed7 | 1570 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1571 | |
1572 | /* | |
1573 | * Add it to the IO-APIC irq-routing table: | |
1574 | */ | |
c8d46cf0 | 1575 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1576 | } |
1577 | ||
32f71aff MR |
1578 | |
1579 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1580 | { |
1581 | int apic, i; | |
1582 | union IO_APIC_reg_00 reg_00; | |
1583 | union IO_APIC_reg_01 reg_01; | |
1584 | union IO_APIC_reg_02 reg_02; | |
1585 | union IO_APIC_reg_03 reg_03; | |
1586 | unsigned long flags; | |
0f978f45 | 1587 | struct irq_cfg *cfg; |
0b8f1efa | 1588 | struct irq_desc *desc; |
8f09cd20 | 1589 | unsigned int irq; |
1da177e4 LT |
1590 | |
1591 | if (apic_verbosity == APIC_QUIET) | |
1592 | return; | |
1593 | ||
36062448 | 1594 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1595 | for (i = 0; i < nr_ioapics; i++) |
1596 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1597 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1598 | |
1599 | /* | |
1600 | * We are a bit conservative about what we expect. We have to | |
1601 | * know about every hardware change ASAP. | |
1602 | */ | |
1603 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1604 | ||
1605 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1606 | ||
1607 | spin_lock_irqsave(&ioapic_lock, flags); | |
1608 | reg_00.raw = io_apic_read(apic, 0); | |
1609 | reg_01.raw = io_apic_read(apic, 1); | |
1610 | if (reg_01.bits.version >= 0x10) | |
1611 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1612 | if (reg_01.bits.version >= 0x20) |
1613 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1614 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1615 | ||
54168ed7 | 1616 | printk("\n"); |
b5ba7e6d | 1617 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1618 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1619 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1620 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1621 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1622 | |
54168ed7 | 1623 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1624 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1625 | |
1626 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1627 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1628 | |
1629 | /* | |
1630 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1631 | * but the value of reg_02 is read as the previous read register | |
1632 | * value, so ignore it if reg_02 == reg_01. | |
1633 | */ | |
1634 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1635 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1636 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1637 | } |
1638 | ||
1639 | /* | |
1640 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1641 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1642 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1643 | */ | |
1644 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1645 | reg_03.raw != reg_01.raw) { | |
1646 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1647 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1648 | } |
1649 | ||
1650 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1651 | ||
d83e94ac YL |
1652 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1653 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1654 | |
1655 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1656 | struct IO_APIC_route_entry entry; | |
1657 | ||
cf4c6a2f | 1658 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1659 | |
54168ed7 IM |
1660 | printk(KERN_DEBUG " %02x %03X ", |
1661 | i, | |
1662 | entry.dest | |
1663 | ); | |
1da177e4 LT |
1664 | |
1665 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1666 | entry.mask, | |
1667 | entry.trigger, | |
1668 | entry.irr, | |
1669 | entry.polarity, | |
1670 | entry.delivery_status, | |
1671 | entry.dest_mode, | |
1672 | entry.delivery_mode, | |
1673 | entry.vector | |
1674 | ); | |
1675 | } | |
1676 | } | |
1da177e4 | 1677 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1678 | for_each_irq_desc(irq, desc) { |
1679 | struct irq_pin_list *entry; | |
1680 | ||
0b8f1efa YL |
1681 | cfg = desc->chip_data; |
1682 | entry = cfg->irq_2_pin; | |
0f978f45 | 1683 | if (!entry) |
1da177e4 | 1684 | continue; |
8f09cd20 | 1685 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1686 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1687 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1688 | printk("\n"); |
1689 | } | |
1690 | ||
1691 | printk(KERN_INFO ".................................... done.\n"); | |
1692 | ||
1693 | return; | |
1694 | } | |
1695 | ||
251e1e44 | 1696 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1697 | { |
251e1e44 | 1698 | int i; |
1da177e4 LT |
1699 | |
1700 | if (apic_verbosity == APIC_QUIET) | |
1701 | return; | |
1702 | ||
251e1e44 IM |
1703 | printk(KERN_DEBUG); |
1704 | ||
1705 | for (i = 0; i < 8; i++) | |
1706 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1707 | ||
1708 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1709 | } |
1710 | ||
32f71aff | 1711 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1712 | { |
97a52714 | 1713 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1714 | u64 icr; |
1da177e4 LT |
1715 | |
1716 | if (apic_verbosity == APIC_QUIET) | |
1717 | return; | |
1718 | ||
251e1e44 | 1719 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1720 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1721 | v = apic_read(APIC_ID); |
54168ed7 | 1722 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1723 | v = apic_read(APIC_LVR); |
1724 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1725 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1726 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1727 | |
1728 | v = apic_read(APIC_TASKPRI); | |
1729 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1730 | ||
54168ed7 | 1731 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1732 | if (!APIC_XAPIC(ver)) { |
1733 | v = apic_read(APIC_ARBPRI); | |
1734 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1735 | v & APIC_ARBPRI_MASK); | |
1736 | } | |
1da177e4 LT |
1737 | v = apic_read(APIC_PROCPRI); |
1738 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1739 | } | |
1740 | ||
a11b5abe YL |
1741 | /* |
1742 | * Remote read supported only in the 82489DX and local APIC for | |
1743 | * Pentium processors. | |
1744 | */ | |
1745 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1746 | v = apic_read(APIC_RRR); | |
1747 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1748 | } | |
1749 | ||
1da177e4 LT |
1750 | v = apic_read(APIC_LDR); |
1751 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1752 | if (!x2apic_enabled()) { |
1753 | v = apic_read(APIC_DFR); | |
1754 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1755 | } | |
1da177e4 LT |
1756 | v = apic_read(APIC_SPIV); |
1757 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1758 | ||
1759 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1760 | print_APIC_field(APIC_ISR); |
1da177e4 | 1761 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1762 | print_APIC_field(APIC_TMR); |
1da177e4 | 1763 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1764 | print_APIC_field(APIC_IRR); |
1da177e4 | 1765 | |
54168ed7 IM |
1766 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1767 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1768 | apic_write(APIC_ESR, 0); |
54168ed7 | 1769 | |
1da177e4 LT |
1770 | v = apic_read(APIC_ESR); |
1771 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1772 | } | |
1773 | ||
7ab6af7a | 1774 | icr = apic_icr_read(); |
0c425cec IM |
1775 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1776 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1777 | |
1778 | v = apic_read(APIC_LVTT); | |
1779 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1780 | ||
1781 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1782 | v = apic_read(APIC_LVTPC); | |
1783 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1784 | } | |
1785 | v = apic_read(APIC_LVT0); | |
1786 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1787 | v = apic_read(APIC_LVT1); | |
1788 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1789 | ||
1790 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1791 | v = apic_read(APIC_LVTERR); | |
1792 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1793 | } | |
1794 | ||
1795 | v = apic_read(APIC_TMICT); | |
1796 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1797 | v = apic_read(APIC_TMCCT); | |
1798 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1799 | v = apic_read(APIC_TDCR); | |
1800 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1801 | |
1802 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1803 | v = apic_read(APIC_EFEAT); | |
1804 | maxlvt = (v >> 16) & 0xff; | |
1805 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1806 | v = apic_read(APIC_ECTRL); | |
1807 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1808 | for (i = 0; i < maxlvt; i++) { | |
1809 | v = apic_read(APIC_EILVTn(i)); | |
1810 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1811 | } | |
1812 | } | |
1da177e4 LT |
1813 | printk("\n"); |
1814 | } | |
1815 | ||
32f71aff | 1816 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1817 | { |
ffd5aae7 YL |
1818 | int cpu; |
1819 | ||
1820 | preempt_disable(); | |
1821 | for_each_online_cpu(cpu) | |
1822 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1823 | preempt_enable(); | |
1da177e4 LT |
1824 | } |
1825 | ||
32f71aff | 1826 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1827 | { |
1da177e4 LT |
1828 | unsigned int v; |
1829 | unsigned long flags; | |
1830 | ||
1831 | if (apic_verbosity == APIC_QUIET) | |
1832 | return; | |
1833 | ||
1834 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1835 | ||
1836 | spin_lock_irqsave(&i8259A_lock, flags); | |
1837 | ||
1838 | v = inb(0xa1) << 8 | inb(0x21); | |
1839 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1840 | ||
1841 | v = inb(0xa0) << 8 | inb(0x20); | |
1842 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1843 | ||
54168ed7 IM |
1844 | outb(0x0b,0xa0); |
1845 | outb(0x0b,0x20); | |
1da177e4 | 1846 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1847 | outb(0x0a,0xa0); |
1848 | outb(0x0a,0x20); | |
1da177e4 LT |
1849 | |
1850 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1851 | ||
1852 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1853 | ||
1854 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1855 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1856 | } | |
1857 | ||
32f71aff MR |
1858 | __apicdebuginit(int) print_all_ICs(void) |
1859 | { | |
1860 | print_PIC(); | |
4797f6b0 YL |
1861 | |
1862 | /* don't print out if apic is not there */ | |
1863 | if (!cpu_has_apic || disable_apic) | |
1864 | return 0; | |
1865 | ||
32f71aff MR |
1866 | print_all_local_APICs(); |
1867 | print_IO_APIC(); | |
1868 | ||
1869 | return 0; | |
1870 | } | |
1871 | ||
1872 | fs_initcall(print_all_ICs); | |
1873 | ||
1da177e4 | 1874 | |
efa2559f YL |
1875 | /* Where if anywhere is the i8259 connect in external int mode */ |
1876 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1877 | ||
54168ed7 | 1878 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1879 | { |
1880 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1881 | int i8259_apic, i8259_pin; |
54168ed7 | 1882 | int apic; |
1da177e4 LT |
1883 | unsigned long flags; |
1884 | ||
1da177e4 LT |
1885 | /* |
1886 | * The number of IO-APIC IRQ registers (== #pins): | |
1887 | */ | |
fcfd636a | 1888 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1889 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1890 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1891 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1892 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1893 | } | |
54168ed7 | 1894 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1895 | int pin; |
1896 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1897 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1898 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1899 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1900 | |
fcfd636a EB |
1901 | /* If the interrupt line is enabled and in ExtInt mode |
1902 | * I have found the pin where the i8259 is connected. | |
1903 | */ | |
1904 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1905 | ioapic_i8259.apic = apic; | |
1906 | ioapic_i8259.pin = pin; | |
1907 | goto found_i8259; | |
1908 | } | |
1909 | } | |
1910 | } | |
1911 | found_i8259: | |
1912 | /* Look to see what if the MP table has reported the ExtINT */ | |
1913 | /* If we could not find the appropriate pin by looking at the ioapic | |
1914 | * the i8259 probably is not connected the ioapic but give the | |
1915 | * mptable a chance anyway. | |
1916 | */ | |
1917 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1918 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1919 | /* Trust the MP table if nothing is setup in the hardware */ | |
1920 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1921 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1922 | ioapic_i8259.pin = i8259_pin; | |
1923 | ioapic_i8259.apic = i8259_apic; | |
1924 | } | |
1925 | /* Complain if the MP table and the hardware disagree */ | |
1926 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1927 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1928 | { | |
1929 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1930 | } |
1931 | ||
1932 | /* | |
1933 | * Do not trust the IO-APIC being empty at bootup | |
1934 | */ | |
1935 | clear_IO_APIC(); | |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * Not an __init, needed by the reboot code | |
1940 | */ | |
1941 | void disable_IO_APIC(void) | |
1942 | { | |
1943 | /* | |
1944 | * Clear the IO-APIC before rebooting: | |
1945 | */ | |
1946 | clear_IO_APIC(); | |
1947 | ||
650927ef | 1948 | /* |
0b968d23 | 1949 | * If the i8259 is routed through an IOAPIC |
650927ef | 1950 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1951 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1952 | * |
1953 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1954 | * as virtual wire B is little complex (need to configure both | |
1955 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1956 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1957 | */ |
7c6d9f97 | 1958 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1959 | struct IO_APIC_route_entry entry; |
650927ef EB |
1960 | |
1961 | memset(&entry, 0, sizeof(entry)); | |
1962 | entry.mask = 0; /* Enabled */ | |
1963 | entry.trigger = 0; /* Edge */ | |
1964 | entry.irr = 0; | |
1965 | entry.polarity = 0; /* High */ | |
1966 | entry.delivery_status = 0; | |
1967 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1968 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1969 | entry.vector = 0; |
54168ed7 | 1970 | entry.dest = read_apic_id(); |
650927ef EB |
1971 | |
1972 | /* | |
1973 | * Add it to the IO-APIC irq-routing table: | |
1974 | */ | |
cf4c6a2f | 1975 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1976 | } |
54168ed7 | 1977 | |
7c6d9f97 SS |
1978 | /* |
1979 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1980 | */ | |
3f4c3955 CG |
1981 | if (cpu_has_apic) |
1982 | disconnect_bsp_APIC(!intr_remapping_enabled && | |
1983 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1984 | } |
1985 | ||
54168ed7 | 1986 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1987 | /* |
1988 | * function to set the IO-APIC physical IDs based on the | |
1989 | * values stored in the MPC table. | |
1990 | * | |
1991 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1992 | */ | |
1993 | ||
1da177e4 LT |
1994 | static void __init setup_ioapic_ids_from_mpc(void) |
1995 | { | |
1996 | union IO_APIC_reg_00 reg_00; | |
1997 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1998 | int apic_id; |
1da177e4 LT |
1999 | int i; |
2000 | unsigned char old_id; | |
2001 | unsigned long flags; | |
2002 | ||
a4dbc34d | 2003 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2004 | return; |
d49c4288 | 2005 | |
ca05fea6 NP |
2006 | /* |
2007 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2008 | * no meaning without the serial APIC bus. | |
2009 | */ | |
7c5c1e42 SL |
2010 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2011 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2012 | return; |
1da177e4 LT |
2013 | /* |
2014 | * This is broken; anything with a real cpu count has to | |
2015 | * circumvent this idiocy regardless. | |
2016 | */ | |
d190cb87 | 2017 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2018 | |
2019 | /* | |
2020 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2021 | */ | |
c8d46cf0 | 2022 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2023 | |
2024 | /* Read the register 0 value */ | |
2025 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2026 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2027 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2028 | |
c8d46cf0 | 2029 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2030 | |
c8d46cf0 | 2031 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2032 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2033 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2034 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2035 | reg_00.bits.ID); | |
c8d46cf0 | 2036 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2037 | } |
2038 | ||
1da177e4 LT |
2039 | /* |
2040 | * Sanity check, is the ID really free? Every APIC in a | |
2041 | * system must have a unique ID or we get lots of nice | |
2042 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2043 | */ | |
d1d7cae8 | 2044 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2045 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2046 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2047 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2048 | for (i = 0; i < get_physical_broadcast(); i++) |
2049 | if (!physid_isset(i, phys_id_present_map)) | |
2050 | break; | |
2051 | if (i >= get_physical_broadcast()) | |
2052 | panic("Max APIC ID exceeded!\n"); | |
2053 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2054 | i); | |
2055 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2056 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2057 | } else { |
2058 | physid_mask_t tmp; | |
8058714a | 2059 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2060 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2061 | "phys_id_present_map\n", | |
c8d46cf0 | 2062 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2063 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2064 | } | |
2065 | ||
2066 | ||
2067 | /* | |
2068 | * We need to adjust the IRQ routing table | |
2069 | * if the ID changed. | |
2070 | */ | |
c8d46cf0 | 2071 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2072 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2073 | if (mp_irqs[i].dstapic == old_id) |
2074 | mp_irqs[i].dstapic | |
c8d46cf0 | 2075 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2076 | |
2077 | /* | |
2078 | * Read the right value from the MPC table and | |
2079 | * write it into the ID register. | |
36062448 | 2080 | */ |
1da177e4 LT |
2081 | apic_printk(APIC_VERBOSE, KERN_INFO |
2082 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2083 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2084 | |
c8d46cf0 | 2085 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2086 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2087 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2088 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2089 | |
2090 | /* | |
2091 | * Sanity check | |
2092 | */ | |
2093 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2094 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2095 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2096 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2097 | printk("could not set ID!\n"); |
2098 | else | |
2099 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2100 | } | |
2101 | } | |
54168ed7 | 2102 | #endif |
1da177e4 | 2103 | |
7ce0bcfd | 2104 | int no_timer_check __initdata; |
8542b200 ZA |
2105 | |
2106 | static int __init notimercheck(char *s) | |
2107 | { | |
2108 | no_timer_check = 1; | |
2109 | return 1; | |
2110 | } | |
2111 | __setup("no_timer_check", notimercheck); | |
2112 | ||
1da177e4 LT |
2113 | /* |
2114 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2115 | * about the timer IRQ. We do the following to work around the situation: | |
2116 | * | |
2117 | * - timer IRQ defaults to IO-APIC IRQ | |
2118 | * - if this function detects that timer IRQs are defunct, then we fall | |
2119 | * back to ISA timer IRQs | |
2120 | */ | |
f0a7a5c9 | 2121 | static int __init timer_irq_works(void) |
1da177e4 LT |
2122 | { |
2123 | unsigned long t1 = jiffies; | |
4aae0702 | 2124 | unsigned long flags; |
1da177e4 | 2125 | |
8542b200 ZA |
2126 | if (no_timer_check) |
2127 | return 1; | |
2128 | ||
4aae0702 | 2129 | local_save_flags(flags); |
1da177e4 LT |
2130 | local_irq_enable(); |
2131 | /* Let ten ticks pass... */ | |
2132 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2133 | local_irq_restore(flags); |
1da177e4 LT |
2134 | |
2135 | /* | |
2136 | * Expect a few ticks at least, to be sure some possible | |
2137 | * glue logic does not lock up after one or two first | |
2138 | * ticks in a non-ExtINT mode. Also the local APIC | |
2139 | * might have cached one ExtINT interrupt. Finally, at | |
2140 | * least one tick may be lost due to delays. | |
2141 | */ | |
54168ed7 IM |
2142 | |
2143 | /* jiffies wrap? */ | |
1d16b53e | 2144 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2145 | return 1; |
1da177e4 LT |
2146 | return 0; |
2147 | } | |
2148 | ||
2149 | /* | |
2150 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2151 | * number of pending IRQ events unhandled. These cases are very rare, | |
2152 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2153 | * better to do it this way as thus we do not have to be aware of | |
2154 | * 'pending' interrupts in the IRQ path, except at this point. | |
2155 | */ | |
2156 | /* | |
2157 | * Edge triggered needs to resend any interrupt | |
2158 | * that was delayed but this is now handled in the device | |
2159 | * independent code. | |
2160 | */ | |
2161 | ||
2162 | /* | |
2163 | * Starting up a edge-triggered IO-APIC interrupt is | |
2164 | * nasty - we need to make sure that we get the edge. | |
2165 | * If it is already asserted for some reason, we need | |
2166 | * return 1 to indicate that is was pending. | |
2167 | * | |
2168 | * This is not complete - we should be able to fake | |
2169 | * an edge even if it isn't on the 8259A... | |
2170 | */ | |
54168ed7 | 2171 | |
f5b9ed7a | 2172 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2173 | { |
2174 | int was_pending = 0; | |
2175 | unsigned long flags; | |
0b8f1efa | 2176 | struct irq_cfg *cfg; |
1da177e4 LT |
2177 | |
2178 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2179 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2180 | disable_8259A_irq(irq); |
2181 | if (i8259A_irq_pending(irq)) | |
2182 | was_pending = 1; | |
2183 | } | |
0b8f1efa | 2184 | cfg = irq_cfg(irq); |
3145e941 | 2185 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2186 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2187 | ||
2188 | return was_pending; | |
2189 | } | |
2190 | ||
ace80ab7 | 2191 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2192 | { |
54168ed7 IM |
2193 | |
2194 | struct irq_cfg *cfg = irq_cfg(irq); | |
2195 | unsigned long flags; | |
2196 | ||
2197 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2198 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2199 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2200 | |
2201 | return 1; | |
2202 | } | |
497c9a19 | 2203 | |
54168ed7 IM |
2204 | /* |
2205 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2206 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2207 | * handled with the level-triggered descriptor, but that one has slightly | |
2208 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2209 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2210 | * races. | |
2211 | */ | |
497c9a19 | 2212 | |
54168ed7 | 2213 | #ifdef CONFIG_SMP |
e85abf8f GH |
2214 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2215 | { | |
2216 | cpumask_var_t cleanup_mask; | |
2217 | ||
2218 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2219 | unsigned int i; | |
2220 | cfg->move_cleanup_count = 0; | |
2221 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2222 | cfg->move_cleanup_count++; | |
2223 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2224 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2225 | } else { | |
2226 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2227 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2228 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2229 | free_cpumask_var(cleanup_mask); | |
2230 | } | |
2231 | cfg->move_in_progress = 0; | |
2232 | } | |
2233 | ||
4420471f | 2234 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2235 | { |
2236 | int apic, pin; | |
2237 | struct irq_pin_list *entry; | |
2238 | u8 vector = cfg->vector; | |
2239 | ||
2977fb3f | 2240 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2241 | unsigned int reg; |
2242 | ||
e85abf8f GH |
2243 | apic = entry->apic; |
2244 | pin = entry->pin; | |
2245 | /* | |
2246 | * With interrupt-remapping, destination information comes | |
2247 | * from interrupt-remapping table entry. | |
2248 | */ | |
2249 | if (!irq_remapped(irq)) | |
2250 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2251 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2252 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2253 | reg |= vector; | |
2254 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2255 | } |
2256 | } | |
2257 | ||
4420471f IM |
2258 | static int |
2259 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2260 | ||
e85abf8f GH |
2261 | /* |
2262 | * Either sets desc->affinity to a valid value, and returns | |
2263 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2264 | * leaves desc->affinity untouched. | |
2265 | */ | |
2266 | static unsigned int | |
2267 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2268 | { | |
2269 | struct irq_cfg *cfg; | |
2270 | unsigned int irq; | |
2271 | ||
2272 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2273 | return BAD_APICID; | |
2274 | ||
2275 | irq = desc->irq; | |
2276 | cfg = desc->chip_data; | |
2277 | if (assign_irq_vector(irq, cfg, mask)) | |
2278 | return BAD_APICID; | |
2279 | ||
e85abf8f GH |
2280 | cpumask_copy(desc->affinity, mask); |
2281 | ||
2282 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2283 | } | |
2284 | ||
4420471f | 2285 | static int |
e85abf8f GH |
2286 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2287 | { | |
2288 | struct irq_cfg *cfg; | |
2289 | unsigned long flags; | |
2290 | unsigned int dest; | |
2291 | unsigned int irq; | |
4420471f | 2292 | int ret = -1; |
e85abf8f GH |
2293 | |
2294 | irq = desc->irq; | |
2295 | cfg = desc->chip_data; | |
2296 | ||
2297 | spin_lock_irqsave(&ioapic_lock, flags); | |
2298 | dest = set_desc_affinity(desc, mask); | |
2299 | if (dest != BAD_APICID) { | |
2300 | /* Only the high 8 bits are valid. */ | |
2301 | dest = SET_APIC_LOGICAL_ID(dest); | |
2302 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2303 | ret = 0; |
e85abf8f GH |
2304 | } |
2305 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2306 | |
2307 | return ret; | |
e85abf8f GH |
2308 | } |
2309 | ||
4420471f | 2310 | static int |
e85abf8f GH |
2311 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2312 | { | |
2313 | struct irq_desc *desc; | |
2314 | ||
2315 | desc = irq_to_desc(irq); | |
2316 | ||
4420471f | 2317 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2318 | } |
497c9a19 | 2319 | |
54168ed7 | 2320 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2321 | |
54168ed7 IM |
2322 | /* |
2323 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2324 | * | |
0280f7c4 SS |
2325 | * For both level and edge triggered, irq migration is a simple atomic |
2326 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2327 | * |
0280f7c4 SS |
2328 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2329 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2330 | * Real vector that is used for interrupting cpu will be coming from | |
2331 | * the interrupt-remapping table entry. | |
54168ed7 | 2332 | */ |
d5dedd45 | 2333 | static int |
e7986739 | 2334 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2335 | { |
54168ed7 | 2336 | struct irq_cfg *cfg; |
54168ed7 | 2337 | struct irte irte; |
54168ed7 | 2338 | unsigned int dest; |
3145e941 | 2339 | unsigned int irq; |
d5dedd45 | 2340 | int ret = -1; |
497c9a19 | 2341 | |
22f65d31 | 2342 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2343 | return ret; |
497c9a19 | 2344 | |
3145e941 | 2345 | irq = desc->irq; |
54168ed7 | 2346 | if (get_irte(irq, &irte)) |
d5dedd45 | 2347 | return ret; |
497c9a19 | 2348 | |
3145e941 YL |
2349 | cfg = desc->chip_data; |
2350 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2351 | return ret; |
54168ed7 | 2352 | |
debccb3e | 2353 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2354 | |
54168ed7 IM |
2355 | irte.vector = cfg->vector; |
2356 | irte.dest_id = IRTE_DEST(dest); | |
2357 | ||
2358 | /* | |
2359 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2360 | */ | |
2361 | modify_irte(irq, &irte); | |
2362 | ||
22f65d31 MT |
2363 | if (cfg->move_in_progress) |
2364 | send_cleanup_vector(cfg); | |
54168ed7 | 2365 | |
7f7ace0c | 2366 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2367 | |
2368 | return 0; | |
54168ed7 IM |
2369 | } |
2370 | ||
54168ed7 IM |
2371 | /* |
2372 | * Migrates the IRQ destination in the process context. | |
2373 | */ | |
d5dedd45 | 2374 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2375 | const struct cpumask *mask) |
54168ed7 | 2376 | { |
d5dedd45 | 2377 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2378 | } |
d5dedd45 | 2379 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2380 | const struct cpumask *mask) |
3145e941 YL |
2381 | { |
2382 | struct irq_desc *desc = irq_to_desc(irq); | |
2383 | ||
d5dedd45 | 2384 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2385 | } |
29b61be6 | 2386 | #else |
d5dedd45 | 2387 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2388 | const struct cpumask *mask) |
2389 | { | |
d5dedd45 | 2390 | return 0; |
29b61be6 | 2391 | } |
54168ed7 IM |
2392 | #endif |
2393 | ||
2394 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2395 | { | |
2396 | unsigned vector, me; | |
8f2466f4 | 2397 | |
54168ed7 | 2398 | ack_APIC_irq(); |
54168ed7 | 2399 | exit_idle(); |
54168ed7 IM |
2400 | irq_enter(); |
2401 | ||
2402 | me = smp_processor_id(); | |
2403 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2404 | unsigned int irq; | |
68a8ca59 | 2405 | unsigned int irr; |
54168ed7 IM |
2406 | struct irq_desc *desc; |
2407 | struct irq_cfg *cfg; | |
2408 | irq = __get_cpu_var(vector_irq)[vector]; | |
2409 | ||
0b8f1efa YL |
2410 | if (irq == -1) |
2411 | continue; | |
2412 | ||
54168ed7 IM |
2413 | desc = irq_to_desc(irq); |
2414 | if (!desc) | |
2415 | continue; | |
2416 | ||
2417 | cfg = irq_cfg(irq); | |
2418 | spin_lock(&desc->lock); | |
2419 | if (!cfg->move_cleanup_count) | |
2420 | goto unlock; | |
2421 | ||
22f65d31 | 2422 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2423 | goto unlock; |
2424 | ||
68a8ca59 SS |
2425 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2426 | /* | |
2427 | * Check if the vector that needs to be cleanedup is | |
2428 | * registered at the cpu's IRR. If so, then this is not | |
2429 | * the best time to clean it up. Lets clean it up in the | |
2430 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2431 | * to myself. | |
2432 | */ | |
2433 | if (irr & (1 << (vector % 32))) { | |
2434 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2435 | goto unlock; | |
2436 | } | |
54168ed7 IM |
2437 | __get_cpu_var(vector_irq)[vector] = -1; |
2438 | cfg->move_cleanup_count--; | |
2439 | unlock: | |
2440 | spin_unlock(&desc->lock); | |
2441 | } | |
2442 | ||
2443 | irq_exit(); | |
2444 | } | |
2445 | ||
3145e941 | 2446 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2447 | { |
3145e941 YL |
2448 | struct irq_desc *desc = *descp; |
2449 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2450 | unsigned vector, me; |
2451 | ||
fcef5911 | 2452 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2453 | return; |
2454 | ||
2455 | vector = ~get_irq_regs()->orig_ax; | |
2456 | me = smp_processor_id(); | |
10b888d6 | 2457 | |
fcef5911 | 2458 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2459 | send_cleanup_vector(cfg); |
497c9a19 YL |
2460 | } |
2461 | #else | |
3145e941 | 2462 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2463 | #endif |
3145e941 | 2464 | |
1d025192 YL |
2465 | static void ack_apic_edge(unsigned int irq) |
2466 | { | |
3145e941 YL |
2467 | struct irq_desc *desc = irq_to_desc(irq); |
2468 | ||
2469 | irq_complete_move(&desc); | |
1d025192 YL |
2470 | move_native_irq(irq); |
2471 | ack_APIC_irq(); | |
2472 | } | |
2473 | ||
3eb2cce8 | 2474 | atomic_t irq_mis_count; |
3eb2cce8 | 2475 | |
047c8fdb YL |
2476 | static void ack_apic_level(unsigned int irq) |
2477 | { | |
3145e941 | 2478 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2479 | unsigned long v; |
2480 | int i; | |
3145e941 | 2481 | struct irq_cfg *cfg; |
54168ed7 | 2482 | int do_unmask_irq = 0; |
047c8fdb | 2483 | |
3145e941 | 2484 | irq_complete_move(&desc); |
047c8fdb | 2485 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2486 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2487 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2488 | do_unmask_irq = 1; |
3145e941 | 2489 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2490 | } |
047c8fdb YL |
2491 | #endif |
2492 | ||
3eb2cce8 | 2493 | /* |
916a0fe7 JF |
2494 | * It appears there is an erratum which affects at least version 0x11 |
2495 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2496 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2497 | * erroneously delivered as edge-triggered one but the respective IRR | |
2498 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2499 | * message but it will never arrive and further interrupts are blocked | |
2500 | * from the source. The exact reason is so far unknown, but the | |
2501 | * phenomenon was observed when two consecutive interrupt requests | |
2502 | * from a given source get delivered to the same CPU and the source is | |
2503 | * temporarily disabled in between. | |
2504 | * | |
2505 | * A workaround is to simulate an EOI message manually. We achieve it | |
2506 | * by setting the trigger mode to edge and then to level when the edge | |
2507 | * trigger mode gets detected in the TMR of a local APIC for a | |
2508 | * level-triggered interrupt. We mask the source for the time of the | |
2509 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2510 | * The idea is from Manfred Spraul. --macro | |
2511 | */ | |
3145e941 YL |
2512 | cfg = desc->chip_data; |
2513 | i = cfg->vector; | |
3eb2cce8 | 2514 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2515 | |
54168ed7 IM |
2516 | /* |
2517 | * We must acknowledge the irq before we move it or the acknowledge will | |
2518 | * not propagate properly. | |
2519 | */ | |
2520 | ack_APIC_irq(); | |
2521 | ||
2522 | /* Now we can move and renable the irq */ | |
2523 | if (unlikely(do_unmask_irq)) { | |
2524 | /* Only migrate the irq if the ack has been received. | |
2525 | * | |
2526 | * On rare occasions the broadcast level triggered ack gets | |
2527 | * delayed going to ioapics, and if we reprogram the | |
2528 | * vector while Remote IRR is still set the irq will never | |
2529 | * fire again. | |
2530 | * | |
2531 | * To prevent this scenario we read the Remote IRR bit | |
2532 | * of the ioapic. This has two effects. | |
2533 | * - On any sane system the read of the ioapic will | |
2534 | * flush writes (and acks) going to the ioapic from | |
2535 | * this cpu. | |
2536 | * - We get to see if the ACK has actually been delivered. | |
2537 | * | |
2538 | * Based on failed experiments of reprogramming the | |
2539 | * ioapic entry from outside of irq context starting | |
2540 | * with masking the ioapic entry and then polling until | |
2541 | * Remote IRR was clear before reprogramming the | |
2542 | * ioapic I don't trust the Remote IRR bit to be | |
2543 | * completey accurate. | |
2544 | * | |
2545 | * However there appears to be no other way to plug | |
2546 | * this race, so if the Remote IRR bit is not | |
2547 | * accurate and is causing problems then it is a hardware bug | |
2548 | * and you can go talk to the chipset vendor about it. | |
2549 | */ | |
3145e941 YL |
2550 | cfg = desc->chip_data; |
2551 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2552 | move_masked_irq(irq); |
3145e941 | 2553 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2554 | } |
1d025192 | 2555 | |
916a0fe7 | 2556 | /* Tail end of version 0x11 I/O APIC bug workaround */ |
1d025192 YL |
2557 | if (!(v & (1 << (i & 0x1f)))) { |
2558 | atomic_inc(&irq_mis_count); | |
2559 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2560 | __mask_and_edge_IO_APIC_irq(cfg); |
2561 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2562 | spin_unlock(&ioapic_lock); |
2563 | } | |
3eb2cce8 | 2564 | } |
1d025192 | 2565 | |
d0b03bd1 | 2566 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2567 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2568 | { | |
25629d81 SS |
2569 | struct irq_pin_list *entry; |
2570 | ||
2977fb3f CG |
2571 | for_each_irq_pin(entry, cfg->irq_2_pin) |
2572 | io_apic_eoi(entry->apic, entry->pin); | |
25629d81 SS |
2573 | } |
2574 | ||
2575 | static void | |
2576 | eoi_ioapic_irq(struct irq_desc *desc) | |
2577 | { | |
2578 | struct irq_cfg *cfg; | |
2579 | unsigned long flags; | |
2580 | unsigned int irq; | |
2581 | ||
2582 | irq = desc->irq; | |
2583 | cfg = desc->chip_data; | |
2584 | ||
2585 | spin_lock_irqsave(&ioapic_lock, flags); | |
2586 | __eoi_ioapic_irq(irq, cfg); | |
2587 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2588 | } | |
2589 | ||
d0b03bd1 HW |
2590 | static void ir_ack_apic_edge(unsigned int irq) |
2591 | { | |
5d0ae2db | 2592 | ack_APIC_irq(); |
d0b03bd1 HW |
2593 | } |
2594 | ||
2595 | static void ir_ack_apic_level(unsigned int irq) | |
2596 | { | |
5d0ae2db WH |
2597 | struct irq_desc *desc = irq_to_desc(irq); |
2598 | ||
2599 | ack_APIC_irq(); | |
2600 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2601 | } |
2602 | #endif /* CONFIG_INTR_REMAP */ | |
2603 | ||
f5b9ed7a | 2604 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2605 | .name = "IO-APIC", |
2606 | .startup = startup_ioapic_irq, | |
2607 | .mask = mask_IO_APIC_irq, | |
2608 | .unmask = unmask_IO_APIC_irq, | |
2609 | .ack = ack_apic_edge, | |
2610 | .eoi = ack_apic_level, | |
54d5d424 | 2611 | #ifdef CONFIG_SMP |
d6c88a50 | 2612 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2613 | #endif |
ace80ab7 | 2614 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2615 | }; |
2616 | ||
54168ed7 | 2617 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2618 | .name = "IR-IO-APIC", |
2619 | .startup = startup_ioapic_irq, | |
2620 | .mask = mask_IO_APIC_irq, | |
2621 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2622 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2623 | .ack = ir_ack_apic_edge, |
2624 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2625 | #ifdef CONFIG_SMP |
d6c88a50 | 2626 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2627 | #endif |
54168ed7 IM |
2628 | #endif |
2629 | .retrigger = ioapic_retrigger_irq, | |
2630 | }; | |
1da177e4 LT |
2631 | |
2632 | static inline void init_IO_APIC_traps(void) | |
2633 | { | |
2634 | int irq; | |
08678b08 | 2635 | struct irq_desc *desc; |
da51a821 | 2636 | struct irq_cfg *cfg; |
1da177e4 LT |
2637 | |
2638 | /* | |
2639 | * NOTE! The local APIC isn't very good at handling | |
2640 | * multiple interrupts at the same interrupt level. | |
2641 | * As the interrupt level is determined by taking the | |
2642 | * vector number and shifting that right by 4, we | |
2643 | * want to spread these out a bit so that they don't | |
2644 | * all fall in the same interrupt level. | |
2645 | * | |
2646 | * Also, we've got to be careful not to trash gate | |
2647 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2648 | */ | |
0b8f1efa | 2649 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2650 | cfg = desc->chip_data; |
2651 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2652 | /* |
2653 | * Hmm.. We don't have an entry for this, | |
2654 | * so default to an old-fashioned 8259 | |
2655 | * interrupt if we can.. | |
2656 | */ | |
99d093d1 | 2657 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2658 | make_8259A_irq(irq); |
0b8f1efa | 2659 | else |
1da177e4 | 2660 | /* Strange. Oh, well.. */ |
08678b08 | 2661 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2662 | } |
2663 | } | |
2664 | } | |
2665 | ||
f5b9ed7a IM |
2666 | /* |
2667 | * The local APIC irq-chip implementation: | |
2668 | */ | |
1da177e4 | 2669 | |
36062448 | 2670 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2671 | { |
2672 | unsigned long v; | |
2673 | ||
2674 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2675 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2676 | } |
2677 | ||
36062448 | 2678 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2679 | { |
f5b9ed7a | 2680 | unsigned long v; |
1da177e4 | 2681 | |
f5b9ed7a | 2682 | v = apic_read(APIC_LVT0); |
593f4a78 | 2683 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2684 | } |
1da177e4 | 2685 | |
3145e941 | 2686 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2687 | { |
2688 | ack_APIC_irq(); | |
2689 | } | |
2690 | ||
f5b9ed7a | 2691 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2692 | .name = "local-APIC", |
f5b9ed7a IM |
2693 | .mask = mask_lapic_irq, |
2694 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2695 | .ack = ack_lapic_irq, |
1da177e4 LT |
2696 | }; |
2697 | ||
3145e941 | 2698 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2699 | { |
08678b08 | 2700 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2701 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2702 | "edge"); | |
c88ac1df MR |
2703 | } |
2704 | ||
e9427101 | 2705 | static void __init setup_nmi(void) |
1da177e4 LT |
2706 | { |
2707 | /* | |
36062448 | 2708 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2709 | * We put the 8259A master into AEOI mode and |
2710 | * unmask on all local APICs LVT0 as NMI. | |
2711 | * | |
2712 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2713 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2714 | * the NMI handler or the timer interrupt. | |
36062448 | 2715 | */ |
1da177e4 LT |
2716 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2717 | ||
e9427101 | 2718 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2719 | |
2720 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2721 | } | |
2722 | ||
2723 | /* | |
2724 | * This looks a bit hackish but it's about the only one way of sending | |
2725 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2726 | * not support the ExtINT mode, unfortunately. We need to send these | |
2727 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2728 | * 8259A interrupt line asserted until INTA. --macro | |
2729 | */ | |
28acf285 | 2730 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2731 | { |
fcfd636a | 2732 | int apic, pin, i; |
1da177e4 LT |
2733 | struct IO_APIC_route_entry entry0, entry1; |
2734 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2735 | |
fcfd636a | 2736 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2737 | if (pin == -1) { |
2738 | WARN_ON_ONCE(1); | |
2739 | return; | |
2740 | } | |
fcfd636a | 2741 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2742 | if (apic == -1) { |
2743 | WARN_ON_ONCE(1); | |
1da177e4 | 2744 | return; |
956fb531 | 2745 | } |
1da177e4 | 2746 | |
cf4c6a2f | 2747 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2748 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2749 | |
2750 | memset(&entry1, 0, sizeof(entry1)); | |
2751 | ||
2752 | entry1.dest_mode = 0; /* physical delivery */ | |
2753 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2754 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2755 | entry1.delivery_mode = dest_ExtINT; |
2756 | entry1.polarity = entry0.polarity; | |
2757 | entry1.trigger = 0; | |
2758 | entry1.vector = 0; | |
2759 | ||
cf4c6a2f | 2760 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2761 | |
2762 | save_control = CMOS_READ(RTC_CONTROL); | |
2763 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2764 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2765 | RTC_FREQ_SELECT); | |
2766 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2767 | ||
2768 | i = 100; | |
2769 | while (i-- > 0) { | |
2770 | mdelay(10); | |
2771 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2772 | i -= 10; | |
2773 | } | |
2774 | ||
2775 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2776 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2777 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2778 | |
cf4c6a2f | 2779 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2780 | } |
2781 | ||
efa2559f | 2782 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2783 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2784 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2785 | { |
2786 | disable_timer_pin_1 = 1; | |
2787 | return 0; | |
2788 | } | |
54168ed7 | 2789 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2790 | |
2791 | int timer_through_8259 __initdata; | |
2792 | ||
1da177e4 LT |
2793 | /* |
2794 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2795 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2796 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2797 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2798 | * |
2799 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2800 | */ |
8542b200 | 2801 | static inline void __init check_timer(void) |
1da177e4 | 2802 | { |
3145e941 YL |
2803 | struct irq_desc *desc = irq_to_desc(0); |
2804 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2805 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2806 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2807 | unsigned long flags; |
047c8fdb | 2808 | int no_pin1 = 0; |
4aae0702 IM |
2809 | |
2810 | local_irq_save(flags); | |
d4d25dec | 2811 | |
1da177e4 LT |
2812 | /* |
2813 | * get/set the timer IRQ vector: | |
2814 | */ | |
2815 | disable_8259A_irq(0); | |
fe402e1f | 2816 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2817 | |
2818 | /* | |
d11d5794 MR |
2819 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2820 | * wire has to be disabled in the local APIC. Also | |
2821 | * timer interrupts need to be acknowledged manually in | |
2822 | * the 8259A for the i82489DX when using the NMI | |
2823 | * watchdog as that APIC treats NMIs as level-triggered. | |
2824 | * The AEOI mode will finish them in the 8259A | |
2825 | * automatically. | |
1da177e4 | 2826 | */ |
593f4a78 | 2827 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2828 | init_8259A(1); |
54168ed7 | 2829 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2830 | { |
2831 | unsigned int ver; | |
2832 | ||
2833 | ver = apic_read(APIC_LVR); | |
2834 | ver = GET_APIC_VERSION(ver); | |
2835 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2836 | } | |
54168ed7 | 2837 | #endif |
1da177e4 | 2838 | |
fcfd636a EB |
2839 | pin1 = find_isa_irq_pin(0, mp_INT); |
2840 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2841 | pin2 = ioapic_i8259.pin; | |
2842 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2843 | |
49a66a0b MR |
2844 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2845 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2846 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2847 | |
691874fa MR |
2848 | /* |
2849 | * Some BIOS writers are clueless and report the ExtINTA | |
2850 | * I/O APIC input from the cascaded 8259A as the timer | |
2851 | * interrupt input. So just in case, if only one pin | |
2852 | * was found above, try it both directly and through the | |
2853 | * 8259A. | |
2854 | */ | |
2855 | if (pin1 == -1) { | |
54168ed7 IM |
2856 | if (intr_remapping_enabled) |
2857 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2858 | pin1 = pin2; |
2859 | apic1 = apic2; | |
2860 | no_pin1 = 1; | |
2861 | } else if (pin2 == -1) { | |
2862 | pin2 = pin1; | |
2863 | apic2 = apic1; | |
2864 | } | |
2865 | ||
1da177e4 LT |
2866 | if (pin1 != -1) { |
2867 | /* | |
2868 | * Ok, does IRQ0 through the IOAPIC work? | |
2869 | */ | |
691874fa | 2870 | if (no_pin1) { |
85ac16d0 | 2871 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2872 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2873 | } else { |
2874 | /* for edge trigger, setup_IO_APIC_irq already | |
2875 | * leave it unmasked. | |
2876 | * so only need to unmask if it is level-trigger | |
2877 | * do we really have level trigger timer? | |
2878 | */ | |
2879 | int idx; | |
2880 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2881 | if (idx != -1 && irq_trigger(idx)) | |
2882 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2883 | } |
1da177e4 LT |
2884 | if (timer_irq_works()) { |
2885 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2886 | setup_nmi(); |
2887 | enable_8259A_irq(0); | |
1da177e4 | 2888 | } |
66759a01 CE |
2889 | if (disable_timer_pin_1 > 0) |
2890 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2891 | goto out; |
1da177e4 | 2892 | } |
54168ed7 IM |
2893 | if (intr_remapping_enabled) |
2894 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2895 | local_irq_disable(); |
fcfd636a | 2896 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2897 | if (!no_pin1) |
49a66a0b MR |
2898 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2899 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2900 | |
49a66a0b MR |
2901 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2902 | "(IRQ0) through the 8259A ...\n"); | |
2903 | apic_printk(APIC_QUIET, KERN_INFO | |
2904 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2905 | /* |
2906 | * legacy devices should be connected to IO APIC #0 | |
2907 | */ | |
85ac16d0 | 2908 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2909 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2910 | enable_8259A_irq(0); |
1da177e4 | 2911 | if (timer_irq_works()) { |
49a66a0b | 2912 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2913 | timer_through_8259 = 1; |
1da177e4 | 2914 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2915 | disable_8259A_irq(0); |
1da177e4 | 2916 | setup_nmi(); |
60134ebe | 2917 | enable_8259A_irq(0); |
1da177e4 | 2918 | } |
4aae0702 | 2919 | goto out; |
1da177e4 LT |
2920 | } |
2921 | /* | |
2922 | * Cleanup, just in case ... | |
2923 | */ | |
f72dccac | 2924 | local_irq_disable(); |
ecd29476 | 2925 | disable_8259A_irq(0); |
fcfd636a | 2926 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2927 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2928 | } |
1da177e4 LT |
2929 | |
2930 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2931 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2932 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2933 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2934 | } |
54168ed7 | 2935 | #ifdef CONFIG_X86_32 |
d11d5794 | 2936 | timer_ack = 0; |
54168ed7 | 2937 | #endif |
1da177e4 | 2938 | |
49a66a0b MR |
2939 | apic_printk(APIC_QUIET, KERN_INFO |
2940 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2941 | |
3145e941 | 2942 | lapic_register_intr(0, desc); |
497c9a19 | 2943 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2944 | enable_8259A_irq(0); |
2945 | ||
2946 | if (timer_irq_works()) { | |
49a66a0b | 2947 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2948 | goto out; |
1da177e4 | 2949 | } |
f72dccac | 2950 | local_irq_disable(); |
e67465f1 | 2951 | disable_8259A_irq(0); |
497c9a19 | 2952 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2953 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2954 | |
49a66a0b MR |
2955 | apic_printk(APIC_QUIET, KERN_INFO |
2956 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2957 | |
1da177e4 LT |
2958 | init_8259A(0); |
2959 | make_8259A_irq(0); | |
593f4a78 | 2960 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2961 | |
2962 | unlock_ExtINT_logic(); | |
2963 | ||
2964 | if (timer_irq_works()) { | |
49a66a0b | 2965 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2966 | goto out; |
1da177e4 | 2967 | } |
f72dccac | 2968 | local_irq_disable(); |
49a66a0b | 2969 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2970 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2971 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2972 | out: |
2973 | local_irq_restore(flags); | |
1da177e4 LT |
2974 | } |
2975 | ||
2976 | /* | |
af174783 MR |
2977 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2978 | * to devices. However there may be an I/O APIC pin available for | |
2979 | * this interrupt regardless. The pin may be left unconnected, but | |
2980 | * typically it will be reused as an ExtINT cascade interrupt for | |
2981 | * the master 8259A. In the MPS case such a pin will normally be | |
2982 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2983 | * there is no provision for ExtINT interrupts, and in the absence | |
2984 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2985 | * interrupt, that is edge-triggered and unmasked by default. We | |
2986 | * used to do this, but it caused problems on some systems because | |
2987 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2988 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2989 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2990 | * the I/O APIC in all cases now. No actual device should request | |
2991 | * it anyway. --macro | |
1da177e4 LT |
2992 | */ |
2993 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2994 | ||
2995 | void __init setup_IO_APIC(void) | |
2996 | { | |
54168ed7 | 2997 | |
54168ed7 IM |
2998 | /* |
2999 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3000 | */ | |
1da177e4 | 3001 | |
af174783 | 3002 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3003 | |
54168ed7 | 3004 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3005 | /* |
54168ed7 IM |
3006 | * Set up IO-APIC IRQ routing. |
3007 | */ | |
3008 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3009 | if (!acpi_ioapic) |
3010 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3011 | #endif |
1da177e4 LT |
3012 | sync_Arb_IDs(); |
3013 | setup_IO_APIC_irqs(); | |
3014 | init_IO_APIC_traps(); | |
1e4c85f9 | 3015 | check_timer(); |
1da177e4 LT |
3016 | } |
3017 | ||
3018 | /* | |
54168ed7 IM |
3019 | * Called after all the initialization is done. If we didnt find any |
3020 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3021 | */ |
36062448 | 3022 | |
1da177e4 LT |
3023 | static int __init io_apic_bug_finalize(void) |
3024 | { | |
d6c88a50 TG |
3025 | if (sis_apic_bug == -1) |
3026 | sis_apic_bug = 0; | |
3027 | return 0; | |
1da177e4 LT |
3028 | } |
3029 | ||
3030 | late_initcall(io_apic_bug_finalize); | |
3031 | ||
3032 | struct sysfs_ioapic_data { | |
3033 | struct sys_device dev; | |
3034 | struct IO_APIC_route_entry entry[0]; | |
3035 | }; | |
54168ed7 | 3036 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3037 | |
438510f6 | 3038 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3039 | { |
3040 | struct IO_APIC_route_entry *entry; | |
3041 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3042 | int i; |
36062448 | 3043 | |
1da177e4 LT |
3044 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3045 | entry = data->entry; | |
54168ed7 IM |
3046 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3047 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3048 | |
3049 | return 0; | |
3050 | } | |
3051 | ||
3052 | static int ioapic_resume(struct sys_device *dev) | |
3053 | { | |
3054 | struct IO_APIC_route_entry *entry; | |
3055 | struct sysfs_ioapic_data *data; | |
3056 | unsigned long flags; | |
3057 | union IO_APIC_reg_00 reg_00; | |
3058 | int i; | |
36062448 | 3059 | |
1da177e4 LT |
3060 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3061 | entry = data->entry; | |
3062 | ||
3063 | spin_lock_irqsave(&ioapic_lock, flags); | |
3064 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3065 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3066 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3067 | io_apic_write(dev->id, 0, reg_00.raw); |
3068 | } | |
1da177e4 | 3069 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3070 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3071 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3072 | |
3073 | return 0; | |
3074 | } | |
3075 | ||
3076 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3077 | .name = "ioapic", |
1da177e4 LT |
3078 | .suspend = ioapic_suspend, |
3079 | .resume = ioapic_resume, | |
3080 | }; | |
3081 | ||
3082 | static int __init ioapic_init_sysfs(void) | |
3083 | { | |
54168ed7 IM |
3084 | struct sys_device * dev; |
3085 | int i, size, error; | |
1da177e4 LT |
3086 | |
3087 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3088 | if (error) | |
3089 | return error; | |
3090 | ||
54168ed7 | 3091 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3092 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3093 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3094 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3095 | if (!mp_ioapic_data[i]) { |
3096 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3097 | continue; | |
3098 | } | |
1da177e4 | 3099 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3100 | dev->id = i; |
1da177e4 LT |
3101 | dev->cls = &ioapic_sysdev_class; |
3102 | error = sysdev_register(dev); | |
3103 | if (error) { | |
3104 | kfree(mp_ioapic_data[i]); | |
3105 | mp_ioapic_data[i] = NULL; | |
3106 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3107 | continue; | |
3108 | } | |
3109 | } | |
3110 | ||
3111 | return 0; | |
3112 | } | |
3113 | ||
3114 | device_initcall(ioapic_init_sysfs); | |
3115 | ||
abcaa2b8 | 3116 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3117 | /* |
95d77884 | 3118 | * Dynamic irq allocate and deallocation |
3fc471ed | 3119 | */ |
d047f53a | 3120 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3121 | { |
ace80ab7 | 3122 | /* Allocate an unused irq */ |
54168ed7 IM |
3123 | unsigned int irq; |
3124 | unsigned int new; | |
3fc471ed | 3125 | unsigned long flags; |
0b8f1efa | 3126 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3127 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3128 | |
3129 | irq = 0; | |
abcaa2b8 YL |
3130 | if (irq_want < nr_irqs_gsi) |
3131 | irq_want = nr_irqs_gsi; | |
3132 | ||
ace80ab7 | 3133 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3134 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3135 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3136 | if (!desc_new) { |
3137 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3138 | continue; |
0b8f1efa YL |
3139 | } |
3140 | cfg_new = desc_new->chip_data; | |
3141 | ||
3142 | if (cfg_new->vector != 0) | |
ace80ab7 | 3143 | continue; |
d047f53a | 3144 | |
15e957d0 | 3145 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3146 | |
fe402e1f | 3147 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3148 | irq = new; |
3149 | break; | |
3150 | } | |
3151 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3152 | |
199751d7 | 3153 | if (irq > 0) { |
3fc471ed | 3154 | dynamic_irq_init(irq); |
0b8f1efa YL |
3155 | /* restore it, in case dynamic_irq_init clear it */ |
3156 | if (desc_new) | |
3157 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3158 | } |
3159 | return irq; | |
3160 | } | |
3161 | ||
199751d7 YL |
3162 | int create_irq(void) |
3163 | { | |
d047f53a | 3164 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3165 | unsigned int irq_want; |
54168ed7 IM |
3166 | int irq; |
3167 | ||
be5d5350 | 3168 | irq_want = nr_irqs_gsi; |
d047f53a | 3169 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3170 | |
3171 | if (irq == 0) | |
3172 | irq = -1; | |
3173 | ||
3174 | return irq; | |
199751d7 YL |
3175 | } |
3176 | ||
3fc471ed EB |
3177 | void destroy_irq(unsigned int irq) |
3178 | { | |
3179 | unsigned long flags; | |
0b8f1efa YL |
3180 | struct irq_cfg *cfg; |
3181 | struct irq_desc *desc; | |
3fc471ed | 3182 | |
0b8f1efa YL |
3183 | /* store it, in case dynamic_irq_cleanup clear it */ |
3184 | desc = irq_to_desc(irq); | |
3185 | cfg = desc->chip_data; | |
3fc471ed | 3186 | dynamic_irq_cleanup(irq); |
0b8f1efa | 3187 | /* connect back irq_cfg */ |
25f6e89b | 3188 | desc->chip_data = cfg; |
3fc471ed | 3189 | |
54168ed7 | 3190 | free_irte(irq); |
3fc471ed | 3191 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3192 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3193 | spin_unlock_irqrestore(&vector_lock, flags); |
3194 | } | |
3fc471ed | 3195 | |
2d3fcc1c | 3196 | /* |
27b46d76 | 3197 | * MSI message composition |
2d3fcc1c EB |
3198 | */ |
3199 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3200 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3201 | { |
497c9a19 YL |
3202 | struct irq_cfg *cfg; |
3203 | int err; | |
2d3fcc1c EB |
3204 | unsigned dest; |
3205 | ||
f1182638 JB |
3206 | if (disable_apic) |
3207 | return -ENXIO; | |
3208 | ||
3145e941 | 3209 | cfg = irq_cfg(irq); |
fe402e1f | 3210 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3211 | if (err) |
3212 | return err; | |
2d3fcc1c | 3213 | |
debccb3e | 3214 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3215 | |
54168ed7 IM |
3216 | if (irq_remapped(irq)) { |
3217 | struct irte irte; | |
3218 | int ir_index; | |
3219 | u16 sub_handle; | |
3220 | ||
3221 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3222 | BUG_ON(ir_index == -1); | |
3223 | ||
3224 | memset (&irte, 0, sizeof(irte)); | |
3225 | ||
3226 | irte.present = 1; | |
9b5bc8dc | 3227 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3228 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3229 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3230 | irte.vector = cfg->vector; |
3231 | irte.dest_id = IRTE_DEST(dest); | |
3232 | ||
f007e99c WH |
3233 | /* Set source-id of interrupt request */ |
3234 | set_msi_sid(&irte, pdev); | |
3235 | ||
54168ed7 IM |
3236 | modify_irte(irq, &irte); |
3237 | ||
3238 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3239 | msg->data = sub_handle; | |
3240 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3241 | MSI_ADDR_IR_SHV | | |
3242 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3243 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3244 | } else { |
9d783ba0 SS |
3245 | if (x2apic_enabled()) |
3246 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3247 | MSI_ADDR_EXT_DEST_ID(dest); | |
3248 | else | |
3249 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3250 | ||
54168ed7 IM |
3251 | msg->address_lo = |
3252 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3253 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3254 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3255 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3256 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3257 | MSI_ADDR_REDIRECTION_CPU: |
3258 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3259 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3260 | |
54168ed7 IM |
3261 | msg->data = |
3262 | MSI_DATA_TRIGGER_EDGE | | |
3263 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3264 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3265 | MSI_DATA_DELIVERY_FIXED: |
3266 | MSI_DATA_DELIVERY_LOWPRI) | | |
3267 | MSI_DATA_VECTOR(cfg->vector); | |
3268 | } | |
497c9a19 | 3269 | return err; |
2d3fcc1c EB |
3270 | } |
3271 | ||
3b7d1921 | 3272 | #ifdef CONFIG_SMP |
d5dedd45 | 3273 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3274 | { |
3145e941 | 3275 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3276 | struct irq_cfg *cfg; |
3b7d1921 EB |
3277 | struct msi_msg msg; |
3278 | unsigned int dest; | |
3b7d1921 | 3279 | |
22f65d31 MT |
3280 | dest = set_desc_affinity(desc, mask); |
3281 | if (dest == BAD_APICID) | |
d5dedd45 | 3282 | return -1; |
2d3fcc1c | 3283 | |
3145e941 | 3284 | cfg = desc->chip_data; |
2d3fcc1c | 3285 | |
3145e941 | 3286 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3287 | |
3288 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3289 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3290 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3291 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3292 | ||
3145e941 | 3293 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3294 | |
3295 | return 0; | |
2d3fcc1c | 3296 | } |
54168ed7 IM |
3297 | #ifdef CONFIG_INTR_REMAP |
3298 | /* | |
3299 | * Migrate the MSI irq to another cpumask. This migration is | |
3300 | * done in the process context using interrupt-remapping hardware. | |
3301 | */ | |
d5dedd45 | 3302 | static int |
e7986739 | 3303 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3304 | { |
3145e941 | 3305 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3306 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3307 | unsigned int dest; |
54168ed7 | 3308 | struct irte irte; |
54168ed7 IM |
3309 | |
3310 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3311 | return -1; |
54168ed7 | 3312 | |
22f65d31 MT |
3313 | dest = set_desc_affinity(desc, mask); |
3314 | if (dest == BAD_APICID) | |
d5dedd45 | 3315 | return -1; |
54168ed7 | 3316 | |
54168ed7 IM |
3317 | irte.vector = cfg->vector; |
3318 | irte.dest_id = IRTE_DEST(dest); | |
3319 | ||
3320 | /* | |
3321 | * atomically update the IRTE with the new destination and vector. | |
3322 | */ | |
3323 | modify_irte(irq, &irte); | |
3324 | ||
3325 | /* | |
3326 | * After this point, all the interrupts will start arriving | |
3327 | * at the new destination. So, time to cleanup the previous | |
3328 | * vector allocation. | |
3329 | */ | |
22f65d31 MT |
3330 | if (cfg->move_in_progress) |
3331 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3332 | |
3333 | return 0; | |
54168ed7 | 3334 | } |
3145e941 | 3335 | |
54168ed7 | 3336 | #endif |
3b7d1921 | 3337 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3338 | |
3b7d1921 EB |
3339 | /* |
3340 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3341 | * which implement the MSI or MSI-X Capability Structure. | |
3342 | */ | |
3343 | static struct irq_chip msi_chip = { | |
3344 | .name = "PCI-MSI", | |
3345 | .unmask = unmask_msi_irq, | |
3346 | .mask = mask_msi_irq, | |
1d025192 | 3347 | .ack = ack_apic_edge, |
3b7d1921 EB |
3348 | #ifdef CONFIG_SMP |
3349 | .set_affinity = set_msi_irq_affinity, | |
3350 | #endif | |
3351 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3352 | }; |
3353 | ||
54168ed7 IM |
3354 | static struct irq_chip msi_ir_chip = { |
3355 | .name = "IR-PCI-MSI", | |
3356 | .unmask = unmask_msi_irq, | |
3357 | .mask = mask_msi_irq, | |
a1e38ca5 | 3358 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3359 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3360 | #ifdef CONFIG_SMP |
3361 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3362 | #endif |
54168ed7 IM |
3363 | #endif |
3364 | .retrigger = ioapic_retrigger_irq, | |
3365 | }; | |
3366 | ||
3367 | /* | |
3368 | * Map the PCI dev to the corresponding remapping hardware unit | |
3369 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3370 | * in it. | |
3371 | */ | |
3372 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3373 | { | |
3374 | struct intel_iommu *iommu; | |
3375 | int index; | |
3376 | ||
3377 | iommu = map_dev_to_ir(dev); | |
3378 | if (!iommu) { | |
3379 | printk(KERN_ERR | |
3380 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3381 | return -ENOENT; | |
3382 | } | |
3383 | ||
3384 | index = alloc_irte(iommu, irq, nvec); | |
3385 | if (index < 0) { | |
3386 | printk(KERN_ERR | |
3387 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3388 | pci_name(dev)); |
54168ed7 IM |
3389 | return -ENOSPC; |
3390 | } | |
3391 | return index; | |
3392 | } | |
1d025192 | 3393 | |
3145e941 | 3394 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3395 | { |
3396 | int ret; | |
3397 | struct msi_msg msg; | |
3398 | ||
3399 | ret = msi_compose_msg(dev, irq, &msg); | |
3400 | if (ret < 0) | |
3401 | return ret; | |
3402 | ||
3145e941 | 3403 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3404 | write_msi_msg(irq, &msg); |
3405 | ||
54168ed7 IM |
3406 | if (irq_remapped(irq)) { |
3407 | struct irq_desc *desc = irq_to_desc(irq); | |
3408 | /* | |
3409 | * irq migration in process context | |
3410 | */ | |
3411 | desc->status |= IRQ_MOVE_PCNTXT; | |
3412 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3413 | } else | |
54168ed7 | 3414 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3415 | |
c81bba49 YL |
3416 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3417 | ||
1d025192 YL |
3418 | return 0; |
3419 | } | |
3420 | ||
047c8fdb YL |
3421 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3422 | { | |
54168ed7 IM |
3423 | unsigned int irq; |
3424 | int ret, sub_handle; | |
0b8f1efa | 3425 | struct msi_desc *msidesc; |
54168ed7 | 3426 | unsigned int irq_want; |
1cc18521 | 3427 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3428 | int index = 0; |
d047f53a | 3429 | int node; |
54168ed7 | 3430 | |
1c8d7b0a MW |
3431 | /* x86 doesn't support multiple MSI yet */ |
3432 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3433 | return 1; | |
3434 | ||
d047f53a | 3435 | node = dev_to_node(&dev->dev); |
be5d5350 | 3436 | irq_want = nr_irqs_gsi; |
54168ed7 | 3437 | sub_handle = 0; |
0b8f1efa | 3438 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3439 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3440 | if (irq == 0) |
3441 | return -1; | |
f1ee5548 | 3442 | irq_want = irq + 1; |
54168ed7 IM |
3443 | if (!intr_remapping_enabled) |
3444 | goto no_ir; | |
3445 | ||
3446 | if (!sub_handle) { | |
3447 | /* | |
3448 | * allocate the consecutive block of IRTE's | |
3449 | * for 'nvec' | |
3450 | */ | |
3451 | index = msi_alloc_irte(dev, irq, nvec); | |
3452 | if (index < 0) { | |
3453 | ret = index; | |
3454 | goto error; | |
3455 | } | |
3456 | } else { | |
3457 | iommu = map_dev_to_ir(dev); | |
3458 | if (!iommu) { | |
3459 | ret = -ENOENT; | |
3460 | goto error; | |
3461 | } | |
3462 | /* | |
3463 | * setup the mapping between the irq and the IRTE | |
3464 | * base index, the sub_handle pointing to the | |
3465 | * appropriate interrupt remap table entry. | |
3466 | */ | |
3467 | set_irte_irq(irq, iommu, index, sub_handle); | |
3468 | } | |
3469 | no_ir: | |
0b8f1efa | 3470 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3471 | if (ret < 0) |
3472 | goto error; | |
3473 | sub_handle++; | |
3474 | } | |
3475 | return 0; | |
047c8fdb YL |
3476 | |
3477 | error: | |
54168ed7 IM |
3478 | destroy_irq(irq); |
3479 | return ret; | |
047c8fdb YL |
3480 | } |
3481 | ||
3b7d1921 EB |
3482 | void arch_teardown_msi_irq(unsigned int irq) |
3483 | { | |
f7feaca7 | 3484 | destroy_irq(irq); |
3b7d1921 EB |
3485 | } |
3486 | ||
9d783ba0 | 3487 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3488 | #ifdef CONFIG_SMP |
d5dedd45 | 3489 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3490 | { |
3145e941 | 3491 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3492 | struct irq_cfg *cfg; |
3493 | struct msi_msg msg; | |
3494 | unsigned int dest; | |
54168ed7 | 3495 | |
22f65d31 MT |
3496 | dest = set_desc_affinity(desc, mask); |
3497 | if (dest == BAD_APICID) | |
d5dedd45 | 3498 | return -1; |
54168ed7 | 3499 | |
3145e941 | 3500 | cfg = desc->chip_data; |
54168ed7 IM |
3501 | |
3502 | dmar_msi_read(irq, &msg); | |
3503 | ||
3504 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3505 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3506 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3507 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3508 | ||
3509 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3510 | |
3511 | return 0; | |
54168ed7 | 3512 | } |
3145e941 | 3513 | |
54168ed7 IM |
3514 | #endif /* CONFIG_SMP */ |
3515 | ||
8f7007aa | 3516 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3517 | .name = "DMAR_MSI", |
3518 | .unmask = dmar_msi_unmask, | |
3519 | .mask = dmar_msi_mask, | |
3520 | .ack = ack_apic_edge, | |
3521 | #ifdef CONFIG_SMP | |
3522 | .set_affinity = dmar_msi_set_affinity, | |
3523 | #endif | |
3524 | .retrigger = ioapic_retrigger_irq, | |
3525 | }; | |
3526 | ||
3527 | int arch_setup_dmar_msi(unsigned int irq) | |
3528 | { | |
3529 | int ret; | |
3530 | struct msi_msg msg; | |
2d3fcc1c | 3531 | |
54168ed7 IM |
3532 | ret = msi_compose_msg(NULL, irq, &msg); |
3533 | if (ret < 0) | |
3534 | return ret; | |
3535 | dmar_msi_write(irq, &msg); | |
3536 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3537 | "edge"); | |
3538 | return 0; | |
3539 | } | |
3540 | #endif | |
3541 | ||
58ac1e76 | 3542 | #ifdef CONFIG_HPET_TIMER |
3543 | ||
3544 | #ifdef CONFIG_SMP | |
d5dedd45 | 3545 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3546 | { |
3145e941 | 3547 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3548 | struct irq_cfg *cfg; |
58ac1e76 | 3549 | struct msi_msg msg; |
3550 | unsigned int dest; | |
58ac1e76 | 3551 | |
22f65d31 MT |
3552 | dest = set_desc_affinity(desc, mask); |
3553 | if (dest == BAD_APICID) | |
d5dedd45 | 3554 | return -1; |
58ac1e76 | 3555 | |
3145e941 | 3556 | cfg = desc->chip_data; |
58ac1e76 | 3557 | |
3558 | hpet_msi_read(irq, &msg); | |
3559 | ||
3560 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3561 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3562 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3563 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3564 | ||
3565 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3566 | |
3567 | return 0; | |
58ac1e76 | 3568 | } |
3145e941 | 3569 | |
58ac1e76 | 3570 | #endif /* CONFIG_SMP */ |
3571 | ||
1cc18521 | 3572 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3573 | .name = "HPET_MSI", |
3574 | .unmask = hpet_msi_unmask, | |
3575 | .mask = hpet_msi_mask, | |
3576 | .ack = ack_apic_edge, | |
3577 | #ifdef CONFIG_SMP | |
3578 | .set_affinity = hpet_msi_set_affinity, | |
3579 | #endif | |
3580 | .retrigger = ioapic_retrigger_irq, | |
3581 | }; | |
3582 | ||
3583 | int arch_setup_hpet_msi(unsigned int irq) | |
3584 | { | |
3585 | int ret; | |
3586 | struct msi_msg msg; | |
6ec3cfec | 3587 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3588 | |
3589 | ret = msi_compose_msg(NULL, irq, &msg); | |
3590 | if (ret < 0) | |
3591 | return ret; | |
3592 | ||
3593 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3594 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3595 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3596 | "edge"); | |
c81bba49 | 3597 | |
58ac1e76 | 3598 | return 0; |
3599 | } | |
3600 | #endif | |
3601 | ||
54168ed7 | 3602 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3603 | /* |
3604 | * Hypertransport interrupt support | |
3605 | */ | |
3606 | #ifdef CONFIG_HT_IRQ | |
3607 | ||
3608 | #ifdef CONFIG_SMP | |
3609 | ||
497c9a19 | 3610 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3611 | { |
ec68307c EB |
3612 | struct ht_irq_msg msg; |
3613 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3614 | |
497c9a19 | 3615 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3616 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3617 | |
497c9a19 | 3618 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3619 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3620 | |
ec68307c | 3621 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3622 | } |
3623 | ||
d5dedd45 | 3624 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3625 | { |
3145e941 | 3626 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3627 | struct irq_cfg *cfg; |
8b955b0d | 3628 | unsigned int dest; |
8b955b0d | 3629 | |
22f65d31 MT |
3630 | dest = set_desc_affinity(desc, mask); |
3631 | if (dest == BAD_APICID) | |
d5dedd45 | 3632 | return -1; |
8b955b0d | 3633 | |
3145e941 | 3634 | cfg = desc->chip_data; |
8b955b0d | 3635 | |
497c9a19 | 3636 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3637 | |
3638 | return 0; | |
8b955b0d | 3639 | } |
3145e941 | 3640 | |
8b955b0d EB |
3641 | #endif |
3642 | ||
c37e108d | 3643 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3644 | .name = "PCI-HT", |
3645 | .mask = mask_ht_irq, | |
3646 | .unmask = unmask_ht_irq, | |
1d025192 | 3647 | .ack = ack_apic_edge, |
8b955b0d EB |
3648 | #ifdef CONFIG_SMP |
3649 | .set_affinity = set_ht_irq_affinity, | |
3650 | #endif | |
3651 | .retrigger = ioapic_retrigger_irq, | |
3652 | }; | |
3653 | ||
3654 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3655 | { | |
497c9a19 YL |
3656 | struct irq_cfg *cfg; |
3657 | int err; | |
8b955b0d | 3658 | |
f1182638 JB |
3659 | if (disable_apic) |
3660 | return -ENXIO; | |
3661 | ||
3145e941 | 3662 | cfg = irq_cfg(irq); |
fe402e1f | 3663 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3664 | if (!err) { |
ec68307c | 3665 | struct ht_irq_msg msg; |
8b955b0d | 3666 | unsigned dest; |
8b955b0d | 3667 | |
debccb3e IM |
3668 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3669 | apic->target_cpus()); | |
8b955b0d | 3670 | |
ec68307c | 3671 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3672 | |
ec68307c EB |
3673 | msg.address_lo = |
3674 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3675 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3676 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3677 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3678 | HT_IRQ_LOW_DM_PHYSICAL : |
3679 | HT_IRQ_LOW_DM_LOGICAL) | | |
3680 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3681 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3682 | HT_IRQ_LOW_MT_FIXED : |
3683 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3684 | HT_IRQ_LOW_IRQ_MASKED; | |
3685 | ||
ec68307c | 3686 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3687 | |
a460e745 IM |
3688 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3689 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3690 | |
3691 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3692 | } |
497c9a19 | 3693 | return err; |
8b955b0d EB |
3694 | } |
3695 | #endif /* CONFIG_HT_IRQ */ | |
3696 | ||
03b48632 | 3697 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3698 | /* |
3699 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3700 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3701 | */ | |
3702 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3703 | unsigned long mmr_offset) | |
3704 | { | |
22f65d31 | 3705 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3706 | struct irq_cfg *cfg; |
3707 | int mmr_pnode; | |
3708 | unsigned long mmr_value; | |
3709 | struct uv_IO_APIC_route_entry *entry; | |
3710 | unsigned long flags; | |
3711 | int err; | |
3712 | ||
1cbac972 CG |
3713 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3714 | ||
3145e941 YL |
3715 | cfg = irq_cfg(irq); |
3716 | ||
e7986739 | 3717 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3718 | if (err != 0) |
3719 | return err; | |
3720 | ||
3721 | spin_lock_irqsave(&vector_lock, flags); | |
3722 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3723 | irq_name); | |
3724 | spin_unlock_irqrestore(&vector_lock, flags); | |
3725 | ||
4173a0e7 DN |
3726 | mmr_value = 0; |
3727 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3728 | entry->vector = cfg->vector; |
3729 | entry->delivery_mode = apic->irq_delivery_mode; | |
3730 | entry->dest_mode = apic->irq_dest_mode; | |
3731 | entry->polarity = 0; | |
3732 | entry->trigger = 0; | |
3733 | entry->mask = 0; | |
3734 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3735 | |
3736 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3737 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3738 | ||
3739 | return irq; | |
3740 | } | |
3741 | ||
3742 | /* | |
3743 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3744 | * longer allowed to be sent. | |
3745 | */ | |
3746 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3747 | { | |
3748 | unsigned long mmr_value; | |
3749 | struct uv_IO_APIC_route_entry *entry; | |
3750 | int mmr_pnode; | |
3751 | ||
1cbac972 CG |
3752 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3753 | ||
4173a0e7 DN |
3754 | mmr_value = 0; |
3755 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3756 | entry->mask = 1; |
3757 | ||
3758 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3759 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3760 | } | |
3761 | #endif /* CONFIG_X86_64 */ | |
3762 | ||
9d6a4d08 YL |
3763 | int __init io_apic_get_redir_entries (int ioapic) |
3764 | { | |
3765 | union IO_APIC_reg_01 reg_01; | |
3766 | unsigned long flags; | |
3767 | ||
3768 | spin_lock_irqsave(&ioapic_lock, flags); | |
3769 | reg_01.raw = io_apic_read(ioapic, 1); | |
3770 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3771 | ||
3772 | return reg_01.bits.entries; | |
3773 | } | |
3774 | ||
be5d5350 | 3775 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3776 | { |
be5d5350 YL |
3777 | int nr = 0; |
3778 | ||
cc6c5006 YL |
3779 | nr = acpi_probe_gsi(); |
3780 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3781 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3782 | } else { |
3783 | /* for acpi=off or acpi is not compiled in */ | |
3784 | int idx; | |
3785 | ||
3786 | nr = 0; | |
3787 | for (idx = 0; idx < nr_ioapics; idx++) | |
3788 | nr += io_apic_get_redir_entries(idx) + 1; | |
3789 | ||
3790 | if (nr > nr_irqs_gsi) | |
3791 | nr_irqs_gsi = nr; | |
3792 | } | |
3793 | ||
3794 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3795 | } |
3796 | ||
4a046d17 YL |
3797 | #ifdef CONFIG_SPARSE_IRQ |
3798 | int __init arch_probe_nr_irqs(void) | |
3799 | { | |
3800 | int nr; | |
3801 | ||
f1ee5548 YL |
3802 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3803 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3804 | |
f1ee5548 YL |
3805 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3806 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3807 | /* | |
3808 | * for MSI and HT dyn irq | |
3809 | */ | |
3810 | nr += nr_irqs_gsi * 16; | |
3811 | #endif | |
3812 | if (nr < nr_irqs) | |
4a046d17 YL |
3813 | nr_irqs = nr; |
3814 | ||
3815 | return 0; | |
3816 | } | |
3817 | #endif | |
3818 | ||
e5198075 YL |
3819 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3820 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3821 | { |
3822 | struct irq_desc *desc; | |
3823 | struct irq_cfg *cfg; | |
3824 | int node; | |
e5198075 YL |
3825 | int ioapic, pin; |
3826 | int trigger, polarity; | |
5ef21837 | 3827 | |
e5198075 | 3828 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3829 | if (!IO_APIC_IRQ(irq)) { |
3830 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3831 | ioapic); | |
3832 | return -EINVAL; | |
3833 | } | |
3834 | ||
3835 | if (dev) | |
3836 | node = dev_to_node(dev); | |
3837 | else | |
3838 | node = cpu_to_node(boot_cpu_id); | |
3839 | ||
3840 | desc = irq_to_desc_alloc_node(irq, node); | |
3841 | if (!desc) { | |
3842 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3843 | return 0; | |
3844 | } | |
3845 | ||
e5198075 YL |
3846 | pin = irq_attr->ioapic_pin; |
3847 | trigger = irq_attr->trigger; | |
3848 | polarity = irq_attr->polarity; | |
3849 | ||
5ef21837 YL |
3850 | /* |
3851 | * IRQs < 16 are already in the irq_2_pin[] map | |
3852 | */ | |
3853 | if (irq >= NR_IRQS_LEGACY) { | |
3854 | cfg = desc->chip_data; | |
f3d1915a CG |
3855 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3856 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3857 | pin, irq); | |
3858 | return 0; | |
3859 | } | |
5ef21837 YL |
3860 | } |
3861 | ||
e5198075 | 3862 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3863 | |
3864 | return 0; | |
3865 | } | |
3866 | ||
e5198075 YL |
3867 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3868 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3869 | { |
e5198075 | 3870 | int ioapic, pin; |
5ef21837 YL |
3871 | /* |
3872 | * Avoid pin reprogramming. PRTs typically include entries | |
3873 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3874 | * we only program the IOAPIC on the first. | |
3875 | */ | |
e5198075 YL |
3876 | ioapic = irq_attr->ioapic; |
3877 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3878 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3879 | pr_debug("Pin %d-%d already programmed\n", | |
3880 | mp_ioapics[ioapic].apicid, pin); | |
3881 | return 0; | |
3882 | } | |
3883 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3884 | ||
e5198075 | 3885 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3886 | } |
3887 | ||
1da177e4 | 3888 | /* -------------------------------------------------------------------------- |
54168ed7 | 3889 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3890 | -------------------------------------------------------------------------- */ |
3891 | ||
888ba6c6 | 3892 | #ifdef CONFIG_ACPI |
1da177e4 | 3893 | |
54168ed7 | 3894 | #ifdef CONFIG_X86_32 |
36062448 | 3895 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3896 | { |
3897 | union IO_APIC_reg_00 reg_00; | |
3898 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3899 | physid_mask_t tmp; | |
3900 | unsigned long flags; | |
3901 | int i = 0; | |
3902 | ||
3903 | /* | |
36062448 PC |
3904 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3905 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3906 | * supports up to 16 on one shared APIC bus. |
36062448 | 3907 | * |
1da177e4 LT |
3908 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3909 | * advantage of new APIC bus architecture. | |
3910 | */ | |
3911 | ||
3912 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3913 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3914 | |
3915 | spin_lock_irqsave(&ioapic_lock, flags); | |
3916 | reg_00.raw = io_apic_read(ioapic, 0); | |
3917 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3918 | ||
3919 | if (apic_id >= get_physical_broadcast()) { | |
3920 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3921 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3922 | apic_id = reg_00.bits.ID; | |
3923 | } | |
3924 | ||
3925 | /* | |
36062448 | 3926 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3927 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3928 | */ | |
d1d7cae8 | 3929 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3930 | |
3931 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3932 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3933 | break; |
3934 | } | |
3935 | ||
3936 | if (i == get_physical_broadcast()) | |
3937 | panic("Max apic_id exceeded!\n"); | |
3938 | ||
3939 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3940 | "trying %d\n", ioapic, apic_id, i); | |
3941 | ||
3942 | apic_id = i; | |
36062448 | 3943 | } |
1da177e4 | 3944 | |
8058714a | 3945 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3946 | physids_or(apic_id_map, apic_id_map, tmp); |
3947 | ||
3948 | if (reg_00.bits.ID != apic_id) { | |
3949 | reg_00.bits.ID = apic_id; | |
3950 | ||
3951 | spin_lock_irqsave(&ioapic_lock, flags); | |
3952 | io_apic_write(ioapic, 0, reg_00.raw); | |
3953 | reg_00.raw = io_apic_read(ioapic, 0); | |
3954 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3955 | ||
3956 | /* Sanity check */ | |
6070f9ec AD |
3957 | if (reg_00.bits.ID != apic_id) { |
3958 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3959 | return -1; | |
3960 | } | |
1da177e4 LT |
3961 | } |
3962 | ||
3963 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3964 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3965 | ||
3966 | return apic_id; | |
3967 | } | |
58f892e0 | 3968 | #endif |
1da177e4 | 3969 | |
36062448 | 3970 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3971 | { |
3972 | union IO_APIC_reg_01 reg_01; | |
3973 | unsigned long flags; | |
3974 | ||
3975 | spin_lock_irqsave(&ioapic_lock, flags); | |
3976 | reg_01.raw = io_apic_read(ioapic, 1); | |
3977 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3978 | ||
3979 | return reg_01.bits.version; | |
3980 | } | |
3981 | ||
61fd47e0 SL |
3982 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3983 | { | |
3984 | int i; | |
3985 | ||
3986 | if (skip_ioapic_setup) | |
3987 | return -1; | |
3988 | ||
3989 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
3990 | if (mp_irqs[i].irqtype == mp_INT && |
3991 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
3992 | break; |
3993 | if (i >= mp_irq_entries) | |
3994 | return -1; | |
3995 | ||
3996 | *trigger = irq_trigger(i); | |
3997 | *polarity = irq_polarity(i); | |
3998 | return 0; | |
3999 | } | |
4000 | ||
888ba6c6 | 4001 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4002 | |
497c9a19 YL |
4003 | /* |
4004 | * This function currently is only a helper for the i386 smp boot process where | |
4005 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4006 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4007 | */ |
4008 | #ifdef CONFIG_SMP | |
4009 | void __init setup_ioapic_dest(void) | |
4010 | { | |
b9c61b70 | 4011 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4012 | struct irq_desc *desc; |
22f65d31 | 4013 | const struct cpumask *mask; |
497c9a19 YL |
4014 | |
4015 | if (skip_ioapic_setup == 1) | |
4016 | return; | |
4017 | ||
b9c61b70 YL |
4018 | #ifdef CONFIG_ACPI |
4019 | if (!acpi_disabled && acpi_ioapic) { | |
4020 | ioapic = mp_find_ioapic(0); | |
4021 | if (ioapic < 0) | |
4022 | ioapic = 0; | |
4023 | } | |
4024 | #endif | |
6c2e9403 | 4025 | |
b9c61b70 YL |
4026 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4027 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4028 | if (irq_entry == -1) | |
4029 | continue; | |
4030 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4031 | |
b9c61b70 | 4032 | desc = irq_to_desc(irq); |
6c2e9403 | 4033 | |
b9c61b70 YL |
4034 | /* |
4035 | * Honour affinities which have been set in early boot | |
4036 | */ | |
4037 | if (desc->status & | |
4038 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4039 | mask = desc->affinity; | |
4040 | else | |
4041 | mask = apic->target_cpus(); | |
497c9a19 | 4042 | |
b9c61b70 YL |
4043 | if (intr_remapping_enabled) |
4044 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4045 | else | |
4046 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4047 | } |
b9c61b70 | 4048 | |
497c9a19 YL |
4049 | } |
4050 | #endif | |
4051 | ||
54168ed7 IM |
4052 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4053 | ||
4054 | static struct resource *ioapic_resources; | |
4055 | ||
4056 | static struct resource * __init ioapic_setup_resources(void) | |
4057 | { | |
4058 | unsigned long n; | |
4059 | struct resource *res; | |
4060 | char *mem; | |
4061 | int i; | |
4062 | ||
4063 | if (nr_ioapics <= 0) | |
4064 | return NULL; | |
4065 | ||
4066 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4067 | n *= nr_ioapics; | |
4068 | ||
4069 | mem = alloc_bootmem(n); | |
4070 | res = (void *)mem; | |
4071 | ||
4072 | if (mem != NULL) { | |
4073 | mem += sizeof(struct resource) * nr_ioapics; | |
4074 | ||
4075 | for (i = 0; i < nr_ioapics; i++) { | |
4076 | res[i].name = mem; | |
4077 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4078 | sprintf(mem, "IOAPIC %u", i); | |
4079 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4080 | } | |
4081 | } | |
4082 | ||
4083 | ioapic_resources = res; | |
4084 | ||
4085 | return res; | |
4086 | } | |
54168ed7 | 4087 | |
f3294a33 YL |
4088 | void __init ioapic_init_mappings(void) |
4089 | { | |
4090 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4091 | struct resource *ioapic_res; |
d6c88a50 | 4092 | int i; |
f3294a33 | 4093 | |
54168ed7 | 4094 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4095 | for (i = 0; i < nr_ioapics; i++) { |
4096 | if (smp_found_config) { | |
b5ba7e6d | 4097 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4098 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4099 | if (!ioapic_phys) { |
4100 | printk(KERN_ERR | |
4101 | "WARNING: bogus zero IO-APIC " | |
4102 | "address found in MPTABLE, " | |
4103 | "disabling IO/APIC support!\n"); | |
4104 | smp_found_config = 0; | |
4105 | skip_ioapic_setup = 1; | |
4106 | goto fake_ioapic_page; | |
4107 | } | |
54168ed7 | 4108 | #endif |
f3294a33 | 4109 | } else { |
54168ed7 | 4110 | #ifdef CONFIG_X86_32 |
f3294a33 | 4111 | fake_ioapic_page: |
54168ed7 | 4112 | #endif |
f3294a33 | 4113 | ioapic_phys = (unsigned long) |
54168ed7 | 4114 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4115 | ioapic_phys = __pa(ioapic_phys); |
4116 | } | |
4117 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4118 | apic_printk(APIC_VERBOSE, |
4119 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4120 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4121 | idx++; |
54168ed7 | 4122 | |
54168ed7 IM |
4123 | if (ioapic_res != NULL) { |
4124 | ioapic_res->start = ioapic_phys; | |
4125 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4126 | ioapic_res++; | |
4127 | } | |
f3294a33 YL |
4128 | } |
4129 | } | |
4130 | ||
54168ed7 IM |
4131 | static int __init ioapic_insert_resources(void) |
4132 | { | |
4133 | int i; | |
4134 | struct resource *r = ioapic_resources; | |
4135 | ||
4136 | if (!r) { | |
04c93ce4 BZ |
4137 | if (nr_ioapics > 0) { |
4138 | printk(KERN_ERR | |
4139 | "IO APIC resources couldn't be allocated.\n"); | |
4140 | return -1; | |
4141 | } | |
4142 | return 0; | |
54168ed7 IM |
4143 | } |
4144 | ||
4145 | for (i = 0; i < nr_ioapics; i++) { | |
4146 | insert_resource(&iomem_resource, r); | |
4147 | r++; | |
4148 | } | |
4149 | ||
4150 | return 0; | |
4151 | } | |
4152 | ||
4153 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4154 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4155 | late_initcall(ioapic_insert_resources); |