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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
4173a0e7 DN |
63 | #include <asm/uv/uv_hub.h> |
64 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 65 | |
7b6aa335 | 66 | #include <asm/apic.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
c2c21745 | 89 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
65a4e574 IM |
102 | void arch_disable_smp_support(void) |
103 | { | |
104 | #ifdef CONFIG_PCI | |
105 | noioapicquirk = 1; | |
106 | noioapicreroute = -1; | |
107 | #endif | |
108 | skip_ioapic_setup = 1; | |
109 | } | |
110 | ||
54168ed7 | 111 | static int __init parse_noapic(char *str) |
efa2559f YL |
112 | { |
113 | /* disable IO-APIC */ | |
65a4e574 | 114 | arch_disable_smp_support(); |
efa2559f YL |
115 | return 0; |
116 | } | |
117 | early_param("noapic", parse_noapic); | |
66759a01 | 118 | |
0f978f45 | 119 | struct irq_pin_list; |
0b8f1efa YL |
120 | |
121 | /* | |
122 | * This is performance-critical, we want to do it O(1) | |
123 | * | |
124 | * the indexing order of this array favors 1:1 mappings | |
125 | * between pins and IRQs. | |
126 | */ | |
127 | ||
128 | struct irq_pin_list { | |
129 | int apic, pin; | |
130 | struct irq_pin_list *next; | |
131 | }; | |
132 | ||
85ac16d0 | 133 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
134 | { |
135 | struct irq_pin_list *pin; | |
0b8f1efa YL |
136 | |
137 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
138 | |
139 | return pin; | |
140 | } | |
141 | ||
a1420f39 | 142 | struct irq_cfg { |
0f978f45 | 143 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
144 | cpumask_var_t domain; |
145 | cpumask_var_t old_domain; | |
497c9a19 | 146 | unsigned move_cleanup_count; |
a1420f39 | 147 | u8 vector; |
497c9a19 | 148 | u8 move_in_progress : 1; |
a1420f39 YL |
149 | }; |
150 | ||
a1420f39 | 151 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
152 | #ifdef CONFIG_SPARSE_IRQ |
153 | static struct irq_cfg irq_cfgx[] = { | |
154 | #else | |
d6c88a50 | 155 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 156 | #endif |
22f65d31 MT |
157 | [0] = { .vector = IRQ0_VECTOR, }, |
158 | [1] = { .vector = IRQ1_VECTOR, }, | |
159 | [2] = { .vector = IRQ2_VECTOR, }, | |
160 | [3] = { .vector = IRQ3_VECTOR, }, | |
161 | [4] = { .vector = IRQ4_VECTOR, }, | |
162 | [5] = { .vector = IRQ5_VECTOR, }, | |
163 | [6] = { .vector = IRQ6_VECTOR, }, | |
164 | [7] = { .vector = IRQ7_VECTOR, }, | |
165 | [8] = { .vector = IRQ8_VECTOR, }, | |
166 | [9] = { .vector = IRQ9_VECTOR, }, | |
167 | [10] = { .vector = IRQ10_VECTOR, }, | |
168 | [11] = { .vector = IRQ11_VECTOR, }, | |
169 | [12] = { .vector = IRQ12_VECTOR, }, | |
170 | [13] = { .vector = IRQ13_VECTOR, }, | |
171 | [14] = { .vector = IRQ14_VECTOR, }, | |
172 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
173 | }; |
174 | ||
13a0c3c2 | 175 | int __init arch_early_irq_init(void) |
8f09cd20 | 176 | { |
0b8f1efa YL |
177 | struct irq_cfg *cfg; |
178 | struct irq_desc *desc; | |
179 | int count; | |
dad213ae | 180 | int node; |
0b8f1efa | 181 | int i; |
d6c88a50 | 182 | |
0b8f1efa YL |
183 | cfg = irq_cfgx; |
184 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 185 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 186 | |
0b8f1efa YL |
187 | for (i = 0; i < count; i++) { |
188 | desc = irq_to_desc(i); | |
189 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
190 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
191 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
22f65d31 MT |
192 | if (i < NR_IRQS_LEGACY) |
193 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 194 | } |
13a0c3c2 YL |
195 | |
196 | return 0; | |
0b8f1efa | 197 | } |
8f09cd20 | 198 | |
0b8f1efa | 199 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 200 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 201 | { |
0b8f1efa YL |
202 | struct irq_cfg *cfg = NULL; |
203 | struct irq_desc *desc; | |
1da177e4 | 204 | |
0b8f1efa YL |
205 | desc = irq_to_desc(irq); |
206 | if (desc) | |
207 | cfg = desc->chip_data; | |
0f978f45 | 208 | |
0b8f1efa | 209 | return cfg; |
8f09cd20 | 210 | } |
d6c88a50 | 211 | |
85ac16d0 | 212 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 213 | { |
0b8f1efa | 214 | struct irq_cfg *cfg; |
0f978f45 | 215 | |
0b8f1efa | 216 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 217 | if (cfg) { |
80855f73 | 218 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
219 | kfree(cfg); |
220 | cfg = NULL; | |
80855f73 MT |
221 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
222 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
223 | free_cpumask_var(cfg->domain); |
224 | kfree(cfg); | |
225 | cfg = NULL; | |
226 | } else { | |
227 | cpumask_clear(cfg->domain); | |
228 | cpumask_clear(cfg->old_domain); | |
229 | } | |
230 | } | |
0f978f45 | 231 | |
0b8f1efa | 232 | return cfg; |
8f09cd20 YL |
233 | } |
234 | ||
85ac16d0 | 235 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 236 | { |
0b8f1efa | 237 | struct irq_cfg *cfg; |
d6c88a50 | 238 | |
0b8f1efa YL |
239 | cfg = desc->chip_data; |
240 | if (!cfg) { | |
85ac16d0 | 241 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
242 | if (!desc->chip_data) { |
243 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
244 | BUG_ON(1); | |
245 | } | |
246 | } | |
1da177e4 | 247 | |
13a0c3c2 | 248 | return 0; |
0b8f1efa | 249 | } |
0f978f45 | 250 | |
fcef5911 | 251 | /* for move_irq_desc */ |
48a1b10a | 252 | static void |
85ac16d0 | 253 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 254 | { |
48a1b10a YL |
255 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
256 | ||
257 | cfg->irq_2_pin = NULL; | |
258 | old_entry = old_cfg->irq_2_pin; | |
259 | if (!old_entry) | |
260 | return; | |
0f978f45 | 261 | |
85ac16d0 | 262 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
263 | if (!entry) |
264 | return; | |
0f978f45 | 265 | |
48a1b10a YL |
266 | entry->apic = old_entry->apic; |
267 | entry->pin = old_entry->pin; | |
268 | head = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | while (old_entry) { | |
85ac16d0 | 272 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
273 | if (!entry) { |
274 | entry = head; | |
275 | while (entry) { | |
276 | head = entry->next; | |
277 | kfree(entry); | |
278 | entry = head; | |
279 | } | |
280 | /* still use the old one */ | |
281 | return; | |
282 | } | |
283 | entry->apic = old_entry->apic; | |
284 | entry->pin = old_entry->pin; | |
285 | tail->next = entry; | |
286 | tail = entry; | |
287 | old_entry = old_entry->next; | |
288 | } | |
0f978f45 | 289 | |
48a1b10a YL |
290 | tail->next = NULL; |
291 | cfg->irq_2_pin = head; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 295 | { |
48a1b10a | 296 | struct irq_pin_list *entry, *next; |
0f978f45 | 297 | |
48a1b10a YL |
298 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
299 | return; | |
301e6190 | 300 | |
48a1b10a | 301 | entry = old_cfg->irq_2_pin; |
0f978f45 | 302 | |
48a1b10a YL |
303 | while (entry) { |
304 | next = entry->next; | |
305 | kfree(entry); | |
306 | entry = next; | |
307 | } | |
308 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 309 | } |
0f978f45 | 310 | |
48a1b10a | 311 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 312 | struct irq_desc *desc, int node) |
0f978f45 | 313 | { |
48a1b10a YL |
314 | struct irq_cfg *cfg; |
315 | struct irq_cfg *old_cfg; | |
0f978f45 | 316 | |
85ac16d0 | 317 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 318 | |
48a1b10a YL |
319 | if (!cfg) |
320 | return; | |
321 | ||
322 | desc->chip_data = cfg; | |
323 | ||
324 | old_cfg = old_desc->chip_data; | |
325 | ||
326 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
327 | ||
85ac16d0 | 328 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 329 | } |
1da177e4 | 330 | |
48a1b10a YL |
331 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
332 | { | |
333 | kfree(old_cfg); | |
334 | } | |
335 | ||
336 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
337 | { | |
338 | struct irq_cfg *old_cfg, *cfg; | |
339 | ||
340 | old_cfg = old_desc->chip_data; | |
341 | cfg = desc->chip_data; | |
342 | ||
343 | if (old_cfg == cfg) | |
344 | return; | |
345 | ||
346 | if (old_cfg) { | |
347 | free_irq_2_pin(old_cfg, cfg); | |
348 | free_irq_cfg(old_cfg); | |
349 | old_desc->chip_data = NULL; | |
350 | } | |
351 | } | |
fcef5911 | 352 | /* end for move_irq_desc */ |
48a1b10a | 353 | |
0b8f1efa YL |
354 | #else |
355 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
356 | { | |
357 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 358 | } |
1da177e4 | 359 | |
0b8f1efa YL |
360 | #endif |
361 | ||
130fe05d LT |
362 | struct io_apic { |
363 | unsigned int index; | |
364 | unsigned int unused[3]; | |
365 | unsigned int data; | |
0280f7c4 SS |
366 | unsigned int unused2[11]; |
367 | unsigned int eoi; | |
130fe05d LT |
368 | }; |
369 | ||
370 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
371 | { | |
372 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 373 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
374 | } |
375 | ||
0280f7c4 SS |
376 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
377 | { | |
378 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
379 | writel(vector, &io_apic->eoi); | |
380 | } | |
381 | ||
130fe05d LT |
382 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
383 | { | |
384 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
385 | writel(reg, &io_apic->index); | |
386 | return readl(&io_apic->data); | |
387 | } | |
388 | ||
389 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
390 | { | |
391 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
392 | writel(reg, &io_apic->index); | |
393 | writel(value, &io_apic->data); | |
394 | } | |
395 | ||
396 | /* | |
397 | * Re-write a value: to be used for read-modify-write | |
398 | * cycles where the read already set up the index register. | |
399 | * | |
400 | * Older SiS APIC requires we rewrite the index register | |
401 | */ | |
402 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
403 | { | |
54168ed7 | 404 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
405 | |
406 | if (sis_apic_bug) | |
407 | writel(reg, &io_apic->index); | |
130fe05d LT |
408 | writel(value, &io_apic->data); |
409 | } | |
410 | ||
3145e941 | 411 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
412 | { |
413 | struct irq_pin_list *entry; | |
414 | unsigned long flags; | |
047c8fdb YL |
415 | |
416 | spin_lock_irqsave(&ioapic_lock, flags); | |
417 | entry = cfg->irq_2_pin; | |
418 | for (;;) { | |
419 | unsigned int reg; | |
420 | int pin; | |
421 | ||
422 | if (!entry) | |
423 | break; | |
424 | pin = entry->pin; | |
425 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
426 | /* Is the remote IRR bit set? */ | |
427 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
428 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
429 | return true; | |
430 | } | |
431 | if (!entry->next) | |
432 | break; | |
433 | entry = entry->next; | |
434 | } | |
435 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
436 | ||
437 | return false; | |
438 | } | |
047c8fdb | 439 | |
cf4c6a2f AK |
440 | union entry_union { |
441 | struct { u32 w1, w2; }; | |
442 | struct IO_APIC_route_entry entry; | |
443 | }; | |
444 | ||
445 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
446 | { | |
447 | union entry_union eu; | |
448 | unsigned long flags; | |
449 | spin_lock_irqsave(&ioapic_lock, flags); | |
450 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
451 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
452 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
453 | return eu.entry; | |
454 | } | |
455 | ||
f9dadfa7 LT |
456 | /* |
457 | * When we write a new IO APIC routing entry, we need to write the high | |
458 | * word first! If the mask bit in the low word is clear, we will enable | |
459 | * the interrupt, and we need to make sure the entry is fully populated | |
460 | * before that happens. | |
461 | */ | |
d15512f4 AK |
462 | static void |
463 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 464 | { |
50a8d4d2 F |
465 | union entry_union eu = {{0, 0}}; |
466 | ||
cf4c6a2f | 467 | eu.entry = e; |
f9dadfa7 LT |
468 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
469 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
470 | } |
471 | ||
ca97ab90 | 472 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
473 | { |
474 | unsigned long flags; | |
475 | spin_lock_irqsave(&ioapic_lock, flags); | |
476 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
477 | spin_unlock_irqrestore(&ioapic_lock, flags); |
478 | } | |
479 | ||
480 | /* | |
481 | * When we mask an IO APIC routing entry, we need to write the low | |
482 | * word first, in order to set the mask bit before we change the | |
483 | * high bits! | |
484 | */ | |
485 | static void ioapic_mask_entry(int apic, int pin) | |
486 | { | |
487 | unsigned long flags; | |
488 | union entry_union eu = { .entry.mask = 1 }; | |
489 | ||
cf4c6a2f AK |
490 | spin_lock_irqsave(&ioapic_lock, flags); |
491 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
492 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
493 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
494 | } | |
495 | ||
1da177e4 LT |
496 | /* |
497 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
498 | * shared ISA-space IRQs, so we have to support them. We are super | |
499 | * fast in the common case, and fast for shared ISA-space IRQs. | |
500 | */ | |
85ac16d0 | 501 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 502 | { |
0f978f45 YL |
503 | struct irq_pin_list *entry; |
504 | ||
0f978f45 YL |
505 | entry = cfg->irq_2_pin; |
506 | if (!entry) { | |
85ac16d0 | 507 | entry = get_one_free_irq_2_pin(node); |
0b8f1efa YL |
508 | if (!entry) { |
509 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
510 | apic, pin); | |
511 | return; | |
512 | } | |
0f978f45 YL |
513 | cfg->irq_2_pin = entry; |
514 | entry->apic = apic; | |
515 | entry->pin = pin; | |
0f978f45 YL |
516 | return; |
517 | } | |
1da177e4 | 518 | |
0f978f45 YL |
519 | while (entry->next) { |
520 | /* not again, please */ | |
521 | if (entry->apic == apic && entry->pin == pin) | |
522 | return; | |
1da177e4 | 523 | |
0f978f45 | 524 | entry = entry->next; |
1da177e4 | 525 | } |
0f978f45 | 526 | |
85ac16d0 | 527 | entry->next = get_one_free_irq_2_pin(node); |
0f978f45 | 528 | entry = entry->next; |
1da177e4 LT |
529 | entry->apic = apic; |
530 | entry->pin = pin; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Reroute an IRQ to a different pin. | |
535 | */ | |
85ac16d0 | 536 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
1da177e4 LT |
537 | int oldapic, int oldpin, |
538 | int newapic, int newpin) | |
539 | { | |
0f978f45 YL |
540 | struct irq_pin_list *entry = cfg->irq_2_pin; |
541 | int replaced = 0; | |
1da177e4 | 542 | |
0f978f45 | 543 | while (entry) { |
1da177e4 LT |
544 | if (entry->apic == oldapic && entry->pin == oldpin) { |
545 | entry->apic = newapic; | |
546 | entry->pin = newpin; | |
0f978f45 YL |
547 | replaced = 1; |
548 | /* every one is different, right? */ | |
1da177e4 | 549 | break; |
0f978f45 YL |
550 | } |
551 | entry = entry->next; | |
1da177e4 | 552 | } |
0f978f45 YL |
553 | |
554 | /* why? call replace before add? */ | |
555 | if (!replaced) | |
85ac16d0 | 556 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
1da177e4 LT |
557 | } |
558 | ||
3145e941 | 559 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
560 | int mask_and, int mask_or, |
561 | void (*final)(struct irq_pin_list *entry)) | |
562 | { | |
563 | int pin; | |
87783be4 | 564 | struct irq_pin_list *entry; |
047c8fdb | 565 | |
87783be4 CG |
566 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
567 | unsigned int reg; | |
568 | pin = entry->pin; | |
569 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
570 | reg &= mask_and; | |
571 | reg |= mask_or; | |
572 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
573 | if (final) | |
574 | final(entry); | |
575 | } | |
576 | } | |
047c8fdb | 577 | |
3145e941 | 578 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 579 | { |
3145e941 | 580 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 581 | } |
047c8fdb | 582 | |
4e738e2f | 583 | #ifdef CONFIG_X86_64 |
7f3e632f | 584 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 585 | { |
87783be4 CG |
586 | /* |
587 | * Synchronize the IO-APIC and the CPU by doing | |
588 | * a dummy read from the IO-APIC | |
589 | */ | |
590 | struct io_apic __iomem *io_apic; | |
591 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 592 | readl(&io_apic->data); |
1da177e4 LT |
593 | } |
594 | ||
3145e941 | 595 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 596 | { |
3145e941 | 597 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
598 | } |
599 | #else /* CONFIG_X86_32 */ | |
3145e941 | 600 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 601 | { |
3145e941 | 602 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 603 | } |
1da177e4 | 604 | |
3145e941 | 605 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 606 | { |
3145e941 | 607 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
608 | IO_APIC_REDIR_MASKED, NULL); |
609 | } | |
1da177e4 | 610 | |
3145e941 | 611 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 612 | { |
3145e941 | 613 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
614 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
615 | } | |
616 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 617 | |
3145e941 | 618 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 619 | { |
3145e941 | 620 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
621 | unsigned long flags; |
622 | ||
3145e941 YL |
623 | BUG_ON(!cfg); |
624 | ||
1da177e4 | 625 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 626 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
627 | spin_unlock_irqrestore(&ioapic_lock, flags); |
628 | } | |
629 | ||
3145e941 | 630 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 631 | { |
3145e941 | 632 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
633 | unsigned long flags; |
634 | ||
635 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 636 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
637 | spin_unlock_irqrestore(&ioapic_lock, flags); |
638 | } | |
639 | ||
3145e941 YL |
640 | static void mask_IO_APIC_irq(unsigned int irq) |
641 | { | |
642 | struct irq_desc *desc = irq_to_desc(irq); | |
643 | ||
644 | mask_IO_APIC_irq_desc(desc); | |
645 | } | |
646 | static void unmask_IO_APIC_irq(unsigned int irq) | |
647 | { | |
648 | struct irq_desc *desc = irq_to_desc(irq); | |
649 | ||
650 | unmask_IO_APIC_irq_desc(desc); | |
651 | } | |
652 | ||
1da177e4 LT |
653 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
654 | { | |
655 | struct IO_APIC_route_entry entry; | |
36062448 | 656 | |
1da177e4 | 657 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 658 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
659 | if (entry.delivery_mode == dest_SMI) |
660 | return; | |
1da177e4 LT |
661 | /* |
662 | * Disable it in the IO-APIC irq-routing table: | |
663 | */ | |
f9dadfa7 | 664 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
665 | } |
666 | ||
54168ed7 | 667 | static void clear_IO_APIC (void) |
1da177e4 LT |
668 | { |
669 | int apic, pin; | |
670 | ||
671 | for (apic = 0; apic < nr_ioapics; apic++) | |
672 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
673 | clear_IO_APIC_pin(apic, pin); | |
674 | } | |
675 | ||
54168ed7 | 676 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
677 | /* |
678 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
679 | * specific CPU-side IRQs. | |
680 | */ | |
681 | ||
682 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
683 | static int pirq_entries[MAX_PIRQS] = { |
684 | [0 ... MAX_PIRQS - 1] = -1 | |
685 | }; | |
1da177e4 | 686 | |
1da177e4 LT |
687 | static int __init ioapic_pirq_setup(char *str) |
688 | { | |
689 | int i, max; | |
690 | int ints[MAX_PIRQS+1]; | |
691 | ||
692 | get_options(str, ARRAY_SIZE(ints), ints); | |
693 | ||
1da177e4 LT |
694 | apic_printk(APIC_VERBOSE, KERN_INFO |
695 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
696 | max = MAX_PIRQS; | |
697 | if (ints[0] < MAX_PIRQS) | |
698 | max = ints[0]; | |
699 | ||
700 | for (i = 0; i < max; i++) { | |
701 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
702 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
703 | /* | |
704 | * PIRQs are mapped upside down, usually. | |
705 | */ | |
706 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
707 | } | |
708 | return 1; | |
709 | } | |
710 | ||
711 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
712 | #endif /* CONFIG_X86_32 */ |
713 | ||
b24696bc FY |
714 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
715 | { | |
716 | int apic; | |
717 | struct IO_APIC_route_entry **ioapic_entries; | |
718 | ||
719 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
720 | GFP_ATOMIC); | |
721 | if (!ioapic_entries) | |
722 | return 0; | |
723 | ||
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
725 | ioapic_entries[apic] = | |
726 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
727 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
728 | if (!ioapic_entries[apic]) | |
729 | goto nomem; | |
730 | } | |
731 | ||
732 | return ioapic_entries; | |
733 | ||
734 | nomem: | |
735 | while (--apic >= 0) | |
736 | kfree(ioapic_entries[apic]); | |
737 | kfree(ioapic_entries); | |
738 | ||
739 | return 0; | |
740 | } | |
54168ed7 IM |
741 | |
742 | /* | |
05c3dc2c | 743 | * Saves all the IO-APIC RTE's |
54168ed7 | 744 | */ |
b24696bc | 745 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 746 | { |
54168ed7 IM |
747 | int apic, pin; |
748 | ||
b24696bc FY |
749 | if (!ioapic_entries) |
750 | return -ENOMEM; | |
54168ed7 IM |
751 | |
752 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
753 | if (!ioapic_entries[apic]) |
754 | return -ENOMEM; | |
54168ed7 | 755 | |
05c3dc2c | 756 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 757 | ioapic_entries[apic][pin] = |
54168ed7 | 758 | ioapic_read_entry(apic, pin); |
b24696bc | 759 | } |
5ffa4eb2 | 760 | |
54168ed7 IM |
761 | return 0; |
762 | } | |
763 | ||
b24696bc FY |
764 | /* |
765 | * Mask all IO APIC entries. | |
766 | */ | |
767 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
768 | { |
769 | int apic, pin; | |
770 | ||
b24696bc FY |
771 | if (!ioapic_entries) |
772 | return; | |
773 | ||
05c3dc2c | 774 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 775 | if (!ioapic_entries[apic]) |
05c3dc2c | 776 | break; |
b24696bc | 777 | |
05c3dc2c SS |
778 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
779 | struct IO_APIC_route_entry entry; | |
780 | ||
b24696bc | 781 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
782 | if (!entry.mask) { |
783 | entry.mask = 1; | |
784 | ioapic_write_entry(apic, pin, entry); | |
785 | } | |
786 | } | |
787 | } | |
788 | } | |
789 | ||
b24696bc FY |
790 | /* |
791 | * Restore IO APIC entries which was saved in ioapic_entries. | |
792 | */ | |
793 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
794 | { |
795 | int apic, pin; | |
796 | ||
b24696bc FY |
797 | if (!ioapic_entries) |
798 | return -ENOMEM; | |
799 | ||
5ffa4eb2 | 800 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
801 | if (!ioapic_entries[apic]) |
802 | return -ENOMEM; | |
803 | ||
54168ed7 IM |
804 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
805 | ioapic_write_entry(apic, pin, | |
b24696bc | 806 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 807 | } |
b24696bc | 808 | return 0; |
54168ed7 IM |
809 | } |
810 | ||
b24696bc FY |
811 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
812 | { | |
813 | int apic; | |
814 | ||
815 | for (apic = 0; apic < nr_ioapics; apic++) | |
816 | kfree(ioapic_entries[apic]); | |
817 | ||
818 | kfree(ioapic_entries); | |
54168ed7 | 819 | } |
1da177e4 LT |
820 | |
821 | /* | |
822 | * Find the IRQ entry number of a certain pin. | |
823 | */ | |
824 | static int find_irq_entry(int apic, int pin, int type) | |
825 | { | |
826 | int i; | |
827 | ||
828 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
829 | if (mp_irqs[i].irqtype == type && |
830 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
831 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
832 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
833 | return i; |
834 | ||
835 | return -1; | |
836 | } | |
837 | ||
838 | /* | |
839 | * Find the pin to which IRQ[irq] (ISA) is connected | |
840 | */ | |
fcfd636a | 841 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
842 | { |
843 | int i; | |
844 | ||
845 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 846 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 847 | |
d27e2b8e | 848 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
849 | (mp_irqs[i].irqtype == type) && |
850 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 851 | |
c2c21745 | 852 | return mp_irqs[i].dstirq; |
1da177e4 LT |
853 | } |
854 | return -1; | |
855 | } | |
856 | ||
fcfd636a EB |
857 | static int __init find_isa_irq_apic(int irq, int type) |
858 | { | |
859 | int i; | |
860 | ||
861 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 862 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 863 | |
73b2961b | 864 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
865 | (mp_irqs[i].irqtype == type) && |
866 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
867 | break; |
868 | } | |
869 | if (i < mp_irq_entries) { | |
870 | int apic; | |
54168ed7 | 871 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 872 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
873 | return apic; |
874 | } | |
875 | } | |
876 | ||
877 | return -1; | |
878 | } | |
879 | ||
c0a282c2 | 880 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
881 | /* |
882 | * EISA Edge/Level control register, ELCR | |
883 | */ | |
884 | static int EISA_ELCR(unsigned int irq) | |
885 | { | |
99d093d1 | 886 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
887 | unsigned int port = 0x4d0 + (irq >> 3); |
888 | return (inb(port) >> (irq & 7)) & 1; | |
889 | } | |
890 | apic_printk(APIC_VERBOSE, KERN_INFO | |
891 | "Broken MPtable reports ISA irq %d\n", irq); | |
892 | return 0; | |
893 | } | |
54168ed7 | 894 | |
c0a282c2 | 895 | #endif |
1da177e4 | 896 | |
6728801d AS |
897 | /* ISA interrupts are always polarity zero edge triggered, |
898 | * when listed as conforming in the MP table. */ | |
899 | ||
900 | #define default_ISA_trigger(idx) (0) | |
901 | #define default_ISA_polarity(idx) (0) | |
902 | ||
1da177e4 LT |
903 | /* EISA interrupts are always polarity zero and can be edge or level |
904 | * trigger depending on the ELCR value. If an interrupt is listed as | |
905 | * EISA conforming in the MP table, that means its trigger type must | |
906 | * be read in from the ELCR */ | |
907 | ||
c2c21745 | 908 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 909 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
910 | |
911 | /* PCI interrupts are always polarity one level triggered, | |
912 | * when listed as conforming in the MP table. */ | |
913 | ||
914 | #define default_PCI_trigger(idx) (1) | |
915 | #define default_PCI_polarity(idx) (1) | |
916 | ||
917 | /* MCA interrupts are always polarity zero level triggered, | |
918 | * when listed as conforming in the MP table. */ | |
919 | ||
920 | #define default_MCA_trigger(idx) (1) | |
6728801d | 921 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 922 | |
61fd47e0 | 923 | static int MPBIOS_polarity(int idx) |
1da177e4 | 924 | { |
c2c21745 | 925 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
926 | int polarity; |
927 | ||
928 | /* | |
929 | * Determine IRQ line polarity (high active or low active): | |
930 | */ | |
c2c21745 | 931 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 932 | { |
54168ed7 IM |
933 | case 0: /* conforms, ie. bus-type dependent polarity */ |
934 | if (test_bit(bus, mp_bus_not_pci)) | |
935 | polarity = default_ISA_polarity(idx); | |
936 | else | |
937 | polarity = default_PCI_polarity(idx); | |
938 | break; | |
939 | case 1: /* high active */ | |
940 | { | |
941 | polarity = 0; | |
942 | break; | |
943 | } | |
944 | case 2: /* reserved */ | |
945 | { | |
946 | printk(KERN_WARNING "broken BIOS!!\n"); | |
947 | polarity = 1; | |
948 | break; | |
949 | } | |
950 | case 3: /* low active */ | |
951 | { | |
952 | polarity = 1; | |
953 | break; | |
954 | } | |
955 | default: /* invalid */ | |
956 | { | |
957 | printk(KERN_WARNING "broken BIOS!!\n"); | |
958 | polarity = 1; | |
959 | break; | |
960 | } | |
1da177e4 LT |
961 | } |
962 | return polarity; | |
963 | } | |
964 | ||
965 | static int MPBIOS_trigger(int idx) | |
966 | { | |
c2c21745 | 967 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
968 | int trigger; |
969 | ||
970 | /* | |
971 | * Determine IRQ trigger mode (edge or level sensitive): | |
972 | */ | |
c2c21745 | 973 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 974 | { |
54168ed7 IM |
975 | case 0: /* conforms, ie. bus-type dependent */ |
976 | if (test_bit(bus, mp_bus_not_pci)) | |
977 | trigger = default_ISA_trigger(idx); | |
978 | else | |
979 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 980 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
981 | switch (mp_bus_id_to_type[bus]) { |
982 | case MP_BUS_ISA: /* ISA pin */ | |
983 | { | |
984 | /* set before the switch */ | |
985 | break; | |
986 | } | |
987 | case MP_BUS_EISA: /* EISA pin */ | |
988 | { | |
989 | trigger = default_EISA_trigger(idx); | |
990 | break; | |
991 | } | |
992 | case MP_BUS_PCI: /* PCI pin */ | |
993 | { | |
994 | /* set before the switch */ | |
995 | break; | |
996 | } | |
997 | case MP_BUS_MCA: /* MCA pin */ | |
998 | { | |
999 | trigger = default_MCA_trigger(idx); | |
1000 | break; | |
1001 | } | |
1002 | default: | |
1003 | { | |
1004 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1005 | trigger = 1; | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | #endif | |
1da177e4 | 1010 | break; |
54168ed7 | 1011 | case 1: /* edge */ |
1da177e4 | 1012 | { |
54168ed7 | 1013 | trigger = 0; |
1da177e4 LT |
1014 | break; |
1015 | } | |
54168ed7 | 1016 | case 2: /* reserved */ |
1da177e4 | 1017 | { |
54168ed7 IM |
1018 | printk(KERN_WARNING "broken BIOS!!\n"); |
1019 | trigger = 1; | |
1da177e4 LT |
1020 | break; |
1021 | } | |
54168ed7 | 1022 | case 3: /* level */ |
1da177e4 | 1023 | { |
54168ed7 | 1024 | trigger = 1; |
1da177e4 LT |
1025 | break; |
1026 | } | |
54168ed7 | 1027 | default: /* invalid */ |
1da177e4 LT |
1028 | { |
1029 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1030 | trigger = 0; |
1da177e4 LT |
1031 | break; |
1032 | } | |
1033 | } | |
1034 | return trigger; | |
1035 | } | |
1036 | ||
1037 | static inline int irq_polarity(int idx) | |
1038 | { | |
1039 | return MPBIOS_polarity(idx); | |
1040 | } | |
1041 | ||
1042 | static inline int irq_trigger(int idx) | |
1043 | { | |
1044 | return MPBIOS_trigger(idx); | |
1045 | } | |
1046 | ||
efa2559f | 1047 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1048 | static int pin_2_irq(int idx, int apic, int pin) |
1049 | { | |
1050 | int irq, i; | |
c2c21745 | 1051 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1052 | |
1053 | /* | |
1054 | * Debugging check, we are in big trouble if this message pops up! | |
1055 | */ | |
c2c21745 | 1056 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1057 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1058 | ||
54168ed7 | 1059 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1060 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1061 | } else { |
643befed AS |
1062 | /* |
1063 | * PCI IRQs are mapped in order | |
1064 | */ | |
1065 | i = irq = 0; | |
1066 | while (i < apic) | |
1067 | irq += nr_ioapic_registers[i++]; | |
1068 | irq += pin; | |
d6c88a50 | 1069 | /* |
54168ed7 IM |
1070 | * For MPS mode, so far only needed by ES7000 platform |
1071 | */ | |
d6c88a50 TG |
1072 | if (ioapic_renumber_irq) |
1073 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1074 | } |
1075 | ||
54168ed7 | 1076 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1077 | /* |
1078 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1079 | */ | |
1080 | if ((pin >= 16) && (pin <= 23)) { | |
1081 | if (pirq_entries[pin-16] != -1) { | |
1082 | if (!pirq_entries[pin-16]) { | |
1083 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1084 | "disabling PIRQ%d\n", pin-16); | |
1085 | } else { | |
1086 | irq = pirq_entries[pin-16]; | |
1087 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1088 | "using PIRQ%d -> IRQ %d\n", | |
1089 | pin-16, irq); | |
1090 | } | |
1091 | } | |
1092 | } | |
54168ed7 IM |
1093 | #endif |
1094 | ||
1da177e4 LT |
1095 | return irq; |
1096 | } | |
1097 | ||
e20c06fd YL |
1098 | /* |
1099 | * Find a specific PCI IRQ entry. | |
1100 | * Not an __init, possibly needed by modules | |
1101 | */ | |
1102 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1103 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1104 | { |
1105 | int apic, i, best_guess = -1; | |
1106 | ||
1107 | apic_printk(APIC_DEBUG, | |
1108 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1109 | bus, slot, pin); | |
1110 | if (test_bit(bus, mp_bus_not_pci)) { | |
1111 | apic_printk(APIC_VERBOSE, | |
1112 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1113 | return -1; | |
1114 | } | |
1115 | for (i = 0; i < mp_irq_entries; i++) { | |
1116 | int lbus = mp_irqs[i].srcbus; | |
1117 | ||
1118 | for (apic = 0; apic < nr_ioapics; apic++) | |
1119 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1120 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1121 | break; | |
1122 | ||
1123 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1124 | !mp_irqs[i].irqtype && | |
1125 | (bus == lbus) && | |
1126 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1127 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1128 | ||
1129 | if (!(apic || IO_APIC_IRQ(irq))) | |
1130 | continue; | |
1131 | ||
1132 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1133 | set_io_apic_irq_attr(irq_attr, apic, |
1134 | mp_irqs[i].dstirq, | |
1135 | irq_trigger(i), | |
1136 | irq_polarity(i)); | |
e20c06fd YL |
1137 | return irq; |
1138 | } | |
1139 | /* | |
1140 | * Use the first all-but-pin matching entry as a | |
1141 | * best-guess fuzzy result for broken mptables. | |
1142 | */ | |
1143 | if (best_guess < 0) { | |
e5198075 YL |
1144 | set_io_apic_irq_attr(irq_attr, apic, |
1145 | mp_irqs[i].dstirq, | |
1146 | irq_trigger(i), | |
1147 | irq_polarity(i)); | |
e20c06fd YL |
1148 | best_guess = irq; |
1149 | } | |
1150 | } | |
1151 | } | |
1152 | return best_guess; | |
1153 | } | |
1154 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1155 | ||
497c9a19 YL |
1156 | void lock_vector_lock(void) |
1157 | { | |
1158 | /* Used to the online set of cpus does not change | |
1159 | * during assign_irq_vector. | |
1160 | */ | |
1161 | spin_lock(&vector_lock); | |
1162 | } | |
1da177e4 | 1163 | |
497c9a19 | 1164 | void unlock_vector_lock(void) |
1da177e4 | 1165 | { |
497c9a19 YL |
1166 | spin_unlock(&vector_lock); |
1167 | } | |
1da177e4 | 1168 | |
e7986739 MT |
1169 | static int |
1170 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1171 | { |
047c8fdb YL |
1172 | /* |
1173 | * NOTE! The local APIC isn't very good at handling | |
1174 | * multiple interrupts at the same interrupt level. | |
1175 | * As the interrupt level is determined by taking the | |
1176 | * vector number and shifting that right by 4, we | |
1177 | * want to spread these out a bit so that they don't | |
1178 | * all fall in the same interrupt level. | |
1179 | * | |
1180 | * Also, we've got to be careful not to trash gate | |
1181 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1182 | */ | |
54168ed7 IM |
1183 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1184 | unsigned int old_vector; | |
22f65d31 MT |
1185 | int cpu, err; |
1186 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1187 | |
54168ed7 IM |
1188 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1189 | return -EBUSY; | |
0a1ad60d | 1190 | |
22f65d31 MT |
1191 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1192 | return -ENOMEM; | |
ace80ab7 | 1193 | |
54168ed7 IM |
1194 | old_vector = cfg->vector; |
1195 | if (old_vector) { | |
22f65d31 MT |
1196 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1197 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1198 | if (!cpumask_empty(tmp_mask)) { | |
1199 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1200 | return 0; |
22f65d31 | 1201 | } |
54168ed7 | 1202 | } |
497c9a19 | 1203 | |
e7986739 | 1204 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1205 | err = -ENOSPC; |
1206 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1207 | int new_cpu; |
1208 | int vector, offset; | |
497c9a19 | 1209 | |
e2d40b18 | 1210 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1211 | |
54168ed7 IM |
1212 | vector = current_vector; |
1213 | offset = current_offset; | |
497c9a19 | 1214 | next: |
54168ed7 IM |
1215 | vector += 8; |
1216 | if (vector >= first_system_vector) { | |
e7986739 | 1217 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1218 | offset = (offset + 1) % 8; |
1219 | vector = FIRST_DEVICE_VECTOR + offset; | |
1220 | } | |
1221 | if (unlikely(current_vector == vector)) | |
1222 | continue; | |
b77b881f YL |
1223 | |
1224 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1225 | goto next; |
b77b881f | 1226 | |
22f65d31 | 1227 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1228 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1229 | goto next; | |
1230 | /* Found one! */ | |
1231 | current_vector = vector; | |
1232 | current_offset = offset; | |
1233 | if (old_vector) { | |
1234 | cfg->move_in_progress = 1; | |
22f65d31 | 1235 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1236 | } |
22f65d31 | 1237 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1238 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1239 | cfg->vector = vector; | |
22f65d31 MT |
1240 | cpumask_copy(cfg->domain, tmp_mask); |
1241 | err = 0; | |
1242 | break; | |
54168ed7 | 1243 | } |
22f65d31 MT |
1244 | free_cpumask_var(tmp_mask); |
1245 | return err; | |
497c9a19 YL |
1246 | } |
1247 | ||
e7986739 MT |
1248 | static int |
1249 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1250 | { |
1251 | int err; | |
ace80ab7 | 1252 | unsigned long flags; |
ace80ab7 EB |
1253 | |
1254 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1255 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1256 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1257 | return err; |
1258 | } | |
1259 | ||
3145e941 | 1260 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1261 | { |
497c9a19 YL |
1262 | int cpu, vector; |
1263 | ||
497c9a19 YL |
1264 | BUG_ON(!cfg->vector); |
1265 | ||
1266 | vector = cfg->vector; | |
22f65d31 | 1267 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1268 | per_cpu(vector_irq, cpu)[vector] = -1; |
1269 | ||
1270 | cfg->vector = 0; | |
22f65d31 | 1271 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1272 | |
1273 | if (likely(!cfg->move_in_progress)) | |
1274 | return; | |
22f65d31 | 1275 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1276 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1277 | vector++) { | |
1278 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1279 | continue; | |
1280 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1281 | break; | |
1282 | } | |
1283 | } | |
1284 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1285 | } |
1286 | ||
1287 | void __setup_vector_irq(int cpu) | |
1288 | { | |
1289 | /* Initialize vector_irq on a new cpu */ | |
1290 | /* This function must be called with vector_lock held */ | |
1291 | int irq, vector; | |
1292 | struct irq_cfg *cfg; | |
0b8f1efa | 1293 | struct irq_desc *desc; |
497c9a19 YL |
1294 | |
1295 | /* Mark the inuse vectors */ | |
0b8f1efa | 1296 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1297 | cfg = desc->chip_data; |
22f65d31 | 1298 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1299 | continue; |
1300 | vector = cfg->vector; | |
497c9a19 YL |
1301 | per_cpu(vector_irq, cpu)[vector] = irq; |
1302 | } | |
1303 | /* Mark the free vectors */ | |
1304 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1305 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1306 | if (irq < 0) | |
1307 | continue; | |
1308 | ||
1309 | cfg = irq_cfg(irq); | |
22f65d31 | 1310 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1311 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1312 | } |
1da177e4 | 1313 | } |
3fde6900 | 1314 | |
f5b9ed7a | 1315 | static struct irq_chip ioapic_chip; |
54168ed7 | 1316 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1317 | |
54168ed7 IM |
1318 | #define IOAPIC_AUTO -1 |
1319 | #define IOAPIC_EDGE 0 | |
1320 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1321 | |
047c8fdb | 1322 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1323 | static inline int IO_APIC_irq_trigger(int irq) |
1324 | { | |
d6c88a50 | 1325 | int apic, idx, pin; |
1d025192 | 1326 | |
d6c88a50 TG |
1327 | for (apic = 0; apic < nr_ioapics; apic++) { |
1328 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1329 | idx = find_irq_entry(apic, pin, mp_INT); | |
1330 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1331 | return irq_trigger(idx); | |
1332 | } | |
1333 | } | |
1334 | /* | |
54168ed7 IM |
1335 | * nonexistent IRQs are edge default |
1336 | */ | |
d6c88a50 | 1337 | return 0; |
1d025192 | 1338 | } |
047c8fdb YL |
1339 | #else |
1340 | static inline int IO_APIC_irq_trigger(int irq) | |
1341 | { | |
54168ed7 | 1342 | return 1; |
047c8fdb YL |
1343 | } |
1344 | #endif | |
1d025192 | 1345 | |
3145e941 | 1346 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1347 | { |
199751d7 | 1348 | |
6ebcc00e | 1349 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1350 | trigger == IOAPIC_LEVEL) |
08678b08 | 1351 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1352 | else |
1353 | desc->status &= ~IRQ_LEVEL; | |
1354 | ||
54168ed7 IM |
1355 | if (irq_remapped(irq)) { |
1356 | desc->status |= IRQ_MOVE_PCNTXT; | |
1357 | if (trigger) | |
1358 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1359 | handle_fasteoi_irq, | |
1360 | "fasteoi"); | |
1361 | else | |
1362 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1363 | handle_edge_irq, "edge"); | |
1364 | return; | |
1365 | } | |
29b61be6 | 1366 | |
047c8fdb YL |
1367 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1368 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1369 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1370 | handle_fasteoi_irq, |
1371 | "fasteoi"); | |
047c8fdb | 1372 | else |
a460e745 | 1373 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1374 | handle_edge_irq, "edge"); |
1da177e4 LT |
1375 | } |
1376 | ||
ca97ab90 JF |
1377 | int setup_ioapic_entry(int apic_id, int irq, |
1378 | struct IO_APIC_route_entry *entry, | |
1379 | unsigned int destination, int trigger, | |
0280f7c4 | 1380 | int polarity, int vector, int pin) |
1da177e4 | 1381 | { |
497c9a19 YL |
1382 | /* |
1383 | * add it to the IO-APIC irq-routing table: | |
1384 | */ | |
1385 | memset(entry,0,sizeof(*entry)); | |
1386 | ||
54168ed7 | 1387 | if (intr_remapping_enabled) { |
c8d46cf0 | 1388 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1389 | struct irte irte; |
1390 | struct IR_IO_APIC_route_entry *ir_entry = | |
1391 | (struct IR_IO_APIC_route_entry *) entry; | |
1392 | int index; | |
1393 | ||
1394 | if (!iommu) | |
c8d46cf0 | 1395 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1396 | |
1397 | index = alloc_irte(iommu, irq, 1); | |
1398 | if (index < 0) | |
c8d46cf0 | 1399 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1400 | |
1401 | memset(&irte, 0, sizeof(irte)); | |
1402 | ||
1403 | irte.present = 1; | |
9b5bc8dc | 1404 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1405 | /* |
1406 | * Trigger mode in the IRTE will always be edge, and the | |
1407 | * actual level or edge trigger will be setup in the IO-APIC | |
1408 | * RTE. This will help simplify level triggered irq migration. | |
1409 | * For more details, see the comments above explainig IO-APIC | |
1410 | * irq migration in the presence of interrupt-remapping. | |
1411 | */ | |
1412 | irte.trigger_mode = 0; | |
9b5bc8dc | 1413 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1414 | irte.vector = vector; |
1415 | irte.dest_id = IRTE_DEST(destination); | |
1416 | ||
f007e99c WH |
1417 | /* Set source-id of interrupt request */ |
1418 | set_ioapic_sid(&irte, apic_id); | |
1419 | ||
54168ed7 IM |
1420 | modify_irte(irq, &irte); |
1421 | ||
1422 | ir_entry->index2 = (index >> 15) & 0x1; | |
1423 | ir_entry->zero = 0; | |
1424 | ir_entry->format = 1; | |
1425 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1426 | /* |
1427 | * IO-APIC RTE will be configured with virtual vector. | |
1428 | * irq handler will do the explicit EOI to the io-apic. | |
1429 | */ | |
1430 | ir_entry->vector = pin; | |
29b61be6 | 1431 | } else { |
9b5bc8dc IM |
1432 | entry->delivery_mode = apic->irq_delivery_mode; |
1433 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1434 | entry->dest = destination; |
0280f7c4 | 1435 | entry->vector = vector; |
54168ed7 | 1436 | } |
497c9a19 | 1437 | |
54168ed7 | 1438 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1439 | entry->trigger = trigger; |
1440 | entry->polarity = polarity; | |
497c9a19 YL |
1441 | |
1442 | /* Mask level triggered irqs. | |
1443 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1444 | */ | |
1445 | if (trigger) | |
1446 | entry->mask = 1; | |
497c9a19 YL |
1447 | return 0; |
1448 | } | |
1449 | ||
c8d46cf0 | 1450 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1451 | int trigger, int polarity) |
497c9a19 YL |
1452 | { |
1453 | struct irq_cfg *cfg; | |
1da177e4 | 1454 | struct IO_APIC_route_entry entry; |
22f65d31 | 1455 | unsigned int dest; |
497c9a19 YL |
1456 | |
1457 | if (!IO_APIC_IRQ(irq)) | |
1458 | return; | |
1459 | ||
3145e941 | 1460 | cfg = desc->chip_data; |
497c9a19 | 1461 | |
fe402e1f | 1462 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1463 | return; |
1464 | ||
debccb3e | 1465 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1466 | |
1467 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1468 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1469 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1470 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1471 | irq, trigger, polarity); |
1472 | ||
1473 | ||
c8d46cf0 | 1474 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1475 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1476 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1477 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1478 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1479 | return; |
1480 | } | |
1481 | ||
3145e941 | 1482 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1483 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1484 | disable_8259A_irq(irq); |
1485 | ||
c8d46cf0 | 1486 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1487 | } |
1488 | ||
b9c61b70 YL |
1489 | static struct { |
1490 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1491 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1492 | ||
497c9a19 YL |
1493 | static void __init setup_IO_APIC_irqs(void) |
1494 | { | |
b9c61b70 | 1495 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1496 | int notcon = 0; |
0b8f1efa | 1497 | struct irq_desc *desc; |
3145e941 | 1498 | struct irq_cfg *cfg; |
85ac16d0 | 1499 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1500 | |
1501 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1502 | ||
b9c61b70 YL |
1503 | #ifdef CONFIG_ACPI |
1504 | if (!acpi_disabled && acpi_ioapic) { | |
1505 | apic_id = mp_find_ioapic(0); | |
1506 | if (apic_id < 0) | |
1507 | apic_id = 0; | |
1508 | } | |
1509 | #endif | |
3c2cbd24 | 1510 | |
b9c61b70 YL |
1511 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1512 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1513 | if (idx == -1) { | |
1514 | if (!notcon) { | |
1515 | notcon = 1; | |
1516 | apic_printk(APIC_VERBOSE, | |
1517 | KERN_DEBUG " %d-%d", | |
1518 | mp_ioapics[apic_id].apicid, pin); | |
1519 | } else | |
1520 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1521 | mp_ioapics[apic_id].apicid, pin); | |
1522 | continue; | |
1523 | } | |
1524 | if (notcon) { | |
1525 | apic_printk(APIC_VERBOSE, | |
1526 | " (apicid-pin) not connected\n"); | |
1527 | notcon = 0; | |
1528 | } | |
33a201fa | 1529 | |
b9c61b70 | 1530 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1531 | |
b9c61b70 YL |
1532 | /* |
1533 | * Skip the timer IRQ if there's a quirk handler | |
1534 | * installed and if it returns 1: | |
1535 | */ | |
1536 | if (apic->multi_timer_check && | |
1537 | apic->multi_timer_check(apic_id, irq)) | |
1538 | continue; | |
36062448 | 1539 | |
b9c61b70 YL |
1540 | desc = irq_to_desc_alloc_node(irq, node); |
1541 | if (!desc) { | |
1542 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1543 | continue; | |
3c2cbd24 | 1544 | } |
b9c61b70 YL |
1545 | cfg = desc->chip_data; |
1546 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1547 | /* |
1548 | * don't mark it in pin_programmed, so later acpi could | |
1549 | * set it correctly when irq < 16 | |
1550 | */ | |
b9c61b70 YL |
1551 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1552 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1553 | } |
1554 | ||
3c2cbd24 CG |
1555 | if (notcon) |
1556 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1557 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1558 | } |
1559 | ||
1560 | /* | |
f7633ce5 | 1561 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1562 | */ |
c8d46cf0 | 1563 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1564 | int vector) |
1da177e4 LT |
1565 | { |
1566 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1567 | |
54168ed7 IM |
1568 | if (intr_remapping_enabled) |
1569 | return; | |
54168ed7 | 1570 | |
36062448 | 1571 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1572 | |
1573 | /* | |
1574 | * We use logical delivery to get the timer IRQ | |
1575 | * to the first CPU. | |
1576 | */ | |
9b5bc8dc | 1577 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1578 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1579 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1580 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1581 | entry.polarity = 0; |
1582 | entry.trigger = 0; | |
1583 | entry.vector = vector; | |
1584 | ||
1585 | /* | |
1586 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1587 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1588 | */ |
54168ed7 | 1589 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1590 | |
1591 | /* | |
1592 | * Add it to the IO-APIC irq-routing table: | |
1593 | */ | |
c8d46cf0 | 1594 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1595 | } |
1596 | ||
32f71aff MR |
1597 | |
1598 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1599 | { |
1600 | int apic, i; | |
1601 | union IO_APIC_reg_00 reg_00; | |
1602 | union IO_APIC_reg_01 reg_01; | |
1603 | union IO_APIC_reg_02 reg_02; | |
1604 | union IO_APIC_reg_03 reg_03; | |
1605 | unsigned long flags; | |
0f978f45 | 1606 | struct irq_cfg *cfg; |
0b8f1efa | 1607 | struct irq_desc *desc; |
8f09cd20 | 1608 | unsigned int irq; |
1da177e4 LT |
1609 | |
1610 | if (apic_verbosity == APIC_QUIET) | |
1611 | return; | |
1612 | ||
36062448 | 1613 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1614 | for (i = 0; i < nr_ioapics; i++) |
1615 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1616 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1617 | |
1618 | /* | |
1619 | * We are a bit conservative about what we expect. We have to | |
1620 | * know about every hardware change ASAP. | |
1621 | */ | |
1622 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1623 | ||
1624 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1625 | ||
1626 | spin_lock_irqsave(&ioapic_lock, flags); | |
1627 | reg_00.raw = io_apic_read(apic, 0); | |
1628 | reg_01.raw = io_apic_read(apic, 1); | |
1629 | if (reg_01.bits.version >= 0x10) | |
1630 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1631 | if (reg_01.bits.version >= 0x20) |
1632 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1633 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1634 | ||
54168ed7 | 1635 | printk("\n"); |
b5ba7e6d | 1636 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1637 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1638 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1639 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1640 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1641 | |
54168ed7 | 1642 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1643 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1644 | |
1645 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1646 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1647 | |
1648 | /* | |
1649 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1650 | * but the value of reg_02 is read as the previous read register | |
1651 | * value, so ignore it if reg_02 == reg_01. | |
1652 | */ | |
1653 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1654 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1655 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1656 | } |
1657 | ||
1658 | /* | |
1659 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1660 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1661 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1662 | */ | |
1663 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1664 | reg_03.raw != reg_01.raw) { | |
1665 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1666 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1667 | } |
1668 | ||
1669 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1670 | ||
d83e94ac YL |
1671 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1672 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1673 | |
1674 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1675 | struct IO_APIC_route_entry entry; | |
1676 | ||
cf4c6a2f | 1677 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1678 | |
54168ed7 IM |
1679 | printk(KERN_DEBUG " %02x %03X ", |
1680 | i, | |
1681 | entry.dest | |
1682 | ); | |
1da177e4 LT |
1683 | |
1684 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1685 | entry.mask, | |
1686 | entry.trigger, | |
1687 | entry.irr, | |
1688 | entry.polarity, | |
1689 | entry.delivery_status, | |
1690 | entry.dest_mode, | |
1691 | entry.delivery_mode, | |
1692 | entry.vector | |
1693 | ); | |
1694 | } | |
1695 | } | |
1da177e4 | 1696 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1697 | for_each_irq_desc(irq, desc) { |
1698 | struct irq_pin_list *entry; | |
1699 | ||
0b8f1efa YL |
1700 | cfg = desc->chip_data; |
1701 | entry = cfg->irq_2_pin; | |
0f978f45 | 1702 | if (!entry) |
1da177e4 | 1703 | continue; |
8f09cd20 | 1704 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1705 | for (;;) { |
1706 | printk("-> %d:%d", entry->apic, entry->pin); | |
1707 | if (!entry->next) | |
1708 | break; | |
0f978f45 | 1709 | entry = entry->next; |
1da177e4 LT |
1710 | } |
1711 | printk("\n"); | |
1712 | } | |
1713 | ||
1714 | printk(KERN_INFO ".................................... done.\n"); | |
1715 | ||
1716 | return; | |
1717 | } | |
1718 | ||
32f71aff | 1719 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1720 | { |
1721 | unsigned int v; | |
1722 | int i, j; | |
1723 | ||
1724 | if (apic_verbosity == APIC_QUIET) | |
1725 | return; | |
1726 | ||
1727 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1728 | for (i = 0; i < 8; i++) { | |
1729 | v = apic_read(base + i*0x10); | |
1730 | for (j = 0; j < 32; j++) { | |
1731 | if (v & (1<<j)) | |
1732 | printk("1"); | |
1733 | else | |
1734 | printk("0"); | |
1735 | } | |
1736 | printk("\n"); | |
1737 | } | |
1738 | } | |
1739 | ||
32f71aff | 1740 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1741 | { |
97a52714 | 1742 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1743 | u64 icr; |
1da177e4 LT |
1744 | |
1745 | if (apic_verbosity == APIC_QUIET) | |
1746 | return; | |
1747 | ||
1748 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1749 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1750 | v = apic_read(APIC_ID); |
54168ed7 | 1751 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1752 | v = apic_read(APIC_LVR); |
1753 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1754 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1755 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1756 | |
1757 | v = apic_read(APIC_TASKPRI); | |
1758 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1759 | ||
54168ed7 | 1760 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1761 | if (!APIC_XAPIC(ver)) { |
1762 | v = apic_read(APIC_ARBPRI); | |
1763 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1764 | v & APIC_ARBPRI_MASK); | |
1765 | } | |
1da177e4 LT |
1766 | v = apic_read(APIC_PROCPRI); |
1767 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1768 | } | |
1769 | ||
a11b5abe YL |
1770 | /* |
1771 | * Remote read supported only in the 82489DX and local APIC for | |
1772 | * Pentium processors. | |
1773 | */ | |
1774 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1775 | v = apic_read(APIC_RRR); | |
1776 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1777 | } | |
1778 | ||
1da177e4 LT |
1779 | v = apic_read(APIC_LDR); |
1780 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1781 | if (!x2apic_enabled()) { |
1782 | v = apic_read(APIC_DFR); | |
1783 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1784 | } | |
1da177e4 LT |
1785 | v = apic_read(APIC_SPIV); |
1786 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1787 | ||
1788 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1789 | print_APIC_bitfield(APIC_ISR); | |
1790 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1791 | print_APIC_bitfield(APIC_TMR); | |
1792 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1793 | print_APIC_bitfield(APIC_IRR); | |
1794 | ||
54168ed7 IM |
1795 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1796 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1797 | apic_write(APIC_ESR, 0); |
54168ed7 | 1798 | |
1da177e4 LT |
1799 | v = apic_read(APIC_ESR); |
1800 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1801 | } | |
1802 | ||
7ab6af7a | 1803 | icr = apic_icr_read(); |
0c425cec IM |
1804 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1805 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1806 | |
1807 | v = apic_read(APIC_LVTT); | |
1808 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1809 | ||
1810 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1811 | v = apic_read(APIC_LVTPC); | |
1812 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1813 | } | |
1814 | v = apic_read(APIC_LVT0); | |
1815 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1816 | v = apic_read(APIC_LVT1); | |
1817 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1818 | ||
1819 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1820 | v = apic_read(APIC_LVTERR); | |
1821 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1822 | } | |
1823 | ||
1824 | v = apic_read(APIC_TMICT); | |
1825 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1826 | v = apic_read(APIC_TMCCT); | |
1827 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1828 | v = apic_read(APIC_TDCR); | |
1829 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1830 | |
1831 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1832 | v = apic_read(APIC_EFEAT); | |
1833 | maxlvt = (v >> 16) & 0xff; | |
1834 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1835 | v = apic_read(APIC_ECTRL); | |
1836 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1837 | for (i = 0; i < maxlvt; i++) { | |
1838 | v = apic_read(APIC_EILVTn(i)); | |
1839 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1840 | } | |
1841 | } | |
1da177e4 LT |
1842 | printk("\n"); |
1843 | } | |
1844 | ||
32f71aff | 1845 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1846 | { |
ffd5aae7 YL |
1847 | int cpu; |
1848 | ||
1849 | preempt_disable(); | |
1850 | for_each_online_cpu(cpu) | |
1851 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1852 | preempt_enable(); | |
1da177e4 LT |
1853 | } |
1854 | ||
32f71aff | 1855 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1856 | { |
1da177e4 LT |
1857 | unsigned int v; |
1858 | unsigned long flags; | |
1859 | ||
1860 | if (apic_verbosity == APIC_QUIET) | |
1861 | return; | |
1862 | ||
1863 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1864 | ||
1865 | spin_lock_irqsave(&i8259A_lock, flags); | |
1866 | ||
1867 | v = inb(0xa1) << 8 | inb(0x21); | |
1868 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1869 | ||
1870 | v = inb(0xa0) << 8 | inb(0x20); | |
1871 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1872 | ||
54168ed7 IM |
1873 | outb(0x0b,0xa0); |
1874 | outb(0x0b,0x20); | |
1da177e4 | 1875 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1876 | outb(0x0a,0xa0); |
1877 | outb(0x0a,0x20); | |
1da177e4 LT |
1878 | |
1879 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1880 | ||
1881 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1882 | ||
1883 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1884 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1885 | } | |
1886 | ||
32f71aff MR |
1887 | __apicdebuginit(int) print_all_ICs(void) |
1888 | { | |
1889 | print_PIC(); | |
4797f6b0 YL |
1890 | |
1891 | /* don't print out if apic is not there */ | |
1892 | if (!cpu_has_apic || disable_apic) | |
1893 | return 0; | |
1894 | ||
32f71aff MR |
1895 | print_all_local_APICs(); |
1896 | print_IO_APIC(); | |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | fs_initcall(print_all_ICs); | |
1902 | ||
1da177e4 | 1903 | |
efa2559f YL |
1904 | /* Where if anywhere is the i8259 connect in external int mode */ |
1905 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1906 | ||
54168ed7 | 1907 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1908 | { |
1909 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1910 | int i8259_apic, i8259_pin; |
54168ed7 | 1911 | int apic; |
1da177e4 LT |
1912 | unsigned long flags; |
1913 | ||
1da177e4 LT |
1914 | /* |
1915 | * The number of IO-APIC IRQ registers (== #pins): | |
1916 | */ | |
fcfd636a | 1917 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1918 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1919 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1920 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1921 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1922 | } | |
54168ed7 | 1923 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1924 | int pin; |
1925 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1926 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1927 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1928 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1929 | |
fcfd636a EB |
1930 | /* If the interrupt line is enabled and in ExtInt mode |
1931 | * I have found the pin where the i8259 is connected. | |
1932 | */ | |
1933 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1934 | ioapic_i8259.apic = apic; | |
1935 | ioapic_i8259.pin = pin; | |
1936 | goto found_i8259; | |
1937 | } | |
1938 | } | |
1939 | } | |
1940 | found_i8259: | |
1941 | /* Look to see what if the MP table has reported the ExtINT */ | |
1942 | /* If we could not find the appropriate pin by looking at the ioapic | |
1943 | * the i8259 probably is not connected the ioapic but give the | |
1944 | * mptable a chance anyway. | |
1945 | */ | |
1946 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1947 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1948 | /* Trust the MP table if nothing is setup in the hardware */ | |
1949 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1950 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1951 | ioapic_i8259.pin = i8259_pin; | |
1952 | ioapic_i8259.apic = i8259_apic; | |
1953 | } | |
1954 | /* Complain if the MP table and the hardware disagree */ | |
1955 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1956 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1957 | { | |
1958 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1959 | } |
1960 | ||
1961 | /* | |
1962 | * Do not trust the IO-APIC being empty at bootup | |
1963 | */ | |
1964 | clear_IO_APIC(); | |
1965 | } | |
1966 | ||
1967 | /* | |
1968 | * Not an __init, needed by the reboot code | |
1969 | */ | |
1970 | void disable_IO_APIC(void) | |
1971 | { | |
1972 | /* | |
1973 | * Clear the IO-APIC before rebooting: | |
1974 | */ | |
1975 | clear_IO_APIC(); | |
1976 | ||
650927ef | 1977 | /* |
0b968d23 | 1978 | * If the i8259 is routed through an IOAPIC |
650927ef | 1979 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1980 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1981 | * |
1982 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1983 | * as virtual wire B is little complex (need to configure both | |
1984 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1985 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1986 | */ |
7c6d9f97 | 1987 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1988 | struct IO_APIC_route_entry entry; |
650927ef EB |
1989 | |
1990 | memset(&entry, 0, sizeof(entry)); | |
1991 | entry.mask = 0; /* Enabled */ | |
1992 | entry.trigger = 0; /* Edge */ | |
1993 | entry.irr = 0; | |
1994 | entry.polarity = 0; /* High */ | |
1995 | entry.delivery_status = 0; | |
1996 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1997 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1998 | entry.vector = 0; |
54168ed7 | 1999 | entry.dest = read_apic_id(); |
650927ef EB |
2000 | |
2001 | /* | |
2002 | * Add it to the IO-APIC irq-routing table: | |
2003 | */ | |
cf4c6a2f | 2004 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2005 | } |
54168ed7 | 2006 | |
7c6d9f97 SS |
2007 | /* |
2008 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2009 | */ | |
3f4c3955 CG |
2010 | if (cpu_has_apic) |
2011 | disconnect_bsp_APIC(!intr_remapping_enabled && | |
2012 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2013 | } |
2014 | ||
54168ed7 | 2015 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2016 | /* |
2017 | * function to set the IO-APIC physical IDs based on the | |
2018 | * values stored in the MPC table. | |
2019 | * | |
2020 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2021 | */ | |
2022 | ||
1da177e4 LT |
2023 | static void __init setup_ioapic_ids_from_mpc(void) |
2024 | { | |
2025 | union IO_APIC_reg_00 reg_00; | |
2026 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2027 | int apic_id; |
1da177e4 LT |
2028 | int i; |
2029 | unsigned char old_id; | |
2030 | unsigned long flags; | |
2031 | ||
a4dbc34d | 2032 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2033 | return; |
d49c4288 | 2034 | |
ca05fea6 NP |
2035 | /* |
2036 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2037 | * no meaning without the serial APIC bus. | |
2038 | */ | |
7c5c1e42 SL |
2039 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2040 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2041 | return; |
1da177e4 LT |
2042 | /* |
2043 | * This is broken; anything with a real cpu count has to | |
2044 | * circumvent this idiocy regardless. | |
2045 | */ | |
d190cb87 | 2046 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2047 | |
2048 | /* | |
2049 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2050 | */ | |
c8d46cf0 | 2051 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2052 | |
2053 | /* Read the register 0 value */ | |
2054 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2055 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2056 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2057 | |
c8d46cf0 | 2058 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2059 | |
c8d46cf0 | 2060 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2061 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2062 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2063 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2064 | reg_00.bits.ID); | |
c8d46cf0 | 2065 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2066 | } |
2067 | ||
1da177e4 LT |
2068 | /* |
2069 | * Sanity check, is the ID really free? Every APIC in a | |
2070 | * system must have a unique ID or we get lots of nice | |
2071 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2072 | */ | |
d1d7cae8 | 2073 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2074 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2075 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2076 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2077 | for (i = 0; i < get_physical_broadcast(); i++) |
2078 | if (!physid_isset(i, phys_id_present_map)) | |
2079 | break; | |
2080 | if (i >= get_physical_broadcast()) | |
2081 | panic("Max APIC ID exceeded!\n"); | |
2082 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2083 | i); | |
2084 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2085 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2086 | } else { |
2087 | physid_mask_t tmp; | |
8058714a | 2088 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2089 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2090 | "phys_id_present_map\n", | |
c8d46cf0 | 2091 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2092 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2093 | } | |
2094 | ||
2095 | ||
2096 | /* | |
2097 | * We need to adjust the IRQ routing table | |
2098 | * if the ID changed. | |
2099 | */ | |
c8d46cf0 | 2100 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2101 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2102 | if (mp_irqs[i].dstapic == old_id) |
2103 | mp_irqs[i].dstapic | |
c8d46cf0 | 2104 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2105 | |
2106 | /* | |
2107 | * Read the right value from the MPC table and | |
2108 | * write it into the ID register. | |
36062448 | 2109 | */ |
1da177e4 LT |
2110 | apic_printk(APIC_VERBOSE, KERN_INFO |
2111 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2112 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2113 | |
c8d46cf0 | 2114 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2115 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2116 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2117 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2118 | |
2119 | /* | |
2120 | * Sanity check | |
2121 | */ | |
2122 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2123 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2124 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2125 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2126 | printk("could not set ID!\n"); |
2127 | else | |
2128 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2129 | } | |
2130 | } | |
54168ed7 | 2131 | #endif |
1da177e4 | 2132 | |
7ce0bcfd | 2133 | int no_timer_check __initdata; |
8542b200 ZA |
2134 | |
2135 | static int __init notimercheck(char *s) | |
2136 | { | |
2137 | no_timer_check = 1; | |
2138 | return 1; | |
2139 | } | |
2140 | __setup("no_timer_check", notimercheck); | |
2141 | ||
1da177e4 LT |
2142 | /* |
2143 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2144 | * about the timer IRQ. We do the following to work around the situation: | |
2145 | * | |
2146 | * - timer IRQ defaults to IO-APIC IRQ | |
2147 | * - if this function detects that timer IRQs are defunct, then we fall | |
2148 | * back to ISA timer IRQs | |
2149 | */ | |
f0a7a5c9 | 2150 | static int __init timer_irq_works(void) |
1da177e4 LT |
2151 | { |
2152 | unsigned long t1 = jiffies; | |
4aae0702 | 2153 | unsigned long flags; |
1da177e4 | 2154 | |
8542b200 ZA |
2155 | if (no_timer_check) |
2156 | return 1; | |
2157 | ||
4aae0702 | 2158 | local_save_flags(flags); |
1da177e4 LT |
2159 | local_irq_enable(); |
2160 | /* Let ten ticks pass... */ | |
2161 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2162 | local_irq_restore(flags); |
1da177e4 LT |
2163 | |
2164 | /* | |
2165 | * Expect a few ticks at least, to be sure some possible | |
2166 | * glue logic does not lock up after one or two first | |
2167 | * ticks in a non-ExtINT mode. Also the local APIC | |
2168 | * might have cached one ExtINT interrupt. Finally, at | |
2169 | * least one tick may be lost due to delays. | |
2170 | */ | |
54168ed7 IM |
2171 | |
2172 | /* jiffies wrap? */ | |
1d16b53e | 2173 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2174 | return 1; |
1da177e4 LT |
2175 | return 0; |
2176 | } | |
2177 | ||
2178 | /* | |
2179 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2180 | * number of pending IRQ events unhandled. These cases are very rare, | |
2181 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2182 | * better to do it this way as thus we do not have to be aware of | |
2183 | * 'pending' interrupts in the IRQ path, except at this point. | |
2184 | */ | |
2185 | /* | |
2186 | * Edge triggered needs to resend any interrupt | |
2187 | * that was delayed but this is now handled in the device | |
2188 | * independent code. | |
2189 | */ | |
2190 | ||
2191 | /* | |
2192 | * Starting up a edge-triggered IO-APIC interrupt is | |
2193 | * nasty - we need to make sure that we get the edge. | |
2194 | * If it is already asserted for some reason, we need | |
2195 | * return 1 to indicate that is was pending. | |
2196 | * | |
2197 | * This is not complete - we should be able to fake | |
2198 | * an edge even if it isn't on the 8259A... | |
2199 | */ | |
54168ed7 | 2200 | |
f5b9ed7a | 2201 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2202 | { |
2203 | int was_pending = 0; | |
2204 | unsigned long flags; | |
0b8f1efa | 2205 | struct irq_cfg *cfg; |
1da177e4 LT |
2206 | |
2207 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2208 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2209 | disable_8259A_irq(irq); |
2210 | if (i8259A_irq_pending(irq)) | |
2211 | was_pending = 1; | |
2212 | } | |
0b8f1efa | 2213 | cfg = irq_cfg(irq); |
3145e941 | 2214 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2215 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2216 | ||
2217 | return was_pending; | |
2218 | } | |
2219 | ||
54168ed7 | 2220 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2221 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2222 | { |
54168ed7 IM |
2223 | |
2224 | struct irq_cfg *cfg = irq_cfg(irq); | |
2225 | unsigned long flags; | |
2226 | ||
2227 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2228 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2229 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2230 | |
2231 | return 1; | |
2232 | } | |
54168ed7 IM |
2233 | #else |
2234 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2235 | { |
dac5f412 | 2236 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2237 | |
d6c88a50 | 2238 | return 1; |
54168ed7 IM |
2239 | } |
2240 | #endif | |
497c9a19 | 2241 | |
54168ed7 IM |
2242 | /* |
2243 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2244 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2245 | * handled with the level-triggered descriptor, but that one has slightly | |
2246 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2247 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2248 | * races. | |
2249 | */ | |
497c9a19 | 2250 | |
54168ed7 | 2251 | #ifdef CONFIG_SMP |
e85abf8f GH |
2252 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2253 | { | |
2254 | cpumask_var_t cleanup_mask; | |
2255 | ||
2256 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2257 | unsigned int i; | |
2258 | cfg->move_cleanup_count = 0; | |
2259 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2260 | cfg->move_cleanup_count++; | |
2261 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2262 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2263 | } else { | |
2264 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2265 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2266 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2267 | free_cpumask_var(cleanup_mask); | |
2268 | } | |
2269 | cfg->move_in_progress = 0; | |
2270 | } | |
2271 | ||
4420471f | 2272 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2273 | { |
2274 | int apic, pin; | |
2275 | struct irq_pin_list *entry; | |
2276 | u8 vector = cfg->vector; | |
2277 | ||
2278 | entry = cfg->irq_2_pin; | |
2279 | for (;;) { | |
2280 | unsigned int reg; | |
2281 | ||
2282 | if (!entry) | |
2283 | break; | |
2284 | ||
2285 | apic = entry->apic; | |
2286 | pin = entry->pin; | |
2287 | /* | |
2288 | * With interrupt-remapping, destination information comes | |
2289 | * from interrupt-remapping table entry. | |
2290 | */ | |
2291 | if (!irq_remapped(irq)) | |
2292 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2293 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2294 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2295 | reg |= vector; | |
2296 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2297 | if (!entry->next) | |
2298 | break; | |
2299 | entry = entry->next; | |
2300 | } | |
2301 | } | |
2302 | ||
4420471f IM |
2303 | static int |
2304 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2305 | ||
e85abf8f GH |
2306 | /* |
2307 | * Either sets desc->affinity to a valid value, and returns | |
2308 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2309 | * leaves desc->affinity untouched. | |
2310 | */ | |
2311 | static unsigned int | |
2312 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2313 | { | |
2314 | struct irq_cfg *cfg; | |
2315 | unsigned int irq; | |
2316 | ||
2317 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2318 | return BAD_APICID; | |
2319 | ||
2320 | irq = desc->irq; | |
2321 | cfg = desc->chip_data; | |
2322 | if (assign_irq_vector(irq, cfg, mask)) | |
2323 | return BAD_APICID; | |
2324 | ||
e85abf8f GH |
2325 | cpumask_copy(desc->affinity, mask); |
2326 | ||
2327 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2328 | } | |
2329 | ||
4420471f | 2330 | static int |
e85abf8f GH |
2331 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2332 | { | |
2333 | struct irq_cfg *cfg; | |
2334 | unsigned long flags; | |
2335 | unsigned int dest; | |
2336 | unsigned int irq; | |
4420471f | 2337 | int ret = -1; |
e85abf8f GH |
2338 | |
2339 | irq = desc->irq; | |
2340 | cfg = desc->chip_data; | |
2341 | ||
2342 | spin_lock_irqsave(&ioapic_lock, flags); | |
2343 | dest = set_desc_affinity(desc, mask); | |
2344 | if (dest != BAD_APICID) { | |
2345 | /* Only the high 8 bits are valid. */ | |
2346 | dest = SET_APIC_LOGICAL_ID(dest); | |
2347 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2348 | ret = 0; |
e85abf8f GH |
2349 | } |
2350 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2351 | |
2352 | return ret; | |
e85abf8f GH |
2353 | } |
2354 | ||
4420471f | 2355 | static int |
e85abf8f GH |
2356 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2357 | { | |
2358 | struct irq_desc *desc; | |
2359 | ||
2360 | desc = irq_to_desc(irq); | |
2361 | ||
4420471f | 2362 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2363 | } |
497c9a19 | 2364 | |
54168ed7 | 2365 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2366 | |
54168ed7 IM |
2367 | /* |
2368 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2369 | * | |
0280f7c4 SS |
2370 | * For both level and edge triggered, irq migration is a simple atomic |
2371 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2372 | * |
0280f7c4 SS |
2373 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2374 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2375 | * Real vector that is used for interrupting cpu will be coming from | |
2376 | * the interrupt-remapping table entry. | |
54168ed7 | 2377 | */ |
d5dedd45 | 2378 | static int |
e7986739 | 2379 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2380 | { |
54168ed7 | 2381 | struct irq_cfg *cfg; |
54168ed7 | 2382 | struct irte irte; |
54168ed7 | 2383 | unsigned int dest; |
3145e941 | 2384 | unsigned int irq; |
d5dedd45 | 2385 | int ret = -1; |
497c9a19 | 2386 | |
22f65d31 | 2387 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2388 | return ret; |
497c9a19 | 2389 | |
3145e941 | 2390 | irq = desc->irq; |
54168ed7 | 2391 | if (get_irte(irq, &irte)) |
d5dedd45 | 2392 | return ret; |
497c9a19 | 2393 | |
3145e941 YL |
2394 | cfg = desc->chip_data; |
2395 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2396 | return ret; |
54168ed7 | 2397 | |
debccb3e | 2398 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2399 | |
54168ed7 IM |
2400 | irte.vector = cfg->vector; |
2401 | irte.dest_id = IRTE_DEST(dest); | |
2402 | ||
2403 | /* | |
2404 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2405 | */ | |
2406 | modify_irte(irq, &irte); | |
2407 | ||
22f65d31 MT |
2408 | if (cfg->move_in_progress) |
2409 | send_cleanup_vector(cfg); | |
54168ed7 | 2410 | |
7f7ace0c | 2411 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2412 | |
2413 | return 0; | |
54168ed7 IM |
2414 | } |
2415 | ||
54168ed7 IM |
2416 | /* |
2417 | * Migrates the IRQ destination in the process context. | |
2418 | */ | |
d5dedd45 | 2419 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2420 | const struct cpumask *mask) |
54168ed7 | 2421 | { |
d5dedd45 | 2422 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2423 | } |
d5dedd45 | 2424 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2425 | const struct cpumask *mask) |
3145e941 YL |
2426 | { |
2427 | struct irq_desc *desc = irq_to_desc(irq); | |
2428 | ||
d5dedd45 | 2429 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2430 | } |
29b61be6 | 2431 | #else |
d5dedd45 | 2432 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2433 | const struct cpumask *mask) |
2434 | { | |
d5dedd45 | 2435 | return 0; |
29b61be6 | 2436 | } |
54168ed7 IM |
2437 | #endif |
2438 | ||
2439 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2440 | { | |
2441 | unsigned vector, me; | |
8f2466f4 | 2442 | |
54168ed7 | 2443 | ack_APIC_irq(); |
54168ed7 | 2444 | exit_idle(); |
54168ed7 IM |
2445 | irq_enter(); |
2446 | ||
2447 | me = smp_processor_id(); | |
2448 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2449 | unsigned int irq; | |
68a8ca59 | 2450 | unsigned int irr; |
54168ed7 IM |
2451 | struct irq_desc *desc; |
2452 | struct irq_cfg *cfg; | |
2453 | irq = __get_cpu_var(vector_irq)[vector]; | |
2454 | ||
0b8f1efa YL |
2455 | if (irq == -1) |
2456 | continue; | |
2457 | ||
54168ed7 IM |
2458 | desc = irq_to_desc(irq); |
2459 | if (!desc) | |
2460 | continue; | |
2461 | ||
2462 | cfg = irq_cfg(irq); | |
2463 | spin_lock(&desc->lock); | |
2464 | if (!cfg->move_cleanup_count) | |
2465 | goto unlock; | |
2466 | ||
22f65d31 | 2467 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2468 | goto unlock; |
2469 | ||
68a8ca59 SS |
2470 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2471 | /* | |
2472 | * Check if the vector that needs to be cleanedup is | |
2473 | * registered at the cpu's IRR. If so, then this is not | |
2474 | * the best time to clean it up. Lets clean it up in the | |
2475 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2476 | * to myself. | |
2477 | */ | |
2478 | if (irr & (1 << (vector % 32))) { | |
2479 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2480 | goto unlock; | |
2481 | } | |
54168ed7 IM |
2482 | __get_cpu_var(vector_irq)[vector] = -1; |
2483 | cfg->move_cleanup_count--; | |
2484 | unlock: | |
2485 | spin_unlock(&desc->lock); | |
2486 | } | |
2487 | ||
2488 | irq_exit(); | |
2489 | } | |
2490 | ||
3145e941 | 2491 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2492 | { |
3145e941 YL |
2493 | struct irq_desc *desc = *descp; |
2494 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2495 | unsigned vector, me; |
2496 | ||
fcef5911 | 2497 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2498 | return; |
2499 | ||
2500 | vector = ~get_irq_regs()->orig_ax; | |
2501 | me = smp_processor_id(); | |
10b888d6 | 2502 | |
fcef5911 | 2503 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2504 | send_cleanup_vector(cfg); |
497c9a19 YL |
2505 | } |
2506 | #else | |
3145e941 | 2507 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2508 | #endif |
3145e941 | 2509 | |
1d025192 YL |
2510 | static void ack_apic_edge(unsigned int irq) |
2511 | { | |
3145e941 YL |
2512 | struct irq_desc *desc = irq_to_desc(irq); |
2513 | ||
2514 | irq_complete_move(&desc); | |
1d025192 YL |
2515 | move_native_irq(irq); |
2516 | ack_APIC_irq(); | |
2517 | } | |
2518 | ||
3eb2cce8 | 2519 | atomic_t irq_mis_count; |
3eb2cce8 | 2520 | |
047c8fdb YL |
2521 | static void ack_apic_level(unsigned int irq) |
2522 | { | |
3145e941 YL |
2523 | struct irq_desc *desc = irq_to_desc(irq); |
2524 | ||
3eb2cce8 YL |
2525 | #ifdef CONFIG_X86_32 |
2526 | unsigned long v; | |
2527 | int i; | |
2528 | #endif | |
3145e941 | 2529 | struct irq_cfg *cfg; |
54168ed7 | 2530 | int do_unmask_irq = 0; |
047c8fdb | 2531 | |
3145e941 | 2532 | irq_complete_move(&desc); |
047c8fdb | 2533 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2534 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2535 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2536 | do_unmask_irq = 1; |
3145e941 | 2537 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2538 | } |
047c8fdb YL |
2539 | #endif |
2540 | ||
3eb2cce8 YL |
2541 | #ifdef CONFIG_X86_32 |
2542 | /* | |
2543 | * It appears there is an erratum which affects at least version 0x11 | |
2544 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2545 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2546 | * erroneously delivered as edge-triggered one but the respective IRR | |
2547 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2548 | * message but it will never arrive and further interrupts are blocked | |
2549 | * from the source. The exact reason is so far unknown, but the | |
2550 | * phenomenon was observed when two consecutive interrupt requests | |
2551 | * from a given source get delivered to the same CPU and the source is | |
2552 | * temporarily disabled in between. | |
2553 | * | |
2554 | * A workaround is to simulate an EOI message manually. We achieve it | |
2555 | * by setting the trigger mode to edge and then to level when the edge | |
2556 | * trigger mode gets detected in the TMR of a local APIC for a | |
2557 | * level-triggered interrupt. We mask the source for the time of the | |
2558 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2559 | * The idea is from Manfred Spraul. --macro | |
2560 | */ | |
3145e941 YL |
2561 | cfg = desc->chip_data; |
2562 | i = cfg->vector; | |
3eb2cce8 YL |
2563 | |
2564 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2565 | #endif | |
2566 | ||
54168ed7 IM |
2567 | /* |
2568 | * We must acknowledge the irq before we move it or the acknowledge will | |
2569 | * not propagate properly. | |
2570 | */ | |
2571 | ack_APIC_irq(); | |
2572 | ||
2573 | /* Now we can move and renable the irq */ | |
2574 | if (unlikely(do_unmask_irq)) { | |
2575 | /* Only migrate the irq if the ack has been received. | |
2576 | * | |
2577 | * On rare occasions the broadcast level triggered ack gets | |
2578 | * delayed going to ioapics, and if we reprogram the | |
2579 | * vector while Remote IRR is still set the irq will never | |
2580 | * fire again. | |
2581 | * | |
2582 | * To prevent this scenario we read the Remote IRR bit | |
2583 | * of the ioapic. This has two effects. | |
2584 | * - On any sane system the read of the ioapic will | |
2585 | * flush writes (and acks) going to the ioapic from | |
2586 | * this cpu. | |
2587 | * - We get to see if the ACK has actually been delivered. | |
2588 | * | |
2589 | * Based on failed experiments of reprogramming the | |
2590 | * ioapic entry from outside of irq context starting | |
2591 | * with masking the ioapic entry and then polling until | |
2592 | * Remote IRR was clear before reprogramming the | |
2593 | * ioapic I don't trust the Remote IRR bit to be | |
2594 | * completey accurate. | |
2595 | * | |
2596 | * However there appears to be no other way to plug | |
2597 | * this race, so if the Remote IRR bit is not | |
2598 | * accurate and is causing problems then it is a hardware bug | |
2599 | * and you can go talk to the chipset vendor about it. | |
2600 | */ | |
3145e941 YL |
2601 | cfg = desc->chip_data; |
2602 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2603 | move_masked_irq(irq); |
3145e941 | 2604 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2605 | } |
1d025192 | 2606 | |
3eb2cce8 | 2607 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2608 | if (!(v & (1 << (i & 0x1f)))) { |
2609 | atomic_inc(&irq_mis_count); | |
2610 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2611 | __mask_and_edge_IO_APIC_irq(cfg); |
2612 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2613 | spin_unlock(&ioapic_lock); |
2614 | } | |
047c8fdb | 2615 | #endif |
3eb2cce8 | 2616 | } |
1d025192 | 2617 | |
d0b03bd1 | 2618 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2619 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2620 | { | |
2621 | int apic, pin; | |
2622 | struct irq_pin_list *entry; | |
2623 | ||
2624 | entry = cfg->irq_2_pin; | |
2625 | for (;;) { | |
2626 | ||
2627 | if (!entry) | |
2628 | break; | |
2629 | ||
2630 | apic = entry->apic; | |
2631 | pin = entry->pin; | |
2632 | io_apic_eoi(apic, pin); | |
2633 | entry = entry->next; | |
2634 | } | |
2635 | } | |
2636 | ||
2637 | static void | |
2638 | eoi_ioapic_irq(struct irq_desc *desc) | |
2639 | { | |
2640 | struct irq_cfg *cfg; | |
2641 | unsigned long flags; | |
2642 | unsigned int irq; | |
2643 | ||
2644 | irq = desc->irq; | |
2645 | cfg = desc->chip_data; | |
2646 | ||
2647 | spin_lock_irqsave(&ioapic_lock, flags); | |
2648 | __eoi_ioapic_irq(irq, cfg); | |
2649 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2650 | } | |
2651 | ||
d0b03bd1 HW |
2652 | static void ir_ack_apic_edge(unsigned int irq) |
2653 | { | |
5d0ae2db | 2654 | ack_APIC_irq(); |
d0b03bd1 HW |
2655 | } |
2656 | ||
2657 | static void ir_ack_apic_level(unsigned int irq) | |
2658 | { | |
5d0ae2db WH |
2659 | struct irq_desc *desc = irq_to_desc(irq); |
2660 | ||
2661 | ack_APIC_irq(); | |
2662 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2663 | } |
2664 | #endif /* CONFIG_INTR_REMAP */ | |
2665 | ||
f5b9ed7a | 2666 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2667 | .name = "IO-APIC", |
2668 | .startup = startup_ioapic_irq, | |
2669 | .mask = mask_IO_APIC_irq, | |
2670 | .unmask = unmask_IO_APIC_irq, | |
2671 | .ack = ack_apic_edge, | |
2672 | .eoi = ack_apic_level, | |
54d5d424 | 2673 | #ifdef CONFIG_SMP |
d6c88a50 | 2674 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2675 | #endif |
ace80ab7 | 2676 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2677 | }; |
2678 | ||
54168ed7 | 2679 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2680 | .name = "IR-IO-APIC", |
2681 | .startup = startup_ioapic_irq, | |
2682 | .mask = mask_IO_APIC_irq, | |
2683 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2684 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2685 | .ack = ir_ack_apic_edge, |
2686 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2687 | #ifdef CONFIG_SMP |
d6c88a50 | 2688 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2689 | #endif |
54168ed7 IM |
2690 | #endif |
2691 | .retrigger = ioapic_retrigger_irq, | |
2692 | }; | |
1da177e4 LT |
2693 | |
2694 | static inline void init_IO_APIC_traps(void) | |
2695 | { | |
2696 | int irq; | |
08678b08 | 2697 | struct irq_desc *desc; |
da51a821 | 2698 | struct irq_cfg *cfg; |
1da177e4 LT |
2699 | |
2700 | /* | |
2701 | * NOTE! The local APIC isn't very good at handling | |
2702 | * multiple interrupts at the same interrupt level. | |
2703 | * As the interrupt level is determined by taking the | |
2704 | * vector number and shifting that right by 4, we | |
2705 | * want to spread these out a bit so that they don't | |
2706 | * all fall in the same interrupt level. | |
2707 | * | |
2708 | * Also, we've got to be careful not to trash gate | |
2709 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2710 | */ | |
0b8f1efa | 2711 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2712 | cfg = desc->chip_data; |
2713 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2714 | /* |
2715 | * Hmm.. We don't have an entry for this, | |
2716 | * so default to an old-fashioned 8259 | |
2717 | * interrupt if we can.. | |
2718 | */ | |
99d093d1 | 2719 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2720 | make_8259A_irq(irq); |
0b8f1efa | 2721 | else |
1da177e4 | 2722 | /* Strange. Oh, well.. */ |
08678b08 | 2723 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2724 | } |
2725 | } | |
2726 | } | |
2727 | ||
f5b9ed7a IM |
2728 | /* |
2729 | * The local APIC irq-chip implementation: | |
2730 | */ | |
1da177e4 | 2731 | |
36062448 | 2732 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2733 | { |
2734 | unsigned long v; | |
2735 | ||
2736 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2737 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2738 | } |
2739 | ||
36062448 | 2740 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2741 | { |
f5b9ed7a | 2742 | unsigned long v; |
1da177e4 | 2743 | |
f5b9ed7a | 2744 | v = apic_read(APIC_LVT0); |
593f4a78 | 2745 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2746 | } |
1da177e4 | 2747 | |
3145e941 | 2748 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2749 | { |
2750 | ack_APIC_irq(); | |
2751 | } | |
2752 | ||
f5b9ed7a | 2753 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2754 | .name = "local-APIC", |
f5b9ed7a IM |
2755 | .mask = mask_lapic_irq, |
2756 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2757 | .ack = ack_lapic_irq, |
1da177e4 LT |
2758 | }; |
2759 | ||
3145e941 | 2760 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2761 | { |
08678b08 | 2762 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2763 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2764 | "edge"); | |
c88ac1df MR |
2765 | } |
2766 | ||
e9427101 | 2767 | static void __init setup_nmi(void) |
1da177e4 LT |
2768 | { |
2769 | /* | |
36062448 | 2770 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2771 | * We put the 8259A master into AEOI mode and |
2772 | * unmask on all local APICs LVT0 as NMI. | |
2773 | * | |
2774 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2775 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2776 | * the NMI handler or the timer interrupt. | |
36062448 | 2777 | */ |
1da177e4 LT |
2778 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2779 | ||
e9427101 | 2780 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2781 | |
2782 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2783 | } | |
2784 | ||
2785 | /* | |
2786 | * This looks a bit hackish but it's about the only one way of sending | |
2787 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2788 | * not support the ExtINT mode, unfortunately. We need to send these | |
2789 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2790 | * 8259A interrupt line asserted until INTA. --macro | |
2791 | */ | |
28acf285 | 2792 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2793 | { |
fcfd636a | 2794 | int apic, pin, i; |
1da177e4 LT |
2795 | struct IO_APIC_route_entry entry0, entry1; |
2796 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2797 | |
fcfd636a | 2798 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2799 | if (pin == -1) { |
2800 | WARN_ON_ONCE(1); | |
2801 | return; | |
2802 | } | |
fcfd636a | 2803 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2804 | if (apic == -1) { |
2805 | WARN_ON_ONCE(1); | |
1da177e4 | 2806 | return; |
956fb531 | 2807 | } |
1da177e4 | 2808 | |
cf4c6a2f | 2809 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2810 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2811 | |
2812 | memset(&entry1, 0, sizeof(entry1)); | |
2813 | ||
2814 | entry1.dest_mode = 0; /* physical delivery */ | |
2815 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2816 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2817 | entry1.delivery_mode = dest_ExtINT; |
2818 | entry1.polarity = entry0.polarity; | |
2819 | entry1.trigger = 0; | |
2820 | entry1.vector = 0; | |
2821 | ||
cf4c6a2f | 2822 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2823 | |
2824 | save_control = CMOS_READ(RTC_CONTROL); | |
2825 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2826 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2827 | RTC_FREQ_SELECT); | |
2828 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2829 | ||
2830 | i = 100; | |
2831 | while (i-- > 0) { | |
2832 | mdelay(10); | |
2833 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2834 | i -= 10; | |
2835 | } | |
2836 | ||
2837 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2838 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2839 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2840 | |
cf4c6a2f | 2841 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2842 | } |
2843 | ||
efa2559f | 2844 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2845 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2846 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2847 | { |
2848 | disable_timer_pin_1 = 1; | |
2849 | return 0; | |
2850 | } | |
54168ed7 | 2851 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2852 | |
2853 | int timer_through_8259 __initdata; | |
2854 | ||
1da177e4 LT |
2855 | /* |
2856 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2857 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2858 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2859 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2860 | * |
2861 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2862 | */ |
8542b200 | 2863 | static inline void __init check_timer(void) |
1da177e4 | 2864 | { |
3145e941 YL |
2865 | struct irq_desc *desc = irq_to_desc(0); |
2866 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2867 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2868 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2869 | unsigned long flags; |
047c8fdb | 2870 | int no_pin1 = 0; |
4aae0702 IM |
2871 | |
2872 | local_irq_save(flags); | |
d4d25dec | 2873 | |
1da177e4 LT |
2874 | /* |
2875 | * get/set the timer IRQ vector: | |
2876 | */ | |
2877 | disable_8259A_irq(0); | |
fe402e1f | 2878 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2879 | |
2880 | /* | |
d11d5794 MR |
2881 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2882 | * wire has to be disabled in the local APIC. Also | |
2883 | * timer interrupts need to be acknowledged manually in | |
2884 | * the 8259A for the i82489DX when using the NMI | |
2885 | * watchdog as that APIC treats NMIs as level-triggered. | |
2886 | * The AEOI mode will finish them in the 8259A | |
2887 | * automatically. | |
1da177e4 | 2888 | */ |
593f4a78 | 2889 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2890 | init_8259A(1); |
54168ed7 | 2891 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2892 | { |
2893 | unsigned int ver; | |
2894 | ||
2895 | ver = apic_read(APIC_LVR); | |
2896 | ver = GET_APIC_VERSION(ver); | |
2897 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2898 | } | |
54168ed7 | 2899 | #endif |
1da177e4 | 2900 | |
fcfd636a EB |
2901 | pin1 = find_isa_irq_pin(0, mp_INT); |
2902 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2903 | pin2 = ioapic_i8259.pin; | |
2904 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2905 | |
49a66a0b MR |
2906 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2907 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2908 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2909 | |
691874fa MR |
2910 | /* |
2911 | * Some BIOS writers are clueless and report the ExtINTA | |
2912 | * I/O APIC input from the cascaded 8259A as the timer | |
2913 | * interrupt input. So just in case, if only one pin | |
2914 | * was found above, try it both directly and through the | |
2915 | * 8259A. | |
2916 | */ | |
2917 | if (pin1 == -1) { | |
54168ed7 IM |
2918 | if (intr_remapping_enabled) |
2919 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2920 | pin1 = pin2; |
2921 | apic1 = apic2; | |
2922 | no_pin1 = 1; | |
2923 | } else if (pin2 == -1) { | |
2924 | pin2 = pin1; | |
2925 | apic2 = apic1; | |
2926 | } | |
2927 | ||
1da177e4 LT |
2928 | if (pin1 != -1) { |
2929 | /* | |
2930 | * Ok, does IRQ0 through the IOAPIC work? | |
2931 | */ | |
691874fa | 2932 | if (no_pin1) { |
85ac16d0 | 2933 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2934 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2935 | } else { |
2936 | /* for edge trigger, setup_IO_APIC_irq already | |
2937 | * leave it unmasked. | |
2938 | * so only need to unmask if it is level-trigger | |
2939 | * do we really have level trigger timer? | |
2940 | */ | |
2941 | int idx; | |
2942 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2943 | if (idx != -1 && irq_trigger(idx)) | |
2944 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2945 | } |
1da177e4 LT |
2946 | if (timer_irq_works()) { |
2947 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2948 | setup_nmi(); |
2949 | enable_8259A_irq(0); | |
1da177e4 | 2950 | } |
66759a01 CE |
2951 | if (disable_timer_pin_1 > 0) |
2952 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2953 | goto out; |
1da177e4 | 2954 | } |
54168ed7 IM |
2955 | if (intr_remapping_enabled) |
2956 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2957 | local_irq_disable(); |
fcfd636a | 2958 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2959 | if (!no_pin1) |
49a66a0b MR |
2960 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2961 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2962 | |
49a66a0b MR |
2963 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2964 | "(IRQ0) through the 8259A ...\n"); | |
2965 | apic_printk(APIC_QUIET, KERN_INFO | |
2966 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2967 | /* |
2968 | * legacy devices should be connected to IO APIC #0 | |
2969 | */ | |
85ac16d0 | 2970 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2971 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2972 | enable_8259A_irq(0); |
1da177e4 | 2973 | if (timer_irq_works()) { |
49a66a0b | 2974 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2975 | timer_through_8259 = 1; |
1da177e4 | 2976 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2977 | disable_8259A_irq(0); |
1da177e4 | 2978 | setup_nmi(); |
60134ebe | 2979 | enable_8259A_irq(0); |
1da177e4 | 2980 | } |
4aae0702 | 2981 | goto out; |
1da177e4 LT |
2982 | } |
2983 | /* | |
2984 | * Cleanup, just in case ... | |
2985 | */ | |
f72dccac | 2986 | local_irq_disable(); |
ecd29476 | 2987 | disable_8259A_irq(0); |
fcfd636a | 2988 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2989 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2990 | } |
1da177e4 LT |
2991 | |
2992 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2993 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2994 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2995 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2996 | } |
54168ed7 | 2997 | #ifdef CONFIG_X86_32 |
d11d5794 | 2998 | timer_ack = 0; |
54168ed7 | 2999 | #endif |
1da177e4 | 3000 | |
49a66a0b MR |
3001 | apic_printk(APIC_QUIET, KERN_INFO |
3002 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3003 | |
3145e941 | 3004 | lapic_register_intr(0, desc); |
497c9a19 | 3005 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3006 | enable_8259A_irq(0); |
3007 | ||
3008 | if (timer_irq_works()) { | |
49a66a0b | 3009 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3010 | goto out; |
1da177e4 | 3011 | } |
f72dccac | 3012 | local_irq_disable(); |
e67465f1 | 3013 | disable_8259A_irq(0); |
497c9a19 | 3014 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3015 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3016 | |
49a66a0b MR |
3017 | apic_printk(APIC_QUIET, KERN_INFO |
3018 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3019 | |
1da177e4 LT |
3020 | init_8259A(0); |
3021 | make_8259A_irq(0); | |
593f4a78 | 3022 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3023 | |
3024 | unlock_ExtINT_logic(); | |
3025 | ||
3026 | if (timer_irq_works()) { | |
49a66a0b | 3027 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3028 | goto out; |
1da177e4 | 3029 | } |
f72dccac | 3030 | local_irq_disable(); |
49a66a0b | 3031 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3032 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3033 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3034 | out: |
3035 | local_irq_restore(flags); | |
1da177e4 LT |
3036 | } |
3037 | ||
3038 | /* | |
af174783 MR |
3039 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3040 | * to devices. However there may be an I/O APIC pin available for | |
3041 | * this interrupt regardless. The pin may be left unconnected, but | |
3042 | * typically it will be reused as an ExtINT cascade interrupt for | |
3043 | * the master 8259A. In the MPS case such a pin will normally be | |
3044 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3045 | * there is no provision for ExtINT interrupts, and in the absence | |
3046 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3047 | * interrupt, that is edge-triggered and unmasked by default. We | |
3048 | * used to do this, but it caused problems on some systems because | |
3049 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3050 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3051 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3052 | * the I/O APIC in all cases now. No actual device should request | |
3053 | * it anyway. --macro | |
1da177e4 LT |
3054 | */ |
3055 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3056 | ||
3057 | void __init setup_IO_APIC(void) | |
3058 | { | |
54168ed7 | 3059 | |
54168ed7 IM |
3060 | /* |
3061 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3062 | */ | |
1da177e4 | 3063 | |
af174783 | 3064 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3065 | |
54168ed7 | 3066 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3067 | /* |
54168ed7 IM |
3068 | * Set up IO-APIC IRQ routing. |
3069 | */ | |
3070 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3071 | if (!acpi_ioapic) |
3072 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3073 | #endif |
1da177e4 LT |
3074 | sync_Arb_IDs(); |
3075 | setup_IO_APIC_irqs(); | |
3076 | init_IO_APIC_traps(); | |
1e4c85f9 | 3077 | check_timer(); |
1da177e4 LT |
3078 | } |
3079 | ||
3080 | /* | |
54168ed7 IM |
3081 | * Called after all the initialization is done. If we didnt find any |
3082 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3083 | */ |
36062448 | 3084 | |
1da177e4 LT |
3085 | static int __init io_apic_bug_finalize(void) |
3086 | { | |
d6c88a50 TG |
3087 | if (sis_apic_bug == -1) |
3088 | sis_apic_bug = 0; | |
3089 | return 0; | |
1da177e4 LT |
3090 | } |
3091 | ||
3092 | late_initcall(io_apic_bug_finalize); | |
3093 | ||
3094 | struct sysfs_ioapic_data { | |
3095 | struct sys_device dev; | |
3096 | struct IO_APIC_route_entry entry[0]; | |
3097 | }; | |
54168ed7 | 3098 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3099 | |
438510f6 | 3100 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3101 | { |
3102 | struct IO_APIC_route_entry *entry; | |
3103 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3104 | int i; |
36062448 | 3105 | |
1da177e4 LT |
3106 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3107 | entry = data->entry; | |
54168ed7 IM |
3108 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3109 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3110 | |
3111 | return 0; | |
3112 | } | |
3113 | ||
3114 | static int ioapic_resume(struct sys_device *dev) | |
3115 | { | |
3116 | struct IO_APIC_route_entry *entry; | |
3117 | struct sysfs_ioapic_data *data; | |
3118 | unsigned long flags; | |
3119 | union IO_APIC_reg_00 reg_00; | |
3120 | int i; | |
36062448 | 3121 | |
1da177e4 LT |
3122 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3123 | entry = data->entry; | |
3124 | ||
3125 | spin_lock_irqsave(&ioapic_lock, flags); | |
3126 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3127 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3128 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3129 | io_apic_write(dev->id, 0, reg_00.raw); |
3130 | } | |
1da177e4 | 3131 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3132 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3133 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3134 | |
3135 | return 0; | |
3136 | } | |
3137 | ||
3138 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3139 | .name = "ioapic", |
1da177e4 LT |
3140 | .suspend = ioapic_suspend, |
3141 | .resume = ioapic_resume, | |
3142 | }; | |
3143 | ||
3144 | static int __init ioapic_init_sysfs(void) | |
3145 | { | |
54168ed7 IM |
3146 | struct sys_device * dev; |
3147 | int i, size, error; | |
1da177e4 LT |
3148 | |
3149 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3150 | if (error) | |
3151 | return error; | |
3152 | ||
54168ed7 | 3153 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3154 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3155 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3156 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3157 | if (!mp_ioapic_data[i]) { |
3158 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3159 | continue; | |
3160 | } | |
1da177e4 | 3161 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3162 | dev->id = i; |
1da177e4 LT |
3163 | dev->cls = &ioapic_sysdev_class; |
3164 | error = sysdev_register(dev); | |
3165 | if (error) { | |
3166 | kfree(mp_ioapic_data[i]); | |
3167 | mp_ioapic_data[i] = NULL; | |
3168 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3169 | continue; | |
3170 | } | |
3171 | } | |
3172 | ||
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | device_initcall(ioapic_init_sysfs); | |
3177 | ||
abcaa2b8 | 3178 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3179 | /* |
95d77884 | 3180 | * Dynamic irq allocate and deallocation |
3fc471ed | 3181 | */ |
d047f53a | 3182 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3183 | { |
ace80ab7 | 3184 | /* Allocate an unused irq */ |
54168ed7 IM |
3185 | unsigned int irq; |
3186 | unsigned int new; | |
3fc471ed | 3187 | unsigned long flags; |
0b8f1efa | 3188 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3189 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3190 | |
3191 | irq = 0; | |
abcaa2b8 YL |
3192 | if (irq_want < nr_irqs_gsi) |
3193 | irq_want = nr_irqs_gsi; | |
3194 | ||
ace80ab7 | 3195 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3196 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3197 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3198 | if (!desc_new) { |
3199 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3200 | continue; |
0b8f1efa YL |
3201 | } |
3202 | cfg_new = desc_new->chip_data; | |
3203 | ||
3204 | if (cfg_new->vector != 0) | |
ace80ab7 | 3205 | continue; |
d047f53a | 3206 | |
15e957d0 | 3207 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3208 | |
fe402e1f | 3209 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3210 | irq = new; |
3211 | break; | |
3212 | } | |
3213 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3214 | |
199751d7 | 3215 | if (irq > 0) { |
3fc471ed | 3216 | dynamic_irq_init(irq); |
0b8f1efa YL |
3217 | /* restore it, in case dynamic_irq_init clear it */ |
3218 | if (desc_new) | |
3219 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3220 | } |
3221 | return irq; | |
3222 | } | |
3223 | ||
199751d7 YL |
3224 | int create_irq(void) |
3225 | { | |
d047f53a | 3226 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3227 | unsigned int irq_want; |
54168ed7 IM |
3228 | int irq; |
3229 | ||
be5d5350 | 3230 | irq_want = nr_irqs_gsi; |
d047f53a | 3231 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3232 | |
3233 | if (irq == 0) | |
3234 | irq = -1; | |
3235 | ||
3236 | return irq; | |
199751d7 YL |
3237 | } |
3238 | ||
3fc471ed EB |
3239 | void destroy_irq(unsigned int irq) |
3240 | { | |
3241 | unsigned long flags; | |
0b8f1efa YL |
3242 | struct irq_cfg *cfg; |
3243 | struct irq_desc *desc; | |
3fc471ed | 3244 | |
0b8f1efa YL |
3245 | /* store it, in case dynamic_irq_cleanup clear it */ |
3246 | desc = irq_to_desc(irq); | |
3247 | cfg = desc->chip_data; | |
3fc471ed | 3248 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3249 | /* connect back irq_cfg */ |
3250 | if (desc) | |
3251 | desc->chip_data = cfg; | |
3fc471ed | 3252 | |
54168ed7 | 3253 | free_irte(irq); |
3fc471ed | 3254 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3255 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3256 | spin_unlock_irqrestore(&vector_lock, flags); |
3257 | } | |
3fc471ed | 3258 | |
2d3fcc1c | 3259 | /* |
27b46d76 | 3260 | * MSI message composition |
2d3fcc1c EB |
3261 | */ |
3262 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3263 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3264 | { |
497c9a19 YL |
3265 | struct irq_cfg *cfg; |
3266 | int err; | |
2d3fcc1c EB |
3267 | unsigned dest; |
3268 | ||
f1182638 JB |
3269 | if (disable_apic) |
3270 | return -ENXIO; | |
3271 | ||
3145e941 | 3272 | cfg = irq_cfg(irq); |
fe402e1f | 3273 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3274 | if (err) |
3275 | return err; | |
2d3fcc1c | 3276 | |
debccb3e | 3277 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3278 | |
54168ed7 IM |
3279 | if (irq_remapped(irq)) { |
3280 | struct irte irte; | |
3281 | int ir_index; | |
3282 | u16 sub_handle; | |
3283 | ||
3284 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3285 | BUG_ON(ir_index == -1); | |
3286 | ||
3287 | memset (&irte, 0, sizeof(irte)); | |
3288 | ||
3289 | irte.present = 1; | |
9b5bc8dc | 3290 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3291 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3292 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3293 | irte.vector = cfg->vector; |
3294 | irte.dest_id = IRTE_DEST(dest); | |
3295 | ||
f007e99c WH |
3296 | /* Set source-id of interrupt request */ |
3297 | set_msi_sid(&irte, pdev); | |
3298 | ||
54168ed7 IM |
3299 | modify_irte(irq, &irte); |
3300 | ||
3301 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3302 | msg->data = sub_handle; | |
3303 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3304 | MSI_ADDR_IR_SHV | | |
3305 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3306 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3307 | } else { |
9d783ba0 SS |
3308 | if (x2apic_enabled()) |
3309 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3310 | MSI_ADDR_EXT_DEST_ID(dest); | |
3311 | else | |
3312 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3313 | ||
54168ed7 IM |
3314 | msg->address_lo = |
3315 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3316 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3317 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3318 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3319 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3320 | MSI_ADDR_REDIRECTION_CPU: |
3321 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3322 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3323 | |
54168ed7 IM |
3324 | msg->data = |
3325 | MSI_DATA_TRIGGER_EDGE | | |
3326 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3327 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3328 | MSI_DATA_DELIVERY_FIXED: |
3329 | MSI_DATA_DELIVERY_LOWPRI) | | |
3330 | MSI_DATA_VECTOR(cfg->vector); | |
3331 | } | |
497c9a19 | 3332 | return err; |
2d3fcc1c EB |
3333 | } |
3334 | ||
3b7d1921 | 3335 | #ifdef CONFIG_SMP |
d5dedd45 | 3336 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3337 | { |
3145e941 | 3338 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3339 | struct irq_cfg *cfg; |
3b7d1921 EB |
3340 | struct msi_msg msg; |
3341 | unsigned int dest; | |
3b7d1921 | 3342 | |
22f65d31 MT |
3343 | dest = set_desc_affinity(desc, mask); |
3344 | if (dest == BAD_APICID) | |
d5dedd45 | 3345 | return -1; |
2d3fcc1c | 3346 | |
3145e941 | 3347 | cfg = desc->chip_data; |
2d3fcc1c | 3348 | |
3145e941 | 3349 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3350 | |
3351 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3352 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3353 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3354 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3355 | ||
3145e941 | 3356 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3357 | |
3358 | return 0; | |
2d3fcc1c | 3359 | } |
54168ed7 IM |
3360 | #ifdef CONFIG_INTR_REMAP |
3361 | /* | |
3362 | * Migrate the MSI irq to another cpumask. This migration is | |
3363 | * done in the process context using interrupt-remapping hardware. | |
3364 | */ | |
d5dedd45 | 3365 | static int |
e7986739 | 3366 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3367 | { |
3145e941 | 3368 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3369 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3370 | unsigned int dest; |
54168ed7 | 3371 | struct irte irte; |
54168ed7 IM |
3372 | |
3373 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3374 | return -1; |
54168ed7 | 3375 | |
22f65d31 MT |
3376 | dest = set_desc_affinity(desc, mask); |
3377 | if (dest == BAD_APICID) | |
d5dedd45 | 3378 | return -1; |
54168ed7 | 3379 | |
54168ed7 IM |
3380 | irte.vector = cfg->vector; |
3381 | irte.dest_id = IRTE_DEST(dest); | |
3382 | ||
3383 | /* | |
3384 | * atomically update the IRTE with the new destination and vector. | |
3385 | */ | |
3386 | modify_irte(irq, &irte); | |
3387 | ||
3388 | /* | |
3389 | * After this point, all the interrupts will start arriving | |
3390 | * at the new destination. So, time to cleanup the previous | |
3391 | * vector allocation. | |
3392 | */ | |
22f65d31 MT |
3393 | if (cfg->move_in_progress) |
3394 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3395 | |
3396 | return 0; | |
54168ed7 | 3397 | } |
3145e941 | 3398 | |
54168ed7 | 3399 | #endif |
3b7d1921 | 3400 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3401 | |
3b7d1921 EB |
3402 | /* |
3403 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3404 | * which implement the MSI or MSI-X Capability Structure. | |
3405 | */ | |
3406 | static struct irq_chip msi_chip = { | |
3407 | .name = "PCI-MSI", | |
3408 | .unmask = unmask_msi_irq, | |
3409 | .mask = mask_msi_irq, | |
1d025192 | 3410 | .ack = ack_apic_edge, |
3b7d1921 EB |
3411 | #ifdef CONFIG_SMP |
3412 | .set_affinity = set_msi_irq_affinity, | |
3413 | #endif | |
3414 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3415 | }; |
3416 | ||
54168ed7 IM |
3417 | static struct irq_chip msi_ir_chip = { |
3418 | .name = "IR-PCI-MSI", | |
3419 | .unmask = unmask_msi_irq, | |
3420 | .mask = mask_msi_irq, | |
a1e38ca5 | 3421 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3422 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3423 | #ifdef CONFIG_SMP |
3424 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3425 | #endif |
54168ed7 IM |
3426 | #endif |
3427 | .retrigger = ioapic_retrigger_irq, | |
3428 | }; | |
3429 | ||
3430 | /* | |
3431 | * Map the PCI dev to the corresponding remapping hardware unit | |
3432 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3433 | * in it. | |
3434 | */ | |
3435 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3436 | { | |
3437 | struct intel_iommu *iommu; | |
3438 | int index; | |
3439 | ||
3440 | iommu = map_dev_to_ir(dev); | |
3441 | if (!iommu) { | |
3442 | printk(KERN_ERR | |
3443 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3444 | return -ENOENT; | |
3445 | } | |
3446 | ||
3447 | index = alloc_irte(iommu, irq, nvec); | |
3448 | if (index < 0) { | |
3449 | printk(KERN_ERR | |
3450 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3451 | pci_name(dev)); |
54168ed7 IM |
3452 | return -ENOSPC; |
3453 | } | |
3454 | return index; | |
3455 | } | |
1d025192 | 3456 | |
3145e941 | 3457 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3458 | { |
3459 | int ret; | |
3460 | struct msi_msg msg; | |
3461 | ||
3462 | ret = msi_compose_msg(dev, irq, &msg); | |
3463 | if (ret < 0) | |
3464 | return ret; | |
3465 | ||
3145e941 | 3466 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3467 | write_msi_msg(irq, &msg); |
3468 | ||
54168ed7 IM |
3469 | if (irq_remapped(irq)) { |
3470 | struct irq_desc *desc = irq_to_desc(irq); | |
3471 | /* | |
3472 | * irq migration in process context | |
3473 | */ | |
3474 | desc->status |= IRQ_MOVE_PCNTXT; | |
3475 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3476 | } else | |
54168ed7 | 3477 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3478 | |
c81bba49 YL |
3479 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3480 | ||
1d025192 YL |
3481 | return 0; |
3482 | } | |
3483 | ||
047c8fdb YL |
3484 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3485 | { | |
54168ed7 IM |
3486 | unsigned int irq; |
3487 | int ret, sub_handle; | |
0b8f1efa | 3488 | struct msi_desc *msidesc; |
54168ed7 | 3489 | unsigned int irq_want; |
1cc18521 | 3490 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3491 | int index = 0; |
d047f53a | 3492 | int node; |
54168ed7 | 3493 | |
1c8d7b0a MW |
3494 | /* x86 doesn't support multiple MSI yet */ |
3495 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3496 | return 1; | |
3497 | ||
d047f53a | 3498 | node = dev_to_node(&dev->dev); |
be5d5350 | 3499 | irq_want = nr_irqs_gsi; |
54168ed7 | 3500 | sub_handle = 0; |
0b8f1efa | 3501 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3502 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3503 | if (irq == 0) |
3504 | return -1; | |
f1ee5548 | 3505 | irq_want = irq + 1; |
54168ed7 IM |
3506 | if (!intr_remapping_enabled) |
3507 | goto no_ir; | |
3508 | ||
3509 | if (!sub_handle) { | |
3510 | /* | |
3511 | * allocate the consecutive block of IRTE's | |
3512 | * for 'nvec' | |
3513 | */ | |
3514 | index = msi_alloc_irte(dev, irq, nvec); | |
3515 | if (index < 0) { | |
3516 | ret = index; | |
3517 | goto error; | |
3518 | } | |
3519 | } else { | |
3520 | iommu = map_dev_to_ir(dev); | |
3521 | if (!iommu) { | |
3522 | ret = -ENOENT; | |
3523 | goto error; | |
3524 | } | |
3525 | /* | |
3526 | * setup the mapping between the irq and the IRTE | |
3527 | * base index, the sub_handle pointing to the | |
3528 | * appropriate interrupt remap table entry. | |
3529 | */ | |
3530 | set_irte_irq(irq, iommu, index, sub_handle); | |
3531 | } | |
3532 | no_ir: | |
0b8f1efa | 3533 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3534 | if (ret < 0) |
3535 | goto error; | |
3536 | sub_handle++; | |
3537 | } | |
3538 | return 0; | |
047c8fdb YL |
3539 | |
3540 | error: | |
54168ed7 IM |
3541 | destroy_irq(irq); |
3542 | return ret; | |
047c8fdb YL |
3543 | } |
3544 | ||
3b7d1921 EB |
3545 | void arch_teardown_msi_irq(unsigned int irq) |
3546 | { | |
f7feaca7 | 3547 | destroy_irq(irq); |
3b7d1921 EB |
3548 | } |
3549 | ||
9d783ba0 | 3550 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3551 | #ifdef CONFIG_SMP |
d5dedd45 | 3552 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3553 | { |
3145e941 | 3554 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3555 | struct irq_cfg *cfg; |
3556 | struct msi_msg msg; | |
3557 | unsigned int dest; | |
54168ed7 | 3558 | |
22f65d31 MT |
3559 | dest = set_desc_affinity(desc, mask); |
3560 | if (dest == BAD_APICID) | |
d5dedd45 | 3561 | return -1; |
54168ed7 | 3562 | |
3145e941 | 3563 | cfg = desc->chip_data; |
54168ed7 IM |
3564 | |
3565 | dmar_msi_read(irq, &msg); | |
3566 | ||
3567 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3568 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3569 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3570 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3571 | ||
3572 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3573 | |
3574 | return 0; | |
54168ed7 | 3575 | } |
3145e941 | 3576 | |
54168ed7 IM |
3577 | #endif /* CONFIG_SMP */ |
3578 | ||
8f7007aa | 3579 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3580 | .name = "DMAR_MSI", |
3581 | .unmask = dmar_msi_unmask, | |
3582 | .mask = dmar_msi_mask, | |
3583 | .ack = ack_apic_edge, | |
3584 | #ifdef CONFIG_SMP | |
3585 | .set_affinity = dmar_msi_set_affinity, | |
3586 | #endif | |
3587 | .retrigger = ioapic_retrigger_irq, | |
3588 | }; | |
3589 | ||
3590 | int arch_setup_dmar_msi(unsigned int irq) | |
3591 | { | |
3592 | int ret; | |
3593 | struct msi_msg msg; | |
2d3fcc1c | 3594 | |
54168ed7 IM |
3595 | ret = msi_compose_msg(NULL, irq, &msg); |
3596 | if (ret < 0) | |
3597 | return ret; | |
3598 | dmar_msi_write(irq, &msg); | |
3599 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3600 | "edge"); | |
3601 | return 0; | |
3602 | } | |
3603 | #endif | |
3604 | ||
58ac1e76 | 3605 | #ifdef CONFIG_HPET_TIMER |
3606 | ||
3607 | #ifdef CONFIG_SMP | |
d5dedd45 | 3608 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3609 | { |
3145e941 | 3610 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3611 | struct irq_cfg *cfg; |
58ac1e76 | 3612 | struct msi_msg msg; |
3613 | unsigned int dest; | |
58ac1e76 | 3614 | |
22f65d31 MT |
3615 | dest = set_desc_affinity(desc, mask); |
3616 | if (dest == BAD_APICID) | |
d5dedd45 | 3617 | return -1; |
58ac1e76 | 3618 | |
3145e941 | 3619 | cfg = desc->chip_data; |
58ac1e76 | 3620 | |
3621 | hpet_msi_read(irq, &msg); | |
3622 | ||
3623 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3624 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3625 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3626 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3627 | ||
3628 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3629 | |
3630 | return 0; | |
58ac1e76 | 3631 | } |
3145e941 | 3632 | |
58ac1e76 | 3633 | #endif /* CONFIG_SMP */ |
3634 | ||
1cc18521 | 3635 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3636 | .name = "HPET_MSI", |
3637 | .unmask = hpet_msi_unmask, | |
3638 | .mask = hpet_msi_mask, | |
3639 | .ack = ack_apic_edge, | |
3640 | #ifdef CONFIG_SMP | |
3641 | .set_affinity = hpet_msi_set_affinity, | |
3642 | #endif | |
3643 | .retrigger = ioapic_retrigger_irq, | |
3644 | }; | |
3645 | ||
3646 | int arch_setup_hpet_msi(unsigned int irq) | |
3647 | { | |
3648 | int ret; | |
3649 | struct msi_msg msg; | |
6ec3cfec | 3650 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3651 | |
3652 | ret = msi_compose_msg(NULL, irq, &msg); | |
3653 | if (ret < 0) | |
3654 | return ret; | |
3655 | ||
3656 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3657 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3658 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3659 | "edge"); | |
c81bba49 | 3660 | |
58ac1e76 | 3661 | return 0; |
3662 | } | |
3663 | #endif | |
3664 | ||
54168ed7 | 3665 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3666 | /* |
3667 | * Hypertransport interrupt support | |
3668 | */ | |
3669 | #ifdef CONFIG_HT_IRQ | |
3670 | ||
3671 | #ifdef CONFIG_SMP | |
3672 | ||
497c9a19 | 3673 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3674 | { |
ec68307c EB |
3675 | struct ht_irq_msg msg; |
3676 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3677 | |
497c9a19 | 3678 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3679 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3680 | |
497c9a19 | 3681 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3682 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3683 | |
ec68307c | 3684 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3685 | } |
3686 | ||
d5dedd45 | 3687 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3688 | { |
3145e941 | 3689 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3690 | struct irq_cfg *cfg; |
8b955b0d | 3691 | unsigned int dest; |
8b955b0d | 3692 | |
22f65d31 MT |
3693 | dest = set_desc_affinity(desc, mask); |
3694 | if (dest == BAD_APICID) | |
d5dedd45 | 3695 | return -1; |
8b955b0d | 3696 | |
3145e941 | 3697 | cfg = desc->chip_data; |
8b955b0d | 3698 | |
497c9a19 | 3699 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3700 | |
3701 | return 0; | |
8b955b0d | 3702 | } |
3145e941 | 3703 | |
8b955b0d EB |
3704 | #endif |
3705 | ||
c37e108d | 3706 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3707 | .name = "PCI-HT", |
3708 | .mask = mask_ht_irq, | |
3709 | .unmask = unmask_ht_irq, | |
1d025192 | 3710 | .ack = ack_apic_edge, |
8b955b0d EB |
3711 | #ifdef CONFIG_SMP |
3712 | .set_affinity = set_ht_irq_affinity, | |
3713 | #endif | |
3714 | .retrigger = ioapic_retrigger_irq, | |
3715 | }; | |
3716 | ||
3717 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3718 | { | |
497c9a19 YL |
3719 | struct irq_cfg *cfg; |
3720 | int err; | |
8b955b0d | 3721 | |
f1182638 JB |
3722 | if (disable_apic) |
3723 | return -ENXIO; | |
3724 | ||
3145e941 | 3725 | cfg = irq_cfg(irq); |
fe402e1f | 3726 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3727 | if (!err) { |
ec68307c | 3728 | struct ht_irq_msg msg; |
8b955b0d | 3729 | unsigned dest; |
8b955b0d | 3730 | |
debccb3e IM |
3731 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3732 | apic->target_cpus()); | |
8b955b0d | 3733 | |
ec68307c | 3734 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3735 | |
ec68307c EB |
3736 | msg.address_lo = |
3737 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3738 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3739 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3740 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3741 | HT_IRQ_LOW_DM_PHYSICAL : |
3742 | HT_IRQ_LOW_DM_LOGICAL) | | |
3743 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3744 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3745 | HT_IRQ_LOW_MT_FIXED : |
3746 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3747 | HT_IRQ_LOW_IRQ_MASKED; | |
3748 | ||
ec68307c | 3749 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3750 | |
a460e745 IM |
3751 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3752 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3753 | |
3754 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3755 | } |
497c9a19 | 3756 | return err; |
8b955b0d EB |
3757 | } |
3758 | #endif /* CONFIG_HT_IRQ */ | |
3759 | ||
03b48632 | 3760 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3761 | /* |
3762 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3763 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3764 | */ | |
3765 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3766 | unsigned long mmr_offset) | |
3767 | { | |
22f65d31 | 3768 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3769 | struct irq_cfg *cfg; |
3770 | int mmr_pnode; | |
3771 | unsigned long mmr_value; | |
3772 | struct uv_IO_APIC_route_entry *entry; | |
3773 | unsigned long flags; | |
3774 | int err; | |
3775 | ||
1cbac972 CG |
3776 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3777 | ||
3145e941 YL |
3778 | cfg = irq_cfg(irq); |
3779 | ||
e7986739 | 3780 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3781 | if (err != 0) |
3782 | return err; | |
3783 | ||
3784 | spin_lock_irqsave(&vector_lock, flags); | |
3785 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3786 | irq_name); | |
3787 | spin_unlock_irqrestore(&vector_lock, flags); | |
3788 | ||
4173a0e7 DN |
3789 | mmr_value = 0; |
3790 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3791 | entry->vector = cfg->vector; |
3792 | entry->delivery_mode = apic->irq_delivery_mode; | |
3793 | entry->dest_mode = apic->irq_dest_mode; | |
3794 | entry->polarity = 0; | |
3795 | entry->trigger = 0; | |
3796 | entry->mask = 0; | |
3797 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3798 | |
3799 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3800 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3801 | ||
3802 | return irq; | |
3803 | } | |
3804 | ||
3805 | /* | |
3806 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3807 | * longer allowed to be sent. | |
3808 | */ | |
3809 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3810 | { | |
3811 | unsigned long mmr_value; | |
3812 | struct uv_IO_APIC_route_entry *entry; | |
3813 | int mmr_pnode; | |
3814 | ||
1cbac972 CG |
3815 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3816 | ||
4173a0e7 DN |
3817 | mmr_value = 0; |
3818 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3819 | entry->mask = 1; |
3820 | ||
3821 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3822 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3823 | } | |
3824 | #endif /* CONFIG_X86_64 */ | |
3825 | ||
9d6a4d08 YL |
3826 | int __init io_apic_get_redir_entries (int ioapic) |
3827 | { | |
3828 | union IO_APIC_reg_01 reg_01; | |
3829 | unsigned long flags; | |
3830 | ||
3831 | spin_lock_irqsave(&ioapic_lock, flags); | |
3832 | reg_01.raw = io_apic_read(ioapic, 1); | |
3833 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3834 | ||
3835 | return reg_01.bits.entries; | |
3836 | } | |
3837 | ||
be5d5350 | 3838 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3839 | { |
be5d5350 YL |
3840 | int nr = 0; |
3841 | ||
cc6c5006 YL |
3842 | nr = acpi_probe_gsi(); |
3843 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3844 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3845 | } else { |
3846 | /* for acpi=off or acpi is not compiled in */ | |
3847 | int idx; | |
3848 | ||
3849 | nr = 0; | |
3850 | for (idx = 0; idx < nr_ioapics; idx++) | |
3851 | nr += io_apic_get_redir_entries(idx) + 1; | |
3852 | ||
3853 | if (nr > nr_irqs_gsi) | |
3854 | nr_irqs_gsi = nr; | |
3855 | } | |
3856 | ||
3857 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3858 | } |
3859 | ||
4a046d17 YL |
3860 | #ifdef CONFIG_SPARSE_IRQ |
3861 | int __init arch_probe_nr_irqs(void) | |
3862 | { | |
3863 | int nr; | |
3864 | ||
f1ee5548 YL |
3865 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3866 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3867 | |
f1ee5548 YL |
3868 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3869 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3870 | /* | |
3871 | * for MSI and HT dyn irq | |
3872 | */ | |
3873 | nr += nr_irqs_gsi * 16; | |
3874 | #endif | |
3875 | if (nr < nr_irqs) | |
4a046d17 YL |
3876 | nr_irqs = nr; |
3877 | ||
3878 | return 0; | |
3879 | } | |
3880 | #endif | |
3881 | ||
e5198075 YL |
3882 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3883 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3884 | { |
3885 | struct irq_desc *desc; | |
3886 | struct irq_cfg *cfg; | |
3887 | int node; | |
e5198075 YL |
3888 | int ioapic, pin; |
3889 | int trigger, polarity; | |
5ef21837 | 3890 | |
e5198075 | 3891 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3892 | if (!IO_APIC_IRQ(irq)) { |
3893 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3894 | ioapic); | |
3895 | return -EINVAL; | |
3896 | } | |
3897 | ||
3898 | if (dev) | |
3899 | node = dev_to_node(dev); | |
3900 | else | |
3901 | node = cpu_to_node(boot_cpu_id); | |
3902 | ||
3903 | desc = irq_to_desc_alloc_node(irq, node); | |
3904 | if (!desc) { | |
3905 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3906 | return 0; | |
3907 | } | |
3908 | ||
e5198075 YL |
3909 | pin = irq_attr->ioapic_pin; |
3910 | trigger = irq_attr->trigger; | |
3911 | polarity = irq_attr->polarity; | |
3912 | ||
5ef21837 YL |
3913 | /* |
3914 | * IRQs < 16 are already in the irq_2_pin[] map | |
3915 | */ | |
3916 | if (irq >= NR_IRQS_LEGACY) { | |
3917 | cfg = desc->chip_data; | |
3918 | add_pin_to_irq_node(cfg, node, ioapic, pin); | |
3919 | } | |
3920 | ||
e5198075 | 3921 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3922 | |
3923 | return 0; | |
3924 | } | |
3925 | ||
e5198075 YL |
3926 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3927 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3928 | { |
e5198075 | 3929 | int ioapic, pin; |
5ef21837 YL |
3930 | /* |
3931 | * Avoid pin reprogramming. PRTs typically include entries | |
3932 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3933 | * we only program the IOAPIC on the first. | |
3934 | */ | |
e5198075 YL |
3935 | ioapic = irq_attr->ioapic; |
3936 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3937 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3938 | pr_debug("Pin %d-%d already programmed\n", | |
3939 | mp_ioapics[ioapic].apicid, pin); | |
3940 | return 0; | |
3941 | } | |
3942 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3943 | ||
e5198075 | 3944 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3945 | } |
3946 | ||
1da177e4 | 3947 | /* -------------------------------------------------------------------------- |
54168ed7 | 3948 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3949 | -------------------------------------------------------------------------- */ |
3950 | ||
888ba6c6 | 3951 | #ifdef CONFIG_ACPI |
1da177e4 | 3952 | |
54168ed7 | 3953 | #ifdef CONFIG_X86_32 |
36062448 | 3954 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3955 | { |
3956 | union IO_APIC_reg_00 reg_00; | |
3957 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3958 | physid_mask_t tmp; | |
3959 | unsigned long flags; | |
3960 | int i = 0; | |
3961 | ||
3962 | /* | |
36062448 PC |
3963 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3964 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3965 | * supports up to 16 on one shared APIC bus. |
36062448 | 3966 | * |
1da177e4 LT |
3967 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3968 | * advantage of new APIC bus architecture. | |
3969 | */ | |
3970 | ||
3971 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3972 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3973 | |
3974 | spin_lock_irqsave(&ioapic_lock, flags); | |
3975 | reg_00.raw = io_apic_read(ioapic, 0); | |
3976 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3977 | ||
3978 | if (apic_id >= get_physical_broadcast()) { | |
3979 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3980 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3981 | apic_id = reg_00.bits.ID; | |
3982 | } | |
3983 | ||
3984 | /* | |
36062448 | 3985 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3986 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3987 | */ | |
d1d7cae8 | 3988 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3989 | |
3990 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3991 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3992 | break; |
3993 | } | |
3994 | ||
3995 | if (i == get_physical_broadcast()) | |
3996 | panic("Max apic_id exceeded!\n"); | |
3997 | ||
3998 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3999 | "trying %d\n", ioapic, apic_id, i); | |
4000 | ||
4001 | apic_id = i; | |
36062448 | 4002 | } |
1da177e4 | 4003 | |
8058714a | 4004 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
4005 | physids_or(apic_id_map, apic_id_map, tmp); |
4006 | ||
4007 | if (reg_00.bits.ID != apic_id) { | |
4008 | reg_00.bits.ID = apic_id; | |
4009 | ||
4010 | spin_lock_irqsave(&ioapic_lock, flags); | |
4011 | io_apic_write(ioapic, 0, reg_00.raw); | |
4012 | reg_00.raw = io_apic_read(ioapic, 0); | |
4013 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4014 | ||
4015 | /* Sanity check */ | |
6070f9ec AD |
4016 | if (reg_00.bits.ID != apic_id) { |
4017 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4018 | return -1; | |
4019 | } | |
1da177e4 LT |
4020 | } |
4021 | ||
4022 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4023 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4024 | ||
4025 | return apic_id; | |
4026 | } | |
58f892e0 | 4027 | #endif |
1da177e4 | 4028 | |
36062448 | 4029 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4030 | { |
4031 | union IO_APIC_reg_01 reg_01; | |
4032 | unsigned long flags; | |
4033 | ||
4034 | spin_lock_irqsave(&ioapic_lock, flags); | |
4035 | reg_01.raw = io_apic_read(ioapic, 1); | |
4036 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4037 | ||
4038 | return reg_01.bits.version; | |
4039 | } | |
4040 | ||
61fd47e0 SL |
4041 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4042 | { | |
4043 | int i; | |
4044 | ||
4045 | if (skip_ioapic_setup) | |
4046 | return -1; | |
4047 | ||
4048 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4049 | if (mp_irqs[i].irqtype == mp_INT && |
4050 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4051 | break; |
4052 | if (i >= mp_irq_entries) | |
4053 | return -1; | |
4054 | ||
4055 | *trigger = irq_trigger(i); | |
4056 | *polarity = irq_polarity(i); | |
4057 | return 0; | |
4058 | } | |
4059 | ||
888ba6c6 | 4060 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4061 | |
497c9a19 YL |
4062 | /* |
4063 | * This function currently is only a helper for the i386 smp boot process where | |
4064 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4065 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4066 | */ |
4067 | #ifdef CONFIG_SMP | |
4068 | void __init setup_ioapic_dest(void) | |
4069 | { | |
b9c61b70 | 4070 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4071 | struct irq_desc *desc; |
22f65d31 | 4072 | const struct cpumask *mask; |
497c9a19 YL |
4073 | |
4074 | if (skip_ioapic_setup == 1) | |
4075 | return; | |
4076 | ||
b9c61b70 YL |
4077 | #ifdef CONFIG_ACPI |
4078 | if (!acpi_disabled && acpi_ioapic) { | |
4079 | ioapic = mp_find_ioapic(0); | |
4080 | if (ioapic < 0) | |
4081 | ioapic = 0; | |
4082 | } | |
4083 | #endif | |
6c2e9403 | 4084 | |
b9c61b70 YL |
4085 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4086 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4087 | if (irq_entry == -1) | |
4088 | continue; | |
4089 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4090 | |
b9c61b70 | 4091 | desc = irq_to_desc(irq); |
6c2e9403 | 4092 | |
b9c61b70 YL |
4093 | /* |
4094 | * Honour affinities which have been set in early boot | |
4095 | */ | |
4096 | if (desc->status & | |
4097 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4098 | mask = desc->affinity; | |
4099 | else | |
4100 | mask = apic->target_cpus(); | |
497c9a19 | 4101 | |
b9c61b70 YL |
4102 | if (intr_remapping_enabled) |
4103 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4104 | else | |
4105 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4106 | } |
b9c61b70 | 4107 | |
497c9a19 YL |
4108 | } |
4109 | #endif | |
4110 | ||
54168ed7 IM |
4111 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4112 | ||
4113 | static struct resource *ioapic_resources; | |
4114 | ||
4115 | static struct resource * __init ioapic_setup_resources(void) | |
4116 | { | |
4117 | unsigned long n; | |
4118 | struct resource *res; | |
4119 | char *mem; | |
4120 | int i; | |
4121 | ||
4122 | if (nr_ioapics <= 0) | |
4123 | return NULL; | |
4124 | ||
4125 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4126 | n *= nr_ioapics; | |
4127 | ||
4128 | mem = alloc_bootmem(n); | |
4129 | res = (void *)mem; | |
4130 | ||
4131 | if (mem != NULL) { | |
4132 | mem += sizeof(struct resource) * nr_ioapics; | |
4133 | ||
4134 | for (i = 0; i < nr_ioapics; i++) { | |
4135 | res[i].name = mem; | |
4136 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4137 | sprintf(mem, "IOAPIC %u", i); | |
4138 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4139 | } | |
4140 | } | |
4141 | ||
4142 | ioapic_resources = res; | |
4143 | ||
4144 | return res; | |
4145 | } | |
54168ed7 | 4146 | |
f3294a33 YL |
4147 | void __init ioapic_init_mappings(void) |
4148 | { | |
4149 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4150 | struct resource *ioapic_res; |
d6c88a50 | 4151 | int i; |
f3294a33 | 4152 | |
54168ed7 | 4153 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4154 | for (i = 0; i < nr_ioapics; i++) { |
4155 | if (smp_found_config) { | |
b5ba7e6d | 4156 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4157 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4158 | if (!ioapic_phys) { |
4159 | printk(KERN_ERR | |
4160 | "WARNING: bogus zero IO-APIC " | |
4161 | "address found in MPTABLE, " | |
4162 | "disabling IO/APIC support!\n"); | |
4163 | smp_found_config = 0; | |
4164 | skip_ioapic_setup = 1; | |
4165 | goto fake_ioapic_page; | |
4166 | } | |
54168ed7 | 4167 | #endif |
f3294a33 | 4168 | } else { |
54168ed7 | 4169 | #ifdef CONFIG_X86_32 |
f3294a33 | 4170 | fake_ioapic_page: |
54168ed7 | 4171 | #endif |
f3294a33 | 4172 | ioapic_phys = (unsigned long) |
54168ed7 | 4173 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4174 | ioapic_phys = __pa(ioapic_phys); |
4175 | } | |
4176 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4177 | apic_printk(APIC_VERBOSE, |
4178 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4179 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4180 | idx++; |
54168ed7 | 4181 | |
54168ed7 IM |
4182 | if (ioapic_res != NULL) { |
4183 | ioapic_res->start = ioapic_phys; | |
4184 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4185 | ioapic_res++; | |
4186 | } | |
f3294a33 YL |
4187 | } |
4188 | } | |
4189 | ||
54168ed7 IM |
4190 | static int __init ioapic_insert_resources(void) |
4191 | { | |
4192 | int i; | |
4193 | struct resource *r = ioapic_resources; | |
4194 | ||
4195 | if (!r) { | |
04c93ce4 BZ |
4196 | if (nr_ioapics > 0) { |
4197 | printk(KERN_ERR | |
4198 | "IO APIC resources couldn't be allocated.\n"); | |
4199 | return -1; | |
4200 | } | |
4201 | return 0; | |
54168ed7 IM |
4202 | } |
4203 | ||
4204 | for (i = 0; i < nr_ioapics; i++) { | |
4205 | insert_resource(&iomem_resource, r); | |
4206 | r++; | |
4207 | } | |
4208 | ||
4209 | return 0; | |
4210 | } | |
4211 | ||
4212 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4213 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4214 | late_initcall(ioapic_insert_resources); |