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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
2a4ab640 FT |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
90 | ||
584f734d | 91 | /* MP IRQ source entries */ |
c2c21745 | 92 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
93 | |
94 | /* # of MP IRQ source entries */ | |
95 | int mp_irq_entries; | |
96 | ||
bc07844a TG |
97 | /* Number of legacy interrupts */ |
98 | static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY; | |
99 | /* GSI interrupts */ | |
100 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
101 | ||
8732fc4b AS |
102 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
103 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
104 | #endif | |
105 | ||
106 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
107 | ||
efa2559f YL |
108 | int skip_ioapic_setup; |
109 | ||
65a4e574 IM |
110 | void arch_disable_smp_support(void) |
111 | { | |
112 | #ifdef CONFIG_PCI | |
113 | noioapicquirk = 1; | |
114 | noioapicreroute = -1; | |
115 | #endif | |
116 | skip_ioapic_setup = 1; | |
117 | } | |
118 | ||
54168ed7 | 119 | static int __init parse_noapic(char *str) |
efa2559f YL |
120 | { |
121 | /* disable IO-APIC */ | |
65a4e574 | 122 | arch_disable_smp_support(); |
efa2559f YL |
123 | return 0; |
124 | } | |
125 | early_param("noapic", parse_noapic); | |
66759a01 | 126 | |
0b8f1efa YL |
127 | struct irq_pin_list { |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
85ac16d0 | 132 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
133 | { |
134 | struct irq_pin_list *pin; | |
0b8f1efa YL |
135 | |
136 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
137 | |
138 | return pin; | |
139 | } | |
140 | ||
a1420f39 | 141 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
142 | #ifdef CONFIG_SPARSE_IRQ |
143 | static struct irq_cfg irq_cfgx[] = { | |
144 | #else | |
d6c88a50 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 146 | #endif |
22f65d31 MT |
147 | [0] = { .vector = IRQ0_VECTOR, }, |
148 | [1] = { .vector = IRQ1_VECTOR, }, | |
149 | [2] = { .vector = IRQ2_VECTOR, }, | |
150 | [3] = { .vector = IRQ3_VECTOR, }, | |
151 | [4] = { .vector = IRQ4_VECTOR, }, | |
152 | [5] = { .vector = IRQ5_VECTOR, }, | |
153 | [6] = { .vector = IRQ6_VECTOR, }, | |
154 | [7] = { .vector = IRQ7_VECTOR, }, | |
155 | [8] = { .vector = IRQ8_VECTOR, }, | |
156 | [9] = { .vector = IRQ9_VECTOR, }, | |
157 | [10] = { .vector = IRQ10_VECTOR, }, | |
158 | [11] = { .vector = IRQ11_VECTOR, }, | |
159 | [12] = { .vector = IRQ12_VECTOR, }, | |
160 | [13] = { .vector = IRQ13_VECTOR, }, | |
161 | [14] = { .vector = IRQ14_VECTOR, }, | |
162 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
163 | }; |
164 | ||
bc07844a TG |
165 | void __init io_apic_disable_legacy(void) |
166 | { | |
167 | nr_legacy_irqs = 0; | |
168 | nr_irqs_gsi = 0; | |
169 | } | |
170 | ||
13a0c3c2 | 171 | int __init arch_early_irq_init(void) |
8f09cd20 | 172 | { |
0b8f1efa YL |
173 | struct irq_cfg *cfg; |
174 | struct irq_desc *desc; | |
175 | int count; | |
dad213ae | 176 | int node; |
0b8f1efa | 177 | int i; |
d6c88a50 | 178 | |
0b8f1efa YL |
179 | cfg = irq_cfgx; |
180 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 181 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
186 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
187 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
bc07844a | 188 | if (i < nr_legacy_irqs) |
22f65d31 | 189 | cpumask_setall(cfg[i].domain); |
0b8f1efa | 190 | } |
13a0c3c2 YL |
191 | |
192 | return 0; | |
0b8f1efa | 193 | } |
8f09cd20 | 194 | |
0b8f1efa | 195 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 196 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 197 | { |
0b8f1efa YL |
198 | struct irq_cfg *cfg = NULL; |
199 | struct irq_desc *desc; | |
1da177e4 | 200 | |
0b8f1efa YL |
201 | desc = irq_to_desc(irq); |
202 | if (desc) | |
203 | cfg = desc->chip_data; | |
0f978f45 | 204 | |
0b8f1efa | 205 | return cfg; |
8f09cd20 | 206 | } |
d6c88a50 | 207 | |
85ac16d0 | 208 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 209 | { |
0b8f1efa | 210 | struct irq_cfg *cfg; |
0f978f45 | 211 | |
0b8f1efa | 212 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 213 | if (cfg) { |
79f55997 | 214 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
215 | kfree(cfg); |
216 | cfg = NULL; | |
79f55997 | 217 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 218 | GFP_ATOMIC, node)) { |
22f65d31 MT |
219 | free_cpumask_var(cfg->domain); |
220 | kfree(cfg); | |
221 | cfg = NULL; | |
22f65d31 MT |
222 | } |
223 | } | |
0f978f45 | 224 | |
0b8f1efa | 225 | return cfg; |
8f09cd20 YL |
226 | } |
227 | ||
85ac16d0 | 228 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 229 | { |
0b8f1efa | 230 | struct irq_cfg *cfg; |
d6c88a50 | 231 | |
0b8f1efa YL |
232 | cfg = desc->chip_data; |
233 | if (!cfg) { | |
85ac16d0 | 234 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
235 | if (!desc->chip_data) { |
236 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
237 | BUG_ON(1); | |
238 | } | |
239 | } | |
1da177e4 | 240 | |
13a0c3c2 | 241 | return 0; |
0b8f1efa | 242 | } |
0f978f45 | 243 | |
fcef5911 | 244 | /* for move_irq_desc */ |
48a1b10a | 245 | static void |
85ac16d0 | 246 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 247 | { |
48a1b10a YL |
248 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
249 | ||
250 | cfg->irq_2_pin = NULL; | |
251 | old_entry = old_cfg->irq_2_pin; | |
252 | if (!old_entry) | |
253 | return; | |
0f978f45 | 254 | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) |
257 | return; | |
0f978f45 | 258 | |
48a1b10a YL |
259 | entry->apic = old_entry->apic; |
260 | entry->pin = old_entry->pin; | |
261 | head = entry; | |
262 | tail = entry; | |
263 | old_entry = old_entry->next; | |
264 | while (old_entry) { | |
85ac16d0 | 265 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
266 | if (!entry) { |
267 | entry = head; | |
268 | while (entry) { | |
269 | head = entry->next; | |
270 | kfree(entry); | |
271 | entry = head; | |
272 | } | |
273 | /* still use the old one */ | |
274 | return; | |
275 | } | |
276 | entry->apic = old_entry->apic; | |
277 | entry->pin = old_entry->pin; | |
278 | tail->next = entry; | |
279 | tail = entry; | |
280 | old_entry = old_entry->next; | |
281 | } | |
0f978f45 | 282 | |
48a1b10a YL |
283 | tail->next = NULL; |
284 | cfg->irq_2_pin = head; | |
0f978f45 | 285 | } |
0f978f45 | 286 | |
48a1b10a | 287 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 288 | { |
48a1b10a | 289 | struct irq_pin_list *entry, *next; |
0f978f45 | 290 | |
48a1b10a YL |
291 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
292 | return; | |
301e6190 | 293 | |
48a1b10a | 294 | entry = old_cfg->irq_2_pin; |
0f978f45 | 295 | |
48a1b10a YL |
296 | while (entry) { |
297 | next = entry->next; | |
298 | kfree(entry); | |
299 | entry = next; | |
300 | } | |
301 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 302 | } |
0f978f45 | 303 | |
48a1b10a | 304 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 305 | struct irq_desc *desc, int node) |
0f978f45 | 306 | { |
48a1b10a YL |
307 | struct irq_cfg *cfg; |
308 | struct irq_cfg *old_cfg; | |
0f978f45 | 309 | |
85ac16d0 | 310 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 311 | |
48a1b10a YL |
312 | if (!cfg) |
313 | return; | |
314 | ||
315 | desc->chip_data = cfg; | |
316 | ||
317 | old_cfg = old_desc->chip_data; | |
318 | ||
319 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
320 | ||
85ac16d0 | 321 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 322 | } |
1da177e4 | 323 | |
48a1b10a YL |
324 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
325 | { | |
326 | kfree(old_cfg); | |
327 | } | |
328 | ||
329 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
330 | { | |
331 | struct irq_cfg *old_cfg, *cfg; | |
332 | ||
333 | old_cfg = old_desc->chip_data; | |
334 | cfg = desc->chip_data; | |
335 | ||
336 | if (old_cfg == cfg) | |
337 | return; | |
338 | ||
339 | if (old_cfg) { | |
340 | free_irq_2_pin(old_cfg, cfg); | |
341 | free_irq_cfg(old_cfg); | |
342 | old_desc->chip_data = NULL; | |
343 | } | |
344 | } | |
fcef5911 | 345 | /* end for move_irq_desc */ |
48a1b10a | 346 | |
0b8f1efa | 347 | #else |
9338ad6f | 348 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
349 | { |
350 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 351 | } |
1da177e4 | 352 | |
0b8f1efa YL |
353 | #endif |
354 | ||
130fe05d LT |
355 | struct io_apic { |
356 | unsigned int index; | |
357 | unsigned int unused[3]; | |
358 | unsigned int data; | |
0280f7c4 SS |
359 | unsigned int unused2[11]; |
360 | unsigned int eoi; | |
130fe05d LT |
361 | }; |
362 | ||
363 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
364 | { | |
365 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 366 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
367 | } |
368 | ||
0280f7c4 SS |
369 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
370 | { | |
371 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
372 | writel(vector, &io_apic->eoi); | |
373 | } | |
374 | ||
130fe05d LT |
375 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
376 | { | |
377 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
378 | writel(reg, &io_apic->index); | |
379 | return readl(&io_apic->data); | |
380 | } | |
381 | ||
382 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
383 | { | |
384 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
385 | writel(reg, &io_apic->index); | |
386 | writel(value, &io_apic->data); | |
387 | } | |
388 | ||
389 | /* | |
390 | * Re-write a value: to be used for read-modify-write | |
391 | * cycles where the read already set up the index register. | |
392 | * | |
393 | * Older SiS APIC requires we rewrite the index register | |
394 | */ | |
395 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
396 | { | |
54168ed7 | 397 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
398 | |
399 | if (sis_apic_bug) | |
400 | writel(reg, &io_apic->index); | |
130fe05d LT |
401 | writel(value, &io_apic->data); |
402 | } | |
403 | ||
3145e941 | 404 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
405 | { |
406 | struct irq_pin_list *entry; | |
407 | unsigned long flags; | |
047c8fdb YL |
408 | |
409 | spin_lock_irqsave(&ioapic_lock, flags); | |
2977fb3f | 410 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
411 | unsigned int reg; |
412 | int pin; | |
413 | ||
047c8fdb YL |
414 | pin = entry->pin; |
415 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
416 | /* Is the remote IRR bit set? */ | |
417 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
418 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
419 | return true; | |
420 | } | |
047c8fdb YL |
421 | } |
422 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
423 | ||
424 | return false; | |
425 | } | |
047c8fdb | 426 | |
cf4c6a2f AK |
427 | union entry_union { |
428 | struct { u32 w1, w2; }; | |
429 | struct IO_APIC_route_entry entry; | |
430 | }; | |
431 | ||
432 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
433 | { | |
434 | union entry_union eu; | |
435 | unsigned long flags; | |
436 | spin_lock_irqsave(&ioapic_lock, flags); | |
437 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
438 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
439 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
440 | return eu.entry; | |
441 | } | |
442 | ||
f9dadfa7 LT |
443 | /* |
444 | * When we write a new IO APIC routing entry, we need to write the high | |
445 | * word first! If the mask bit in the low word is clear, we will enable | |
446 | * the interrupt, and we need to make sure the entry is fully populated | |
447 | * before that happens. | |
448 | */ | |
d15512f4 AK |
449 | static void |
450 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 451 | { |
50a8d4d2 F |
452 | union entry_union eu = {{0, 0}}; |
453 | ||
cf4c6a2f | 454 | eu.entry = e; |
f9dadfa7 LT |
455 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
456 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
457 | } |
458 | ||
ca97ab90 | 459 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
460 | { |
461 | unsigned long flags; | |
462 | spin_lock_irqsave(&ioapic_lock, flags); | |
463 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
464 | spin_unlock_irqrestore(&ioapic_lock, flags); |
465 | } | |
466 | ||
467 | /* | |
468 | * When we mask an IO APIC routing entry, we need to write the low | |
469 | * word first, in order to set the mask bit before we change the | |
470 | * high bits! | |
471 | */ | |
472 | static void ioapic_mask_entry(int apic, int pin) | |
473 | { | |
474 | unsigned long flags; | |
475 | union entry_union eu = { .entry.mask = 1 }; | |
476 | ||
cf4c6a2f AK |
477 | spin_lock_irqsave(&ioapic_lock, flags); |
478 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
479 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
480 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
481 | } | |
482 | ||
1da177e4 LT |
483 | /* |
484 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
485 | * shared ISA-space IRQs, so we have to support them. We are super | |
486 | * fast in the common case, and fast for shared ISA-space IRQs. | |
487 | */ | |
f3d1915a CG |
488 | static int |
489 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 490 | { |
2977fb3f | 491 | struct irq_pin_list **last, *entry; |
0f978f45 | 492 | |
2977fb3f CG |
493 | /* don't allow duplicates */ |
494 | last = &cfg->irq_2_pin; | |
495 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 496 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 497 | return 0; |
2977fb3f | 498 | last = &entry->next; |
1da177e4 | 499 | } |
0f978f45 | 500 | |
875e68ec | 501 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 502 | if (!entry) { |
f3d1915a CG |
503 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
504 | node, apic, pin); | |
505 | return -ENOMEM; | |
a7428cd2 | 506 | } |
1da177e4 LT |
507 | entry->apic = apic; |
508 | entry->pin = pin; | |
875e68ec | 509 | |
2977fb3f | 510 | *last = entry; |
f3d1915a CG |
511 | return 0; |
512 | } | |
513 | ||
514 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
515 | { | |
516 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
517 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
518 | } |
519 | ||
520 | /* | |
521 | * Reroute an IRQ to a different pin. | |
522 | */ | |
85ac16d0 | 523 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
524 | int oldapic, int oldpin, |
525 | int newapic, int newpin) | |
1da177e4 | 526 | { |
535b6429 | 527 | struct irq_pin_list *entry; |
1da177e4 | 528 | |
2977fb3f | 529 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
530 | if (entry->apic == oldapic && entry->pin == oldpin) { |
531 | entry->apic = newapic; | |
532 | entry->pin = newpin; | |
0f978f45 | 533 | /* every one is different, right? */ |
4eea6fff | 534 | return; |
0f978f45 | 535 | } |
1da177e4 | 536 | } |
0f978f45 | 537 | |
4eea6fff JF |
538 | /* old apic/pin didn't exist, so just add new ones */ |
539 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
540 | } |
541 | ||
2f210deb JF |
542 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
543 | int mask_and, int mask_or, | |
544 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 CG |
545 | { |
546 | int pin; | |
87783be4 | 547 | struct irq_pin_list *entry; |
047c8fdb | 548 | |
2977fb3f | 549 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
87783be4 CG |
550 | unsigned int reg; |
551 | pin = entry->pin; | |
552 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
553 | reg &= mask_and; | |
554 | reg |= mask_or; | |
555 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
556 | if (final) | |
557 | final(entry); | |
558 | } | |
559 | } | |
047c8fdb | 560 | |
3145e941 | 561 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 562 | { |
3145e941 | 563 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 564 | } |
047c8fdb | 565 | |
7f3e632f | 566 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 567 | { |
87783be4 CG |
568 | /* |
569 | * Synchronize the IO-APIC and the CPU by doing | |
570 | * a dummy read from the IO-APIC | |
571 | */ | |
572 | struct io_apic __iomem *io_apic; | |
573 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 574 | readl(&io_apic->data); |
1da177e4 LT |
575 | } |
576 | ||
3145e941 | 577 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 578 | { |
3145e941 | 579 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 580 | } |
1da177e4 | 581 | |
3145e941 | 582 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 583 | { |
3145e941 | 584 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
585 | IO_APIC_REDIR_MASKED, NULL); |
586 | } | |
1da177e4 | 587 | |
3145e941 | 588 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 589 | { |
3145e941 | 590 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
591 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
592 | } | |
047c8fdb | 593 | |
3145e941 | 594 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 595 | { |
3145e941 | 596 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
597 | unsigned long flags; |
598 | ||
3145e941 YL |
599 | BUG_ON(!cfg); |
600 | ||
1da177e4 | 601 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 602 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
603 | spin_unlock_irqrestore(&ioapic_lock, flags); |
604 | } | |
605 | ||
3145e941 | 606 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 607 | { |
3145e941 | 608 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
609 | unsigned long flags; |
610 | ||
611 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 612 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
613 | spin_unlock_irqrestore(&ioapic_lock, flags); |
614 | } | |
615 | ||
3145e941 YL |
616 | static void mask_IO_APIC_irq(unsigned int irq) |
617 | { | |
618 | struct irq_desc *desc = irq_to_desc(irq); | |
619 | ||
620 | mask_IO_APIC_irq_desc(desc); | |
621 | } | |
622 | static void unmask_IO_APIC_irq(unsigned int irq) | |
623 | { | |
624 | struct irq_desc *desc = irq_to_desc(irq); | |
625 | ||
626 | unmask_IO_APIC_irq_desc(desc); | |
627 | } | |
628 | ||
1da177e4 LT |
629 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
630 | { | |
631 | struct IO_APIC_route_entry entry; | |
36062448 | 632 | |
1da177e4 | 633 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 634 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
635 | if (entry.delivery_mode == dest_SMI) |
636 | return; | |
1da177e4 LT |
637 | /* |
638 | * Disable it in the IO-APIC irq-routing table: | |
639 | */ | |
f9dadfa7 | 640 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
641 | } |
642 | ||
54168ed7 | 643 | static void clear_IO_APIC (void) |
1da177e4 LT |
644 | { |
645 | int apic, pin; | |
646 | ||
647 | for (apic = 0; apic < nr_ioapics; apic++) | |
648 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
649 | clear_IO_APIC_pin(apic, pin); | |
650 | } | |
651 | ||
54168ed7 | 652 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
653 | /* |
654 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
655 | * specific CPU-side IRQs. | |
656 | */ | |
657 | ||
658 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
659 | static int pirq_entries[MAX_PIRQS] = { |
660 | [0 ... MAX_PIRQS - 1] = -1 | |
661 | }; | |
1da177e4 | 662 | |
1da177e4 LT |
663 | static int __init ioapic_pirq_setup(char *str) |
664 | { | |
665 | int i, max; | |
666 | int ints[MAX_PIRQS+1]; | |
667 | ||
668 | get_options(str, ARRAY_SIZE(ints), ints); | |
669 | ||
1da177e4 LT |
670 | apic_printk(APIC_VERBOSE, KERN_INFO |
671 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
672 | max = MAX_PIRQS; | |
673 | if (ints[0] < MAX_PIRQS) | |
674 | max = ints[0]; | |
675 | ||
676 | for (i = 0; i < max; i++) { | |
677 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
678 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
679 | /* | |
680 | * PIRQs are mapped upside down, usually. | |
681 | */ | |
682 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
683 | } | |
684 | return 1; | |
685 | } | |
686 | ||
687 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
688 | #endif /* CONFIG_X86_32 */ |
689 | ||
b24696bc FY |
690 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
691 | { | |
692 | int apic; | |
693 | struct IO_APIC_route_entry **ioapic_entries; | |
694 | ||
695 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
696 | GFP_ATOMIC); | |
697 | if (!ioapic_entries) | |
698 | return 0; | |
699 | ||
700 | for (apic = 0; apic < nr_ioapics; apic++) { | |
701 | ioapic_entries[apic] = | |
702 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
703 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
704 | if (!ioapic_entries[apic]) | |
705 | goto nomem; | |
706 | } | |
707 | ||
708 | return ioapic_entries; | |
709 | ||
710 | nomem: | |
711 | while (--apic >= 0) | |
712 | kfree(ioapic_entries[apic]); | |
713 | kfree(ioapic_entries); | |
714 | ||
715 | return 0; | |
716 | } | |
54168ed7 IM |
717 | |
718 | /* | |
05c3dc2c | 719 | * Saves all the IO-APIC RTE's |
54168ed7 | 720 | */ |
b24696bc | 721 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 722 | { |
54168ed7 IM |
723 | int apic, pin; |
724 | ||
b24696bc FY |
725 | if (!ioapic_entries) |
726 | return -ENOMEM; | |
54168ed7 IM |
727 | |
728 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
729 | if (!ioapic_entries[apic]) |
730 | return -ENOMEM; | |
54168ed7 | 731 | |
05c3dc2c | 732 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 733 | ioapic_entries[apic][pin] = |
54168ed7 | 734 | ioapic_read_entry(apic, pin); |
b24696bc | 735 | } |
5ffa4eb2 | 736 | |
54168ed7 IM |
737 | return 0; |
738 | } | |
739 | ||
b24696bc FY |
740 | /* |
741 | * Mask all IO APIC entries. | |
742 | */ | |
743 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
744 | { |
745 | int apic, pin; | |
746 | ||
b24696bc FY |
747 | if (!ioapic_entries) |
748 | return; | |
749 | ||
05c3dc2c | 750 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 751 | if (!ioapic_entries[apic]) |
05c3dc2c | 752 | break; |
b24696bc | 753 | |
05c3dc2c SS |
754 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
755 | struct IO_APIC_route_entry entry; | |
756 | ||
b24696bc | 757 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
758 | if (!entry.mask) { |
759 | entry.mask = 1; | |
760 | ioapic_write_entry(apic, pin, entry); | |
761 | } | |
762 | } | |
763 | } | |
764 | } | |
765 | ||
b24696bc FY |
766 | /* |
767 | * Restore IO APIC entries which was saved in ioapic_entries. | |
768 | */ | |
769 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
770 | { |
771 | int apic, pin; | |
772 | ||
b24696bc FY |
773 | if (!ioapic_entries) |
774 | return -ENOMEM; | |
775 | ||
5ffa4eb2 | 776 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
777 | if (!ioapic_entries[apic]) |
778 | return -ENOMEM; | |
779 | ||
54168ed7 IM |
780 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
781 | ioapic_write_entry(apic, pin, | |
b24696bc | 782 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 783 | } |
b24696bc | 784 | return 0; |
54168ed7 IM |
785 | } |
786 | ||
b24696bc FY |
787 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
788 | { | |
789 | int apic; | |
790 | ||
791 | for (apic = 0; apic < nr_ioapics; apic++) | |
792 | kfree(ioapic_entries[apic]); | |
793 | ||
794 | kfree(ioapic_entries); | |
54168ed7 | 795 | } |
1da177e4 LT |
796 | |
797 | /* | |
798 | * Find the IRQ entry number of a certain pin. | |
799 | */ | |
800 | static int find_irq_entry(int apic, int pin, int type) | |
801 | { | |
802 | int i; | |
803 | ||
804 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
805 | if (mp_irqs[i].irqtype == type && |
806 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
807 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
808 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
809 | return i; |
810 | ||
811 | return -1; | |
812 | } | |
813 | ||
814 | /* | |
815 | * Find the pin to which IRQ[irq] (ISA) is connected | |
816 | */ | |
fcfd636a | 817 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
818 | { |
819 | int i; | |
820 | ||
821 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 822 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 823 | |
d27e2b8e | 824 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
825 | (mp_irqs[i].irqtype == type) && |
826 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 827 | |
c2c21745 | 828 | return mp_irqs[i].dstirq; |
1da177e4 LT |
829 | } |
830 | return -1; | |
831 | } | |
832 | ||
fcfd636a EB |
833 | static int __init find_isa_irq_apic(int irq, int type) |
834 | { | |
835 | int i; | |
836 | ||
837 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 838 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 839 | |
73b2961b | 840 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
841 | (mp_irqs[i].irqtype == type) && |
842 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
843 | break; |
844 | } | |
845 | if (i < mp_irq_entries) { | |
846 | int apic; | |
54168ed7 | 847 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 848 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
849 | return apic; |
850 | } | |
851 | } | |
852 | ||
853 | return -1; | |
854 | } | |
855 | ||
c0a282c2 | 856 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
857 | /* |
858 | * EISA Edge/Level control register, ELCR | |
859 | */ | |
860 | static int EISA_ELCR(unsigned int irq) | |
861 | { | |
bc07844a | 862 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
863 | unsigned int port = 0x4d0 + (irq >> 3); |
864 | return (inb(port) >> (irq & 7)) & 1; | |
865 | } | |
866 | apic_printk(APIC_VERBOSE, KERN_INFO | |
867 | "Broken MPtable reports ISA irq %d\n", irq); | |
868 | return 0; | |
869 | } | |
54168ed7 | 870 | |
c0a282c2 | 871 | #endif |
1da177e4 | 872 | |
6728801d AS |
873 | /* ISA interrupts are always polarity zero edge triggered, |
874 | * when listed as conforming in the MP table. */ | |
875 | ||
876 | #define default_ISA_trigger(idx) (0) | |
877 | #define default_ISA_polarity(idx) (0) | |
878 | ||
1da177e4 LT |
879 | /* EISA interrupts are always polarity zero and can be edge or level |
880 | * trigger depending on the ELCR value. If an interrupt is listed as | |
881 | * EISA conforming in the MP table, that means its trigger type must | |
882 | * be read in from the ELCR */ | |
883 | ||
c2c21745 | 884 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 885 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
886 | |
887 | /* PCI interrupts are always polarity one level triggered, | |
888 | * when listed as conforming in the MP table. */ | |
889 | ||
890 | #define default_PCI_trigger(idx) (1) | |
891 | #define default_PCI_polarity(idx) (1) | |
892 | ||
893 | /* MCA interrupts are always polarity zero level triggered, | |
894 | * when listed as conforming in the MP table. */ | |
895 | ||
896 | #define default_MCA_trigger(idx) (1) | |
6728801d | 897 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 898 | |
61fd47e0 | 899 | static int MPBIOS_polarity(int idx) |
1da177e4 | 900 | { |
c2c21745 | 901 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
902 | int polarity; |
903 | ||
904 | /* | |
905 | * Determine IRQ line polarity (high active or low active): | |
906 | */ | |
c2c21745 | 907 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 908 | { |
54168ed7 IM |
909 | case 0: /* conforms, ie. bus-type dependent polarity */ |
910 | if (test_bit(bus, mp_bus_not_pci)) | |
911 | polarity = default_ISA_polarity(idx); | |
912 | else | |
913 | polarity = default_PCI_polarity(idx); | |
914 | break; | |
915 | case 1: /* high active */ | |
916 | { | |
917 | polarity = 0; | |
918 | break; | |
919 | } | |
920 | case 2: /* reserved */ | |
921 | { | |
922 | printk(KERN_WARNING "broken BIOS!!\n"); | |
923 | polarity = 1; | |
924 | break; | |
925 | } | |
926 | case 3: /* low active */ | |
927 | { | |
928 | polarity = 1; | |
929 | break; | |
930 | } | |
931 | default: /* invalid */ | |
932 | { | |
933 | printk(KERN_WARNING "broken BIOS!!\n"); | |
934 | polarity = 1; | |
935 | break; | |
936 | } | |
1da177e4 LT |
937 | } |
938 | return polarity; | |
939 | } | |
940 | ||
941 | static int MPBIOS_trigger(int idx) | |
942 | { | |
c2c21745 | 943 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
944 | int trigger; |
945 | ||
946 | /* | |
947 | * Determine IRQ trigger mode (edge or level sensitive): | |
948 | */ | |
c2c21745 | 949 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 950 | { |
54168ed7 IM |
951 | case 0: /* conforms, ie. bus-type dependent */ |
952 | if (test_bit(bus, mp_bus_not_pci)) | |
953 | trigger = default_ISA_trigger(idx); | |
954 | else | |
955 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 956 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
957 | switch (mp_bus_id_to_type[bus]) { |
958 | case MP_BUS_ISA: /* ISA pin */ | |
959 | { | |
960 | /* set before the switch */ | |
961 | break; | |
962 | } | |
963 | case MP_BUS_EISA: /* EISA pin */ | |
964 | { | |
965 | trigger = default_EISA_trigger(idx); | |
966 | break; | |
967 | } | |
968 | case MP_BUS_PCI: /* PCI pin */ | |
969 | { | |
970 | /* set before the switch */ | |
971 | break; | |
972 | } | |
973 | case MP_BUS_MCA: /* MCA pin */ | |
974 | { | |
975 | trigger = default_MCA_trigger(idx); | |
976 | break; | |
977 | } | |
978 | default: | |
979 | { | |
980 | printk(KERN_WARNING "broken BIOS!!\n"); | |
981 | trigger = 1; | |
982 | break; | |
983 | } | |
984 | } | |
985 | #endif | |
1da177e4 | 986 | break; |
54168ed7 | 987 | case 1: /* edge */ |
1da177e4 | 988 | { |
54168ed7 | 989 | trigger = 0; |
1da177e4 LT |
990 | break; |
991 | } | |
54168ed7 | 992 | case 2: /* reserved */ |
1da177e4 | 993 | { |
54168ed7 IM |
994 | printk(KERN_WARNING "broken BIOS!!\n"); |
995 | trigger = 1; | |
1da177e4 LT |
996 | break; |
997 | } | |
54168ed7 | 998 | case 3: /* level */ |
1da177e4 | 999 | { |
54168ed7 | 1000 | trigger = 1; |
1da177e4 LT |
1001 | break; |
1002 | } | |
54168ed7 | 1003 | default: /* invalid */ |
1da177e4 LT |
1004 | { |
1005 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1006 | trigger = 0; |
1da177e4 LT |
1007 | break; |
1008 | } | |
1009 | } | |
1010 | return trigger; | |
1011 | } | |
1012 | ||
1013 | static inline int irq_polarity(int idx) | |
1014 | { | |
1015 | return MPBIOS_polarity(idx); | |
1016 | } | |
1017 | ||
1018 | static inline int irq_trigger(int idx) | |
1019 | { | |
1020 | return MPBIOS_trigger(idx); | |
1021 | } | |
1022 | ||
efa2559f | 1023 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1024 | static int pin_2_irq(int idx, int apic, int pin) |
1025 | { | |
1026 | int irq, i; | |
c2c21745 | 1027 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1028 | |
1029 | /* | |
1030 | * Debugging check, we are in big trouble if this message pops up! | |
1031 | */ | |
c2c21745 | 1032 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1033 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1034 | ||
54168ed7 | 1035 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1036 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1037 | } else { |
643befed AS |
1038 | /* |
1039 | * PCI IRQs are mapped in order | |
1040 | */ | |
1041 | i = irq = 0; | |
1042 | while (i < apic) | |
1043 | irq += nr_ioapic_registers[i++]; | |
1044 | irq += pin; | |
d6c88a50 | 1045 | /* |
54168ed7 IM |
1046 | * For MPS mode, so far only needed by ES7000 platform |
1047 | */ | |
d6c88a50 TG |
1048 | if (ioapic_renumber_irq) |
1049 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1050 | } |
1051 | ||
54168ed7 | 1052 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1053 | /* |
1054 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1055 | */ | |
1056 | if ((pin >= 16) && (pin <= 23)) { | |
1057 | if (pirq_entries[pin-16] != -1) { | |
1058 | if (!pirq_entries[pin-16]) { | |
1059 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1060 | "disabling PIRQ%d\n", pin-16); | |
1061 | } else { | |
1062 | irq = pirq_entries[pin-16]; | |
1063 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1064 | "using PIRQ%d -> IRQ %d\n", | |
1065 | pin-16, irq); | |
1066 | } | |
1067 | } | |
1068 | } | |
54168ed7 IM |
1069 | #endif |
1070 | ||
1da177e4 LT |
1071 | return irq; |
1072 | } | |
1073 | ||
e20c06fd YL |
1074 | /* |
1075 | * Find a specific PCI IRQ entry. | |
1076 | * Not an __init, possibly needed by modules | |
1077 | */ | |
1078 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1079 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1080 | { |
1081 | int apic, i, best_guess = -1; | |
1082 | ||
1083 | apic_printk(APIC_DEBUG, | |
1084 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1085 | bus, slot, pin); | |
1086 | if (test_bit(bus, mp_bus_not_pci)) { | |
1087 | apic_printk(APIC_VERBOSE, | |
1088 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1089 | return -1; | |
1090 | } | |
1091 | for (i = 0; i < mp_irq_entries; i++) { | |
1092 | int lbus = mp_irqs[i].srcbus; | |
1093 | ||
1094 | for (apic = 0; apic < nr_ioapics; apic++) | |
1095 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1096 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1097 | break; | |
1098 | ||
1099 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1100 | !mp_irqs[i].irqtype && | |
1101 | (bus == lbus) && | |
1102 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1103 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1104 | ||
1105 | if (!(apic || IO_APIC_IRQ(irq))) | |
1106 | continue; | |
1107 | ||
1108 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1109 | set_io_apic_irq_attr(irq_attr, apic, |
1110 | mp_irqs[i].dstirq, | |
1111 | irq_trigger(i), | |
1112 | irq_polarity(i)); | |
e20c06fd YL |
1113 | return irq; |
1114 | } | |
1115 | /* | |
1116 | * Use the first all-but-pin matching entry as a | |
1117 | * best-guess fuzzy result for broken mptables. | |
1118 | */ | |
1119 | if (best_guess < 0) { | |
e5198075 YL |
1120 | set_io_apic_irq_attr(irq_attr, apic, |
1121 | mp_irqs[i].dstirq, | |
1122 | irq_trigger(i), | |
1123 | irq_polarity(i)); | |
e20c06fd YL |
1124 | best_guess = irq; |
1125 | } | |
1126 | } | |
1127 | } | |
1128 | return best_guess; | |
1129 | } | |
1130 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1131 | ||
497c9a19 YL |
1132 | void lock_vector_lock(void) |
1133 | { | |
1134 | /* Used to the online set of cpus does not change | |
1135 | * during assign_irq_vector. | |
1136 | */ | |
1137 | spin_lock(&vector_lock); | |
1138 | } | |
1da177e4 | 1139 | |
497c9a19 | 1140 | void unlock_vector_lock(void) |
1da177e4 | 1141 | { |
497c9a19 YL |
1142 | spin_unlock(&vector_lock); |
1143 | } | |
1da177e4 | 1144 | |
e7986739 MT |
1145 | static int |
1146 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1147 | { |
047c8fdb YL |
1148 | /* |
1149 | * NOTE! The local APIC isn't very good at handling | |
1150 | * multiple interrupts at the same interrupt level. | |
1151 | * As the interrupt level is determined by taking the | |
1152 | * vector number and shifting that right by 4, we | |
1153 | * want to spread these out a bit so that they don't | |
1154 | * all fall in the same interrupt level. | |
1155 | * | |
1156 | * Also, we've got to be careful not to trash gate | |
1157 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1158 | */ | |
54168ed7 IM |
1159 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1160 | unsigned int old_vector; | |
22f65d31 MT |
1161 | int cpu, err; |
1162 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1163 | |
23359a88 | 1164 | if (cfg->move_in_progress) |
54168ed7 | 1165 | return -EBUSY; |
0a1ad60d | 1166 | |
22f65d31 MT |
1167 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1168 | return -ENOMEM; | |
ace80ab7 | 1169 | |
54168ed7 IM |
1170 | old_vector = cfg->vector; |
1171 | if (old_vector) { | |
22f65d31 MT |
1172 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1173 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1174 | if (!cpumask_empty(tmp_mask)) { | |
1175 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1176 | return 0; |
22f65d31 | 1177 | } |
54168ed7 | 1178 | } |
497c9a19 | 1179 | |
e7986739 | 1180 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1181 | err = -ENOSPC; |
1182 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1183 | int new_cpu; |
1184 | int vector, offset; | |
497c9a19 | 1185 | |
e2d40b18 | 1186 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1187 | |
54168ed7 IM |
1188 | vector = current_vector; |
1189 | offset = current_offset; | |
497c9a19 | 1190 | next: |
54168ed7 IM |
1191 | vector += 8; |
1192 | if (vector >= first_system_vector) { | |
e7986739 | 1193 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1194 | offset = (offset + 1) % 8; |
1195 | vector = FIRST_DEVICE_VECTOR + offset; | |
1196 | } | |
1197 | if (unlikely(current_vector == vector)) | |
1198 | continue; | |
b77b881f YL |
1199 | |
1200 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1201 | goto next; |
b77b881f | 1202 | |
22f65d31 | 1203 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1204 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1205 | goto next; | |
1206 | /* Found one! */ | |
1207 | current_vector = vector; | |
1208 | current_offset = offset; | |
1209 | if (old_vector) { | |
1210 | cfg->move_in_progress = 1; | |
22f65d31 | 1211 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1212 | } |
22f65d31 | 1213 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1214 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1215 | cfg->vector = vector; | |
22f65d31 MT |
1216 | cpumask_copy(cfg->domain, tmp_mask); |
1217 | err = 0; | |
1218 | break; | |
54168ed7 | 1219 | } |
22f65d31 MT |
1220 | free_cpumask_var(tmp_mask); |
1221 | return err; | |
497c9a19 YL |
1222 | } |
1223 | ||
9338ad6f | 1224 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1225 | { |
1226 | int err; | |
ace80ab7 | 1227 | unsigned long flags; |
ace80ab7 EB |
1228 | |
1229 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1230 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1231 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1232 | return err; |
1233 | } | |
1234 | ||
3145e941 | 1235 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1236 | { |
497c9a19 YL |
1237 | int cpu, vector; |
1238 | ||
497c9a19 YL |
1239 | BUG_ON(!cfg->vector); |
1240 | ||
1241 | vector = cfg->vector; | |
22f65d31 | 1242 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1243 | per_cpu(vector_irq, cpu)[vector] = -1; |
1244 | ||
1245 | cfg->vector = 0; | |
22f65d31 | 1246 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1247 | |
1248 | if (likely(!cfg->move_in_progress)) | |
1249 | return; | |
22f65d31 | 1250 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1251 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1252 | vector++) { | |
1253 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1254 | continue; | |
1255 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1256 | break; | |
1257 | } | |
1258 | } | |
1259 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1260 | } |
1261 | ||
1262 | void __setup_vector_irq(int cpu) | |
1263 | { | |
1264 | /* Initialize vector_irq on a new cpu */ | |
1265 | /* This function must be called with vector_lock held */ | |
1266 | int irq, vector; | |
1267 | struct irq_cfg *cfg; | |
0b8f1efa | 1268 | struct irq_desc *desc; |
497c9a19 YL |
1269 | |
1270 | /* Mark the inuse vectors */ | |
0b8f1efa | 1271 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1272 | cfg = desc->chip_data; |
22f65d31 | 1273 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1274 | continue; |
1275 | vector = cfg->vector; | |
497c9a19 YL |
1276 | per_cpu(vector_irq, cpu)[vector] = irq; |
1277 | } | |
1278 | /* Mark the free vectors */ | |
1279 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1280 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1281 | if (irq < 0) | |
1282 | continue; | |
1283 | ||
1284 | cfg = irq_cfg(irq); | |
22f65d31 | 1285 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1286 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1287 | } |
1da177e4 | 1288 | } |
3fde6900 | 1289 | |
f5b9ed7a | 1290 | static struct irq_chip ioapic_chip; |
54168ed7 | 1291 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1292 | |
54168ed7 IM |
1293 | #define IOAPIC_AUTO -1 |
1294 | #define IOAPIC_EDGE 0 | |
1295 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1296 | |
047c8fdb | 1297 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1298 | static inline int IO_APIC_irq_trigger(int irq) |
1299 | { | |
d6c88a50 | 1300 | int apic, idx, pin; |
1d025192 | 1301 | |
d6c88a50 TG |
1302 | for (apic = 0; apic < nr_ioapics; apic++) { |
1303 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1304 | idx = find_irq_entry(apic, pin, mp_INT); | |
1305 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1306 | return irq_trigger(idx); | |
1307 | } | |
1308 | } | |
1309 | /* | |
54168ed7 IM |
1310 | * nonexistent IRQs are edge default |
1311 | */ | |
d6c88a50 | 1312 | return 0; |
1d025192 | 1313 | } |
047c8fdb YL |
1314 | #else |
1315 | static inline int IO_APIC_irq_trigger(int irq) | |
1316 | { | |
54168ed7 | 1317 | return 1; |
047c8fdb YL |
1318 | } |
1319 | #endif | |
1d025192 | 1320 | |
3145e941 | 1321 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1322 | { |
199751d7 | 1323 | |
6ebcc00e | 1324 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1325 | trigger == IOAPIC_LEVEL) |
08678b08 | 1326 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1327 | else |
1328 | desc->status &= ~IRQ_LEVEL; | |
1329 | ||
54168ed7 IM |
1330 | if (irq_remapped(irq)) { |
1331 | desc->status |= IRQ_MOVE_PCNTXT; | |
1332 | if (trigger) | |
1333 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1334 | handle_fasteoi_irq, | |
1335 | "fasteoi"); | |
1336 | else | |
1337 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1338 | handle_edge_irq, "edge"); | |
1339 | return; | |
1340 | } | |
29b61be6 | 1341 | |
047c8fdb YL |
1342 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1343 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1344 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1345 | handle_fasteoi_irq, |
1346 | "fasteoi"); | |
047c8fdb | 1347 | else |
a460e745 | 1348 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1349 | handle_edge_irq, "edge"); |
1da177e4 LT |
1350 | } |
1351 | ||
ca97ab90 JF |
1352 | int setup_ioapic_entry(int apic_id, int irq, |
1353 | struct IO_APIC_route_entry *entry, | |
1354 | unsigned int destination, int trigger, | |
0280f7c4 | 1355 | int polarity, int vector, int pin) |
1da177e4 | 1356 | { |
497c9a19 YL |
1357 | /* |
1358 | * add it to the IO-APIC irq-routing table: | |
1359 | */ | |
1360 | memset(entry,0,sizeof(*entry)); | |
1361 | ||
54168ed7 | 1362 | if (intr_remapping_enabled) { |
c8d46cf0 | 1363 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1364 | struct irte irte; |
1365 | struct IR_IO_APIC_route_entry *ir_entry = | |
1366 | (struct IR_IO_APIC_route_entry *) entry; | |
1367 | int index; | |
1368 | ||
1369 | if (!iommu) | |
c8d46cf0 | 1370 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1371 | |
1372 | index = alloc_irte(iommu, irq, 1); | |
1373 | if (index < 0) | |
c8d46cf0 | 1374 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1375 | |
1376 | memset(&irte, 0, sizeof(irte)); | |
1377 | ||
1378 | irte.present = 1; | |
9b5bc8dc | 1379 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1380 | /* |
1381 | * Trigger mode in the IRTE will always be edge, and the | |
1382 | * actual level or edge trigger will be setup in the IO-APIC | |
1383 | * RTE. This will help simplify level triggered irq migration. | |
1384 | * For more details, see the comments above explainig IO-APIC | |
1385 | * irq migration in the presence of interrupt-remapping. | |
1386 | */ | |
1387 | irte.trigger_mode = 0; | |
9b5bc8dc | 1388 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1389 | irte.vector = vector; |
1390 | irte.dest_id = IRTE_DEST(destination); | |
1391 | ||
f007e99c WH |
1392 | /* Set source-id of interrupt request */ |
1393 | set_ioapic_sid(&irte, apic_id); | |
1394 | ||
54168ed7 IM |
1395 | modify_irte(irq, &irte); |
1396 | ||
1397 | ir_entry->index2 = (index >> 15) & 0x1; | |
1398 | ir_entry->zero = 0; | |
1399 | ir_entry->format = 1; | |
1400 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1401 | /* |
1402 | * IO-APIC RTE will be configured with virtual vector. | |
1403 | * irq handler will do the explicit EOI to the io-apic. | |
1404 | */ | |
1405 | ir_entry->vector = pin; | |
29b61be6 | 1406 | } else { |
9b5bc8dc IM |
1407 | entry->delivery_mode = apic->irq_delivery_mode; |
1408 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1409 | entry->dest = destination; |
0280f7c4 | 1410 | entry->vector = vector; |
54168ed7 | 1411 | } |
497c9a19 | 1412 | |
54168ed7 | 1413 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1414 | entry->trigger = trigger; |
1415 | entry->polarity = polarity; | |
497c9a19 YL |
1416 | |
1417 | /* Mask level triggered irqs. | |
1418 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1419 | */ | |
1420 | if (trigger) | |
1421 | entry->mask = 1; | |
497c9a19 YL |
1422 | return 0; |
1423 | } | |
1424 | ||
c8d46cf0 | 1425 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1426 | int trigger, int polarity) |
497c9a19 YL |
1427 | { |
1428 | struct irq_cfg *cfg; | |
1da177e4 | 1429 | struct IO_APIC_route_entry entry; |
22f65d31 | 1430 | unsigned int dest; |
497c9a19 YL |
1431 | |
1432 | if (!IO_APIC_IRQ(irq)) | |
1433 | return; | |
1434 | ||
3145e941 | 1435 | cfg = desc->chip_data; |
497c9a19 | 1436 | |
fe402e1f | 1437 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1438 | return; |
1439 | ||
debccb3e | 1440 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1441 | |
1442 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1443 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1444 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1445 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1446 | irq, trigger, polarity); |
1447 | ||
1448 | ||
c8d46cf0 | 1449 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1450 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1451 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1452 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1453 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1454 | return; |
1455 | } | |
1456 | ||
3145e941 | 1457 | ioapic_register_intr(irq, desc, trigger); |
bc07844a | 1458 | if (irq < nr_legacy_irqs) |
497c9a19 YL |
1459 | disable_8259A_irq(irq); |
1460 | ||
c8d46cf0 | 1461 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1462 | } |
1463 | ||
b9c61b70 YL |
1464 | static struct { |
1465 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1466 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1467 | ||
497c9a19 YL |
1468 | static void __init setup_IO_APIC_irqs(void) |
1469 | { | |
b9c61b70 | 1470 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1471 | int notcon = 0; |
0b8f1efa | 1472 | struct irq_desc *desc; |
3145e941 | 1473 | struct irq_cfg *cfg; |
85ac16d0 | 1474 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1475 | |
1476 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1477 | ||
b9c61b70 YL |
1478 | #ifdef CONFIG_ACPI |
1479 | if (!acpi_disabled && acpi_ioapic) { | |
1480 | apic_id = mp_find_ioapic(0); | |
1481 | if (apic_id < 0) | |
1482 | apic_id = 0; | |
1483 | } | |
1484 | #endif | |
3c2cbd24 | 1485 | |
b9c61b70 YL |
1486 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1487 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1488 | if (idx == -1) { | |
1489 | if (!notcon) { | |
1490 | notcon = 1; | |
1491 | apic_printk(APIC_VERBOSE, | |
1492 | KERN_DEBUG " %d-%d", | |
1493 | mp_ioapics[apic_id].apicid, pin); | |
1494 | } else | |
1495 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1496 | mp_ioapics[apic_id].apicid, pin); | |
1497 | continue; | |
1498 | } | |
1499 | if (notcon) { | |
1500 | apic_printk(APIC_VERBOSE, | |
1501 | " (apicid-pin) not connected\n"); | |
1502 | notcon = 0; | |
1503 | } | |
33a201fa | 1504 | |
b9c61b70 | 1505 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1506 | |
b9c61b70 YL |
1507 | /* |
1508 | * Skip the timer IRQ if there's a quirk handler | |
1509 | * installed and if it returns 1: | |
1510 | */ | |
1511 | if (apic->multi_timer_check && | |
1512 | apic->multi_timer_check(apic_id, irq)) | |
1513 | continue; | |
36062448 | 1514 | |
b9c61b70 YL |
1515 | desc = irq_to_desc_alloc_node(irq, node); |
1516 | if (!desc) { | |
1517 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1518 | continue; | |
3c2cbd24 | 1519 | } |
b9c61b70 YL |
1520 | cfg = desc->chip_data; |
1521 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1522 | /* |
1523 | * don't mark it in pin_programmed, so later acpi could | |
1524 | * set it correctly when irq < 16 | |
1525 | */ | |
b9c61b70 YL |
1526 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1527 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1528 | } |
1529 | ||
3c2cbd24 CG |
1530 | if (notcon) |
1531 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1532 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1533 | } |
1534 | ||
1535 | /* | |
f7633ce5 | 1536 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1537 | */ |
c8d46cf0 | 1538 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1539 | int vector) |
1da177e4 LT |
1540 | { |
1541 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1542 | |
54168ed7 IM |
1543 | if (intr_remapping_enabled) |
1544 | return; | |
54168ed7 | 1545 | |
36062448 | 1546 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1547 | |
1548 | /* | |
1549 | * We use logical delivery to get the timer IRQ | |
1550 | * to the first CPU. | |
1551 | */ | |
9b5bc8dc | 1552 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1553 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1554 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1555 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1556 | entry.polarity = 0; |
1557 | entry.trigger = 0; | |
1558 | entry.vector = vector; | |
1559 | ||
1560 | /* | |
1561 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1562 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1563 | */ |
54168ed7 | 1564 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1565 | |
1566 | /* | |
1567 | * Add it to the IO-APIC irq-routing table: | |
1568 | */ | |
c8d46cf0 | 1569 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1570 | } |
1571 | ||
32f71aff MR |
1572 | |
1573 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1574 | { |
1575 | int apic, i; | |
1576 | union IO_APIC_reg_00 reg_00; | |
1577 | union IO_APIC_reg_01 reg_01; | |
1578 | union IO_APIC_reg_02 reg_02; | |
1579 | union IO_APIC_reg_03 reg_03; | |
1580 | unsigned long flags; | |
0f978f45 | 1581 | struct irq_cfg *cfg; |
0b8f1efa | 1582 | struct irq_desc *desc; |
8f09cd20 | 1583 | unsigned int irq; |
1da177e4 | 1584 | |
36062448 | 1585 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1586 | for (i = 0; i < nr_ioapics; i++) |
1587 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1588 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1589 | |
1590 | /* | |
1591 | * We are a bit conservative about what we expect. We have to | |
1592 | * know about every hardware change ASAP. | |
1593 | */ | |
1594 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1595 | ||
1596 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1597 | ||
1598 | spin_lock_irqsave(&ioapic_lock, flags); | |
1599 | reg_00.raw = io_apic_read(apic, 0); | |
1600 | reg_01.raw = io_apic_read(apic, 1); | |
1601 | if (reg_01.bits.version >= 0x10) | |
1602 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1603 | if (reg_01.bits.version >= 0x20) |
1604 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1605 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1606 | ||
54168ed7 | 1607 | printk("\n"); |
b5ba7e6d | 1608 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1609 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1610 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1611 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1612 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1613 | |
54168ed7 | 1614 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1615 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1616 | |
1617 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1618 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1619 | |
1620 | /* | |
1621 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1622 | * but the value of reg_02 is read as the previous read register | |
1623 | * value, so ignore it if reg_02 == reg_01. | |
1624 | */ | |
1625 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1626 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1627 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1628 | } |
1629 | ||
1630 | /* | |
1631 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1632 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1633 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1634 | */ | |
1635 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1636 | reg_03.raw != reg_01.raw) { | |
1637 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1638 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1639 | } |
1640 | ||
1641 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1642 | ||
d83e94ac YL |
1643 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1644 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1645 | |
1646 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1647 | struct IO_APIC_route_entry entry; | |
1648 | ||
cf4c6a2f | 1649 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1650 | |
54168ed7 IM |
1651 | printk(KERN_DEBUG " %02x %03X ", |
1652 | i, | |
1653 | entry.dest | |
1654 | ); | |
1da177e4 LT |
1655 | |
1656 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1657 | entry.mask, | |
1658 | entry.trigger, | |
1659 | entry.irr, | |
1660 | entry.polarity, | |
1661 | entry.delivery_status, | |
1662 | entry.dest_mode, | |
1663 | entry.delivery_mode, | |
1664 | entry.vector | |
1665 | ); | |
1666 | } | |
1667 | } | |
1da177e4 | 1668 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1669 | for_each_irq_desc(irq, desc) { |
1670 | struct irq_pin_list *entry; | |
1671 | ||
0b8f1efa YL |
1672 | cfg = desc->chip_data; |
1673 | entry = cfg->irq_2_pin; | |
0f978f45 | 1674 | if (!entry) |
1da177e4 | 1675 | continue; |
8f09cd20 | 1676 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1677 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1678 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1679 | printk("\n"); |
1680 | } | |
1681 | ||
1682 | printk(KERN_INFO ".................................... done.\n"); | |
1683 | ||
1684 | return; | |
1685 | } | |
1686 | ||
251e1e44 | 1687 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1688 | { |
251e1e44 | 1689 | int i; |
1da177e4 | 1690 | |
251e1e44 IM |
1691 | printk(KERN_DEBUG); |
1692 | ||
1693 | for (i = 0; i < 8; i++) | |
1694 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1695 | ||
1696 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1697 | } |
1698 | ||
32f71aff | 1699 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1700 | { |
97a52714 | 1701 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1702 | u64 icr; |
1da177e4 | 1703 | |
251e1e44 | 1704 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1705 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1706 | v = apic_read(APIC_ID); |
54168ed7 | 1707 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1708 | v = apic_read(APIC_LVR); |
1709 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1710 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1711 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1712 | |
1713 | v = apic_read(APIC_TASKPRI); | |
1714 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1715 | ||
54168ed7 | 1716 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1717 | if (!APIC_XAPIC(ver)) { |
1718 | v = apic_read(APIC_ARBPRI); | |
1719 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1720 | v & APIC_ARBPRI_MASK); | |
1721 | } | |
1da177e4 LT |
1722 | v = apic_read(APIC_PROCPRI); |
1723 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1724 | } | |
1725 | ||
a11b5abe YL |
1726 | /* |
1727 | * Remote read supported only in the 82489DX and local APIC for | |
1728 | * Pentium processors. | |
1729 | */ | |
1730 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1731 | v = apic_read(APIC_RRR); | |
1732 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1733 | } | |
1734 | ||
1da177e4 LT |
1735 | v = apic_read(APIC_LDR); |
1736 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1737 | if (!x2apic_enabled()) { |
1738 | v = apic_read(APIC_DFR); | |
1739 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1740 | } | |
1da177e4 LT |
1741 | v = apic_read(APIC_SPIV); |
1742 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1743 | ||
1744 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1745 | print_APIC_field(APIC_ISR); |
1da177e4 | 1746 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1747 | print_APIC_field(APIC_TMR); |
1da177e4 | 1748 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1749 | print_APIC_field(APIC_IRR); |
1da177e4 | 1750 | |
54168ed7 IM |
1751 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1752 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1753 | apic_write(APIC_ESR, 0); |
54168ed7 | 1754 | |
1da177e4 LT |
1755 | v = apic_read(APIC_ESR); |
1756 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1757 | } | |
1758 | ||
7ab6af7a | 1759 | icr = apic_icr_read(); |
0c425cec IM |
1760 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1761 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1762 | |
1763 | v = apic_read(APIC_LVTT); | |
1764 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1765 | ||
1766 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1767 | v = apic_read(APIC_LVTPC); | |
1768 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1769 | } | |
1770 | v = apic_read(APIC_LVT0); | |
1771 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1772 | v = apic_read(APIC_LVT1); | |
1773 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1774 | ||
1775 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1776 | v = apic_read(APIC_LVTERR); | |
1777 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1778 | } | |
1779 | ||
1780 | v = apic_read(APIC_TMICT); | |
1781 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1782 | v = apic_read(APIC_TMCCT); | |
1783 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1784 | v = apic_read(APIC_TDCR); | |
1785 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1786 | |
1787 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1788 | v = apic_read(APIC_EFEAT); | |
1789 | maxlvt = (v >> 16) & 0xff; | |
1790 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1791 | v = apic_read(APIC_ECTRL); | |
1792 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1793 | for (i = 0; i < maxlvt; i++) { | |
1794 | v = apic_read(APIC_EILVTn(i)); | |
1795 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1796 | } | |
1797 | } | |
1da177e4 LT |
1798 | printk("\n"); |
1799 | } | |
1800 | ||
2626eb2b | 1801 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1802 | { |
ffd5aae7 YL |
1803 | int cpu; |
1804 | ||
2626eb2b CG |
1805 | if (!maxcpu) |
1806 | return; | |
1807 | ||
ffd5aae7 | 1808 | preempt_disable(); |
2626eb2b CG |
1809 | for_each_online_cpu(cpu) { |
1810 | if (cpu >= maxcpu) | |
1811 | break; | |
ffd5aae7 | 1812 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1813 | } |
ffd5aae7 | 1814 | preempt_enable(); |
1da177e4 LT |
1815 | } |
1816 | ||
32f71aff | 1817 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1818 | { |
1da177e4 LT |
1819 | unsigned int v; |
1820 | unsigned long flags; | |
1821 | ||
2626eb2b | 1822 | if (!nr_legacy_irqs) |
1da177e4 LT |
1823 | return; |
1824 | ||
1825 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1826 | ||
1827 | spin_lock_irqsave(&i8259A_lock, flags); | |
1828 | ||
1829 | v = inb(0xa1) << 8 | inb(0x21); | |
1830 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1831 | ||
1832 | v = inb(0xa0) << 8 | inb(0x20); | |
1833 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1834 | ||
54168ed7 IM |
1835 | outb(0x0b,0xa0); |
1836 | outb(0x0b,0x20); | |
1da177e4 | 1837 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1838 | outb(0x0a,0xa0); |
1839 | outb(0x0a,0x20); | |
1da177e4 LT |
1840 | |
1841 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1842 | ||
1843 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1844 | ||
1845 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1846 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1847 | } | |
1848 | ||
2626eb2b CG |
1849 | static int __initdata show_lapic = 1; |
1850 | static __init int setup_show_lapic(char *arg) | |
1851 | { | |
1852 | int num = -1; | |
1853 | ||
1854 | if (strcmp(arg, "all") == 0) { | |
1855 | show_lapic = CONFIG_NR_CPUS; | |
1856 | } else { | |
1857 | get_option(&arg, &num); | |
1858 | if (num >= 0) | |
1859 | show_lapic = num; | |
1860 | } | |
1861 | ||
1862 | return 1; | |
1863 | } | |
1864 | __setup("show_lapic=", setup_show_lapic); | |
1865 | ||
1866 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1867 | { |
2626eb2b CG |
1868 | if (apic_verbosity == APIC_QUIET) |
1869 | return 0; | |
1870 | ||
32f71aff | 1871 | print_PIC(); |
4797f6b0 YL |
1872 | |
1873 | /* don't print out if apic is not there */ | |
8312136f | 1874 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1875 | return 0; |
1876 | ||
2626eb2b | 1877 | print_local_APICs(show_lapic); |
32f71aff MR |
1878 | print_IO_APIC(); |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
2626eb2b | 1883 | fs_initcall(print_ICs); |
32f71aff | 1884 | |
1da177e4 | 1885 | |
efa2559f YL |
1886 | /* Where if anywhere is the i8259 connect in external int mode */ |
1887 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1888 | ||
54168ed7 | 1889 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1890 | { |
1891 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1892 | int i8259_apic, i8259_pin; |
54168ed7 | 1893 | int apic; |
1da177e4 LT |
1894 | unsigned long flags; |
1895 | ||
1da177e4 LT |
1896 | /* |
1897 | * The number of IO-APIC IRQ registers (== #pins): | |
1898 | */ | |
fcfd636a | 1899 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1900 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1901 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1902 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1903 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1904 | } | |
bc07844a TG |
1905 | |
1906 | if (!nr_legacy_irqs) | |
1907 | return; | |
1908 | ||
54168ed7 | 1909 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1910 | int pin; |
1911 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1912 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1913 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1914 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1915 | |
fcfd636a EB |
1916 | /* If the interrupt line is enabled and in ExtInt mode |
1917 | * I have found the pin where the i8259 is connected. | |
1918 | */ | |
1919 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1920 | ioapic_i8259.apic = apic; | |
1921 | ioapic_i8259.pin = pin; | |
1922 | goto found_i8259; | |
1923 | } | |
1924 | } | |
1925 | } | |
1926 | found_i8259: | |
1927 | /* Look to see what if the MP table has reported the ExtINT */ | |
1928 | /* If we could not find the appropriate pin by looking at the ioapic | |
1929 | * the i8259 probably is not connected the ioapic but give the | |
1930 | * mptable a chance anyway. | |
1931 | */ | |
1932 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1933 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1934 | /* Trust the MP table if nothing is setup in the hardware */ | |
1935 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1936 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1937 | ioapic_i8259.pin = i8259_pin; | |
1938 | ioapic_i8259.apic = i8259_apic; | |
1939 | } | |
1940 | /* Complain if the MP table and the hardware disagree */ | |
1941 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1942 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1943 | { | |
1944 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1945 | } |
1946 | ||
1947 | /* | |
1948 | * Do not trust the IO-APIC being empty at bootup | |
1949 | */ | |
1950 | clear_IO_APIC(); | |
1951 | } | |
1952 | ||
1953 | /* | |
1954 | * Not an __init, needed by the reboot code | |
1955 | */ | |
1956 | void disable_IO_APIC(void) | |
1957 | { | |
1958 | /* | |
1959 | * Clear the IO-APIC before rebooting: | |
1960 | */ | |
1961 | clear_IO_APIC(); | |
1962 | ||
bc07844a TG |
1963 | if (!nr_legacy_irqs) |
1964 | return; | |
1965 | ||
650927ef | 1966 | /* |
0b968d23 | 1967 | * If the i8259 is routed through an IOAPIC |
650927ef | 1968 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1969 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1970 | * |
1971 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1972 | * as virtual wire B is little complex (need to configure both | |
1973 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1974 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1975 | */ |
7c6d9f97 | 1976 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1977 | struct IO_APIC_route_entry entry; |
650927ef EB |
1978 | |
1979 | memset(&entry, 0, sizeof(entry)); | |
1980 | entry.mask = 0; /* Enabled */ | |
1981 | entry.trigger = 0; /* Edge */ | |
1982 | entry.irr = 0; | |
1983 | entry.polarity = 0; /* High */ | |
1984 | entry.delivery_status = 0; | |
1985 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1986 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1987 | entry.vector = 0; |
54168ed7 | 1988 | entry.dest = read_apic_id(); |
650927ef EB |
1989 | |
1990 | /* | |
1991 | * Add it to the IO-APIC irq-routing table: | |
1992 | */ | |
cf4c6a2f | 1993 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1994 | } |
54168ed7 | 1995 | |
7c6d9f97 SS |
1996 | /* |
1997 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1998 | */ | |
8312136f | 1999 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2000 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2001 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2002 | } |
2003 | ||
54168ed7 | 2004 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2005 | /* |
2006 | * function to set the IO-APIC physical IDs based on the | |
2007 | * values stored in the MPC table. | |
2008 | * | |
2009 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2010 | */ | |
2011 | ||
de934103 | 2012 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2013 | { |
2014 | union IO_APIC_reg_00 reg_00; | |
2015 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2016 | int apic_id; |
1da177e4 LT |
2017 | int i; |
2018 | unsigned char old_id; | |
2019 | unsigned long flags; | |
2020 | ||
de934103 | 2021 | if (acpi_ioapic) |
d49c4288 | 2022 | return; |
ca05fea6 NP |
2023 | /* |
2024 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2025 | * no meaning without the serial APIC bus. | |
2026 | */ | |
7c5c1e42 SL |
2027 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2028 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2029 | return; |
1da177e4 LT |
2030 | /* |
2031 | * This is broken; anything with a real cpu count has to | |
2032 | * circumvent this idiocy regardless. | |
2033 | */ | |
d190cb87 | 2034 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2035 | |
2036 | /* | |
2037 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2038 | */ | |
c8d46cf0 | 2039 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2040 | |
2041 | /* Read the register 0 value */ | |
2042 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2043 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2044 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2045 | |
c8d46cf0 | 2046 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2047 | |
c8d46cf0 | 2048 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2049 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2050 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2051 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2052 | reg_00.bits.ID); | |
c8d46cf0 | 2053 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2054 | } |
2055 | ||
1da177e4 LT |
2056 | /* |
2057 | * Sanity check, is the ID really free? Every APIC in a | |
2058 | * system must have a unique ID or we get lots of nice | |
2059 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2060 | */ | |
d1d7cae8 | 2061 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2062 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2063 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2064 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2065 | for (i = 0; i < get_physical_broadcast(); i++) |
2066 | if (!physid_isset(i, phys_id_present_map)) | |
2067 | break; | |
2068 | if (i >= get_physical_broadcast()) | |
2069 | panic("Max APIC ID exceeded!\n"); | |
2070 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2071 | i); | |
2072 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2073 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2074 | } else { |
2075 | physid_mask_t tmp; | |
8058714a | 2076 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2077 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2078 | "phys_id_present_map\n", | |
c8d46cf0 | 2079 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2080 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2081 | } | |
2082 | ||
2083 | ||
2084 | /* | |
2085 | * We need to adjust the IRQ routing table | |
2086 | * if the ID changed. | |
2087 | */ | |
c8d46cf0 | 2088 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2089 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2090 | if (mp_irqs[i].dstapic == old_id) |
2091 | mp_irqs[i].dstapic | |
c8d46cf0 | 2092 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2093 | |
2094 | /* | |
2095 | * Read the right value from the MPC table and | |
2096 | * write it into the ID register. | |
36062448 | 2097 | */ |
1da177e4 LT |
2098 | apic_printk(APIC_VERBOSE, KERN_INFO |
2099 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2100 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2101 | |
c8d46cf0 | 2102 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2103 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2104 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2105 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2106 | |
2107 | /* | |
2108 | * Sanity check | |
2109 | */ | |
2110 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2111 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2112 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2113 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2114 | printk("could not set ID!\n"); |
2115 | else | |
2116 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2117 | } | |
2118 | } | |
54168ed7 | 2119 | #endif |
1da177e4 | 2120 | |
7ce0bcfd | 2121 | int no_timer_check __initdata; |
8542b200 ZA |
2122 | |
2123 | static int __init notimercheck(char *s) | |
2124 | { | |
2125 | no_timer_check = 1; | |
2126 | return 1; | |
2127 | } | |
2128 | __setup("no_timer_check", notimercheck); | |
2129 | ||
1da177e4 LT |
2130 | /* |
2131 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2132 | * about the timer IRQ. We do the following to work around the situation: | |
2133 | * | |
2134 | * - timer IRQ defaults to IO-APIC IRQ | |
2135 | * - if this function detects that timer IRQs are defunct, then we fall | |
2136 | * back to ISA timer IRQs | |
2137 | */ | |
f0a7a5c9 | 2138 | static int __init timer_irq_works(void) |
1da177e4 LT |
2139 | { |
2140 | unsigned long t1 = jiffies; | |
4aae0702 | 2141 | unsigned long flags; |
1da177e4 | 2142 | |
8542b200 ZA |
2143 | if (no_timer_check) |
2144 | return 1; | |
2145 | ||
4aae0702 | 2146 | local_save_flags(flags); |
1da177e4 LT |
2147 | local_irq_enable(); |
2148 | /* Let ten ticks pass... */ | |
2149 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2150 | local_irq_restore(flags); |
1da177e4 LT |
2151 | |
2152 | /* | |
2153 | * Expect a few ticks at least, to be sure some possible | |
2154 | * glue logic does not lock up after one or two first | |
2155 | * ticks in a non-ExtINT mode. Also the local APIC | |
2156 | * might have cached one ExtINT interrupt. Finally, at | |
2157 | * least one tick may be lost due to delays. | |
2158 | */ | |
54168ed7 IM |
2159 | |
2160 | /* jiffies wrap? */ | |
1d16b53e | 2161 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2162 | return 1; |
1da177e4 LT |
2163 | return 0; |
2164 | } | |
2165 | ||
2166 | /* | |
2167 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2168 | * number of pending IRQ events unhandled. These cases are very rare, | |
2169 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2170 | * better to do it this way as thus we do not have to be aware of | |
2171 | * 'pending' interrupts in the IRQ path, except at this point. | |
2172 | */ | |
2173 | /* | |
2174 | * Edge triggered needs to resend any interrupt | |
2175 | * that was delayed but this is now handled in the device | |
2176 | * independent code. | |
2177 | */ | |
2178 | ||
2179 | /* | |
2180 | * Starting up a edge-triggered IO-APIC interrupt is | |
2181 | * nasty - we need to make sure that we get the edge. | |
2182 | * If it is already asserted for some reason, we need | |
2183 | * return 1 to indicate that is was pending. | |
2184 | * | |
2185 | * This is not complete - we should be able to fake | |
2186 | * an edge even if it isn't on the 8259A... | |
2187 | */ | |
54168ed7 | 2188 | |
f5b9ed7a | 2189 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2190 | { |
2191 | int was_pending = 0; | |
2192 | unsigned long flags; | |
0b8f1efa | 2193 | struct irq_cfg *cfg; |
1da177e4 LT |
2194 | |
2195 | spin_lock_irqsave(&ioapic_lock, flags); | |
bc07844a | 2196 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
2197 | disable_8259A_irq(irq); |
2198 | if (i8259A_irq_pending(irq)) | |
2199 | was_pending = 1; | |
2200 | } | |
0b8f1efa | 2201 | cfg = irq_cfg(irq); |
3145e941 | 2202 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2203 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2204 | ||
2205 | return was_pending; | |
2206 | } | |
2207 | ||
ace80ab7 | 2208 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2209 | { |
54168ed7 IM |
2210 | |
2211 | struct irq_cfg *cfg = irq_cfg(irq); | |
2212 | unsigned long flags; | |
2213 | ||
2214 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2215 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2216 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2217 | |
2218 | return 1; | |
2219 | } | |
497c9a19 | 2220 | |
54168ed7 IM |
2221 | /* |
2222 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2223 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2224 | * handled with the level-triggered descriptor, but that one has slightly | |
2225 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2226 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2227 | * races. | |
2228 | */ | |
497c9a19 | 2229 | |
54168ed7 | 2230 | #ifdef CONFIG_SMP |
9338ad6f | 2231 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2232 | { |
2233 | cpumask_var_t cleanup_mask; | |
2234 | ||
2235 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2236 | unsigned int i; | |
e85abf8f GH |
2237 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2238 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2239 | } else { | |
2240 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2241 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2242 | free_cpumask_var(cleanup_mask); | |
2243 | } | |
2244 | cfg->move_in_progress = 0; | |
2245 | } | |
2246 | ||
4420471f | 2247 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2248 | { |
2249 | int apic, pin; | |
2250 | struct irq_pin_list *entry; | |
2251 | u8 vector = cfg->vector; | |
2252 | ||
2977fb3f | 2253 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2254 | unsigned int reg; |
2255 | ||
e85abf8f GH |
2256 | apic = entry->apic; |
2257 | pin = entry->pin; | |
2258 | /* | |
2259 | * With interrupt-remapping, destination information comes | |
2260 | * from interrupt-remapping table entry. | |
2261 | */ | |
2262 | if (!irq_remapped(irq)) | |
2263 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2264 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2265 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2266 | reg |= vector; | |
2267 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2268 | } |
2269 | } | |
2270 | ||
2271 | /* | |
2272 | * Either sets desc->affinity to a valid value, and returns | |
2273 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2274 | * leaves desc->affinity untouched. | |
2275 | */ | |
9338ad6f | 2276 | unsigned int |
e85abf8f GH |
2277 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) |
2278 | { | |
2279 | struct irq_cfg *cfg; | |
2280 | unsigned int irq; | |
2281 | ||
2282 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2283 | return BAD_APICID; | |
2284 | ||
2285 | irq = desc->irq; | |
2286 | cfg = desc->chip_data; | |
2287 | if (assign_irq_vector(irq, cfg, mask)) | |
2288 | return BAD_APICID; | |
2289 | ||
e85abf8f GH |
2290 | cpumask_copy(desc->affinity, mask); |
2291 | ||
2292 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2293 | } | |
2294 | ||
4420471f | 2295 | static int |
e85abf8f GH |
2296 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2297 | { | |
2298 | struct irq_cfg *cfg; | |
2299 | unsigned long flags; | |
2300 | unsigned int dest; | |
2301 | unsigned int irq; | |
4420471f | 2302 | int ret = -1; |
e85abf8f GH |
2303 | |
2304 | irq = desc->irq; | |
2305 | cfg = desc->chip_data; | |
2306 | ||
2307 | spin_lock_irqsave(&ioapic_lock, flags); | |
2308 | dest = set_desc_affinity(desc, mask); | |
2309 | if (dest != BAD_APICID) { | |
2310 | /* Only the high 8 bits are valid. */ | |
2311 | dest = SET_APIC_LOGICAL_ID(dest); | |
2312 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2313 | ret = 0; |
e85abf8f GH |
2314 | } |
2315 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2316 | |
2317 | return ret; | |
e85abf8f GH |
2318 | } |
2319 | ||
4420471f | 2320 | static int |
e85abf8f GH |
2321 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2322 | { | |
2323 | struct irq_desc *desc; | |
2324 | ||
2325 | desc = irq_to_desc(irq); | |
2326 | ||
4420471f | 2327 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2328 | } |
497c9a19 | 2329 | |
54168ed7 | 2330 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2331 | |
54168ed7 IM |
2332 | /* |
2333 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2334 | * | |
0280f7c4 SS |
2335 | * For both level and edge triggered, irq migration is a simple atomic |
2336 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2337 | * |
0280f7c4 SS |
2338 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2339 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2340 | * Real vector that is used for interrupting cpu will be coming from | |
2341 | * the interrupt-remapping table entry. | |
54168ed7 | 2342 | */ |
d5dedd45 | 2343 | static int |
e7986739 | 2344 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2345 | { |
54168ed7 | 2346 | struct irq_cfg *cfg; |
54168ed7 | 2347 | struct irte irte; |
54168ed7 | 2348 | unsigned int dest; |
3145e941 | 2349 | unsigned int irq; |
d5dedd45 | 2350 | int ret = -1; |
497c9a19 | 2351 | |
22f65d31 | 2352 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2353 | return ret; |
497c9a19 | 2354 | |
3145e941 | 2355 | irq = desc->irq; |
54168ed7 | 2356 | if (get_irte(irq, &irte)) |
d5dedd45 | 2357 | return ret; |
497c9a19 | 2358 | |
3145e941 YL |
2359 | cfg = desc->chip_data; |
2360 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2361 | return ret; |
54168ed7 | 2362 | |
debccb3e | 2363 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2364 | |
54168ed7 IM |
2365 | irte.vector = cfg->vector; |
2366 | irte.dest_id = IRTE_DEST(dest); | |
2367 | ||
2368 | /* | |
2369 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2370 | */ | |
2371 | modify_irte(irq, &irte); | |
2372 | ||
22f65d31 MT |
2373 | if (cfg->move_in_progress) |
2374 | send_cleanup_vector(cfg); | |
54168ed7 | 2375 | |
7f7ace0c | 2376 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2377 | |
2378 | return 0; | |
54168ed7 IM |
2379 | } |
2380 | ||
54168ed7 IM |
2381 | /* |
2382 | * Migrates the IRQ destination in the process context. | |
2383 | */ | |
d5dedd45 | 2384 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2385 | const struct cpumask *mask) |
54168ed7 | 2386 | { |
d5dedd45 | 2387 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2388 | } |
d5dedd45 | 2389 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2390 | const struct cpumask *mask) |
3145e941 YL |
2391 | { |
2392 | struct irq_desc *desc = irq_to_desc(irq); | |
2393 | ||
d5dedd45 | 2394 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2395 | } |
29b61be6 | 2396 | #else |
d5dedd45 | 2397 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2398 | const struct cpumask *mask) |
2399 | { | |
d5dedd45 | 2400 | return 0; |
29b61be6 | 2401 | } |
54168ed7 IM |
2402 | #endif |
2403 | ||
2404 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2405 | { | |
2406 | unsigned vector, me; | |
8f2466f4 | 2407 | |
54168ed7 | 2408 | ack_APIC_irq(); |
54168ed7 | 2409 | exit_idle(); |
54168ed7 IM |
2410 | irq_enter(); |
2411 | ||
2412 | me = smp_processor_id(); | |
2413 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2414 | unsigned int irq; | |
68a8ca59 | 2415 | unsigned int irr; |
54168ed7 IM |
2416 | struct irq_desc *desc; |
2417 | struct irq_cfg *cfg; | |
2418 | irq = __get_cpu_var(vector_irq)[vector]; | |
2419 | ||
0b8f1efa YL |
2420 | if (irq == -1) |
2421 | continue; | |
2422 | ||
54168ed7 IM |
2423 | desc = irq_to_desc(irq); |
2424 | if (!desc) | |
2425 | continue; | |
2426 | ||
2427 | cfg = irq_cfg(irq); | |
2428 | spin_lock(&desc->lock); | |
54168ed7 | 2429 | |
22f65d31 | 2430 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2431 | goto unlock; |
2432 | ||
68a8ca59 SS |
2433 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2434 | /* | |
2435 | * Check if the vector that needs to be cleanedup is | |
2436 | * registered at the cpu's IRR. If so, then this is not | |
2437 | * the best time to clean it up. Lets clean it up in the | |
2438 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2439 | * to myself. | |
2440 | */ | |
2441 | if (irr & (1 << (vector % 32))) { | |
2442 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2443 | goto unlock; | |
2444 | } | |
54168ed7 | 2445 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 IM |
2446 | unlock: |
2447 | spin_unlock(&desc->lock); | |
2448 | } | |
2449 | ||
2450 | irq_exit(); | |
2451 | } | |
2452 | ||
a5e74b84 | 2453 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2454 | { |
3145e941 YL |
2455 | struct irq_desc *desc = *descp; |
2456 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2457 | unsigned me; |
54168ed7 | 2458 | |
fcef5911 | 2459 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2460 | return; |
2461 | ||
54168ed7 | 2462 | me = smp_processor_id(); |
10b888d6 | 2463 | |
fcef5911 | 2464 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2465 | send_cleanup_vector(cfg); |
497c9a19 | 2466 | } |
a5e74b84 SS |
2467 | |
2468 | static void irq_complete_move(struct irq_desc **descp) | |
2469 | { | |
2470 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2471 | } | |
2472 | ||
2473 | void irq_force_complete_move(int irq) | |
2474 | { | |
2475 | struct irq_desc *desc = irq_to_desc(irq); | |
2476 | struct irq_cfg *cfg = desc->chip_data; | |
2477 | ||
2478 | __irq_complete_move(&desc, cfg->vector); | |
2479 | } | |
497c9a19 | 2480 | #else |
3145e941 | 2481 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2482 | #endif |
3145e941 | 2483 | |
1d025192 YL |
2484 | static void ack_apic_edge(unsigned int irq) |
2485 | { | |
3145e941 YL |
2486 | struct irq_desc *desc = irq_to_desc(irq); |
2487 | ||
2488 | irq_complete_move(&desc); | |
1d025192 YL |
2489 | move_native_irq(irq); |
2490 | ack_APIC_irq(); | |
2491 | } | |
2492 | ||
3eb2cce8 | 2493 | atomic_t irq_mis_count; |
3eb2cce8 | 2494 | |
b3ec0a37 SS |
2495 | static int use_eoi_reg __read_mostly; |
2496 | ||
2497 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) | |
2498 | { | |
2499 | struct irq_pin_list *entry; | |
2500 | ||
2501 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2502 | if (irq_remapped(irq)) | |
2503 | io_apic_eoi(entry->apic, entry->pin); | |
2504 | else | |
2505 | io_apic_eoi(entry->apic, cfg->vector); | |
2506 | } | |
2507 | } | |
2508 | ||
2509 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2510 | { | |
2511 | struct irq_cfg *cfg; | |
2512 | unsigned long flags; | |
2513 | unsigned int irq; | |
2514 | ||
2515 | irq = desc->irq; | |
2516 | cfg = desc->chip_data; | |
2517 | ||
2518 | spin_lock_irqsave(&ioapic_lock, flags); | |
2519 | __eoi_ioapic_irq(irq, cfg); | |
2520 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2521 | } | |
2522 | ||
2523 | static int ioapic_supports_eoi(void) | |
2524 | { | |
2525 | struct pci_dev *root; | |
2526 | ||
2527 | root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
2528 | if (root && root->vendor == PCI_VENDOR_ID_INTEL && | |
2529 | mp_ioapics[0].apicver >= 0x2) { | |
2530 | use_eoi_reg = 1; | |
2531 | printk(KERN_INFO "IO-APIC supports EOI register\n"); | |
2532 | } else | |
2533 | printk(KERN_INFO "IO-APIC doesn't support EOI\n"); | |
2534 | ||
2535 | return 0; | |
2536 | } | |
2537 | ||
2538 | fs_initcall(ioapic_supports_eoi); | |
2539 | ||
047c8fdb YL |
2540 | static void ack_apic_level(unsigned int irq) |
2541 | { | |
3145e941 | 2542 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2543 | unsigned long v; |
2544 | int i; | |
3145e941 | 2545 | struct irq_cfg *cfg; |
54168ed7 | 2546 | int do_unmask_irq = 0; |
047c8fdb | 2547 | |
3145e941 | 2548 | irq_complete_move(&desc); |
047c8fdb | 2549 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2550 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2551 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2552 | do_unmask_irq = 1; |
3145e941 | 2553 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2554 | } |
047c8fdb YL |
2555 | #endif |
2556 | ||
3eb2cce8 | 2557 | /* |
916a0fe7 JF |
2558 | * It appears there is an erratum which affects at least version 0x11 |
2559 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2560 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2561 | * erroneously delivered as edge-triggered one but the respective IRR | |
2562 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2563 | * message but it will never arrive and further interrupts are blocked | |
2564 | * from the source. The exact reason is so far unknown, but the | |
2565 | * phenomenon was observed when two consecutive interrupt requests | |
2566 | * from a given source get delivered to the same CPU and the source is | |
2567 | * temporarily disabled in between. | |
2568 | * | |
2569 | * A workaround is to simulate an EOI message manually. We achieve it | |
2570 | * by setting the trigger mode to edge and then to level when the edge | |
2571 | * trigger mode gets detected in the TMR of a local APIC for a | |
2572 | * level-triggered interrupt. We mask the source for the time of the | |
2573 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2574 | * The idea is from Manfred Spraul. --macro | |
2575 | */ | |
3145e941 YL |
2576 | cfg = desc->chip_data; |
2577 | i = cfg->vector; | |
3eb2cce8 | 2578 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2579 | |
54168ed7 IM |
2580 | /* |
2581 | * We must acknowledge the irq before we move it or the acknowledge will | |
2582 | * not propagate properly. | |
2583 | */ | |
2584 | ack_APIC_irq(); | |
2585 | ||
2586 | /* Now we can move and renable the irq */ | |
2587 | if (unlikely(do_unmask_irq)) { | |
2588 | /* Only migrate the irq if the ack has been received. | |
2589 | * | |
2590 | * On rare occasions the broadcast level triggered ack gets | |
2591 | * delayed going to ioapics, and if we reprogram the | |
2592 | * vector while Remote IRR is still set the irq will never | |
2593 | * fire again. | |
2594 | * | |
2595 | * To prevent this scenario we read the Remote IRR bit | |
2596 | * of the ioapic. This has two effects. | |
2597 | * - On any sane system the read of the ioapic will | |
2598 | * flush writes (and acks) going to the ioapic from | |
2599 | * this cpu. | |
2600 | * - We get to see if the ACK has actually been delivered. | |
2601 | * | |
2602 | * Based on failed experiments of reprogramming the | |
2603 | * ioapic entry from outside of irq context starting | |
2604 | * with masking the ioapic entry and then polling until | |
2605 | * Remote IRR was clear before reprogramming the | |
2606 | * ioapic I don't trust the Remote IRR bit to be | |
2607 | * completey accurate. | |
2608 | * | |
2609 | * However there appears to be no other way to plug | |
2610 | * this race, so if the Remote IRR bit is not | |
2611 | * accurate and is causing problems then it is a hardware bug | |
2612 | * and you can go talk to the chipset vendor about it. | |
2613 | */ | |
3145e941 YL |
2614 | cfg = desc->chip_data; |
2615 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2616 | move_masked_irq(irq); |
3145e941 | 2617 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2618 | } |
1d025192 | 2619 | |
916a0fe7 | 2620 | /* Tail end of version 0x11 I/O APIC bug workaround */ |
1d025192 YL |
2621 | if (!(v & (1 << (i & 0x1f)))) { |
2622 | atomic_inc(&irq_mis_count); | |
b3ec0a37 SS |
2623 | |
2624 | if (use_eoi_reg) | |
2625 | eoi_ioapic_irq(desc); | |
2626 | else { | |
2627 | spin_lock(&ioapic_lock); | |
2628 | __mask_and_edge_IO_APIC_irq(cfg); | |
2629 | __unmask_and_level_IO_APIC_irq(cfg); | |
2630 | spin_unlock(&ioapic_lock); | |
2631 | } | |
1d025192 | 2632 | } |
3eb2cce8 | 2633 | } |
1d025192 | 2634 | |
d0b03bd1 HW |
2635 | #ifdef CONFIG_INTR_REMAP |
2636 | static void ir_ack_apic_edge(unsigned int irq) | |
2637 | { | |
5d0ae2db | 2638 | ack_APIC_irq(); |
d0b03bd1 HW |
2639 | } |
2640 | ||
2641 | static void ir_ack_apic_level(unsigned int irq) | |
2642 | { | |
5d0ae2db WH |
2643 | struct irq_desc *desc = irq_to_desc(irq); |
2644 | ||
2645 | ack_APIC_irq(); | |
2646 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2647 | } |
2648 | #endif /* CONFIG_INTR_REMAP */ | |
2649 | ||
f5b9ed7a | 2650 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2651 | .name = "IO-APIC", |
2652 | .startup = startup_ioapic_irq, | |
2653 | .mask = mask_IO_APIC_irq, | |
2654 | .unmask = unmask_IO_APIC_irq, | |
2655 | .ack = ack_apic_edge, | |
2656 | .eoi = ack_apic_level, | |
54d5d424 | 2657 | #ifdef CONFIG_SMP |
d6c88a50 | 2658 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2659 | #endif |
ace80ab7 | 2660 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2661 | }; |
2662 | ||
54168ed7 | 2663 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2664 | .name = "IR-IO-APIC", |
2665 | .startup = startup_ioapic_irq, | |
2666 | .mask = mask_IO_APIC_irq, | |
2667 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2668 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2669 | .ack = ir_ack_apic_edge, |
2670 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2671 | #ifdef CONFIG_SMP |
d6c88a50 | 2672 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2673 | #endif |
54168ed7 IM |
2674 | #endif |
2675 | .retrigger = ioapic_retrigger_irq, | |
2676 | }; | |
1da177e4 LT |
2677 | |
2678 | static inline void init_IO_APIC_traps(void) | |
2679 | { | |
2680 | int irq; | |
08678b08 | 2681 | struct irq_desc *desc; |
da51a821 | 2682 | struct irq_cfg *cfg; |
1da177e4 LT |
2683 | |
2684 | /* | |
2685 | * NOTE! The local APIC isn't very good at handling | |
2686 | * multiple interrupts at the same interrupt level. | |
2687 | * As the interrupt level is determined by taking the | |
2688 | * vector number and shifting that right by 4, we | |
2689 | * want to spread these out a bit so that they don't | |
2690 | * all fall in the same interrupt level. | |
2691 | * | |
2692 | * Also, we've got to be careful not to trash gate | |
2693 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2694 | */ | |
0b8f1efa | 2695 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2696 | cfg = desc->chip_data; |
2697 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2698 | /* |
2699 | * Hmm.. We don't have an entry for this, | |
2700 | * so default to an old-fashioned 8259 | |
2701 | * interrupt if we can.. | |
2702 | */ | |
bc07844a | 2703 | if (irq < nr_legacy_irqs) |
1da177e4 | 2704 | make_8259A_irq(irq); |
0b8f1efa | 2705 | else |
1da177e4 | 2706 | /* Strange. Oh, well.. */ |
08678b08 | 2707 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2708 | } |
2709 | } | |
2710 | } | |
2711 | ||
f5b9ed7a IM |
2712 | /* |
2713 | * The local APIC irq-chip implementation: | |
2714 | */ | |
1da177e4 | 2715 | |
36062448 | 2716 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2717 | { |
2718 | unsigned long v; | |
2719 | ||
2720 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2721 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2722 | } |
2723 | ||
36062448 | 2724 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2725 | { |
f5b9ed7a | 2726 | unsigned long v; |
1da177e4 | 2727 | |
f5b9ed7a | 2728 | v = apic_read(APIC_LVT0); |
593f4a78 | 2729 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2730 | } |
1da177e4 | 2731 | |
3145e941 | 2732 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2733 | { |
2734 | ack_APIC_irq(); | |
2735 | } | |
2736 | ||
f5b9ed7a | 2737 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2738 | .name = "local-APIC", |
f5b9ed7a IM |
2739 | .mask = mask_lapic_irq, |
2740 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2741 | .ack = ack_lapic_irq, |
1da177e4 LT |
2742 | }; |
2743 | ||
3145e941 | 2744 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2745 | { |
08678b08 | 2746 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2747 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2748 | "edge"); | |
c88ac1df MR |
2749 | } |
2750 | ||
e9427101 | 2751 | static void __init setup_nmi(void) |
1da177e4 LT |
2752 | { |
2753 | /* | |
36062448 | 2754 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2755 | * We put the 8259A master into AEOI mode and |
2756 | * unmask on all local APICs LVT0 as NMI. | |
2757 | * | |
2758 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2759 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2760 | * the NMI handler or the timer interrupt. | |
36062448 | 2761 | */ |
1da177e4 LT |
2762 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2763 | ||
e9427101 | 2764 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2765 | |
2766 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2767 | } | |
2768 | ||
2769 | /* | |
2770 | * This looks a bit hackish but it's about the only one way of sending | |
2771 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2772 | * not support the ExtINT mode, unfortunately. We need to send these | |
2773 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2774 | * 8259A interrupt line asserted until INTA. --macro | |
2775 | */ | |
28acf285 | 2776 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2777 | { |
fcfd636a | 2778 | int apic, pin, i; |
1da177e4 LT |
2779 | struct IO_APIC_route_entry entry0, entry1; |
2780 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2781 | |
fcfd636a | 2782 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2783 | if (pin == -1) { |
2784 | WARN_ON_ONCE(1); | |
2785 | return; | |
2786 | } | |
fcfd636a | 2787 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2788 | if (apic == -1) { |
2789 | WARN_ON_ONCE(1); | |
1da177e4 | 2790 | return; |
956fb531 | 2791 | } |
1da177e4 | 2792 | |
cf4c6a2f | 2793 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2794 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2795 | |
2796 | memset(&entry1, 0, sizeof(entry1)); | |
2797 | ||
2798 | entry1.dest_mode = 0; /* physical delivery */ | |
2799 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2800 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2801 | entry1.delivery_mode = dest_ExtINT; |
2802 | entry1.polarity = entry0.polarity; | |
2803 | entry1.trigger = 0; | |
2804 | entry1.vector = 0; | |
2805 | ||
cf4c6a2f | 2806 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2807 | |
2808 | save_control = CMOS_READ(RTC_CONTROL); | |
2809 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2810 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2811 | RTC_FREQ_SELECT); | |
2812 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2813 | ||
2814 | i = 100; | |
2815 | while (i-- > 0) { | |
2816 | mdelay(10); | |
2817 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2818 | i -= 10; | |
2819 | } | |
2820 | ||
2821 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2822 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2823 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2824 | |
cf4c6a2f | 2825 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2826 | } |
2827 | ||
efa2559f | 2828 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2829 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2830 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2831 | { |
2832 | disable_timer_pin_1 = 1; | |
2833 | return 0; | |
2834 | } | |
54168ed7 | 2835 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2836 | |
2837 | int timer_through_8259 __initdata; | |
2838 | ||
1da177e4 LT |
2839 | /* |
2840 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2841 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2842 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2843 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2844 | * |
2845 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2846 | */ |
8542b200 | 2847 | static inline void __init check_timer(void) |
1da177e4 | 2848 | { |
3145e941 YL |
2849 | struct irq_desc *desc = irq_to_desc(0); |
2850 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2851 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2852 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2853 | unsigned long flags; |
047c8fdb | 2854 | int no_pin1 = 0; |
4aae0702 IM |
2855 | |
2856 | local_irq_save(flags); | |
d4d25dec | 2857 | |
1da177e4 LT |
2858 | /* |
2859 | * get/set the timer IRQ vector: | |
2860 | */ | |
2861 | disable_8259A_irq(0); | |
fe402e1f | 2862 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2863 | |
2864 | /* | |
d11d5794 MR |
2865 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2866 | * wire has to be disabled in the local APIC. Also | |
2867 | * timer interrupts need to be acknowledged manually in | |
2868 | * the 8259A for the i82489DX when using the NMI | |
2869 | * watchdog as that APIC treats NMIs as level-triggered. | |
2870 | * The AEOI mode will finish them in the 8259A | |
2871 | * automatically. | |
1da177e4 | 2872 | */ |
593f4a78 | 2873 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2874 | init_8259A(1); |
54168ed7 | 2875 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2876 | { |
2877 | unsigned int ver; | |
2878 | ||
2879 | ver = apic_read(APIC_LVR); | |
2880 | ver = GET_APIC_VERSION(ver); | |
2881 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2882 | } | |
54168ed7 | 2883 | #endif |
1da177e4 | 2884 | |
fcfd636a EB |
2885 | pin1 = find_isa_irq_pin(0, mp_INT); |
2886 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2887 | pin2 = ioapic_i8259.pin; | |
2888 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2889 | |
49a66a0b MR |
2890 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2891 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2892 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2893 | |
691874fa MR |
2894 | /* |
2895 | * Some BIOS writers are clueless and report the ExtINTA | |
2896 | * I/O APIC input from the cascaded 8259A as the timer | |
2897 | * interrupt input. So just in case, if only one pin | |
2898 | * was found above, try it both directly and through the | |
2899 | * 8259A. | |
2900 | */ | |
2901 | if (pin1 == -1) { | |
54168ed7 IM |
2902 | if (intr_remapping_enabled) |
2903 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2904 | pin1 = pin2; |
2905 | apic1 = apic2; | |
2906 | no_pin1 = 1; | |
2907 | } else if (pin2 == -1) { | |
2908 | pin2 = pin1; | |
2909 | apic2 = apic1; | |
2910 | } | |
2911 | ||
1da177e4 LT |
2912 | if (pin1 != -1) { |
2913 | /* | |
2914 | * Ok, does IRQ0 through the IOAPIC work? | |
2915 | */ | |
691874fa | 2916 | if (no_pin1) { |
85ac16d0 | 2917 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2918 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2919 | } else { |
2920 | /* for edge trigger, setup_IO_APIC_irq already | |
2921 | * leave it unmasked. | |
2922 | * so only need to unmask if it is level-trigger | |
2923 | * do we really have level trigger timer? | |
2924 | */ | |
2925 | int idx; | |
2926 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2927 | if (idx != -1 && irq_trigger(idx)) | |
2928 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2929 | } |
1da177e4 LT |
2930 | if (timer_irq_works()) { |
2931 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2932 | setup_nmi(); |
2933 | enable_8259A_irq(0); | |
1da177e4 | 2934 | } |
66759a01 CE |
2935 | if (disable_timer_pin_1 > 0) |
2936 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2937 | goto out; |
1da177e4 | 2938 | } |
54168ed7 IM |
2939 | if (intr_remapping_enabled) |
2940 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2941 | local_irq_disable(); |
fcfd636a | 2942 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2943 | if (!no_pin1) |
49a66a0b MR |
2944 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2945 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2946 | |
49a66a0b MR |
2947 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2948 | "(IRQ0) through the 8259A ...\n"); | |
2949 | apic_printk(APIC_QUIET, KERN_INFO | |
2950 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2951 | /* |
2952 | * legacy devices should be connected to IO APIC #0 | |
2953 | */ | |
85ac16d0 | 2954 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2955 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2956 | enable_8259A_irq(0); |
1da177e4 | 2957 | if (timer_irq_works()) { |
49a66a0b | 2958 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2959 | timer_through_8259 = 1; |
1da177e4 | 2960 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2961 | disable_8259A_irq(0); |
1da177e4 | 2962 | setup_nmi(); |
60134ebe | 2963 | enable_8259A_irq(0); |
1da177e4 | 2964 | } |
4aae0702 | 2965 | goto out; |
1da177e4 LT |
2966 | } |
2967 | /* | |
2968 | * Cleanup, just in case ... | |
2969 | */ | |
f72dccac | 2970 | local_irq_disable(); |
ecd29476 | 2971 | disable_8259A_irq(0); |
fcfd636a | 2972 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2973 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2974 | } |
1da177e4 LT |
2975 | |
2976 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2977 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2978 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2979 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2980 | } |
54168ed7 | 2981 | #ifdef CONFIG_X86_32 |
d11d5794 | 2982 | timer_ack = 0; |
54168ed7 | 2983 | #endif |
1da177e4 | 2984 | |
49a66a0b MR |
2985 | apic_printk(APIC_QUIET, KERN_INFO |
2986 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2987 | |
3145e941 | 2988 | lapic_register_intr(0, desc); |
497c9a19 | 2989 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2990 | enable_8259A_irq(0); |
2991 | ||
2992 | if (timer_irq_works()) { | |
49a66a0b | 2993 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2994 | goto out; |
1da177e4 | 2995 | } |
f72dccac | 2996 | local_irq_disable(); |
e67465f1 | 2997 | disable_8259A_irq(0); |
497c9a19 | 2998 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2999 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3000 | |
49a66a0b MR |
3001 | apic_printk(APIC_QUIET, KERN_INFO |
3002 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3003 | |
1da177e4 LT |
3004 | init_8259A(0); |
3005 | make_8259A_irq(0); | |
593f4a78 | 3006 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3007 | |
3008 | unlock_ExtINT_logic(); | |
3009 | ||
3010 | if (timer_irq_works()) { | |
49a66a0b | 3011 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3012 | goto out; |
1da177e4 | 3013 | } |
f72dccac | 3014 | local_irq_disable(); |
49a66a0b | 3015 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3016 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3017 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3018 | out: |
3019 | local_irq_restore(flags); | |
1da177e4 LT |
3020 | } |
3021 | ||
3022 | /* | |
af174783 MR |
3023 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3024 | * to devices. However there may be an I/O APIC pin available for | |
3025 | * this interrupt regardless. The pin may be left unconnected, but | |
3026 | * typically it will be reused as an ExtINT cascade interrupt for | |
3027 | * the master 8259A. In the MPS case such a pin will normally be | |
3028 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3029 | * there is no provision for ExtINT interrupts, and in the absence | |
3030 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3031 | * interrupt, that is edge-triggered and unmasked by default. We | |
3032 | * used to do this, but it caused problems on some systems because | |
3033 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3034 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3035 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3036 | * the I/O APIC in all cases now. No actual device should request | |
3037 | * it anyway. --macro | |
1da177e4 | 3038 | */ |
bc07844a | 3039 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3040 | |
3041 | void __init setup_IO_APIC(void) | |
3042 | { | |
54168ed7 | 3043 | |
54168ed7 IM |
3044 | /* |
3045 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3046 | */ | |
bc07844a | 3047 | io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3048 | |
54168ed7 | 3049 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3050 | /* |
54168ed7 IM |
3051 | * Set up IO-APIC IRQ routing. |
3052 | */ | |
de934103 TG |
3053 | x86_init.mpparse.setup_ioapic_ids(); |
3054 | ||
1da177e4 LT |
3055 | sync_Arb_IDs(); |
3056 | setup_IO_APIC_irqs(); | |
3057 | init_IO_APIC_traps(); | |
bc07844a TG |
3058 | if (nr_legacy_irqs) |
3059 | check_timer(); | |
1da177e4 LT |
3060 | } |
3061 | ||
3062 | /* | |
54168ed7 IM |
3063 | * Called after all the initialization is done. If we didnt find any |
3064 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3065 | */ |
36062448 | 3066 | |
1da177e4 LT |
3067 | static int __init io_apic_bug_finalize(void) |
3068 | { | |
d6c88a50 TG |
3069 | if (sis_apic_bug == -1) |
3070 | sis_apic_bug = 0; | |
3071 | return 0; | |
1da177e4 LT |
3072 | } |
3073 | ||
3074 | late_initcall(io_apic_bug_finalize); | |
3075 | ||
3076 | struct sysfs_ioapic_data { | |
3077 | struct sys_device dev; | |
3078 | struct IO_APIC_route_entry entry[0]; | |
3079 | }; | |
54168ed7 | 3080 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3081 | |
438510f6 | 3082 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3083 | { |
3084 | struct IO_APIC_route_entry *entry; | |
3085 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3086 | int i; |
36062448 | 3087 | |
1da177e4 LT |
3088 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3089 | entry = data->entry; | |
54168ed7 IM |
3090 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3091 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3092 | |
3093 | return 0; | |
3094 | } | |
3095 | ||
3096 | static int ioapic_resume(struct sys_device *dev) | |
3097 | { | |
3098 | struct IO_APIC_route_entry *entry; | |
3099 | struct sysfs_ioapic_data *data; | |
3100 | unsigned long flags; | |
3101 | union IO_APIC_reg_00 reg_00; | |
3102 | int i; | |
36062448 | 3103 | |
1da177e4 LT |
3104 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3105 | entry = data->entry; | |
3106 | ||
3107 | spin_lock_irqsave(&ioapic_lock, flags); | |
3108 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3109 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3110 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3111 | io_apic_write(dev->id, 0, reg_00.raw); |
3112 | } | |
1da177e4 | 3113 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3114 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3115 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3116 | |
3117 | return 0; | |
3118 | } | |
3119 | ||
3120 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3121 | .name = "ioapic", |
1da177e4 LT |
3122 | .suspend = ioapic_suspend, |
3123 | .resume = ioapic_resume, | |
3124 | }; | |
3125 | ||
3126 | static int __init ioapic_init_sysfs(void) | |
3127 | { | |
54168ed7 IM |
3128 | struct sys_device * dev; |
3129 | int i, size, error; | |
1da177e4 LT |
3130 | |
3131 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3132 | if (error) | |
3133 | return error; | |
3134 | ||
54168ed7 | 3135 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3136 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3137 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3138 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3139 | if (!mp_ioapic_data[i]) { |
3140 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3141 | continue; | |
3142 | } | |
1da177e4 | 3143 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3144 | dev->id = i; |
1da177e4 LT |
3145 | dev->cls = &ioapic_sysdev_class; |
3146 | error = sysdev_register(dev); | |
3147 | if (error) { | |
3148 | kfree(mp_ioapic_data[i]); | |
3149 | mp_ioapic_data[i] = NULL; | |
3150 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3151 | continue; | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | return 0; | |
3156 | } | |
3157 | ||
3158 | device_initcall(ioapic_init_sysfs); | |
3159 | ||
3fc471ed | 3160 | /* |
95d77884 | 3161 | * Dynamic irq allocate and deallocation |
3fc471ed | 3162 | */ |
d047f53a | 3163 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3164 | { |
ace80ab7 | 3165 | /* Allocate an unused irq */ |
54168ed7 IM |
3166 | unsigned int irq; |
3167 | unsigned int new; | |
3fc471ed | 3168 | unsigned long flags; |
0b8f1efa | 3169 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3170 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3171 | |
3172 | irq = 0; | |
abcaa2b8 YL |
3173 | if (irq_want < nr_irqs_gsi) |
3174 | irq_want = nr_irqs_gsi; | |
3175 | ||
ace80ab7 | 3176 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3177 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3178 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3179 | if (!desc_new) { |
3180 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3181 | continue; |
0b8f1efa YL |
3182 | } |
3183 | cfg_new = desc_new->chip_data; | |
3184 | ||
3185 | if (cfg_new->vector != 0) | |
ace80ab7 | 3186 | continue; |
d047f53a | 3187 | |
15e957d0 | 3188 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3189 | |
fe402e1f | 3190 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3191 | irq = new; |
3192 | break; | |
3193 | } | |
3194 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3195 | |
199751d7 | 3196 | if (irq > 0) { |
3fc471ed | 3197 | dynamic_irq_init(irq); |
0b8f1efa YL |
3198 | /* restore it, in case dynamic_irq_init clear it */ |
3199 | if (desc_new) | |
3200 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3201 | } |
3202 | return irq; | |
3203 | } | |
3204 | ||
199751d7 YL |
3205 | int create_irq(void) |
3206 | { | |
d047f53a | 3207 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3208 | unsigned int irq_want; |
54168ed7 IM |
3209 | int irq; |
3210 | ||
be5d5350 | 3211 | irq_want = nr_irqs_gsi; |
d047f53a | 3212 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3213 | |
3214 | if (irq == 0) | |
3215 | irq = -1; | |
3216 | ||
3217 | return irq; | |
199751d7 YL |
3218 | } |
3219 | ||
3fc471ed EB |
3220 | void destroy_irq(unsigned int irq) |
3221 | { | |
3222 | unsigned long flags; | |
0b8f1efa YL |
3223 | struct irq_cfg *cfg; |
3224 | struct irq_desc *desc; | |
3fc471ed | 3225 | |
0b8f1efa YL |
3226 | /* store it, in case dynamic_irq_cleanup clear it */ |
3227 | desc = irq_to_desc(irq); | |
3228 | cfg = desc->chip_data; | |
3fc471ed | 3229 | dynamic_irq_cleanup(irq); |
0b8f1efa | 3230 | /* connect back irq_cfg */ |
25f6e89b | 3231 | desc->chip_data = cfg; |
3fc471ed | 3232 | |
54168ed7 | 3233 | free_irte(irq); |
3fc471ed | 3234 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3235 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3236 | spin_unlock_irqrestore(&vector_lock, flags); |
3237 | } | |
3fc471ed | 3238 | |
2d3fcc1c | 3239 | /* |
27b46d76 | 3240 | * MSI message composition |
2d3fcc1c EB |
3241 | */ |
3242 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3243 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3244 | { |
497c9a19 YL |
3245 | struct irq_cfg *cfg; |
3246 | int err; | |
2d3fcc1c EB |
3247 | unsigned dest; |
3248 | ||
f1182638 JB |
3249 | if (disable_apic) |
3250 | return -ENXIO; | |
3251 | ||
3145e941 | 3252 | cfg = irq_cfg(irq); |
fe402e1f | 3253 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3254 | if (err) |
3255 | return err; | |
2d3fcc1c | 3256 | |
debccb3e | 3257 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3258 | |
54168ed7 IM |
3259 | if (irq_remapped(irq)) { |
3260 | struct irte irte; | |
3261 | int ir_index; | |
3262 | u16 sub_handle; | |
3263 | ||
3264 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3265 | BUG_ON(ir_index == -1); | |
3266 | ||
3267 | memset (&irte, 0, sizeof(irte)); | |
3268 | ||
3269 | irte.present = 1; | |
9b5bc8dc | 3270 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3271 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3272 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3273 | irte.vector = cfg->vector; |
3274 | irte.dest_id = IRTE_DEST(dest); | |
3275 | ||
f007e99c WH |
3276 | /* Set source-id of interrupt request */ |
3277 | set_msi_sid(&irte, pdev); | |
3278 | ||
54168ed7 IM |
3279 | modify_irte(irq, &irte); |
3280 | ||
3281 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3282 | msg->data = sub_handle; | |
3283 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3284 | MSI_ADDR_IR_SHV | | |
3285 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3286 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3287 | } else { |
9d783ba0 SS |
3288 | if (x2apic_enabled()) |
3289 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3290 | MSI_ADDR_EXT_DEST_ID(dest); | |
3291 | else | |
3292 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3293 | ||
54168ed7 IM |
3294 | msg->address_lo = |
3295 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3296 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3297 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3298 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3299 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3300 | MSI_ADDR_REDIRECTION_CPU: |
3301 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3302 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3303 | |
54168ed7 IM |
3304 | msg->data = |
3305 | MSI_DATA_TRIGGER_EDGE | | |
3306 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3307 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3308 | MSI_DATA_DELIVERY_FIXED: |
3309 | MSI_DATA_DELIVERY_LOWPRI) | | |
3310 | MSI_DATA_VECTOR(cfg->vector); | |
3311 | } | |
497c9a19 | 3312 | return err; |
2d3fcc1c EB |
3313 | } |
3314 | ||
3b7d1921 | 3315 | #ifdef CONFIG_SMP |
d5dedd45 | 3316 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3317 | { |
3145e941 | 3318 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3319 | struct irq_cfg *cfg; |
3b7d1921 EB |
3320 | struct msi_msg msg; |
3321 | unsigned int dest; | |
3b7d1921 | 3322 | |
22f65d31 MT |
3323 | dest = set_desc_affinity(desc, mask); |
3324 | if (dest == BAD_APICID) | |
d5dedd45 | 3325 | return -1; |
2d3fcc1c | 3326 | |
3145e941 | 3327 | cfg = desc->chip_data; |
2d3fcc1c | 3328 | |
3145e941 | 3329 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3330 | |
3331 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3332 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3333 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3334 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3335 | ||
3145e941 | 3336 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3337 | |
3338 | return 0; | |
2d3fcc1c | 3339 | } |
54168ed7 IM |
3340 | #ifdef CONFIG_INTR_REMAP |
3341 | /* | |
3342 | * Migrate the MSI irq to another cpumask. This migration is | |
3343 | * done in the process context using interrupt-remapping hardware. | |
3344 | */ | |
d5dedd45 | 3345 | static int |
e7986739 | 3346 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3347 | { |
3145e941 | 3348 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3349 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3350 | unsigned int dest; |
54168ed7 | 3351 | struct irte irte; |
54168ed7 IM |
3352 | |
3353 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3354 | return -1; |
54168ed7 | 3355 | |
22f65d31 MT |
3356 | dest = set_desc_affinity(desc, mask); |
3357 | if (dest == BAD_APICID) | |
d5dedd45 | 3358 | return -1; |
54168ed7 | 3359 | |
54168ed7 IM |
3360 | irte.vector = cfg->vector; |
3361 | irte.dest_id = IRTE_DEST(dest); | |
3362 | ||
3363 | /* | |
3364 | * atomically update the IRTE with the new destination and vector. | |
3365 | */ | |
3366 | modify_irte(irq, &irte); | |
3367 | ||
3368 | /* | |
3369 | * After this point, all the interrupts will start arriving | |
3370 | * at the new destination. So, time to cleanup the previous | |
3371 | * vector allocation. | |
3372 | */ | |
22f65d31 MT |
3373 | if (cfg->move_in_progress) |
3374 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3375 | |
3376 | return 0; | |
54168ed7 | 3377 | } |
3145e941 | 3378 | |
54168ed7 | 3379 | #endif |
3b7d1921 | 3380 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3381 | |
3b7d1921 EB |
3382 | /* |
3383 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3384 | * which implement the MSI or MSI-X Capability Structure. | |
3385 | */ | |
3386 | static struct irq_chip msi_chip = { | |
3387 | .name = "PCI-MSI", | |
3388 | .unmask = unmask_msi_irq, | |
3389 | .mask = mask_msi_irq, | |
1d025192 | 3390 | .ack = ack_apic_edge, |
3b7d1921 EB |
3391 | #ifdef CONFIG_SMP |
3392 | .set_affinity = set_msi_irq_affinity, | |
3393 | #endif | |
3394 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3395 | }; |
3396 | ||
54168ed7 IM |
3397 | static struct irq_chip msi_ir_chip = { |
3398 | .name = "IR-PCI-MSI", | |
3399 | .unmask = unmask_msi_irq, | |
3400 | .mask = mask_msi_irq, | |
a1e38ca5 | 3401 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3402 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3403 | #ifdef CONFIG_SMP |
3404 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3405 | #endif |
54168ed7 IM |
3406 | #endif |
3407 | .retrigger = ioapic_retrigger_irq, | |
3408 | }; | |
3409 | ||
3410 | /* | |
3411 | * Map the PCI dev to the corresponding remapping hardware unit | |
3412 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3413 | * in it. | |
3414 | */ | |
3415 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3416 | { | |
3417 | struct intel_iommu *iommu; | |
3418 | int index; | |
3419 | ||
3420 | iommu = map_dev_to_ir(dev); | |
3421 | if (!iommu) { | |
3422 | printk(KERN_ERR | |
3423 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3424 | return -ENOENT; | |
3425 | } | |
3426 | ||
3427 | index = alloc_irte(iommu, irq, nvec); | |
3428 | if (index < 0) { | |
3429 | printk(KERN_ERR | |
3430 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3431 | pci_name(dev)); |
54168ed7 IM |
3432 | return -ENOSPC; |
3433 | } | |
3434 | return index; | |
3435 | } | |
1d025192 | 3436 | |
3145e941 | 3437 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3438 | { |
3439 | int ret; | |
3440 | struct msi_msg msg; | |
3441 | ||
3442 | ret = msi_compose_msg(dev, irq, &msg); | |
3443 | if (ret < 0) | |
3444 | return ret; | |
3445 | ||
3145e941 | 3446 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3447 | write_msi_msg(irq, &msg); |
3448 | ||
54168ed7 IM |
3449 | if (irq_remapped(irq)) { |
3450 | struct irq_desc *desc = irq_to_desc(irq); | |
3451 | /* | |
3452 | * irq migration in process context | |
3453 | */ | |
3454 | desc->status |= IRQ_MOVE_PCNTXT; | |
3455 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3456 | } else | |
54168ed7 | 3457 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3458 | |
c81bba49 YL |
3459 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3460 | ||
1d025192 YL |
3461 | return 0; |
3462 | } | |
3463 | ||
047c8fdb YL |
3464 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3465 | { | |
54168ed7 IM |
3466 | unsigned int irq; |
3467 | int ret, sub_handle; | |
0b8f1efa | 3468 | struct msi_desc *msidesc; |
54168ed7 | 3469 | unsigned int irq_want; |
1cc18521 | 3470 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3471 | int index = 0; |
d047f53a | 3472 | int node; |
54168ed7 | 3473 | |
1c8d7b0a MW |
3474 | /* x86 doesn't support multiple MSI yet */ |
3475 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3476 | return 1; | |
3477 | ||
d047f53a | 3478 | node = dev_to_node(&dev->dev); |
be5d5350 | 3479 | irq_want = nr_irqs_gsi; |
54168ed7 | 3480 | sub_handle = 0; |
0b8f1efa | 3481 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3482 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3483 | if (irq == 0) |
3484 | return -1; | |
f1ee5548 | 3485 | irq_want = irq + 1; |
54168ed7 IM |
3486 | if (!intr_remapping_enabled) |
3487 | goto no_ir; | |
3488 | ||
3489 | if (!sub_handle) { | |
3490 | /* | |
3491 | * allocate the consecutive block of IRTE's | |
3492 | * for 'nvec' | |
3493 | */ | |
3494 | index = msi_alloc_irte(dev, irq, nvec); | |
3495 | if (index < 0) { | |
3496 | ret = index; | |
3497 | goto error; | |
3498 | } | |
3499 | } else { | |
3500 | iommu = map_dev_to_ir(dev); | |
3501 | if (!iommu) { | |
3502 | ret = -ENOENT; | |
3503 | goto error; | |
3504 | } | |
3505 | /* | |
3506 | * setup the mapping between the irq and the IRTE | |
3507 | * base index, the sub_handle pointing to the | |
3508 | * appropriate interrupt remap table entry. | |
3509 | */ | |
3510 | set_irte_irq(irq, iommu, index, sub_handle); | |
3511 | } | |
3512 | no_ir: | |
0b8f1efa | 3513 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3514 | if (ret < 0) |
3515 | goto error; | |
3516 | sub_handle++; | |
3517 | } | |
3518 | return 0; | |
047c8fdb YL |
3519 | |
3520 | error: | |
54168ed7 IM |
3521 | destroy_irq(irq); |
3522 | return ret; | |
047c8fdb YL |
3523 | } |
3524 | ||
3b7d1921 EB |
3525 | void arch_teardown_msi_irq(unsigned int irq) |
3526 | { | |
f7feaca7 | 3527 | destroy_irq(irq); |
3b7d1921 EB |
3528 | } |
3529 | ||
9d783ba0 | 3530 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3531 | #ifdef CONFIG_SMP |
d5dedd45 | 3532 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3533 | { |
3145e941 | 3534 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3535 | struct irq_cfg *cfg; |
3536 | struct msi_msg msg; | |
3537 | unsigned int dest; | |
54168ed7 | 3538 | |
22f65d31 MT |
3539 | dest = set_desc_affinity(desc, mask); |
3540 | if (dest == BAD_APICID) | |
d5dedd45 | 3541 | return -1; |
54168ed7 | 3542 | |
3145e941 | 3543 | cfg = desc->chip_data; |
54168ed7 IM |
3544 | |
3545 | dmar_msi_read(irq, &msg); | |
3546 | ||
3547 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3548 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3549 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3550 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3551 | ||
3552 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3553 | |
3554 | return 0; | |
54168ed7 | 3555 | } |
3145e941 | 3556 | |
54168ed7 IM |
3557 | #endif /* CONFIG_SMP */ |
3558 | ||
8f7007aa | 3559 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3560 | .name = "DMAR_MSI", |
3561 | .unmask = dmar_msi_unmask, | |
3562 | .mask = dmar_msi_mask, | |
3563 | .ack = ack_apic_edge, | |
3564 | #ifdef CONFIG_SMP | |
3565 | .set_affinity = dmar_msi_set_affinity, | |
3566 | #endif | |
3567 | .retrigger = ioapic_retrigger_irq, | |
3568 | }; | |
3569 | ||
3570 | int arch_setup_dmar_msi(unsigned int irq) | |
3571 | { | |
3572 | int ret; | |
3573 | struct msi_msg msg; | |
2d3fcc1c | 3574 | |
54168ed7 IM |
3575 | ret = msi_compose_msg(NULL, irq, &msg); |
3576 | if (ret < 0) | |
3577 | return ret; | |
3578 | dmar_msi_write(irq, &msg); | |
3579 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3580 | "edge"); | |
3581 | return 0; | |
3582 | } | |
3583 | #endif | |
3584 | ||
58ac1e76 | 3585 | #ifdef CONFIG_HPET_TIMER |
3586 | ||
3587 | #ifdef CONFIG_SMP | |
d5dedd45 | 3588 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3589 | { |
3145e941 | 3590 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3591 | struct irq_cfg *cfg; |
58ac1e76 | 3592 | struct msi_msg msg; |
3593 | unsigned int dest; | |
58ac1e76 | 3594 | |
22f65d31 MT |
3595 | dest = set_desc_affinity(desc, mask); |
3596 | if (dest == BAD_APICID) | |
d5dedd45 | 3597 | return -1; |
58ac1e76 | 3598 | |
3145e941 | 3599 | cfg = desc->chip_data; |
58ac1e76 | 3600 | |
3601 | hpet_msi_read(irq, &msg); | |
3602 | ||
3603 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3604 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3605 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3606 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3607 | ||
3608 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3609 | |
3610 | return 0; | |
58ac1e76 | 3611 | } |
3145e941 | 3612 | |
58ac1e76 | 3613 | #endif /* CONFIG_SMP */ |
3614 | ||
1cc18521 | 3615 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3616 | .name = "HPET_MSI", |
3617 | .unmask = hpet_msi_unmask, | |
3618 | .mask = hpet_msi_mask, | |
3619 | .ack = ack_apic_edge, | |
3620 | #ifdef CONFIG_SMP | |
3621 | .set_affinity = hpet_msi_set_affinity, | |
3622 | #endif | |
3623 | .retrigger = ioapic_retrigger_irq, | |
3624 | }; | |
3625 | ||
3626 | int arch_setup_hpet_msi(unsigned int irq) | |
3627 | { | |
3628 | int ret; | |
3629 | struct msi_msg msg; | |
6ec3cfec | 3630 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3631 | |
3632 | ret = msi_compose_msg(NULL, irq, &msg); | |
3633 | if (ret < 0) | |
3634 | return ret; | |
3635 | ||
3636 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3637 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3638 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3639 | "edge"); | |
c81bba49 | 3640 | |
58ac1e76 | 3641 | return 0; |
3642 | } | |
3643 | #endif | |
3644 | ||
54168ed7 | 3645 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3646 | /* |
3647 | * Hypertransport interrupt support | |
3648 | */ | |
3649 | #ifdef CONFIG_HT_IRQ | |
3650 | ||
3651 | #ifdef CONFIG_SMP | |
3652 | ||
497c9a19 | 3653 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3654 | { |
ec68307c EB |
3655 | struct ht_irq_msg msg; |
3656 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3657 | |
497c9a19 | 3658 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3659 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3660 | |
497c9a19 | 3661 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3662 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3663 | |
ec68307c | 3664 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3665 | } |
3666 | ||
d5dedd45 | 3667 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3668 | { |
3145e941 | 3669 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3670 | struct irq_cfg *cfg; |
8b955b0d | 3671 | unsigned int dest; |
8b955b0d | 3672 | |
22f65d31 MT |
3673 | dest = set_desc_affinity(desc, mask); |
3674 | if (dest == BAD_APICID) | |
d5dedd45 | 3675 | return -1; |
8b955b0d | 3676 | |
3145e941 | 3677 | cfg = desc->chip_data; |
8b955b0d | 3678 | |
497c9a19 | 3679 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3680 | |
3681 | return 0; | |
8b955b0d | 3682 | } |
3145e941 | 3683 | |
8b955b0d EB |
3684 | #endif |
3685 | ||
c37e108d | 3686 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3687 | .name = "PCI-HT", |
3688 | .mask = mask_ht_irq, | |
3689 | .unmask = unmask_ht_irq, | |
1d025192 | 3690 | .ack = ack_apic_edge, |
8b955b0d EB |
3691 | #ifdef CONFIG_SMP |
3692 | .set_affinity = set_ht_irq_affinity, | |
3693 | #endif | |
3694 | .retrigger = ioapic_retrigger_irq, | |
3695 | }; | |
3696 | ||
3697 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3698 | { | |
497c9a19 YL |
3699 | struct irq_cfg *cfg; |
3700 | int err; | |
8b955b0d | 3701 | |
f1182638 JB |
3702 | if (disable_apic) |
3703 | return -ENXIO; | |
3704 | ||
3145e941 | 3705 | cfg = irq_cfg(irq); |
fe402e1f | 3706 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3707 | if (!err) { |
ec68307c | 3708 | struct ht_irq_msg msg; |
8b955b0d | 3709 | unsigned dest; |
8b955b0d | 3710 | |
debccb3e IM |
3711 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3712 | apic->target_cpus()); | |
8b955b0d | 3713 | |
ec68307c | 3714 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3715 | |
ec68307c EB |
3716 | msg.address_lo = |
3717 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3718 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3719 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3720 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3721 | HT_IRQ_LOW_DM_PHYSICAL : |
3722 | HT_IRQ_LOW_DM_LOGICAL) | | |
3723 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3724 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3725 | HT_IRQ_LOW_MT_FIXED : |
3726 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3727 | HT_IRQ_LOW_IRQ_MASKED; | |
3728 | ||
ec68307c | 3729 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3730 | |
a460e745 IM |
3731 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3732 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3733 | |
3734 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3735 | } |
497c9a19 | 3736 | return err; |
8b955b0d EB |
3737 | } |
3738 | #endif /* CONFIG_HT_IRQ */ | |
3739 | ||
9d6a4d08 YL |
3740 | int __init io_apic_get_redir_entries (int ioapic) |
3741 | { | |
3742 | union IO_APIC_reg_01 reg_01; | |
3743 | unsigned long flags; | |
3744 | ||
3745 | spin_lock_irqsave(&ioapic_lock, flags); | |
3746 | reg_01.raw = io_apic_read(ioapic, 1); | |
3747 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3748 | ||
3749 | return reg_01.bits.entries; | |
3750 | } | |
3751 | ||
be5d5350 | 3752 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3753 | { |
be5d5350 YL |
3754 | int nr = 0; |
3755 | ||
cc6c5006 YL |
3756 | nr = acpi_probe_gsi(); |
3757 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3758 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3759 | } else { |
3760 | /* for acpi=off or acpi is not compiled in */ | |
3761 | int idx; | |
3762 | ||
3763 | nr = 0; | |
3764 | for (idx = 0; idx < nr_ioapics; idx++) | |
3765 | nr += io_apic_get_redir_entries(idx) + 1; | |
3766 | ||
3767 | if (nr > nr_irqs_gsi) | |
3768 | nr_irqs_gsi = nr; | |
3769 | } | |
3770 | ||
3771 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3772 | } |
3773 | ||
4a046d17 YL |
3774 | #ifdef CONFIG_SPARSE_IRQ |
3775 | int __init arch_probe_nr_irqs(void) | |
3776 | { | |
3777 | int nr; | |
3778 | ||
f1ee5548 YL |
3779 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3780 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3781 | |
f1ee5548 YL |
3782 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3783 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3784 | /* | |
3785 | * for MSI and HT dyn irq | |
3786 | */ | |
3787 | nr += nr_irqs_gsi * 16; | |
3788 | #endif | |
3789 | if (nr < nr_irqs) | |
4a046d17 YL |
3790 | nr_irqs = nr; |
3791 | ||
3792 | return 0; | |
3793 | } | |
3794 | #endif | |
3795 | ||
e5198075 YL |
3796 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3797 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3798 | { |
3799 | struct irq_desc *desc; | |
3800 | struct irq_cfg *cfg; | |
3801 | int node; | |
e5198075 YL |
3802 | int ioapic, pin; |
3803 | int trigger, polarity; | |
5ef21837 | 3804 | |
e5198075 | 3805 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3806 | if (!IO_APIC_IRQ(irq)) { |
3807 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3808 | ioapic); | |
3809 | return -EINVAL; | |
3810 | } | |
3811 | ||
3812 | if (dev) | |
3813 | node = dev_to_node(dev); | |
3814 | else | |
3815 | node = cpu_to_node(boot_cpu_id); | |
3816 | ||
3817 | desc = irq_to_desc_alloc_node(irq, node); | |
3818 | if (!desc) { | |
3819 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3820 | return 0; | |
3821 | } | |
3822 | ||
e5198075 YL |
3823 | pin = irq_attr->ioapic_pin; |
3824 | trigger = irq_attr->trigger; | |
3825 | polarity = irq_attr->polarity; | |
3826 | ||
5ef21837 YL |
3827 | /* |
3828 | * IRQs < 16 are already in the irq_2_pin[] map | |
3829 | */ | |
bc07844a | 3830 | if (irq >= nr_legacy_irqs) { |
5ef21837 | 3831 | cfg = desc->chip_data; |
f3d1915a CG |
3832 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3833 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3834 | pin, irq); | |
3835 | return 0; | |
3836 | } | |
5ef21837 YL |
3837 | } |
3838 | ||
e5198075 | 3839 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3840 | |
3841 | return 0; | |
3842 | } | |
3843 | ||
e5198075 YL |
3844 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3845 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3846 | { |
e5198075 | 3847 | int ioapic, pin; |
5ef21837 YL |
3848 | /* |
3849 | * Avoid pin reprogramming. PRTs typically include entries | |
3850 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3851 | * we only program the IOAPIC on the first. | |
3852 | */ | |
e5198075 YL |
3853 | ioapic = irq_attr->ioapic; |
3854 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3855 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3856 | pr_debug("Pin %d-%d already programmed\n", | |
3857 | mp_ioapics[ioapic].apicid, pin); | |
3858 | return 0; | |
3859 | } | |
3860 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3861 | ||
e5198075 | 3862 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3863 | } |
3864 | ||
2a4ab640 FT |
3865 | u8 __init io_apic_unique_id(u8 id) |
3866 | { | |
3867 | #ifdef CONFIG_X86_32 | |
3868 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3869 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3870 | return io_apic_get_unique_id(nr_ioapics, id); | |
3871 | else | |
3872 | return id; | |
3873 | #else | |
3874 | int i; | |
3875 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3876 | |
2a4ab640 FT |
3877 | bitmap_zero(used, 256); |
3878 | for (i = 0; i < nr_ioapics; i++) { | |
3879 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3880 | __set_bit(ia->apicid, used); | |
3881 | } | |
3882 | if (!test_bit(id, used)) | |
3883 | return id; | |
3884 | return find_first_zero_bit(used, 256); | |
3885 | #endif | |
3886 | } | |
1da177e4 | 3887 | |
54168ed7 | 3888 | #ifdef CONFIG_X86_32 |
36062448 | 3889 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3890 | { |
3891 | union IO_APIC_reg_00 reg_00; | |
3892 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3893 | physid_mask_t tmp; | |
3894 | unsigned long flags; | |
3895 | int i = 0; | |
3896 | ||
3897 | /* | |
36062448 PC |
3898 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3899 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3900 | * supports up to 16 on one shared APIC bus. |
36062448 | 3901 | * |
1da177e4 LT |
3902 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3903 | * advantage of new APIC bus architecture. | |
3904 | */ | |
3905 | ||
3906 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3907 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3908 | |
3909 | spin_lock_irqsave(&ioapic_lock, flags); | |
3910 | reg_00.raw = io_apic_read(ioapic, 0); | |
3911 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3912 | ||
3913 | if (apic_id >= get_physical_broadcast()) { | |
3914 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3915 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3916 | apic_id = reg_00.bits.ID; | |
3917 | } | |
3918 | ||
3919 | /* | |
36062448 | 3920 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3921 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3922 | */ | |
d1d7cae8 | 3923 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3924 | |
3925 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3926 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3927 | break; |
3928 | } | |
3929 | ||
3930 | if (i == get_physical_broadcast()) | |
3931 | panic("Max apic_id exceeded!\n"); | |
3932 | ||
3933 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3934 | "trying %d\n", ioapic, apic_id, i); | |
3935 | ||
3936 | apic_id = i; | |
36062448 | 3937 | } |
1da177e4 | 3938 | |
8058714a | 3939 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3940 | physids_or(apic_id_map, apic_id_map, tmp); |
3941 | ||
3942 | if (reg_00.bits.ID != apic_id) { | |
3943 | reg_00.bits.ID = apic_id; | |
3944 | ||
3945 | spin_lock_irqsave(&ioapic_lock, flags); | |
3946 | io_apic_write(ioapic, 0, reg_00.raw); | |
3947 | reg_00.raw = io_apic_read(ioapic, 0); | |
3948 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3949 | ||
3950 | /* Sanity check */ | |
6070f9ec AD |
3951 | if (reg_00.bits.ID != apic_id) { |
3952 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3953 | return -1; | |
3954 | } | |
1da177e4 LT |
3955 | } |
3956 | ||
3957 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3958 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3959 | ||
3960 | return apic_id; | |
3961 | } | |
58f892e0 | 3962 | #endif |
1da177e4 | 3963 | |
36062448 | 3964 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3965 | { |
3966 | union IO_APIC_reg_01 reg_01; | |
3967 | unsigned long flags; | |
3968 | ||
3969 | spin_lock_irqsave(&ioapic_lock, flags); | |
3970 | reg_01.raw = io_apic_read(ioapic, 1); | |
3971 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3972 | ||
3973 | return reg_01.bits.version; | |
3974 | } | |
3975 | ||
61fd47e0 SL |
3976 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3977 | { | |
3978 | int i; | |
3979 | ||
3980 | if (skip_ioapic_setup) | |
3981 | return -1; | |
3982 | ||
3983 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
3984 | if (mp_irqs[i].irqtype == mp_INT && |
3985 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
3986 | break; |
3987 | if (i >= mp_irq_entries) | |
3988 | return -1; | |
3989 | ||
3990 | *trigger = irq_trigger(i); | |
3991 | *polarity = irq_polarity(i); | |
3992 | return 0; | |
3993 | } | |
3994 | ||
497c9a19 YL |
3995 | /* |
3996 | * This function currently is only a helper for the i386 smp boot process where | |
3997 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3998 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3999 | */ |
4000 | #ifdef CONFIG_SMP | |
4001 | void __init setup_ioapic_dest(void) | |
4002 | { | |
b9c61b70 | 4003 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4004 | struct irq_desc *desc; |
22f65d31 | 4005 | const struct cpumask *mask; |
497c9a19 YL |
4006 | |
4007 | if (skip_ioapic_setup == 1) | |
4008 | return; | |
4009 | ||
b9c61b70 YL |
4010 | #ifdef CONFIG_ACPI |
4011 | if (!acpi_disabled && acpi_ioapic) { | |
4012 | ioapic = mp_find_ioapic(0); | |
4013 | if (ioapic < 0) | |
4014 | ioapic = 0; | |
4015 | } | |
4016 | #endif | |
6c2e9403 | 4017 | |
b9c61b70 YL |
4018 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4019 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4020 | if (irq_entry == -1) | |
4021 | continue; | |
4022 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4023 | |
b9c61b70 | 4024 | desc = irq_to_desc(irq); |
6c2e9403 | 4025 | |
b9c61b70 YL |
4026 | /* |
4027 | * Honour affinities which have been set in early boot | |
4028 | */ | |
4029 | if (desc->status & | |
4030 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4031 | mask = desc->affinity; | |
4032 | else | |
4033 | mask = apic->target_cpus(); | |
497c9a19 | 4034 | |
b9c61b70 YL |
4035 | if (intr_remapping_enabled) |
4036 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4037 | else | |
4038 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4039 | } |
b9c61b70 | 4040 | |
497c9a19 YL |
4041 | } |
4042 | #endif | |
4043 | ||
54168ed7 IM |
4044 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4045 | ||
4046 | static struct resource *ioapic_resources; | |
4047 | ||
ffc43836 | 4048 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4049 | { |
4050 | unsigned long n; | |
4051 | struct resource *res; | |
4052 | char *mem; | |
4053 | int i; | |
4054 | ||
4055 | if (nr_ioapics <= 0) | |
4056 | return NULL; | |
4057 | ||
4058 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4059 | n *= nr_ioapics; | |
4060 | ||
4061 | mem = alloc_bootmem(n); | |
4062 | res = (void *)mem; | |
4063 | ||
ffc43836 | 4064 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4065 | |
ffc43836 CG |
4066 | for (i = 0; i < nr_ioapics; i++) { |
4067 | res[i].name = mem; | |
4068 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4069 | sprintf(mem, "IOAPIC %u", i); | |
4070 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
54168ed7 IM |
4071 | } |
4072 | ||
4073 | ioapic_resources = res; | |
4074 | ||
4075 | return res; | |
4076 | } | |
54168ed7 | 4077 | |
f3294a33 YL |
4078 | void __init ioapic_init_mappings(void) |
4079 | { | |
4080 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4081 | struct resource *ioapic_res; |
d6c88a50 | 4082 | int i; |
f3294a33 | 4083 | |
ffc43836 | 4084 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4085 | for (i = 0; i < nr_ioapics; i++) { |
4086 | if (smp_found_config) { | |
b5ba7e6d | 4087 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4088 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4089 | if (!ioapic_phys) { |
4090 | printk(KERN_ERR | |
4091 | "WARNING: bogus zero IO-APIC " | |
4092 | "address found in MPTABLE, " | |
4093 | "disabling IO/APIC support!\n"); | |
4094 | smp_found_config = 0; | |
4095 | skip_ioapic_setup = 1; | |
4096 | goto fake_ioapic_page; | |
4097 | } | |
54168ed7 | 4098 | #endif |
f3294a33 | 4099 | } else { |
54168ed7 | 4100 | #ifdef CONFIG_X86_32 |
f3294a33 | 4101 | fake_ioapic_page: |
54168ed7 | 4102 | #endif |
f3294a33 | 4103 | ioapic_phys = (unsigned long) |
54168ed7 | 4104 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4105 | ioapic_phys = __pa(ioapic_phys); |
4106 | } | |
4107 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4108 | apic_printk(APIC_VERBOSE, |
4109 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4110 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4111 | idx++; |
54168ed7 | 4112 | |
ffc43836 | 4113 | ioapic_res->start = ioapic_phys; |
46dc281b | 4114 | ioapic_res->end = ioapic_phys + PAGE_SIZE-1; |
ffc43836 | 4115 | ioapic_res++; |
f3294a33 YL |
4116 | } |
4117 | } | |
4118 | ||
857fdc53 | 4119 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4120 | { |
4121 | int i; | |
4122 | struct resource *r = ioapic_resources; | |
4123 | ||
4124 | if (!r) { | |
857fdc53 | 4125 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4126 | printk(KERN_ERR |
4127 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4128 | return; |
54168ed7 IM |
4129 | } |
4130 | ||
4131 | for (i = 0; i < nr_ioapics; i++) { | |
4132 | insert_resource(&iomem_resource, r); | |
4133 | r++; | |
4134 | } | |
54168ed7 | 4135 | } |
2a4ab640 FT |
4136 | |
4137 | int mp_find_ioapic(int gsi) | |
4138 | { | |
4139 | int i = 0; | |
4140 | ||
4141 | /* Find the IOAPIC that manages this GSI. */ | |
4142 | for (i = 0; i < nr_ioapics; i++) { | |
4143 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4144 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4145 | return i; | |
4146 | } | |
54168ed7 | 4147 | |
2a4ab640 FT |
4148 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4149 | return -1; | |
4150 | } | |
4151 | ||
4152 | int mp_find_ioapic_pin(int ioapic, int gsi) | |
4153 | { | |
4154 | if (WARN_ON(ioapic == -1)) | |
4155 | return -1; | |
4156 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4157 | return -1; | |
4158 | ||
4159 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4160 | } | |
4161 | ||
4162 | static int bad_ioapic(unsigned long address) | |
4163 | { | |
4164 | if (nr_ioapics >= MAX_IO_APICS) { | |
4165 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4166 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4167 | return 1; | |
4168 | } | |
4169 | if (!address) { | |
4170 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4171 | " found in table, skipping!\n"); | |
4172 | return 1; | |
4173 | } | |
54168ed7 IM |
4174 | return 0; |
4175 | } | |
4176 | ||
2a4ab640 FT |
4177 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4178 | { | |
4179 | int idx = 0; | |
4180 | ||
4181 | if (bad_ioapic(address)) | |
4182 | return; | |
4183 | ||
4184 | idx = nr_ioapics; | |
4185 | ||
4186 | mp_ioapics[idx].type = MP_IOAPIC; | |
4187 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4188 | mp_ioapics[idx].apicaddr = address; | |
4189 | ||
4190 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4191 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4192 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4193 | ||
4194 | /* | |
4195 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4196 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4197 | */ | |
4198 | mp_gsi_routing[idx].gsi_base = gsi_base; | |
4199 | mp_gsi_routing[idx].gsi_end = gsi_base + | |
4200 | io_apic_get_redir_entries(idx); | |
4201 | ||
4202 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4203 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4204 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4205 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4206 | ||
4207 | nr_ioapics++; | |
4208 | } |