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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
132 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
133 | { | |
134 | struct irq_pin_list *pin; | |
135 | int node; | |
136 | ||
137 | node = cpu_to_node(cpu); | |
138 | ||
139 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
140 | |
141 | return pin; | |
142 | } | |
143 | ||
a1420f39 | 144 | struct irq_cfg { |
0f978f45 | 145 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
146 | cpumask_var_t domain; |
147 | cpumask_var_t old_domain; | |
497c9a19 | 148 | unsigned move_cleanup_count; |
a1420f39 | 149 | u8 vector; |
497c9a19 | 150 | u8 move_in_progress : 1; |
48a1b10a YL |
151 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
152 | u8 move_desc_pending : 1; | |
153 | #endif | |
a1420f39 YL |
154 | }; |
155 | ||
a1420f39 | 156 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
157 | #ifdef CONFIG_SPARSE_IRQ |
158 | static struct irq_cfg irq_cfgx[] = { | |
159 | #else | |
d6c88a50 | 160 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 161 | #endif |
22f65d31 MT |
162 | [0] = { .vector = IRQ0_VECTOR, }, |
163 | [1] = { .vector = IRQ1_VECTOR, }, | |
164 | [2] = { .vector = IRQ2_VECTOR, }, | |
165 | [3] = { .vector = IRQ3_VECTOR, }, | |
166 | [4] = { .vector = IRQ4_VECTOR, }, | |
167 | [5] = { .vector = IRQ5_VECTOR, }, | |
168 | [6] = { .vector = IRQ6_VECTOR, }, | |
169 | [7] = { .vector = IRQ7_VECTOR, }, | |
170 | [8] = { .vector = IRQ8_VECTOR, }, | |
171 | [9] = { .vector = IRQ9_VECTOR, }, | |
172 | [10] = { .vector = IRQ10_VECTOR, }, | |
173 | [11] = { .vector = IRQ11_VECTOR, }, | |
174 | [12] = { .vector = IRQ12_VECTOR, }, | |
175 | [13] = { .vector = IRQ13_VECTOR, }, | |
176 | [14] = { .vector = IRQ14_VECTOR, }, | |
177 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
178 | }; |
179 | ||
13a0c3c2 | 180 | int __init arch_early_irq_init(void) |
8f09cd20 | 181 | { |
0b8f1efa YL |
182 | struct irq_cfg *cfg; |
183 | struct irq_desc *desc; | |
184 | int count; | |
185 | int i; | |
d6c88a50 | 186 | |
0b8f1efa YL |
187 | cfg = irq_cfgx; |
188 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 189 | |
0b8f1efa YL |
190 | for (i = 0; i < count; i++) { |
191 | desc = irq_to_desc(i); | |
192 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
193 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
194 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
195 | if (i < NR_IRQS_LEGACY) | |
196 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 197 | } |
13a0c3c2 YL |
198 | |
199 | return 0; | |
0b8f1efa | 200 | } |
8f09cd20 | 201 | |
0b8f1efa | 202 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 203 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 204 | { |
0b8f1efa YL |
205 | struct irq_cfg *cfg = NULL; |
206 | struct irq_desc *desc; | |
1da177e4 | 207 | |
0b8f1efa YL |
208 | desc = irq_to_desc(irq); |
209 | if (desc) | |
210 | cfg = desc->chip_data; | |
0f978f45 | 211 | |
0b8f1efa | 212 | return cfg; |
8f09cd20 | 213 | } |
d6c88a50 | 214 | |
0b8f1efa | 215 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
8f09cd20 | 216 | { |
0b8f1efa YL |
217 | struct irq_cfg *cfg; |
218 | int node; | |
219 | ||
220 | node = cpu_to_node(cpu); | |
0f978f45 | 221 | |
0b8f1efa | 222 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 223 | if (cfg) { |
80855f73 | 224 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
225 | kfree(cfg); |
226 | cfg = NULL; | |
80855f73 MT |
227 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
228 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
229 | free_cpumask_var(cfg->domain); |
230 | kfree(cfg); | |
231 | cfg = NULL; | |
232 | } else { | |
233 | cpumask_clear(cfg->domain); | |
234 | cpumask_clear(cfg->old_domain); | |
235 | } | |
236 | } | |
0f978f45 | 237 | |
0b8f1efa | 238 | return cfg; |
8f09cd20 YL |
239 | } |
240 | ||
13a0c3c2 | 241 | int arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 242 | { |
0b8f1efa | 243 | struct irq_cfg *cfg; |
d6c88a50 | 244 | |
0b8f1efa YL |
245 | cfg = desc->chip_data; |
246 | if (!cfg) { | |
247 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
248 | if (!desc->chip_data) { | |
249 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
250 | BUG_ON(1); | |
251 | } | |
252 | } | |
1da177e4 | 253 | |
13a0c3c2 | 254 | return 0; |
0b8f1efa | 255 | } |
0f978f45 | 256 | |
48a1b10a | 257 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
d6c88a50 | 258 | |
48a1b10a YL |
259 | static void |
260 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
0f978f45 | 261 | { |
48a1b10a YL |
262 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
263 | ||
264 | cfg->irq_2_pin = NULL; | |
265 | old_entry = old_cfg->irq_2_pin; | |
266 | if (!old_entry) | |
267 | return; | |
0f978f45 | 268 | |
48a1b10a YL |
269 | entry = get_one_free_irq_2_pin(cpu); |
270 | if (!entry) | |
271 | return; | |
0f978f45 | 272 | |
48a1b10a YL |
273 | entry->apic = old_entry->apic; |
274 | entry->pin = old_entry->pin; | |
275 | head = entry; | |
276 | tail = entry; | |
277 | old_entry = old_entry->next; | |
278 | while (old_entry) { | |
279 | entry = get_one_free_irq_2_pin(cpu); | |
280 | if (!entry) { | |
281 | entry = head; | |
282 | while (entry) { | |
283 | head = entry->next; | |
284 | kfree(entry); | |
285 | entry = head; | |
286 | } | |
287 | /* still use the old one */ | |
288 | return; | |
289 | } | |
290 | entry->apic = old_entry->apic; | |
291 | entry->pin = old_entry->pin; | |
292 | tail->next = entry; | |
293 | tail = entry; | |
294 | old_entry = old_entry->next; | |
295 | } | |
0f978f45 | 296 | |
48a1b10a YL |
297 | tail->next = NULL; |
298 | cfg->irq_2_pin = head; | |
0f978f45 | 299 | } |
0f978f45 | 300 | |
48a1b10a | 301 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 302 | { |
48a1b10a | 303 | struct irq_pin_list *entry, *next; |
0f978f45 | 304 | |
48a1b10a YL |
305 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
306 | return; | |
301e6190 | 307 | |
48a1b10a | 308 | entry = old_cfg->irq_2_pin; |
0f978f45 | 309 | |
48a1b10a YL |
310 | while (entry) { |
311 | next = entry->next; | |
312 | kfree(entry); | |
313 | entry = next; | |
314 | } | |
315 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 316 | } |
0f978f45 | 317 | |
48a1b10a YL |
318 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
319 | struct irq_desc *desc, int cpu) | |
0f978f45 | 320 | { |
48a1b10a YL |
321 | struct irq_cfg *cfg; |
322 | struct irq_cfg *old_cfg; | |
0f978f45 | 323 | |
48a1b10a | 324 | cfg = get_one_free_irq_cfg(cpu); |
301e6190 | 325 | |
48a1b10a YL |
326 | if (!cfg) |
327 | return; | |
328 | ||
329 | desc->chip_data = cfg; | |
330 | ||
331 | old_cfg = old_desc->chip_data; | |
332 | ||
333 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
334 | ||
335 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
0f978f45 | 336 | } |
1da177e4 | 337 | |
48a1b10a YL |
338 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
339 | { | |
340 | kfree(old_cfg); | |
341 | } | |
342 | ||
343 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
344 | { | |
345 | struct irq_cfg *old_cfg, *cfg; | |
346 | ||
347 | old_cfg = old_desc->chip_data; | |
348 | cfg = desc->chip_data; | |
349 | ||
350 | if (old_cfg == cfg) | |
351 | return; | |
352 | ||
353 | if (old_cfg) { | |
354 | free_irq_2_pin(old_cfg, cfg); | |
355 | free_irq_cfg(old_cfg); | |
356 | old_desc->chip_data = NULL; | |
357 | } | |
358 | } | |
359 | ||
d733e00d IM |
360 | static void |
361 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
48a1b10a YL |
362 | { |
363 | struct irq_cfg *cfg = desc->chip_data; | |
364 | ||
365 | if (!cfg->move_in_progress) { | |
366 | /* it means that domain is not changed */ | |
7f7ace0c | 367 | if (!cpumask_intersects(desc->affinity, mask)) |
48a1b10a YL |
368 | cfg->move_desc_pending = 1; |
369 | } | |
0f978f45 | 370 | } |
48a1b10a YL |
371 | #endif |
372 | ||
0b8f1efa YL |
373 | #else |
374 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
375 | { | |
376 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 377 | } |
1da177e4 | 378 | |
0b8f1efa YL |
379 | #endif |
380 | ||
48a1b10a | 381 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
382 | static inline void |
383 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 YL |
384 | { |
385 | } | |
48a1b10a | 386 | #endif |
1da177e4 | 387 | |
130fe05d LT |
388 | struct io_apic { |
389 | unsigned int index; | |
390 | unsigned int unused[3]; | |
391 | unsigned int data; | |
0280f7c4 SS |
392 | unsigned int unused2[11]; |
393 | unsigned int eoi; | |
130fe05d LT |
394 | }; |
395 | ||
396 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
397 | { | |
398 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 399 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
400 | } |
401 | ||
0280f7c4 SS |
402 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
403 | { | |
404 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
405 | writel(vector, &io_apic->eoi); | |
406 | } | |
407 | ||
130fe05d LT |
408 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
409 | { | |
410 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
411 | writel(reg, &io_apic->index); | |
412 | return readl(&io_apic->data); | |
413 | } | |
414 | ||
415 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
416 | { | |
417 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
418 | writel(reg, &io_apic->index); | |
419 | writel(value, &io_apic->data); | |
420 | } | |
421 | ||
422 | /* | |
423 | * Re-write a value: to be used for read-modify-write | |
424 | * cycles where the read already set up the index register. | |
425 | * | |
426 | * Older SiS APIC requires we rewrite the index register | |
427 | */ | |
428 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
429 | { | |
54168ed7 | 430 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
431 | |
432 | if (sis_apic_bug) | |
433 | writel(reg, &io_apic->index); | |
130fe05d LT |
434 | writel(value, &io_apic->data); |
435 | } | |
436 | ||
3145e941 | 437 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
438 | { |
439 | struct irq_pin_list *entry; | |
440 | unsigned long flags; | |
047c8fdb YL |
441 | |
442 | spin_lock_irqsave(&ioapic_lock, flags); | |
443 | entry = cfg->irq_2_pin; | |
444 | for (;;) { | |
445 | unsigned int reg; | |
446 | int pin; | |
447 | ||
448 | if (!entry) | |
449 | break; | |
450 | pin = entry->pin; | |
451 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
452 | /* Is the remote IRR bit set? */ | |
453 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
454 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
455 | return true; | |
456 | } | |
457 | if (!entry->next) | |
458 | break; | |
459 | entry = entry->next; | |
460 | } | |
461 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
462 | ||
463 | return false; | |
464 | } | |
047c8fdb | 465 | |
cf4c6a2f AK |
466 | union entry_union { |
467 | struct { u32 w1, w2; }; | |
468 | struct IO_APIC_route_entry entry; | |
469 | }; | |
470 | ||
471 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
472 | { | |
473 | union entry_union eu; | |
474 | unsigned long flags; | |
475 | spin_lock_irqsave(&ioapic_lock, flags); | |
476 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
477 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
478 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
479 | return eu.entry; | |
480 | } | |
481 | ||
f9dadfa7 LT |
482 | /* |
483 | * When we write a new IO APIC routing entry, we need to write the high | |
484 | * word first! If the mask bit in the low word is clear, we will enable | |
485 | * the interrupt, and we need to make sure the entry is fully populated | |
486 | * before that happens. | |
487 | */ | |
d15512f4 AK |
488 | static void |
489 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 490 | { |
cf4c6a2f AK |
491 | union entry_union eu; |
492 | eu.entry = e; | |
f9dadfa7 LT |
493 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
494 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
495 | } |
496 | ||
ca97ab90 | 497 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
498 | { |
499 | unsigned long flags; | |
500 | spin_lock_irqsave(&ioapic_lock, flags); | |
501 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
502 | spin_unlock_irqrestore(&ioapic_lock, flags); |
503 | } | |
504 | ||
505 | /* | |
506 | * When we mask an IO APIC routing entry, we need to write the low | |
507 | * word first, in order to set the mask bit before we change the | |
508 | * high bits! | |
509 | */ | |
510 | static void ioapic_mask_entry(int apic, int pin) | |
511 | { | |
512 | unsigned long flags; | |
513 | union entry_union eu = { .entry.mask = 1 }; | |
514 | ||
cf4c6a2f AK |
515 | spin_lock_irqsave(&ioapic_lock, flags); |
516 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
517 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
518 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
519 | } | |
520 | ||
497c9a19 | 521 | #ifdef CONFIG_SMP |
22f65d31 MT |
522 | static void send_cleanup_vector(struct irq_cfg *cfg) |
523 | { | |
524 | cpumask_var_t cleanup_mask; | |
525 | ||
526 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
527 | unsigned int i; | |
528 | cfg->move_cleanup_count = 0; | |
529 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
530 | cfg->move_cleanup_count++; | |
531 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
dac5f412 | 532 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
533 | } else { |
534 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
535 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
dac5f412 | 536 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
537 | free_cpumask_var(cleanup_mask); |
538 | } | |
539 | cfg->move_in_progress = 0; | |
540 | } | |
541 | ||
3145e941 | 542 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
543 | { |
544 | int apic, pin; | |
497c9a19 | 545 | struct irq_pin_list *entry; |
3145e941 | 546 | u8 vector = cfg->vector; |
497c9a19 | 547 | |
497c9a19 YL |
548 | entry = cfg->irq_2_pin; |
549 | for (;;) { | |
550 | unsigned int reg; | |
551 | ||
552 | if (!entry) | |
553 | break; | |
554 | ||
555 | apic = entry->apic; | |
556 | pin = entry->pin; | |
54168ed7 IM |
557 | /* |
558 | * With interrupt-remapping, destination information comes | |
559 | * from interrupt-remapping table entry. | |
560 | */ | |
561 | if (!irq_remapped(irq)) | |
562 | io_apic_write(apic, 0x11 + pin*2, dest); | |
497c9a19 YL |
563 | reg = io_apic_read(apic, 0x10 + pin*2); |
564 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
565 | reg |= vector; | |
54168ed7 | 566 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
567 | if (!entry->next) |
568 | break; | |
569 | entry = entry->next; | |
570 | } | |
571 | } | |
efa2559f | 572 | |
e7986739 MT |
573 | static int |
574 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 575 | |
22f65d31 | 576 | /* |
debccb3e IM |
577 | * Either sets desc->affinity to a valid value, and returns |
578 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
579 | * leaves desc->affinity untouched. | |
22f65d31 MT |
580 | */ |
581 | static unsigned int | |
582 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
583 | { |
584 | struct irq_cfg *cfg; | |
3145e941 | 585 | unsigned int irq; |
497c9a19 | 586 | |
0de26520 | 587 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 588 | return BAD_APICID; |
497c9a19 | 589 | |
3145e941 YL |
590 | irq = desc->irq; |
591 | cfg = desc->chip_data; | |
592 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 593 | return BAD_APICID; |
497c9a19 | 594 | |
fa74c907 | 595 | /* check that before desc->addinity get updated */ |
3145e941 | 596 | set_extra_move_desc(desc, mask); |
debccb3e | 597 | |
e06b1b56 RR |
598 | cpumask_copy(desc->affinity, mask); |
599 | ||
600 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
22f65d31 | 601 | } |
3145e941 | 602 | |
22f65d31 MT |
603 | static void |
604 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
605 | { |
606 | struct irq_cfg *cfg; | |
607 | unsigned long flags; | |
608 | unsigned int dest; | |
22f65d31 | 609 | unsigned int irq; |
497c9a19 | 610 | |
22f65d31 MT |
611 | irq = desc->irq; |
612 | cfg = desc->chip_data; | |
497c9a19 | 613 | |
497c9a19 | 614 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
615 | dest = set_desc_affinity(desc, mask); |
616 | if (dest != BAD_APICID) { | |
617 | /* Only the high 8 bits are valid. */ | |
618 | dest = SET_APIC_LOGICAL_ID(dest); | |
619 | __target_IO_APIC_irq(irq, dest, cfg); | |
620 | } | |
497c9a19 YL |
621 | spin_unlock_irqrestore(&ioapic_lock, flags); |
622 | } | |
497c9a19 | 623 | |
22f65d31 MT |
624 | static void |
625 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
626 | { |
627 | struct irq_desc *desc; | |
497c9a19 | 628 | |
54168ed7 | 629 | desc = irq_to_desc(irq); |
3145e941 YL |
630 | |
631 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 632 | } |
497c9a19 YL |
633 | #endif /* CONFIG_SMP */ |
634 | ||
1da177e4 LT |
635 | /* |
636 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
637 | * shared ISA-space IRQs, so we have to support them. We are super | |
638 | * fast in the common case, and fast for shared ISA-space IRQs. | |
639 | */ | |
3145e941 | 640 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 641 | { |
0f978f45 YL |
642 | struct irq_pin_list *entry; |
643 | ||
0f978f45 YL |
644 | entry = cfg->irq_2_pin; |
645 | if (!entry) { | |
0b8f1efa YL |
646 | entry = get_one_free_irq_2_pin(cpu); |
647 | if (!entry) { | |
648 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
649 | apic, pin); | |
650 | return; | |
651 | } | |
0f978f45 YL |
652 | cfg->irq_2_pin = entry; |
653 | entry->apic = apic; | |
654 | entry->pin = pin; | |
0f978f45 YL |
655 | return; |
656 | } | |
1da177e4 | 657 | |
0f978f45 YL |
658 | while (entry->next) { |
659 | /* not again, please */ | |
660 | if (entry->apic == apic && entry->pin == pin) | |
661 | return; | |
1da177e4 | 662 | |
0f978f45 | 663 | entry = entry->next; |
1da177e4 | 664 | } |
0f978f45 | 665 | |
0b8f1efa | 666 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 667 | entry = entry->next; |
1da177e4 LT |
668 | entry->apic = apic; |
669 | entry->pin = pin; | |
670 | } | |
671 | ||
672 | /* | |
673 | * Reroute an IRQ to a different pin. | |
674 | */ | |
3145e941 | 675 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
676 | int oldapic, int oldpin, |
677 | int newapic, int newpin) | |
678 | { | |
0f978f45 YL |
679 | struct irq_pin_list *entry = cfg->irq_2_pin; |
680 | int replaced = 0; | |
1da177e4 | 681 | |
0f978f45 | 682 | while (entry) { |
1da177e4 LT |
683 | if (entry->apic == oldapic && entry->pin == oldpin) { |
684 | entry->apic = newapic; | |
685 | entry->pin = newpin; | |
0f978f45 YL |
686 | replaced = 1; |
687 | /* every one is different, right? */ | |
1da177e4 | 688 | break; |
0f978f45 YL |
689 | } |
690 | entry = entry->next; | |
1da177e4 | 691 | } |
0f978f45 YL |
692 | |
693 | /* why? call replace before add? */ | |
694 | if (!replaced) | |
3145e941 | 695 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
696 | } |
697 | ||
3145e941 | 698 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
699 | int mask_and, int mask_or, |
700 | void (*final)(struct irq_pin_list *entry)) | |
701 | { | |
702 | int pin; | |
87783be4 | 703 | struct irq_pin_list *entry; |
047c8fdb | 704 | |
87783be4 CG |
705 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
706 | unsigned int reg; | |
707 | pin = entry->pin; | |
708 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
709 | reg &= mask_and; | |
710 | reg |= mask_or; | |
711 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
712 | if (final) | |
713 | final(entry); | |
714 | } | |
715 | } | |
047c8fdb | 716 | |
3145e941 | 717 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 718 | { |
3145e941 | 719 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 720 | } |
047c8fdb | 721 | |
4e738e2f | 722 | #ifdef CONFIG_X86_64 |
7f3e632f | 723 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 724 | { |
87783be4 CG |
725 | /* |
726 | * Synchronize the IO-APIC and the CPU by doing | |
727 | * a dummy read from the IO-APIC | |
728 | */ | |
729 | struct io_apic __iomem *io_apic; | |
730 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 731 | readl(&io_apic->data); |
1da177e4 LT |
732 | } |
733 | ||
3145e941 | 734 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 735 | { |
3145e941 | 736 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
737 | } |
738 | #else /* CONFIG_X86_32 */ | |
3145e941 | 739 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 740 | { |
3145e941 | 741 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 742 | } |
1da177e4 | 743 | |
3145e941 | 744 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 745 | { |
3145e941 | 746 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
747 | IO_APIC_REDIR_MASKED, NULL); |
748 | } | |
1da177e4 | 749 | |
3145e941 | 750 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 751 | { |
3145e941 | 752 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
753 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
754 | } | |
755 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 756 | |
3145e941 | 757 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 758 | { |
3145e941 | 759 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
760 | unsigned long flags; |
761 | ||
3145e941 YL |
762 | BUG_ON(!cfg); |
763 | ||
1da177e4 | 764 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 765 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
766 | spin_unlock_irqrestore(&ioapic_lock, flags); |
767 | } | |
768 | ||
3145e941 | 769 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 770 | { |
3145e941 | 771 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
772 | unsigned long flags; |
773 | ||
774 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 775 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
776 | spin_unlock_irqrestore(&ioapic_lock, flags); |
777 | } | |
778 | ||
3145e941 YL |
779 | static void mask_IO_APIC_irq(unsigned int irq) |
780 | { | |
781 | struct irq_desc *desc = irq_to_desc(irq); | |
782 | ||
783 | mask_IO_APIC_irq_desc(desc); | |
784 | } | |
785 | static void unmask_IO_APIC_irq(unsigned int irq) | |
786 | { | |
787 | struct irq_desc *desc = irq_to_desc(irq); | |
788 | ||
789 | unmask_IO_APIC_irq_desc(desc); | |
790 | } | |
791 | ||
1da177e4 LT |
792 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
793 | { | |
794 | struct IO_APIC_route_entry entry; | |
36062448 | 795 | |
1da177e4 | 796 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 797 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
798 | if (entry.delivery_mode == dest_SMI) |
799 | return; | |
1da177e4 LT |
800 | /* |
801 | * Disable it in the IO-APIC irq-routing table: | |
802 | */ | |
f9dadfa7 | 803 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
804 | } |
805 | ||
54168ed7 | 806 | static void clear_IO_APIC (void) |
1da177e4 LT |
807 | { |
808 | int apic, pin; | |
809 | ||
810 | for (apic = 0; apic < nr_ioapics; apic++) | |
811 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
812 | clear_IO_APIC_pin(apic, pin); | |
813 | } | |
814 | ||
54168ed7 | 815 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
816 | /* |
817 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
818 | * specific CPU-side IRQs. | |
819 | */ | |
820 | ||
821 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
822 | static int pirq_entries[MAX_PIRQS] = { |
823 | [0 ... MAX_PIRQS - 1] = -1 | |
824 | }; | |
1da177e4 | 825 | |
1da177e4 LT |
826 | static int __init ioapic_pirq_setup(char *str) |
827 | { | |
828 | int i, max; | |
829 | int ints[MAX_PIRQS+1]; | |
830 | ||
831 | get_options(str, ARRAY_SIZE(ints), ints); | |
832 | ||
1da177e4 LT |
833 | apic_printk(APIC_VERBOSE, KERN_INFO |
834 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
835 | max = MAX_PIRQS; | |
836 | if (ints[0] < MAX_PIRQS) | |
837 | max = ints[0]; | |
838 | ||
839 | for (i = 0; i < max; i++) { | |
840 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
841 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
842 | /* | |
843 | * PIRQs are mapped upside down, usually. | |
844 | */ | |
845 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
846 | } | |
847 | return 1; | |
848 | } | |
849 | ||
850 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
851 | #endif /* CONFIG_X86_32 */ |
852 | ||
853 | #ifdef CONFIG_INTR_REMAP | |
b24696bc FY |
854 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
855 | { | |
856 | int apic; | |
857 | struct IO_APIC_route_entry **ioapic_entries; | |
858 | ||
859 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
860 | GFP_ATOMIC); | |
861 | if (!ioapic_entries) | |
862 | return 0; | |
863 | ||
864 | for (apic = 0; apic < nr_ioapics; apic++) { | |
865 | ioapic_entries[apic] = | |
866 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
867 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
868 | if (!ioapic_entries[apic]) | |
869 | goto nomem; | |
870 | } | |
871 | ||
872 | return ioapic_entries; | |
873 | ||
874 | nomem: | |
875 | while (--apic >= 0) | |
876 | kfree(ioapic_entries[apic]); | |
877 | kfree(ioapic_entries); | |
878 | ||
879 | return 0; | |
880 | } | |
54168ed7 IM |
881 | |
882 | /* | |
05c3dc2c | 883 | * Saves all the IO-APIC RTE's |
54168ed7 | 884 | */ |
b24696bc | 885 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 886 | { |
54168ed7 IM |
887 | int apic, pin; |
888 | ||
b24696bc FY |
889 | if (!ioapic_entries) |
890 | return -ENOMEM; | |
54168ed7 IM |
891 | |
892 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
893 | if (!ioapic_entries[apic]) |
894 | return -ENOMEM; | |
54168ed7 | 895 | |
05c3dc2c | 896 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 897 | ioapic_entries[apic][pin] = |
54168ed7 | 898 | ioapic_read_entry(apic, pin); |
b24696bc | 899 | } |
5ffa4eb2 | 900 | |
54168ed7 IM |
901 | return 0; |
902 | } | |
903 | ||
b24696bc FY |
904 | /* |
905 | * Mask all IO APIC entries. | |
906 | */ | |
907 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
908 | { |
909 | int apic, pin; | |
910 | ||
b24696bc FY |
911 | if (!ioapic_entries) |
912 | return; | |
913 | ||
05c3dc2c | 914 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 915 | if (!ioapic_entries[apic]) |
05c3dc2c | 916 | break; |
b24696bc | 917 | |
05c3dc2c SS |
918 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
919 | struct IO_APIC_route_entry entry; | |
920 | ||
b24696bc | 921 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
922 | if (!entry.mask) { |
923 | entry.mask = 1; | |
924 | ioapic_write_entry(apic, pin, entry); | |
925 | } | |
926 | } | |
927 | } | |
928 | } | |
929 | ||
b24696bc FY |
930 | /* |
931 | * Restore IO APIC entries which was saved in ioapic_entries. | |
932 | */ | |
933 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
934 | { |
935 | int apic, pin; | |
936 | ||
b24696bc FY |
937 | if (!ioapic_entries) |
938 | return -ENOMEM; | |
939 | ||
5ffa4eb2 | 940 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
941 | if (!ioapic_entries[apic]) |
942 | return -ENOMEM; | |
943 | ||
54168ed7 IM |
944 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
945 | ioapic_write_entry(apic, pin, | |
b24696bc | 946 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 947 | } |
b24696bc | 948 | return 0; |
54168ed7 IM |
949 | } |
950 | ||
b24696bc FY |
951 | void reinit_intr_remapped_IO_APIC(int intr_remapping, |
952 | struct IO_APIC_route_entry **ioapic_entries) | |
953 | ||
54168ed7 IM |
954 | { |
955 | /* | |
956 | * for now plain restore of previous settings. | |
957 | * TBD: In the case of OS enabling interrupt-remapping, | |
958 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
959 | * table entries. for now, do a plain restore, and wait for | |
960 | * the setup_IO_APIC_irqs() to do proper initialization. | |
961 | */ | |
b24696bc FY |
962 | restore_IO_APIC_setup(ioapic_entries); |
963 | } | |
964 | ||
965 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) | |
966 | { | |
967 | int apic; | |
968 | ||
969 | for (apic = 0; apic < nr_ioapics; apic++) | |
970 | kfree(ioapic_entries[apic]); | |
971 | ||
972 | kfree(ioapic_entries); | |
54168ed7 IM |
973 | } |
974 | #endif | |
1da177e4 LT |
975 | |
976 | /* | |
977 | * Find the IRQ entry number of a certain pin. | |
978 | */ | |
979 | static int find_irq_entry(int apic, int pin, int type) | |
980 | { | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
984 | if (mp_irqs[i].irqtype == type && |
985 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
986 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
987 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
988 | return i; |
989 | ||
990 | return -1; | |
991 | } | |
992 | ||
993 | /* | |
994 | * Find the pin to which IRQ[irq] (ISA) is connected | |
995 | */ | |
fcfd636a | 996 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
997 | { |
998 | int i; | |
999 | ||
1000 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1001 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 1002 | |
d27e2b8e | 1003 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
1004 | (mp_irqs[i].irqtype == type) && |
1005 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 1006 | |
c2c21745 | 1007 | return mp_irqs[i].dstirq; |
1da177e4 LT |
1008 | } |
1009 | return -1; | |
1010 | } | |
1011 | ||
fcfd636a EB |
1012 | static int __init find_isa_irq_apic(int irq, int type) |
1013 | { | |
1014 | int i; | |
1015 | ||
1016 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1017 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 1018 | |
73b2961b | 1019 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
1020 | (mp_irqs[i].irqtype == type) && |
1021 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
1022 | break; |
1023 | } | |
1024 | if (i < mp_irq_entries) { | |
1025 | int apic; | |
54168ed7 | 1026 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 1027 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
1028 | return apic; |
1029 | } | |
1030 | } | |
1031 | ||
1032 | return -1; | |
1033 | } | |
1034 | ||
1da177e4 LT |
1035 | /* |
1036 | * Find a specific PCI IRQ entry. | |
1037 | * Not an __init, possibly needed by modules | |
1038 | */ | |
1039 | static int pin_2_irq(int idx, int apic, int pin); | |
1040 | ||
1041 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1042 | { | |
1043 | int apic, i, best_guess = -1; | |
1044 | ||
54168ed7 IM |
1045 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1046 | bus, slot, pin); | |
ce6444d3 | 1047 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1048 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1049 | return -1; |
1050 | } | |
1051 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1052 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
1053 | |
1054 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
1055 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
1056 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1057 | break; |
1058 | ||
47cab822 | 1059 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 1060 | !mp_irqs[i].irqtype && |
1da177e4 | 1061 | (bus == lbus) && |
c2c21745 JSR |
1062 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
1063 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
1064 | |
1065 | if (!(apic || IO_APIC_IRQ(irq))) | |
1066 | continue; | |
1067 | ||
c2c21745 | 1068 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
1069 | return irq; |
1070 | /* | |
1071 | * Use the first all-but-pin matching entry as a | |
1072 | * best-guess fuzzy result for broken mptables. | |
1073 | */ | |
1074 | if (best_guess < 0) | |
1075 | best_guess = irq; | |
1076 | } | |
1077 | } | |
1078 | return best_guess; | |
1079 | } | |
54168ed7 | 1080 | |
129f6946 | 1081 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1082 | |
c0a282c2 | 1083 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1084 | /* |
1085 | * EISA Edge/Level control register, ELCR | |
1086 | */ | |
1087 | static int EISA_ELCR(unsigned int irq) | |
1088 | { | |
99d093d1 | 1089 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1090 | unsigned int port = 0x4d0 + (irq >> 3); |
1091 | return (inb(port) >> (irq & 7)) & 1; | |
1092 | } | |
1093 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1094 | "Broken MPtable reports ISA irq %d\n", irq); | |
1095 | return 0; | |
1096 | } | |
54168ed7 | 1097 | |
c0a282c2 | 1098 | #endif |
1da177e4 | 1099 | |
6728801d AS |
1100 | /* ISA interrupts are always polarity zero edge triggered, |
1101 | * when listed as conforming in the MP table. */ | |
1102 | ||
1103 | #define default_ISA_trigger(idx) (0) | |
1104 | #define default_ISA_polarity(idx) (0) | |
1105 | ||
1da177e4 LT |
1106 | /* EISA interrupts are always polarity zero and can be edge or level |
1107 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1108 | * EISA conforming in the MP table, that means its trigger type must | |
1109 | * be read in from the ELCR */ | |
1110 | ||
c2c21745 | 1111 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 1112 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1113 | |
1114 | /* PCI interrupts are always polarity one level triggered, | |
1115 | * when listed as conforming in the MP table. */ | |
1116 | ||
1117 | #define default_PCI_trigger(idx) (1) | |
1118 | #define default_PCI_polarity(idx) (1) | |
1119 | ||
1120 | /* MCA interrupts are always polarity zero level triggered, | |
1121 | * when listed as conforming in the MP table. */ | |
1122 | ||
1123 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1124 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1125 | |
61fd47e0 | 1126 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1127 | { |
c2c21745 | 1128 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1129 | int polarity; |
1130 | ||
1131 | /* | |
1132 | * Determine IRQ line polarity (high active or low active): | |
1133 | */ | |
c2c21745 | 1134 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 1135 | { |
54168ed7 IM |
1136 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1137 | if (test_bit(bus, mp_bus_not_pci)) | |
1138 | polarity = default_ISA_polarity(idx); | |
1139 | else | |
1140 | polarity = default_PCI_polarity(idx); | |
1141 | break; | |
1142 | case 1: /* high active */ | |
1143 | { | |
1144 | polarity = 0; | |
1145 | break; | |
1146 | } | |
1147 | case 2: /* reserved */ | |
1148 | { | |
1149 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1150 | polarity = 1; | |
1151 | break; | |
1152 | } | |
1153 | case 3: /* low active */ | |
1154 | { | |
1155 | polarity = 1; | |
1156 | break; | |
1157 | } | |
1158 | default: /* invalid */ | |
1159 | { | |
1160 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1161 | polarity = 1; | |
1162 | break; | |
1163 | } | |
1da177e4 LT |
1164 | } |
1165 | return polarity; | |
1166 | } | |
1167 | ||
1168 | static int MPBIOS_trigger(int idx) | |
1169 | { | |
c2c21745 | 1170 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1171 | int trigger; |
1172 | ||
1173 | /* | |
1174 | * Determine IRQ trigger mode (edge or level sensitive): | |
1175 | */ | |
c2c21745 | 1176 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1177 | { |
54168ed7 IM |
1178 | case 0: /* conforms, ie. bus-type dependent */ |
1179 | if (test_bit(bus, mp_bus_not_pci)) | |
1180 | trigger = default_ISA_trigger(idx); | |
1181 | else | |
1182 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1183 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1184 | switch (mp_bus_id_to_type[bus]) { |
1185 | case MP_BUS_ISA: /* ISA pin */ | |
1186 | { | |
1187 | /* set before the switch */ | |
1188 | break; | |
1189 | } | |
1190 | case MP_BUS_EISA: /* EISA pin */ | |
1191 | { | |
1192 | trigger = default_EISA_trigger(idx); | |
1193 | break; | |
1194 | } | |
1195 | case MP_BUS_PCI: /* PCI pin */ | |
1196 | { | |
1197 | /* set before the switch */ | |
1198 | break; | |
1199 | } | |
1200 | case MP_BUS_MCA: /* MCA pin */ | |
1201 | { | |
1202 | trigger = default_MCA_trigger(idx); | |
1203 | break; | |
1204 | } | |
1205 | default: | |
1206 | { | |
1207 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1208 | trigger = 1; | |
1209 | break; | |
1210 | } | |
1211 | } | |
1212 | #endif | |
1da177e4 | 1213 | break; |
54168ed7 | 1214 | case 1: /* edge */ |
1da177e4 | 1215 | { |
54168ed7 | 1216 | trigger = 0; |
1da177e4 LT |
1217 | break; |
1218 | } | |
54168ed7 | 1219 | case 2: /* reserved */ |
1da177e4 | 1220 | { |
54168ed7 IM |
1221 | printk(KERN_WARNING "broken BIOS!!\n"); |
1222 | trigger = 1; | |
1da177e4 LT |
1223 | break; |
1224 | } | |
54168ed7 | 1225 | case 3: /* level */ |
1da177e4 | 1226 | { |
54168ed7 | 1227 | trigger = 1; |
1da177e4 LT |
1228 | break; |
1229 | } | |
54168ed7 | 1230 | default: /* invalid */ |
1da177e4 LT |
1231 | { |
1232 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1233 | trigger = 0; |
1da177e4 LT |
1234 | break; |
1235 | } | |
1236 | } | |
1237 | return trigger; | |
1238 | } | |
1239 | ||
1240 | static inline int irq_polarity(int idx) | |
1241 | { | |
1242 | return MPBIOS_polarity(idx); | |
1243 | } | |
1244 | ||
1245 | static inline int irq_trigger(int idx) | |
1246 | { | |
1247 | return MPBIOS_trigger(idx); | |
1248 | } | |
1249 | ||
efa2559f | 1250 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1251 | static int pin_2_irq(int idx, int apic, int pin) |
1252 | { | |
1253 | int irq, i; | |
c2c21745 | 1254 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1255 | |
1256 | /* | |
1257 | * Debugging check, we are in big trouble if this message pops up! | |
1258 | */ | |
c2c21745 | 1259 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1260 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1261 | ||
54168ed7 | 1262 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1263 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1264 | } else { |
643befed AS |
1265 | /* |
1266 | * PCI IRQs are mapped in order | |
1267 | */ | |
1268 | i = irq = 0; | |
1269 | while (i < apic) | |
1270 | irq += nr_ioapic_registers[i++]; | |
1271 | irq += pin; | |
d6c88a50 | 1272 | /* |
54168ed7 IM |
1273 | * For MPS mode, so far only needed by ES7000 platform |
1274 | */ | |
d6c88a50 TG |
1275 | if (ioapic_renumber_irq) |
1276 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1277 | } |
1278 | ||
54168ed7 | 1279 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1280 | /* |
1281 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1282 | */ | |
1283 | if ((pin >= 16) && (pin <= 23)) { | |
1284 | if (pirq_entries[pin-16] != -1) { | |
1285 | if (!pirq_entries[pin-16]) { | |
1286 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1287 | "disabling PIRQ%d\n", pin-16); | |
1288 | } else { | |
1289 | irq = pirq_entries[pin-16]; | |
1290 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1291 | "using PIRQ%d -> IRQ %d\n", | |
1292 | pin-16, irq); | |
1293 | } | |
1294 | } | |
1295 | } | |
54168ed7 IM |
1296 | #endif |
1297 | ||
1da177e4 LT |
1298 | return irq; |
1299 | } | |
1300 | ||
497c9a19 YL |
1301 | void lock_vector_lock(void) |
1302 | { | |
1303 | /* Used to the online set of cpus does not change | |
1304 | * during assign_irq_vector. | |
1305 | */ | |
1306 | spin_lock(&vector_lock); | |
1307 | } | |
1da177e4 | 1308 | |
497c9a19 | 1309 | void unlock_vector_lock(void) |
1da177e4 | 1310 | { |
497c9a19 YL |
1311 | spin_unlock(&vector_lock); |
1312 | } | |
1da177e4 | 1313 | |
e7986739 MT |
1314 | static int |
1315 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1316 | { |
047c8fdb YL |
1317 | /* |
1318 | * NOTE! The local APIC isn't very good at handling | |
1319 | * multiple interrupts at the same interrupt level. | |
1320 | * As the interrupt level is determined by taking the | |
1321 | * vector number and shifting that right by 4, we | |
1322 | * want to spread these out a bit so that they don't | |
1323 | * all fall in the same interrupt level. | |
1324 | * | |
1325 | * Also, we've got to be careful not to trash gate | |
1326 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1327 | */ | |
54168ed7 IM |
1328 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1329 | unsigned int old_vector; | |
22f65d31 MT |
1330 | int cpu, err; |
1331 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1332 | |
54168ed7 IM |
1333 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1334 | return -EBUSY; | |
0a1ad60d | 1335 | |
22f65d31 MT |
1336 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1337 | return -ENOMEM; | |
ace80ab7 | 1338 | |
54168ed7 IM |
1339 | old_vector = cfg->vector; |
1340 | if (old_vector) { | |
22f65d31 MT |
1341 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1342 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1343 | if (!cpumask_empty(tmp_mask)) { | |
1344 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1345 | return 0; |
22f65d31 | 1346 | } |
54168ed7 | 1347 | } |
497c9a19 | 1348 | |
e7986739 | 1349 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1350 | err = -ENOSPC; |
1351 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1352 | int new_cpu; |
1353 | int vector, offset; | |
497c9a19 | 1354 | |
e2d40b18 | 1355 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1356 | |
54168ed7 IM |
1357 | vector = current_vector; |
1358 | offset = current_offset; | |
497c9a19 | 1359 | next: |
54168ed7 IM |
1360 | vector += 8; |
1361 | if (vector >= first_system_vector) { | |
e7986739 | 1362 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1363 | offset = (offset + 1) % 8; |
1364 | vector = FIRST_DEVICE_VECTOR + offset; | |
1365 | } | |
1366 | if (unlikely(current_vector == vector)) | |
1367 | continue; | |
b77b881f YL |
1368 | |
1369 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1370 | goto next; |
b77b881f | 1371 | |
22f65d31 | 1372 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1373 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1374 | goto next; | |
1375 | /* Found one! */ | |
1376 | current_vector = vector; | |
1377 | current_offset = offset; | |
1378 | if (old_vector) { | |
1379 | cfg->move_in_progress = 1; | |
22f65d31 | 1380 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1381 | } |
22f65d31 | 1382 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1383 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1384 | cfg->vector = vector; | |
22f65d31 MT |
1385 | cpumask_copy(cfg->domain, tmp_mask); |
1386 | err = 0; | |
1387 | break; | |
54168ed7 | 1388 | } |
22f65d31 MT |
1389 | free_cpumask_var(tmp_mask); |
1390 | return err; | |
497c9a19 YL |
1391 | } |
1392 | ||
e7986739 MT |
1393 | static int |
1394 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1395 | { |
1396 | int err; | |
ace80ab7 | 1397 | unsigned long flags; |
ace80ab7 EB |
1398 | |
1399 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1400 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1401 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1402 | return err; |
1403 | } | |
1404 | ||
3145e941 | 1405 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1406 | { |
497c9a19 YL |
1407 | int cpu, vector; |
1408 | ||
497c9a19 YL |
1409 | BUG_ON(!cfg->vector); |
1410 | ||
1411 | vector = cfg->vector; | |
22f65d31 | 1412 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1413 | per_cpu(vector_irq, cpu)[vector] = -1; |
1414 | ||
1415 | cfg->vector = 0; | |
22f65d31 | 1416 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1417 | |
1418 | if (likely(!cfg->move_in_progress)) | |
1419 | return; | |
22f65d31 | 1420 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1421 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1422 | vector++) { | |
1423 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1424 | continue; | |
1425 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1426 | break; | |
1427 | } | |
1428 | } | |
1429 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1430 | } |
1431 | ||
1432 | void __setup_vector_irq(int cpu) | |
1433 | { | |
1434 | /* Initialize vector_irq on a new cpu */ | |
1435 | /* This function must be called with vector_lock held */ | |
1436 | int irq, vector; | |
1437 | struct irq_cfg *cfg; | |
0b8f1efa | 1438 | struct irq_desc *desc; |
497c9a19 YL |
1439 | |
1440 | /* Mark the inuse vectors */ | |
0b8f1efa | 1441 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1442 | cfg = desc->chip_data; |
22f65d31 | 1443 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1444 | continue; |
1445 | vector = cfg->vector; | |
497c9a19 YL |
1446 | per_cpu(vector_irq, cpu)[vector] = irq; |
1447 | } | |
1448 | /* Mark the free vectors */ | |
1449 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1450 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1451 | if (irq < 0) | |
1452 | continue; | |
1453 | ||
1454 | cfg = irq_cfg(irq); | |
22f65d31 | 1455 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1456 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1457 | } |
1da177e4 | 1458 | } |
3fde6900 | 1459 | |
f5b9ed7a | 1460 | static struct irq_chip ioapic_chip; |
54168ed7 | 1461 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1462 | |
54168ed7 IM |
1463 | #define IOAPIC_AUTO -1 |
1464 | #define IOAPIC_EDGE 0 | |
1465 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1466 | |
047c8fdb | 1467 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1468 | static inline int IO_APIC_irq_trigger(int irq) |
1469 | { | |
d6c88a50 | 1470 | int apic, idx, pin; |
1d025192 | 1471 | |
d6c88a50 TG |
1472 | for (apic = 0; apic < nr_ioapics; apic++) { |
1473 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1474 | idx = find_irq_entry(apic, pin, mp_INT); | |
1475 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1476 | return irq_trigger(idx); | |
1477 | } | |
1478 | } | |
1479 | /* | |
54168ed7 IM |
1480 | * nonexistent IRQs are edge default |
1481 | */ | |
d6c88a50 | 1482 | return 0; |
1d025192 | 1483 | } |
047c8fdb YL |
1484 | #else |
1485 | static inline int IO_APIC_irq_trigger(int irq) | |
1486 | { | |
54168ed7 | 1487 | return 1; |
047c8fdb YL |
1488 | } |
1489 | #endif | |
1d025192 | 1490 | |
3145e941 | 1491 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1492 | { |
199751d7 | 1493 | |
6ebcc00e | 1494 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1495 | trigger == IOAPIC_LEVEL) |
08678b08 | 1496 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1497 | else |
1498 | desc->status &= ~IRQ_LEVEL; | |
1499 | ||
54168ed7 IM |
1500 | if (irq_remapped(irq)) { |
1501 | desc->status |= IRQ_MOVE_PCNTXT; | |
1502 | if (trigger) | |
1503 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1504 | handle_fasteoi_irq, | |
1505 | "fasteoi"); | |
1506 | else | |
1507 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1508 | handle_edge_irq, "edge"); | |
1509 | return; | |
1510 | } | |
29b61be6 | 1511 | |
047c8fdb YL |
1512 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1513 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1514 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1515 | handle_fasteoi_irq, |
1516 | "fasteoi"); | |
047c8fdb | 1517 | else |
a460e745 | 1518 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1519 | handle_edge_irq, "edge"); |
1da177e4 LT |
1520 | } |
1521 | ||
ca97ab90 JF |
1522 | int setup_ioapic_entry(int apic_id, int irq, |
1523 | struct IO_APIC_route_entry *entry, | |
1524 | unsigned int destination, int trigger, | |
0280f7c4 | 1525 | int polarity, int vector, int pin) |
1da177e4 | 1526 | { |
497c9a19 YL |
1527 | /* |
1528 | * add it to the IO-APIC irq-routing table: | |
1529 | */ | |
1530 | memset(entry,0,sizeof(*entry)); | |
1531 | ||
54168ed7 | 1532 | if (intr_remapping_enabled) { |
c8d46cf0 | 1533 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1534 | struct irte irte; |
1535 | struct IR_IO_APIC_route_entry *ir_entry = | |
1536 | (struct IR_IO_APIC_route_entry *) entry; | |
1537 | int index; | |
1538 | ||
1539 | if (!iommu) | |
c8d46cf0 | 1540 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1541 | |
1542 | index = alloc_irte(iommu, irq, 1); | |
1543 | if (index < 0) | |
c8d46cf0 | 1544 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1545 | |
1546 | memset(&irte, 0, sizeof(irte)); | |
1547 | ||
1548 | irte.present = 1; | |
9b5bc8dc | 1549 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1550 | /* |
1551 | * Trigger mode in the IRTE will always be edge, and the | |
1552 | * actual level or edge trigger will be setup in the IO-APIC | |
1553 | * RTE. This will help simplify level triggered irq migration. | |
1554 | * For more details, see the comments above explainig IO-APIC | |
1555 | * irq migration in the presence of interrupt-remapping. | |
1556 | */ | |
1557 | irte.trigger_mode = 0; | |
9b5bc8dc | 1558 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1559 | irte.vector = vector; |
1560 | irte.dest_id = IRTE_DEST(destination); | |
1561 | ||
1562 | modify_irte(irq, &irte); | |
1563 | ||
1564 | ir_entry->index2 = (index >> 15) & 0x1; | |
1565 | ir_entry->zero = 0; | |
1566 | ir_entry->format = 1; | |
1567 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1568 | /* |
1569 | * IO-APIC RTE will be configured with virtual vector. | |
1570 | * irq handler will do the explicit EOI to the io-apic. | |
1571 | */ | |
1572 | ir_entry->vector = pin; | |
29b61be6 | 1573 | } else { |
9b5bc8dc IM |
1574 | entry->delivery_mode = apic->irq_delivery_mode; |
1575 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1576 | entry->dest = destination; |
0280f7c4 | 1577 | entry->vector = vector; |
54168ed7 | 1578 | } |
497c9a19 | 1579 | |
54168ed7 | 1580 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1581 | entry->trigger = trigger; |
1582 | entry->polarity = polarity; | |
497c9a19 YL |
1583 | |
1584 | /* Mask level triggered irqs. | |
1585 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1586 | */ | |
1587 | if (trigger) | |
1588 | entry->mask = 1; | |
497c9a19 YL |
1589 | return 0; |
1590 | } | |
1591 | ||
c8d46cf0 | 1592 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1593 | int trigger, int polarity) |
497c9a19 YL |
1594 | { |
1595 | struct irq_cfg *cfg; | |
1da177e4 | 1596 | struct IO_APIC_route_entry entry; |
22f65d31 | 1597 | unsigned int dest; |
497c9a19 YL |
1598 | |
1599 | if (!IO_APIC_IRQ(irq)) | |
1600 | return; | |
1601 | ||
3145e941 | 1602 | cfg = desc->chip_data; |
497c9a19 | 1603 | |
fe402e1f | 1604 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1605 | return; |
1606 | ||
debccb3e | 1607 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1608 | |
1609 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1610 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1611 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1612 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1613 | irq, trigger, polarity); |
1614 | ||
1615 | ||
c8d46cf0 | 1616 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1617 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1618 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1619 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1620 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1621 | return; |
1622 | } | |
1623 | ||
3145e941 | 1624 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1625 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1626 | disable_8259A_irq(irq); |
1627 | ||
c8d46cf0 | 1628 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1629 | } |
1630 | ||
1631 | static void __init setup_IO_APIC_irqs(void) | |
1632 | { | |
c8d46cf0 | 1633 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1634 | int notcon = 0; |
0b8f1efa | 1635 | struct irq_desc *desc; |
3145e941 | 1636 | struct irq_cfg *cfg; |
0b8f1efa | 1637 | int cpu = boot_cpu_id; |
1da177e4 LT |
1638 | |
1639 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1640 | ||
c8d46cf0 IM |
1641 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1642 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1643 | |
c8d46cf0 | 1644 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1645 | if (idx == -1) { |
2a554fb1 | 1646 | if (!notcon) { |
3c2cbd24 | 1647 | notcon = 1; |
2a554fb1 CG |
1648 | apic_printk(APIC_VERBOSE, |
1649 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1650 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1651 | } else |
1652 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1653 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1654 | continue; |
1655 | } | |
56ffa1a0 CG |
1656 | if (notcon) { |
1657 | apic_printk(APIC_VERBOSE, | |
1658 | " (apicid-pin) not connected\n"); | |
1659 | notcon = 0; | |
1660 | } | |
3c2cbd24 | 1661 | |
c8d46cf0 | 1662 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa IM |
1663 | |
1664 | /* | |
1665 | * Skip the timer IRQ if there's a quirk handler | |
1666 | * installed and if it returns 1: | |
1667 | */ | |
1668 | if (apic->multi_timer_check && | |
1669 | apic->multi_timer_check(apic_id, irq)) | |
3c2cbd24 | 1670 | continue; |
33a201fa | 1671 | |
0b8f1efa YL |
1672 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1673 | if (!desc) { | |
1674 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1675 | continue; | |
1676 | } | |
3145e941 | 1677 | cfg = desc->chip_data; |
c8d46cf0 | 1678 | add_pin_to_irq_cpu(cfg, cpu, apic_id, pin); |
36062448 | 1679 | |
c8d46cf0 | 1680 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1681 | irq_trigger(idx), irq_polarity(idx)); |
1682 | } | |
1da177e4 LT |
1683 | } |
1684 | ||
3c2cbd24 CG |
1685 | if (notcon) |
1686 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1687 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1688 | } |
1689 | ||
1690 | /* | |
f7633ce5 | 1691 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1692 | */ |
c8d46cf0 | 1693 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1694 | int vector) |
1da177e4 LT |
1695 | { |
1696 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1697 | |
54168ed7 IM |
1698 | if (intr_remapping_enabled) |
1699 | return; | |
54168ed7 | 1700 | |
36062448 | 1701 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1702 | |
1703 | /* | |
1704 | * We use logical delivery to get the timer IRQ | |
1705 | * to the first CPU. | |
1706 | */ | |
9b5bc8dc | 1707 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1708 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1709 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1710 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1711 | entry.polarity = 0; |
1712 | entry.trigger = 0; | |
1713 | entry.vector = vector; | |
1714 | ||
1715 | /* | |
1716 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1717 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1718 | */ |
54168ed7 | 1719 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1720 | |
1721 | /* | |
1722 | * Add it to the IO-APIC irq-routing table: | |
1723 | */ | |
c8d46cf0 | 1724 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1725 | } |
1726 | ||
32f71aff MR |
1727 | |
1728 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1729 | { |
1730 | int apic, i; | |
1731 | union IO_APIC_reg_00 reg_00; | |
1732 | union IO_APIC_reg_01 reg_01; | |
1733 | union IO_APIC_reg_02 reg_02; | |
1734 | union IO_APIC_reg_03 reg_03; | |
1735 | unsigned long flags; | |
0f978f45 | 1736 | struct irq_cfg *cfg; |
0b8f1efa | 1737 | struct irq_desc *desc; |
8f09cd20 | 1738 | unsigned int irq; |
1da177e4 LT |
1739 | |
1740 | if (apic_verbosity == APIC_QUIET) | |
1741 | return; | |
1742 | ||
36062448 | 1743 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1744 | for (i = 0; i < nr_ioapics; i++) |
1745 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1746 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1747 | |
1748 | /* | |
1749 | * We are a bit conservative about what we expect. We have to | |
1750 | * know about every hardware change ASAP. | |
1751 | */ | |
1752 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1753 | ||
1754 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1755 | ||
1756 | spin_lock_irqsave(&ioapic_lock, flags); | |
1757 | reg_00.raw = io_apic_read(apic, 0); | |
1758 | reg_01.raw = io_apic_read(apic, 1); | |
1759 | if (reg_01.bits.version >= 0x10) | |
1760 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1761 | if (reg_01.bits.version >= 0x20) |
1762 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1763 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1764 | ||
54168ed7 | 1765 | printk("\n"); |
b5ba7e6d | 1766 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1767 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1768 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1769 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1770 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1771 | |
54168ed7 | 1772 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1773 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1774 | |
1775 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1776 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1777 | |
1778 | /* | |
1779 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1780 | * but the value of reg_02 is read as the previous read register | |
1781 | * value, so ignore it if reg_02 == reg_01. | |
1782 | */ | |
1783 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1784 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1785 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1786 | } |
1787 | ||
1788 | /* | |
1789 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1790 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1791 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1792 | */ | |
1793 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1794 | reg_03.raw != reg_01.raw) { | |
1795 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1796 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1797 | } |
1798 | ||
1799 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1800 | ||
d83e94ac YL |
1801 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1802 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1803 | |
1804 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1805 | struct IO_APIC_route_entry entry; | |
1806 | ||
cf4c6a2f | 1807 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1808 | |
54168ed7 IM |
1809 | printk(KERN_DEBUG " %02x %03X ", |
1810 | i, | |
1811 | entry.dest | |
1812 | ); | |
1da177e4 LT |
1813 | |
1814 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1815 | entry.mask, | |
1816 | entry.trigger, | |
1817 | entry.irr, | |
1818 | entry.polarity, | |
1819 | entry.delivery_status, | |
1820 | entry.dest_mode, | |
1821 | entry.delivery_mode, | |
1822 | entry.vector | |
1823 | ); | |
1824 | } | |
1825 | } | |
1da177e4 | 1826 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1827 | for_each_irq_desc(irq, desc) { |
1828 | struct irq_pin_list *entry; | |
1829 | ||
0b8f1efa YL |
1830 | cfg = desc->chip_data; |
1831 | entry = cfg->irq_2_pin; | |
0f978f45 | 1832 | if (!entry) |
1da177e4 | 1833 | continue; |
8f09cd20 | 1834 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1835 | for (;;) { |
1836 | printk("-> %d:%d", entry->apic, entry->pin); | |
1837 | if (!entry->next) | |
1838 | break; | |
0f978f45 | 1839 | entry = entry->next; |
1da177e4 LT |
1840 | } |
1841 | printk("\n"); | |
1842 | } | |
1843 | ||
1844 | printk(KERN_INFO ".................................... done.\n"); | |
1845 | ||
1846 | return; | |
1847 | } | |
1848 | ||
32f71aff | 1849 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1850 | { |
1851 | unsigned int v; | |
1852 | int i, j; | |
1853 | ||
1854 | if (apic_verbosity == APIC_QUIET) | |
1855 | return; | |
1856 | ||
1857 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1858 | for (i = 0; i < 8; i++) { | |
1859 | v = apic_read(base + i*0x10); | |
1860 | for (j = 0; j < 32; j++) { | |
1861 | if (v & (1<<j)) | |
1862 | printk("1"); | |
1863 | else | |
1864 | printk("0"); | |
1865 | } | |
1866 | printk("\n"); | |
1867 | } | |
1868 | } | |
1869 | ||
32f71aff | 1870 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1871 | { |
1872 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1873 | u64 icr; |
1da177e4 LT |
1874 | |
1875 | if (apic_verbosity == APIC_QUIET) | |
1876 | return; | |
1877 | ||
1878 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1879 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1880 | v = apic_read(APIC_ID); |
54168ed7 | 1881 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1882 | v = apic_read(APIC_LVR); |
1883 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1884 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1885 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1886 | |
1887 | v = apic_read(APIC_TASKPRI); | |
1888 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1889 | ||
54168ed7 | 1890 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1891 | if (!APIC_XAPIC(ver)) { |
1892 | v = apic_read(APIC_ARBPRI); | |
1893 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1894 | v & APIC_ARBPRI_MASK); | |
1895 | } | |
1da177e4 LT |
1896 | v = apic_read(APIC_PROCPRI); |
1897 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1898 | } | |
1899 | ||
a11b5abe YL |
1900 | /* |
1901 | * Remote read supported only in the 82489DX and local APIC for | |
1902 | * Pentium processors. | |
1903 | */ | |
1904 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1905 | v = apic_read(APIC_RRR); | |
1906 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1907 | } | |
1908 | ||
1da177e4 LT |
1909 | v = apic_read(APIC_LDR); |
1910 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1911 | if (!x2apic_enabled()) { |
1912 | v = apic_read(APIC_DFR); | |
1913 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1914 | } | |
1da177e4 LT |
1915 | v = apic_read(APIC_SPIV); |
1916 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1917 | ||
1918 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1919 | print_APIC_bitfield(APIC_ISR); | |
1920 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1921 | print_APIC_bitfield(APIC_TMR); | |
1922 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1923 | print_APIC_bitfield(APIC_IRR); | |
1924 | ||
54168ed7 IM |
1925 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1926 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1927 | apic_write(APIC_ESR, 0); |
54168ed7 | 1928 | |
1da177e4 LT |
1929 | v = apic_read(APIC_ESR); |
1930 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1931 | } | |
1932 | ||
7ab6af7a | 1933 | icr = apic_icr_read(); |
0c425cec IM |
1934 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1935 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1936 | |
1937 | v = apic_read(APIC_LVTT); | |
1938 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1939 | ||
1940 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1941 | v = apic_read(APIC_LVTPC); | |
1942 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1943 | } | |
1944 | v = apic_read(APIC_LVT0); | |
1945 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1946 | v = apic_read(APIC_LVT1); | |
1947 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1948 | ||
1949 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1950 | v = apic_read(APIC_LVTERR); | |
1951 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1952 | } | |
1953 | ||
1954 | v = apic_read(APIC_TMICT); | |
1955 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1956 | v = apic_read(APIC_TMCCT); | |
1957 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1958 | v = apic_read(APIC_TDCR); | |
1959 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1960 | printk("\n"); | |
1961 | } | |
1962 | ||
32f71aff | 1963 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1964 | { |
ffd5aae7 YL |
1965 | int cpu; |
1966 | ||
1967 | preempt_disable(); | |
1968 | for_each_online_cpu(cpu) | |
1969 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1970 | preempt_enable(); | |
1da177e4 LT |
1971 | } |
1972 | ||
32f71aff | 1973 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1974 | { |
1da177e4 LT |
1975 | unsigned int v; |
1976 | unsigned long flags; | |
1977 | ||
1978 | if (apic_verbosity == APIC_QUIET) | |
1979 | return; | |
1980 | ||
1981 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1982 | ||
1983 | spin_lock_irqsave(&i8259A_lock, flags); | |
1984 | ||
1985 | v = inb(0xa1) << 8 | inb(0x21); | |
1986 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1987 | ||
1988 | v = inb(0xa0) << 8 | inb(0x20); | |
1989 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1990 | ||
54168ed7 IM |
1991 | outb(0x0b,0xa0); |
1992 | outb(0x0b,0x20); | |
1da177e4 | 1993 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1994 | outb(0x0a,0xa0); |
1995 | outb(0x0a,0x20); | |
1da177e4 LT |
1996 | |
1997 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1998 | ||
1999 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
2000 | ||
2001 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
2002 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
2003 | } | |
2004 | ||
32f71aff MR |
2005 | __apicdebuginit(int) print_all_ICs(void) |
2006 | { | |
2007 | print_PIC(); | |
2008 | print_all_local_APICs(); | |
2009 | print_IO_APIC(); | |
2010 | ||
2011 | return 0; | |
2012 | } | |
2013 | ||
2014 | fs_initcall(print_all_ICs); | |
2015 | ||
1da177e4 | 2016 | |
efa2559f YL |
2017 | /* Where if anywhere is the i8259 connect in external int mode */ |
2018 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
2019 | ||
54168ed7 | 2020 | void __init enable_IO_APIC(void) |
1da177e4 LT |
2021 | { |
2022 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 2023 | int i8259_apic, i8259_pin; |
54168ed7 | 2024 | int apic; |
1da177e4 LT |
2025 | unsigned long flags; |
2026 | ||
1da177e4 LT |
2027 | /* |
2028 | * The number of IO-APIC IRQ registers (== #pins): | |
2029 | */ | |
fcfd636a | 2030 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 2031 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 2032 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 2033 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
2034 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
2035 | } | |
54168ed7 | 2036 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2037 | int pin; |
2038 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2039 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2040 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2041 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2042 | |
fcfd636a EB |
2043 | /* If the interrupt line is enabled and in ExtInt mode |
2044 | * I have found the pin where the i8259 is connected. | |
2045 | */ | |
2046 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2047 | ioapic_i8259.apic = apic; | |
2048 | ioapic_i8259.pin = pin; | |
2049 | goto found_i8259; | |
2050 | } | |
2051 | } | |
2052 | } | |
2053 | found_i8259: | |
2054 | /* Look to see what if the MP table has reported the ExtINT */ | |
2055 | /* If we could not find the appropriate pin by looking at the ioapic | |
2056 | * the i8259 probably is not connected the ioapic but give the | |
2057 | * mptable a chance anyway. | |
2058 | */ | |
2059 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2060 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2061 | /* Trust the MP table if nothing is setup in the hardware */ | |
2062 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2063 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2064 | ioapic_i8259.pin = i8259_pin; | |
2065 | ioapic_i8259.apic = i8259_apic; | |
2066 | } | |
2067 | /* Complain if the MP table and the hardware disagree */ | |
2068 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2069 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2070 | { | |
2071 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2072 | } |
2073 | ||
2074 | /* | |
2075 | * Do not trust the IO-APIC being empty at bootup | |
2076 | */ | |
2077 | clear_IO_APIC(); | |
2078 | } | |
2079 | ||
2080 | /* | |
2081 | * Not an __init, needed by the reboot code | |
2082 | */ | |
2083 | void disable_IO_APIC(void) | |
2084 | { | |
2085 | /* | |
2086 | * Clear the IO-APIC before rebooting: | |
2087 | */ | |
2088 | clear_IO_APIC(); | |
2089 | ||
650927ef | 2090 | /* |
0b968d23 | 2091 | * If the i8259 is routed through an IOAPIC |
650927ef | 2092 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2093 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2094 | * |
2095 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2096 | * as virtual wire B is little complex (need to configure both | |
2097 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2098 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2099 | */ |
7c6d9f97 | 2100 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2101 | struct IO_APIC_route_entry entry; |
650927ef EB |
2102 | |
2103 | memset(&entry, 0, sizeof(entry)); | |
2104 | entry.mask = 0; /* Enabled */ | |
2105 | entry.trigger = 0; /* Edge */ | |
2106 | entry.irr = 0; | |
2107 | entry.polarity = 0; /* High */ | |
2108 | entry.delivery_status = 0; | |
2109 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2110 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2111 | entry.vector = 0; |
54168ed7 | 2112 | entry.dest = read_apic_id(); |
650927ef EB |
2113 | |
2114 | /* | |
2115 | * Add it to the IO-APIC irq-routing table: | |
2116 | */ | |
cf4c6a2f | 2117 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2118 | } |
54168ed7 | 2119 | |
7c6d9f97 SS |
2120 | /* |
2121 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2122 | */ | |
2123 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
2124 | } |
2125 | ||
54168ed7 | 2126 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2127 | /* |
2128 | * function to set the IO-APIC physical IDs based on the | |
2129 | * values stored in the MPC table. | |
2130 | * | |
2131 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2132 | */ | |
2133 | ||
1da177e4 LT |
2134 | static void __init setup_ioapic_ids_from_mpc(void) |
2135 | { | |
2136 | union IO_APIC_reg_00 reg_00; | |
2137 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2138 | int apic_id; |
1da177e4 LT |
2139 | int i; |
2140 | unsigned char old_id; | |
2141 | unsigned long flags; | |
2142 | ||
a4dbc34d | 2143 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2144 | return; |
d49c4288 | 2145 | |
ca05fea6 NP |
2146 | /* |
2147 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2148 | * no meaning without the serial APIC bus. | |
2149 | */ | |
7c5c1e42 SL |
2150 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2151 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2152 | return; |
1da177e4 LT |
2153 | /* |
2154 | * This is broken; anything with a real cpu count has to | |
2155 | * circumvent this idiocy regardless. | |
2156 | */ | |
d190cb87 | 2157 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2158 | |
2159 | /* | |
2160 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2161 | */ | |
c8d46cf0 | 2162 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2163 | |
2164 | /* Read the register 0 value */ | |
2165 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2166 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2167 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2168 | |
c8d46cf0 | 2169 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2170 | |
c8d46cf0 | 2171 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2172 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2173 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2174 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2175 | reg_00.bits.ID); | |
c8d46cf0 | 2176 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2177 | } |
2178 | ||
1da177e4 LT |
2179 | /* |
2180 | * Sanity check, is the ID really free? Every APIC in a | |
2181 | * system must have a unique ID or we get lots of nice | |
2182 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2183 | */ | |
d1d7cae8 | 2184 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2185 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2186 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2187 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2188 | for (i = 0; i < get_physical_broadcast(); i++) |
2189 | if (!physid_isset(i, phys_id_present_map)) | |
2190 | break; | |
2191 | if (i >= get_physical_broadcast()) | |
2192 | panic("Max APIC ID exceeded!\n"); | |
2193 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2194 | i); | |
2195 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2196 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2197 | } else { |
2198 | physid_mask_t tmp; | |
8058714a | 2199 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2200 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2201 | "phys_id_present_map\n", | |
c8d46cf0 | 2202 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2203 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2204 | } | |
2205 | ||
2206 | ||
2207 | /* | |
2208 | * We need to adjust the IRQ routing table | |
2209 | * if the ID changed. | |
2210 | */ | |
c8d46cf0 | 2211 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2212 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2213 | if (mp_irqs[i].dstapic == old_id) |
2214 | mp_irqs[i].dstapic | |
c8d46cf0 | 2215 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2216 | |
2217 | /* | |
2218 | * Read the right value from the MPC table and | |
2219 | * write it into the ID register. | |
36062448 | 2220 | */ |
1da177e4 LT |
2221 | apic_printk(APIC_VERBOSE, KERN_INFO |
2222 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2223 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2224 | |
c8d46cf0 | 2225 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2226 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2227 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2228 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2229 | |
2230 | /* | |
2231 | * Sanity check | |
2232 | */ | |
2233 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2234 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2235 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2236 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2237 | printk("could not set ID!\n"); |
2238 | else | |
2239 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2240 | } | |
2241 | } | |
54168ed7 | 2242 | #endif |
1da177e4 | 2243 | |
7ce0bcfd | 2244 | int no_timer_check __initdata; |
8542b200 ZA |
2245 | |
2246 | static int __init notimercheck(char *s) | |
2247 | { | |
2248 | no_timer_check = 1; | |
2249 | return 1; | |
2250 | } | |
2251 | __setup("no_timer_check", notimercheck); | |
2252 | ||
1da177e4 LT |
2253 | /* |
2254 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2255 | * about the timer IRQ. We do the following to work around the situation: | |
2256 | * | |
2257 | * - timer IRQ defaults to IO-APIC IRQ | |
2258 | * - if this function detects that timer IRQs are defunct, then we fall | |
2259 | * back to ISA timer IRQs | |
2260 | */ | |
f0a7a5c9 | 2261 | static int __init timer_irq_works(void) |
1da177e4 LT |
2262 | { |
2263 | unsigned long t1 = jiffies; | |
4aae0702 | 2264 | unsigned long flags; |
1da177e4 | 2265 | |
8542b200 ZA |
2266 | if (no_timer_check) |
2267 | return 1; | |
2268 | ||
4aae0702 | 2269 | local_save_flags(flags); |
1da177e4 LT |
2270 | local_irq_enable(); |
2271 | /* Let ten ticks pass... */ | |
2272 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2273 | local_irq_restore(flags); |
1da177e4 LT |
2274 | |
2275 | /* | |
2276 | * Expect a few ticks at least, to be sure some possible | |
2277 | * glue logic does not lock up after one or two first | |
2278 | * ticks in a non-ExtINT mode. Also the local APIC | |
2279 | * might have cached one ExtINT interrupt. Finally, at | |
2280 | * least one tick may be lost due to delays. | |
2281 | */ | |
54168ed7 IM |
2282 | |
2283 | /* jiffies wrap? */ | |
1d16b53e | 2284 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2285 | return 1; |
1da177e4 LT |
2286 | return 0; |
2287 | } | |
2288 | ||
2289 | /* | |
2290 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2291 | * number of pending IRQ events unhandled. These cases are very rare, | |
2292 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2293 | * better to do it this way as thus we do not have to be aware of | |
2294 | * 'pending' interrupts in the IRQ path, except at this point. | |
2295 | */ | |
2296 | /* | |
2297 | * Edge triggered needs to resend any interrupt | |
2298 | * that was delayed but this is now handled in the device | |
2299 | * independent code. | |
2300 | */ | |
2301 | ||
2302 | /* | |
2303 | * Starting up a edge-triggered IO-APIC interrupt is | |
2304 | * nasty - we need to make sure that we get the edge. | |
2305 | * If it is already asserted for some reason, we need | |
2306 | * return 1 to indicate that is was pending. | |
2307 | * | |
2308 | * This is not complete - we should be able to fake | |
2309 | * an edge even if it isn't on the 8259A... | |
2310 | */ | |
54168ed7 | 2311 | |
f5b9ed7a | 2312 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2313 | { |
2314 | int was_pending = 0; | |
2315 | unsigned long flags; | |
0b8f1efa | 2316 | struct irq_cfg *cfg; |
1da177e4 LT |
2317 | |
2318 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2319 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2320 | disable_8259A_irq(irq); |
2321 | if (i8259A_irq_pending(irq)) | |
2322 | was_pending = 1; | |
2323 | } | |
0b8f1efa | 2324 | cfg = irq_cfg(irq); |
3145e941 | 2325 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2326 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2327 | ||
2328 | return was_pending; | |
2329 | } | |
2330 | ||
54168ed7 | 2331 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2332 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2333 | { |
54168ed7 IM |
2334 | |
2335 | struct irq_cfg *cfg = irq_cfg(irq); | |
2336 | unsigned long flags; | |
2337 | ||
2338 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2339 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2340 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2341 | |
2342 | return 1; | |
2343 | } | |
54168ed7 IM |
2344 | #else |
2345 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2346 | { |
dac5f412 | 2347 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2348 | |
d6c88a50 | 2349 | return 1; |
54168ed7 IM |
2350 | } |
2351 | #endif | |
497c9a19 | 2352 | |
54168ed7 IM |
2353 | /* |
2354 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2355 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2356 | * handled with the level-triggered descriptor, but that one has slightly | |
2357 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2358 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2359 | * races. | |
2360 | */ | |
497c9a19 | 2361 | |
54168ed7 | 2362 | #ifdef CONFIG_SMP |
497c9a19 | 2363 | |
54168ed7 | 2364 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2365 | |
54168ed7 IM |
2366 | /* |
2367 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2368 | * | |
0280f7c4 SS |
2369 | * For both level and edge triggered, irq migration is a simple atomic |
2370 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2371 | * |
0280f7c4 SS |
2372 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2373 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2374 | * Real vector that is used for interrupting cpu will be coming from | |
2375 | * the interrupt-remapping table entry. | |
54168ed7 | 2376 | */ |
e7986739 MT |
2377 | static void |
2378 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2379 | { |
54168ed7 | 2380 | struct irq_cfg *cfg; |
54168ed7 | 2381 | struct irte irte; |
54168ed7 | 2382 | unsigned int dest; |
3145e941 | 2383 | unsigned int irq; |
497c9a19 | 2384 | |
22f65d31 | 2385 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2386 | return; |
2387 | ||
3145e941 | 2388 | irq = desc->irq; |
54168ed7 IM |
2389 | if (get_irte(irq, &irte)) |
2390 | return; | |
497c9a19 | 2391 | |
3145e941 YL |
2392 | cfg = desc->chip_data; |
2393 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2394 | return; |
2395 | ||
3145e941 YL |
2396 | set_extra_move_desc(desc, mask); |
2397 | ||
debccb3e | 2398 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2399 | |
54168ed7 IM |
2400 | irte.vector = cfg->vector; |
2401 | irte.dest_id = IRTE_DEST(dest); | |
2402 | ||
2403 | /* | |
2404 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2405 | */ | |
2406 | modify_irte(irq, &irte); | |
2407 | ||
22f65d31 MT |
2408 | if (cfg->move_in_progress) |
2409 | send_cleanup_vector(cfg); | |
54168ed7 | 2410 | |
7f7ace0c | 2411 | cpumask_copy(desc->affinity, mask); |
54168ed7 IM |
2412 | } |
2413 | ||
54168ed7 IM |
2414 | /* |
2415 | * Migrates the IRQ destination in the process context. | |
2416 | */ | |
968ea6d8 RR |
2417 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2418 | const struct cpumask *mask) | |
54168ed7 | 2419 | { |
3145e941 YL |
2420 | migrate_ioapic_irq_desc(desc, mask); |
2421 | } | |
968ea6d8 RR |
2422 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2423 | const struct cpumask *mask) | |
3145e941 YL |
2424 | { |
2425 | struct irq_desc *desc = irq_to_desc(irq); | |
2426 | ||
2427 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 | 2428 | } |
29b61be6 SS |
2429 | #else |
2430 | static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, | |
2431 | const struct cpumask *mask) | |
2432 | { | |
2433 | } | |
54168ed7 IM |
2434 | #endif |
2435 | ||
2436 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2437 | { | |
2438 | unsigned vector, me; | |
8f2466f4 | 2439 | |
54168ed7 | 2440 | ack_APIC_irq(); |
54168ed7 | 2441 | exit_idle(); |
54168ed7 IM |
2442 | irq_enter(); |
2443 | ||
2444 | me = smp_processor_id(); | |
2445 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2446 | unsigned int irq; | |
68a8ca59 | 2447 | unsigned int irr; |
54168ed7 IM |
2448 | struct irq_desc *desc; |
2449 | struct irq_cfg *cfg; | |
2450 | irq = __get_cpu_var(vector_irq)[vector]; | |
2451 | ||
0b8f1efa YL |
2452 | if (irq == -1) |
2453 | continue; | |
2454 | ||
54168ed7 IM |
2455 | desc = irq_to_desc(irq); |
2456 | if (!desc) | |
2457 | continue; | |
2458 | ||
2459 | cfg = irq_cfg(irq); | |
2460 | spin_lock(&desc->lock); | |
2461 | if (!cfg->move_cleanup_count) | |
2462 | goto unlock; | |
2463 | ||
22f65d31 | 2464 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2465 | goto unlock; |
2466 | ||
68a8ca59 SS |
2467 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2468 | /* | |
2469 | * Check if the vector that needs to be cleanedup is | |
2470 | * registered at the cpu's IRR. If so, then this is not | |
2471 | * the best time to clean it up. Lets clean it up in the | |
2472 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2473 | * to myself. | |
2474 | */ | |
2475 | if (irr & (1 << (vector % 32))) { | |
2476 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2477 | goto unlock; | |
2478 | } | |
54168ed7 IM |
2479 | __get_cpu_var(vector_irq)[vector] = -1; |
2480 | cfg->move_cleanup_count--; | |
2481 | unlock: | |
2482 | spin_unlock(&desc->lock); | |
2483 | } | |
2484 | ||
2485 | irq_exit(); | |
2486 | } | |
2487 | ||
3145e941 | 2488 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2489 | { |
3145e941 YL |
2490 | struct irq_desc *desc = *descp; |
2491 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2492 | unsigned vector, me; |
2493 | ||
48a1b10a YL |
2494 | if (likely(!cfg->move_in_progress)) { |
2495 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2496 | if (likely(!cfg->move_desc_pending)) | |
2497 | return; | |
2498 | ||
b9098957 | 2499 | /* domain has not changed, but affinity did */ |
48a1b10a | 2500 | me = smp_processor_id(); |
7f7ace0c | 2501 | if (cpumask_test_cpu(me, desc->affinity)) { |
48a1b10a YL |
2502 | *descp = desc = move_irq_desc(desc, me); |
2503 | /* get the new one */ | |
2504 | cfg = desc->chip_data; | |
2505 | cfg->move_desc_pending = 0; | |
2506 | } | |
2507 | #endif | |
54168ed7 | 2508 | return; |
48a1b10a | 2509 | } |
54168ed7 IM |
2510 | |
2511 | vector = ~get_irq_regs()->orig_ax; | |
2512 | me = smp_processor_id(); | |
10b888d6 YL |
2513 | |
2514 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) { | |
48a1b10a YL |
2515 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2516 | *descp = desc = move_irq_desc(desc, me); | |
2517 | /* get the new one */ | |
2518 | cfg = desc->chip_data; | |
2519 | #endif | |
22f65d31 | 2520 | send_cleanup_vector(cfg); |
10b888d6 | 2521 | } |
497c9a19 YL |
2522 | } |
2523 | #else | |
3145e941 | 2524 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2525 | #endif |
3145e941 | 2526 | |
d0b03bd1 | 2527 | #ifdef CONFIG_X86_X2APIC |
0280f7c4 SS |
2528 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2529 | { | |
2530 | int apic, pin; | |
2531 | struct irq_pin_list *entry; | |
2532 | ||
2533 | entry = cfg->irq_2_pin; | |
2534 | for (;;) { | |
2535 | ||
2536 | if (!entry) | |
2537 | break; | |
2538 | ||
2539 | apic = entry->apic; | |
2540 | pin = entry->pin; | |
2541 | io_apic_eoi(apic, pin); | |
2542 | entry = entry->next; | |
2543 | } | |
2544 | } | |
2545 | ||
2546 | static void | |
2547 | eoi_ioapic_irq(struct irq_desc *desc) | |
2548 | { | |
2549 | struct irq_cfg *cfg; | |
2550 | unsigned long flags; | |
2551 | unsigned int irq; | |
2552 | ||
2553 | irq = desc->irq; | |
2554 | cfg = desc->chip_data; | |
2555 | ||
2556 | spin_lock_irqsave(&ioapic_lock, flags); | |
2557 | __eoi_ioapic_irq(irq, cfg); | |
2558 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2559 | } | |
2560 | ||
54168ed7 IM |
2561 | static void ack_x2apic_level(unsigned int irq) |
2562 | { | |
0280f7c4 | 2563 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 | 2564 | ack_x2APIC_irq(); |
0280f7c4 | 2565 | eoi_ioapic_irq(desc); |
54168ed7 IM |
2566 | } |
2567 | ||
2568 | static void ack_x2apic_edge(unsigned int irq) | |
2569 | { | |
2570 | ack_x2APIC_irq(); | |
2571 | } | |
2572 | #endif | |
497c9a19 | 2573 | |
1d025192 YL |
2574 | static void ack_apic_edge(unsigned int irq) |
2575 | { | |
3145e941 YL |
2576 | struct irq_desc *desc = irq_to_desc(irq); |
2577 | ||
2578 | irq_complete_move(&desc); | |
1d025192 YL |
2579 | move_native_irq(irq); |
2580 | ack_APIC_irq(); | |
2581 | } | |
2582 | ||
3eb2cce8 | 2583 | atomic_t irq_mis_count; |
3eb2cce8 | 2584 | |
047c8fdb YL |
2585 | static void ack_apic_level(unsigned int irq) |
2586 | { | |
3145e941 YL |
2587 | struct irq_desc *desc = irq_to_desc(irq); |
2588 | ||
3eb2cce8 YL |
2589 | #ifdef CONFIG_X86_32 |
2590 | unsigned long v; | |
2591 | int i; | |
2592 | #endif | |
3145e941 | 2593 | struct irq_cfg *cfg; |
54168ed7 | 2594 | int do_unmask_irq = 0; |
047c8fdb | 2595 | |
3145e941 | 2596 | irq_complete_move(&desc); |
047c8fdb | 2597 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2598 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2599 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2600 | do_unmask_irq = 1; |
3145e941 | 2601 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2602 | } |
047c8fdb YL |
2603 | #endif |
2604 | ||
3eb2cce8 YL |
2605 | #ifdef CONFIG_X86_32 |
2606 | /* | |
2607 | * It appears there is an erratum which affects at least version 0x11 | |
2608 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2609 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2610 | * erroneously delivered as edge-triggered one but the respective IRR | |
2611 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2612 | * message but it will never arrive and further interrupts are blocked | |
2613 | * from the source. The exact reason is so far unknown, but the | |
2614 | * phenomenon was observed when two consecutive interrupt requests | |
2615 | * from a given source get delivered to the same CPU and the source is | |
2616 | * temporarily disabled in between. | |
2617 | * | |
2618 | * A workaround is to simulate an EOI message manually. We achieve it | |
2619 | * by setting the trigger mode to edge and then to level when the edge | |
2620 | * trigger mode gets detected in the TMR of a local APIC for a | |
2621 | * level-triggered interrupt. We mask the source for the time of the | |
2622 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2623 | * The idea is from Manfred Spraul. --macro | |
2624 | */ | |
3145e941 YL |
2625 | cfg = desc->chip_data; |
2626 | i = cfg->vector; | |
3eb2cce8 YL |
2627 | |
2628 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2629 | #endif | |
2630 | ||
54168ed7 IM |
2631 | /* |
2632 | * We must acknowledge the irq before we move it or the acknowledge will | |
2633 | * not propagate properly. | |
2634 | */ | |
2635 | ack_APIC_irq(); | |
2636 | ||
2637 | /* Now we can move and renable the irq */ | |
2638 | if (unlikely(do_unmask_irq)) { | |
2639 | /* Only migrate the irq if the ack has been received. | |
2640 | * | |
2641 | * On rare occasions the broadcast level triggered ack gets | |
2642 | * delayed going to ioapics, and if we reprogram the | |
2643 | * vector while Remote IRR is still set the irq will never | |
2644 | * fire again. | |
2645 | * | |
2646 | * To prevent this scenario we read the Remote IRR bit | |
2647 | * of the ioapic. This has two effects. | |
2648 | * - On any sane system the read of the ioapic will | |
2649 | * flush writes (and acks) going to the ioapic from | |
2650 | * this cpu. | |
2651 | * - We get to see if the ACK has actually been delivered. | |
2652 | * | |
2653 | * Based on failed experiments of reprogramming the | |
2654 | * ioapic entry from outside of irq context starting | |
2655 | * with masking the ioapic entry and then polling until | |
2656 | * Remote IRR was clear before reprogramming the | |
2657 | * ioapic I don't trust the Remote IRR bit to be | |
2658 | * completey accurate. | |
2659 | * | |
2660 | * However there appears to be no other way to plug | |
2661 | * this race, so if the Remote IRR bit is not | |
2662 | * accurate and is causing problems then it is a hardware bug | |
2663 | * and you can go talk to the chipset vendor about it. | |
2664 | */ | |
3145e941 YL |
2665 | cfg = desc->chip_data; |
2666 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2667 | move_masked_irq(irq); |
3145e941 | 2668 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2669 | } |
1d025192 | 2670 | |
3eb2cce8 | 2671 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2672 | if (!(v & (1 << (i & 0x1f)))) { |
2673 | atomic_inc(&irq_mis_count); | |
2674 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2675 | __mask_and_edge_IO_APIC_irq(cfg); |
2676 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2677 | spin_unlock(&ioapic_lock); |
2678 | } | |
047c8fdb | 2679 | #endif |
3eb2cce8 | 2680 | } |
1d025192 | 2681 | |
d0b03bd1 HW |
2682 | #ifdef CONFIG_INTR_REMAP |
2683 | static void ir_ack_apic_edge(unsigned int irq) | |
2684 | { | |
2685 | #ifdef CONFIG_X86_X2APIC | |
2686 | if (x2apic_enabled()) | |
2687 | return ack_x2apic_edge(irq); | |
2688 | #endif | |
2689 | return ack_apic_edge(irq); | |
2690 | } | |
2691 | ||
2692 | static void ir_ack_apic_level(unsigned int irq) | |
2693 | { | |
2694 | #ifdef CONFIG_X86_X2APIC | |
2695 | if (x2apic_enabled()) | |
2696 | return ack_x2apic_level(irq); | |
2697 | #endif | |
2698 | return ack_apic_level(irq); | |
2699 | } | |
2700 | #endif /* CONFIG_INTR_REMAP */ | |
2701 | ||
f5b9ed7a | 2702 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2703 | .name = "IO-APIC", |
2704 | .startup = startup_ioapic_irq, | |
2705 | .mask = mask_IO_APIC_irq, | |
2706 | .unmask = unmask_IO_APIC_irq, | |
2707 | .ack = ack_apic_edge, | |
2708 | .eoi = ack_apic_level, | |
54d5d424 | 2709 | #ifdef CONFIG_SMP |
d6c88a50 | 2710 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2711 | #endif |
ace80ab7 | 2712 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2713 | }; |
2714 | ||
54168ed7 | 2715 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2716 | .name = "IR-IO-APIC", |
2717 | .startup = startup_ioapic_irq, | |
2718 | .mask = mask_IO_APIC_irq, | |
2719 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2720 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2721 | .ack = ir_ack_apic_edge, |
2722 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2723 | #ifdef CONFIG_SMP |
d6c88a50 | 2724 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2725 | #endif |
54168ed7 IM |
2726 | #endif |
2727 | .retrigger = ioapic_retrigger_irq, | |
2728 | }; | |
1da177e4 LT |
2729 | |
2730 | static inline void init_IO_APIC_traps(void) | |
2731 | { | |
2732 | int irq; | |
08678b08 | 2733 | struct irq_desc *desc; |
da51a821 | 2734 | struct irq_cfg *cfg; |
1da177e4 LT |
2735 | |
2736 | /* | |
2737 | * NOTE! The local APIC isn't very good at handling | |
2738 | * multiple interrupts at the same interrupt level. | |
2739 | * As the interrupt level is determined by taking the | |
2740 | * vector number and shifting that right by 4, we | |
2741 | * want to spread these out a bit so that they don't | |
2742 | * all fall in the same interrupt level. | |
2743 | * | |
2744 | * Also, we've got to be careful not to trash gate | |
2745 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2746 | */ | |
0b8f1efa | 2747 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2748 | cfg = desc->chip_data; |
2749 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2750 | /* |
2751 | * Hmm.. We don't have an entry for this, | |
2752 | * so default to an old-fashioned 8259 | |
2753 | * interrupt if we can.. | |
2754 | */ | |
99d093d1 | 2755 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2756 | make_8259A_irq(irq); |
0b8f1efa | 2757 | else |
1da177e4 | 2758 | /* Strange. Oh, well.. */ |
08678b08 | 2759 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2760 | } |
2761 | } | |
2762 | } | |
2763 | ||
f5b9ed7a IM |
2764 | /* |
2765 | * The local APIC irq-chip implementation: | |
2766 | */ | |
1da177e4 | 2767 | |
36062448 | 2768 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2769 | { |
2770 | unsigned long v; | |
2771 | ||
2772 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2773 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2774 | } |
2775 | ||
36062448 | 2776 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2777 | { |
f5b9ed7a | 2778 | unsigned long v; |
1da177e4 | 2779 | |
f5b9ed7a | 2780 | v = apic_read(APIC_LVT0); |
593f4a78 | 2781 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2782 | } |
1da177e4 | 2783 | |
3145e941 | 2784 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2785 | { |
2786 | ack_APIC_irq(); | |
2787 | } | |
2788 | ||
f5b9ed7a | 2789 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2790 | .name = "local-APIC", |
f5b9ed7a IM |
2791 | .mask = mask_lapic_irq, |
2792 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2793 | .ack = ack_lapic_irq, |
1da177e4 LT |
2794 | }; |
2795 | ||
3145e941 | 2796 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2797 | { |
08678b08 | 2798 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2799 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2800 | "edge"); | |
c88ac1df MR |
2801 | } |
2802 | ||
e9427101 | 2803 | static void __init setup_nmi(void) |
1da177e4 LT |
2804 | { |
2805 | /* | |
36062448 | 2806 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2807 | * We put the 8259A master into AEOI mode and |
2808 | * unmask on all local APICs LVT0 as NMI. | |
2809 | * | |
2810 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2811 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2812 | * the NMI handler or the timer interrupt. | |
36062448 | 2813 | */ |
1da177e4 LT |
2814 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2815 | ||
e9427101 | 2816 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2817 | |
2818 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2819 | } | |
2820 | ||
2821 | /* | |
2822 | * This looks a bit hackish but it's about the only one way of sending | |
2823 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2824 | * not support the ExtINT mode, unfortunately. We need to send these | |
2825 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2826 | * 8259A interrupt line asserted until INTA. --macro | |
2827 | */ | |
28acf285 | 2828 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2829 | { |
fcfd636a | 2830 | int apic, pin, i; |
1da177e4 LT |
2831 | struct IO_APIC_route_entry entry0, entry1; |
2832 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2833 | |
fcfd636a | 2834 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2835 | if (pin == -1) { |
2836 | WARN_ON_ONCE(1); | |
2837 | return; | |
2838 | } | |
fcfd636a | 2839 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2840 | if (apic == -1) { |
2841 | WARN_ON_ONCE(1); | |
1da177e4 | 2842 | return; |
956fb531 | 2843 | } |
1da177e4 | 2844 | |
cf4c6a2f | 2845 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2846 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2847 | |
2848 | memset(&entry1, 0, sizeof(entry1)); | |
2849 | ||
2850 | entry1.dest_mode = 0; /* physical delivery */ | |
2851 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2852 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2853 | entry1.delivery_mode = dest_ExtINT; |
2854 | entry1.polarity = entry0.polarity; | |
2855 | entry1.trigger = 0; | |
2856 | entry1.vector = 0; | |
2857 | ||
cf4c6a2f | 2858 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2859 | |
2860 | save_control = CMOS_READ(RTC_CONTROL); | |
2861 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2862 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2863 | RTC_FREQ_SELECT); | |
2864 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2865 | ||
2866 | i = 100; | |
2867 | while (i-- > 0) { | |
2868 | mdelay(10); | |
2869 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2870 | i -= 10; | |
2871 | } | |
2872 | ||
2873 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2874 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2875 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2876 | |
cf4c6a2f | 2877 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2878 | } |
2879 | ||
efa2559f | 2880 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2881 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2882 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2883 | { |
2884 | disable_timer_pin_1 = 1; | |
2885 | return 0; | |
2886 | } | |
54168ed7 | 2887 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2888 | |
2889 | int timer_through_8259 __initdata; | |
2890 | ||
1da177e4 LT |
2891 | /* |
2892 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2893 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2894 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2895 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2896 | * |
2897 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2898 | */ |
8542b200 | 2899 | static inline void __init check_timer(void) |
1da177e4 | 2900 | { |
3145e941 YL |
2901 | struct irq_desc *desc = irq_to_desc(0); |
2902 | struct irq_cfg *cfg = desc->chip_data; | |
2903 | int cpu = boot_cpu_id; | |
fcfd636a | 2904 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2905 | unsigned long flags; |
047c8fdb | 2906 | int no_pin1 = 0; |
4aae0702 IM |
2907 | |
2908 | local_irq_save(flags); | |
d4d25dec | 2909 | |
1da177e4 LT |
2910 | /* |
2911 | * get/set the timer IRQ vector: | |
2912 | */ | |
2913 | disable_8259A_irq(0); | |
fe402e1f | 2914 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2915 | |
2916 | /* | |
d11d5794 MR |
2917 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2918 | * wire has to be disabled in the local APIC. Also | |
2919 | * timer interrupts need to be acknowledged manually in | |
2920 | * the 8259A for the i82489DX when using the NMI | |
2921 | * watchdog as that APIC treats NMIs as level-triggered. | |
2922 | * The AEOI mode will finish them in the 8259A | |
2923 | * automatically. | |
1da177e4 | 2924 | */ |
593f4a78 | 2925 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2926 | init_8259A(1); |
54168ed7 | 2927 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2928 | { |
2929 | unsigned int ver; | |
2930 | ||
2931 | ver = apic_read(APIC_LVR); | |
2932 | ver = GET_APIC_VERSION(ver); | |
2933 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2934 | } | |
54168ed7 | 2935 | #endif |
1da177e4 | 2936 | |
fcfd636a EB |
2937 | pin1 = find_isa_irq_pin(0, mp_INT); |
2938 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2939 | pin2 = ioapic_i8259.pin; | |
2940 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2941 | |
49a66a0b MR |
2942 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2943 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2944 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2945 | |
691874fa MR |
2946 | /* |
2947 | * Some BIOS writers are clueless and report the ExtINTA | |
2948 | * I/O APIC input from the cascaded 8259A as the timer | |
2949 | * interrupt input. So just in case, if only one pin | |
2950 | * was found above, try it both directly and through the | |
2951 | * 8259A. | |
2952 | */ | |
2953 | if (pin1 == -1) { | |
54168ed7 IM |
2954 | if (intr_remapping_enabled) |
2955 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2956 | pin1 = pin2; |
2957 | apic1 = apic2; | |
2958 | no_pin1 = 1; | |
2959 | } else if (pin2 == -1) { | |
2960 | pin2 = pin1; | |
2961 | apic2 = apic1; | |
2962 | } | |
2963 | ||
1da177e4 LT |
2964 | if (pin1 != -1) { |
2965 | /* | |
2966 | * Ok, does IRQ0 through the IOAPIC work? | |
2967 | */ | |
691874fa | 2968 | if (no_pin1) { |
3145e941 | 2969 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2970 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2971 | } else { |
2972 | /* for edge trigger, setup_IO_APIC_irq already | |
2973 | * leave it unmasked. | |
2974 | * so only need to unmask if it is level-trigger | |
2975 | * do we really have level trigger timer? | |
2976 | */ | |
2977 | int idx; | |
2978 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2979 | if (idx != -1 && irq_trigger(idx)) | |
2980 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2981 | } |
1da177e4 LT |
2982 | if (timer_irq_works()) { |
2983 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2984 | setup_nmi(); |
2985 | enable_8259A_irq(0); | |
1da177e4 | 2986 | } |
66759a01 CE |
2987 | if (disable_timer_pin_1 > 0) |
2988 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2989 | goto out; |
1da177e4 | 2990 | } |
54168ed7 IM |
2991 | if (intr_remapping_enabled) |
2992 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2993 | local_irq_disable(); |
fcfd636a | 2994 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2995 | if (!no_pin1) |
49a66a0b MR |
2996 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2997 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2998 | |
49a66a0b MR |
2999 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3000 | "(IRQ0) through the 8259A ...\n"); | |
3001 | apic_printk(APIC_QUIET, KERN_INFO | |
3002 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3003 | /* |
3004 | * legacy devices should be connected to IO APIC #0 | |
3005 | */ | |
3145e941 | 3006 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 3007 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 3008 | enable_8259A_irq(0); |
1da177e4 | 3009 | if (timer_irq_works()) { |
49a66a0b | 3010 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3011 | timer_through_8259 = 1; |
1da177e4 | 3012 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 3013 | disable_8259A_irq(0); |
1da177e4 | 3014 | setup_nmi(); |
60134ebe | 3015 | enable_8259A_irq(0); |
1da177e4 | 3016 | } |
4aae0702 | 3017 | goto out; |
1da177e4 LT |
3018 | } |
3019 | /* | |
3020 | * Cleanup, just in case ... | |
3021 | */ | |
f72dccac | 3022 | local_irq_disable(); |
ecd29476 | 3023 | disable_8259A_irq(0); |
fcfd636a | 3024 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3025 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3026 | } |
1da177e4 LT |
3027 | |
3028 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3029 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3030 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3031 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3032 | } |
54168ed7 | 3033 | #ifdef CONFIG_X86_32 |
d11d5794 | 3034 | timer_ack = 0; |
54168ed7 | 3035 | #endif |
1da177e4 | 3036 | |
49a66a0b MR |
3037 | apic_printk(APIC_QUIET, KERN_INFO |
3038 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3039 | |
3145e941 | 3040 | lapic_register_intr(0, desc); |
497c9a19 | 3041 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3042 | enable_8259A_irq(0); |
3043 | ||
3044 | if (timer_irq_works()) { | |
49a66a0b | 3045 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3046 | goto out; |
1da177e4 | 3047 | } |
f72dccac | 3048 | local_irq_disable(); |
e67465f1 | 3049 | disable_8259A_irq(0); |
497c9a19 | 3050 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3051 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3052 | |
49a66a0b MR |
3053 | apic_printk(APIC_QUIET, KERN_INFO |
3054 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3055 | |
1da177e4 LT |
3056 | init_8259A(0); |
3057 | make_8259A_irq(0); | |
593f4a78 | 3058 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3059 | |
3060 | unlock_ExtINT_logic(); | |
3061 | ||
3062 | if (timer_irq_works()) { | |
49a66a0b | 3063 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3064 | goto out; |
1da177e4 | 3065 | } |
f72dccac | 3066 | local_irq_disable(); |
49a66a0b | 3067 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3068 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3069 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3070 | out: |
3071 | local_irq_restore(flags); | |
1da177e4 LT |
3072 | } |
3073 | ||
3074 | /* | |
af174783 MR |
3075 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3076 | * to devices. However there may be an I/O APIC pin available for | |
3077 | * this interrupt regardless. The pin may be left unconnected, but | |
3078 | * typically it will be reused as an ExtINT cascade interrupt for | |
3079 | * the master 8259A. In the MPS case such a pin will normally be | |
3080 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3081 | * there is no provision for ExtINT interrupts, and in the absence | |
3082 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3083 | * interrupt, that is edge-triggered and unmasked by default. We | |
3084 | * used to do this, but it caused problems on some systems because | |
3085 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3086 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3087 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3088 | * the I/O APIC in all cases now. No actual device should request | |
3089 | * it anyway. --macro | |
1da177e4 LT |
3090 | */ |
3091 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3092 | ||
3093 | void __init setup_IO_APIC(void) | |
3094 | { | |
54168ed7 | 3095 | |
54168ed7 IM |
3096 | /* |
3097 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3098 | */ | |
1da177e4 | 3099 | |
af174783 | 3100 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3101 | |
54168ed7 | 3102 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3103 | /* |
54168ed7 IM |
3104 | * Set up IO-APIC IRQ routing. |
3105 | */ | |
3106 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3107 | if (!acpi_ioapic) |
3108 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3109 | #endif |
1da177e4 LT |
3110 | sync_Arb_IDs(); |
3111 | setup_IO_APIC_irqs(); | |
3112 | init_IO_APIC_traps(); | |
1e4c85f9 | 3113 | check_timer(); |
1da177e4 LT |
3114 | } |
3115 | ||
3116 | /* | |
54168ed7 IM |
3117 | * Called after all the initialization is done. If we didnt find any |
3118 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3119 | */ |
36062448 | 3120 | |
1da177e4 LT |
3121 | static int __init io_apic_bug_finalize(void) |
3122 | { | |
d6c88a50 TG |
3123 | if (sis_apic_bug == -1) |
3124 | sis_apic_bug = 0; | |
3125 | return 0; | |
1da177e4 LT |
3126 | } |
3127 | ||
3128 | late_initcall(io_apic_bug_finalize); | |
3129 | ||
3130 | struct sysfs_ioapic_data { | |
3131 | struct sys_device dev; | |
3132 | struct IO_APIC_route_entry entry[0]; | |
3133 | }; | |
54168ed7 | 3134 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3135 | |
438510f6 | 3136 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3137 | { |
3138 | struct IO_APIC_route_entry *entry; | |
3139 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3140 | int i; |
36062448 | 3141 | |
1da177e4 LT |
3142 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3143 | entry = data->entry; | |
54168ed7 IM |
3144 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3145 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3146 | |
3147 | return 0; | |
3148 | } | |
3149 | ||
3150 | static int ioapic_resume(struct sys_device *dev) | |
3151 | { | |
3152 | struct IO_APIC_route_entry *entry; | |
3153 | struct sysfs_ioapic_data *data; | |
3154 | unsigned long flags; | |
3155 | union IO_APIC_reg_00 reg_00; | |
3156 | int i; | |
36062448 | 3157 | |
1da177e4 LT |
3158 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3159 | entry = data->entry; | |
3160 | ||
3161 | spin_lock_irqsave(&ioapic_lock, flags); | |
3162 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3163 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3164 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3165 | io_apic_write(dev->id, 0, reg_00.raw); |
3166 | } | |
1da177e4 | 3167 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3168 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3169 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3170 | |
3171 | return 0; | |
3172 | } | |
3173 | ||
3174 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3175 | .name = "ioapic", |
1da177e4 LT |
3176 | .suspend = ioapic_suspend, |
3177 | .resume = ioapic_resume, | |
3178 | }; | |
3179 | ||
3180 | static int __init ioapic_init_sysfs(void) | |
3181 | { | |
54168ed7 IM |
3182 | struct sys_device * dev; |
3183 | int i, size, error; | |
1da177e4 LT |
3184 | |
3185 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3186 | if (error) | |
3187 | return error; | |
3188 | ||
54168ed7 | 3189 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3190 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3191 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3192 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3193 | if (!mp_ioapic_data[i]) { |
3194 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3195 | continue; | |
3196 | } | |
1da177e4 | 3197 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3198 | dev->id = i; |
1da177e4 LT |
3199 | dev->cls = &ioapic_sysdev_class; |
3200 | error = sysdev_register(dev); | |
3201 | if (error) { | |
3202 | kfree(mp_ioapic_data[i]); | |
3203 | mp_ioapic_data[i] = NULL; | |
3204 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3205 | continue; | |
3206 | } | |
3207 | } | |
3208 | ||
3209 | return 0; | |
3210 | } | |
3211 | ||
3212 | device_initcall(ioapic_init_sysfs); | |
3213 | ||
abcaa2b8 | 3214 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3215 | /* |
95d77884 | 3216 | * Dynamic irq allocate and deallocation |
3fc471ed | 3217 | */ |
199751d7 | 3218 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3219 | { |
ace80ab7 | 3220 | /* Allocate an unused irq */ |
54168ed7 IM |
3221 | unsigned int irq; |
3222 | unsigned int new; | |
3fc471ed | 3223 | unsigned long flags; |
0b8f1efa YL |
3224 | struct irq_cfg *cfg_new = NULL; |
3225 | int cpu = boot_cpu_id; | |
3226 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3227 | |
3228 | irq = 0; | |
abcaa2b8 YL |
3229 | if (irq_want < nr_irqs_gsi) |
3230 | irq_want = nr_irqs_gsi; | |
3231 | ||
ace80ab7 | 3232 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3233 | for (new = irq_want; new < nr_irqs; new++) { |
0b8f1efa YL |
3234 | desc_new = irq_to_desc_alloc_cpu(new, cpu); |
3235 | if (!desc_new) { | |
3236 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3237 | continue; |
0b8f1efa YL |
3238 | } |
3239 | cfg_new = desc_new->chip_data; | |
3240 | ||
3241 | if (cfg_new->vector != 0) | |
ace80ab7 | 3242 | continue; |
fe402e1f | 3243 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3244 | irq = new; |
3245 | break; | |
3246 | } | |
3247 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3248 | |
199751d7 | 3249 | if (irq > 0) { |
3fc471ed | 3250 | dynamic_irq_init(irq); |
0b8f1efa YL |
3251 | /* restore it, in case dynamic_irq_init clear it */ |
3252 | if (desc_new) | |
3253 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3254 | } |
3255 | return irq; | |
3256 | } | |
3257 | ||
199751d7 YL |
3258 | int create_irq(void) |
3259 | { | |
be5d5350 | 3260 | unsigned int irq_want; |
54168ed7 IM |
3261 | int irq; |
3262 | ||
be5d5350 YL |
3263 | irq_want = nr_irqs_gsi; |
3264 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3265 | |
3266 | if (irq == 0) | |
3267 | irq = -1; | |
3268 | ||
3269 | return irq; | |
199751d7 YL |
3270 | } |
3271 | ||
3fc471ed EB |
3272 | void destroy_irq(unsigned int irq) |
3273 | { | |
3274 | unsigned long flags; | |
0b8f1efa YL |
3275 | struct irq_cfg *cfg; |
3276 | struct irq_desc *desc; | |
3fc471ed | 3277 | |
0b8f1efa YL |
3278 | /* store it, in case dynamic_irq_cleanup clear it */ |
3279 | desc = irq_to_desc(irq); | |
3280 | cfg = desc->chip_data; | |
3fc471ed | 3281 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3282 | /* connect back irq_cfg */ |
3283 | if (desc) | |
3284 | desc->chip_data = cfg; | |
3fc471ed | 3285 | |
54168ed7 | 3286 | free_irte(irq); |
3fc471ed | 3287 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3288 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3289 | spin_unlock_irqrestore(&vector_lock, flags); |
3290 | } | |
3fc471ed | 3291 | |
2d3fcc1c | 3292 | /* |
27b46d76 | 3293 | * MSI message composition |
2d3fcc1c EB |
3294 | */ |
3295 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3296 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3297 | { |
497c9a19 YL |
3298 | struct irq_cfg *cfg; |
3299 | int err; | |
2d3fcc1c EB |
3300 | unsigned dest; |
3301 | ||
f1182638 JB |
3302 | if (disable_apic) |
3303 | return -ENXIO; | |
3304 | ||
3145e941 | 3305 | cfg = irq_cfg(irq); |
fe402e1f | 3306 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3307 | if (err) |
3308 | return err; | |
2d3fcc1c | 3309 | |
debccb3e | 3310 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3311 | |
54168ed7 IM |
3312 | if (irq_remapped(irq)) { |
3313 | struct irte irte; | |
3314 | int ir_index; | |
3315 | u16 sub_handle; | |
3316 | ||
3317 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3318 | BUG_ON(ir_index == -1); | |
3319 | ||
3320 | memset (&irte, 0, sizeof(irte)); | |
3321 | ||
3322 | irte.present = 1; | |
9b5bc8dc | 3323 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3324 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3325 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3326 | irte.vector = cfg->vector; |
3327 | irte.dest_id = IRTE_DEST(dest); | |
3328 | ||
3329 | modify_irte(irq, &irte); | |
3330 | ||
3331 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3332 | msg->data = sub_handle; | |
3333 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3334 | MSI_ADDR_IR_SHV | | |
3335 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3336 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3337 | } else { |
9d783ba0 SS |
3338 | if (x2apic_enabled()) |
3339 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3340 | MSI_ADDR_EXT_DEST_ID(dest); | |
3341 | else | |
3342 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3343 | ||
54168ed7 IM |
3344 | msg->address_lo = |
3345 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3346 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3347 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3348 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3349 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3350 | MSI_ADDR_REDIRECTION_CPU: |
3351 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3352 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3353 | |
54168ed7 IM |
3354 | msg->data = |
3355 | MSI_DATA_TRIGGER_EDGE | | |
3356 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3357 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3358 | MSI_DATA_DELIVERY_FIXED: |
3359 | MSI_DATA_DELIVERY_LOWPRI) | | |
3360 | MSI_DATA_VECTOR(cfg->vector); | |
3361 | } | |
497c9a19 | 3362 | return err; |
2d3fcc1c EB |
3363 | } |
3364 | ||
3b7d1921 | 3365 | #ifdef CONFIG_SMP |
0de26520 | 3366 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3367 | { |
3145e941 | 3368 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3369 | struct irq_cfg *cfg; |
3b7d1921 EB |
3370 | struct msi_msg msg; |
3371 | unsigned int dest; | |
3b7d1921 | 3372 | |
22f65d31 MT |
3373 | dest = set_desc_affinity(desc, mask); |
3374 | if (dest == BAD_APICID) | |
497c9a19 | 3375 | return; |
2d3fcc1c | 3376 | |
3145e941 | 3377 | cfg = desc->chip_data; |
2d3fcc1c | 3378 | |
3145e941 | 3379 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3380 | |
3381 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3382 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3383 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3384 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3385 | ||
3145e941 | 3386 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3387 | } |
54168ed7 IM |
3388 | #ifdef CONFIG_INTR_REMAP |
3389 | /* | |
3390 | * Migrate the MSI irq to another cpumask. This migration is | |
3391 | * done in the process context using interrupt-remapping hardware. | |
3392 | */ | |
e7986739 MT |
3393 | static void |
3394 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3395 | { |
3145e941 | 3396 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3397 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3398 | unsigned int dest; |
54168ed7 | 3399 | struct irte irte; |
54168ed7 IM |
3400 | |
3401 | if (get_irte(irq, &irte)) | |
3402 | return; | |
3403 | ||
22f65d31 MT |
3404 | dest = set_desc_affinity(desc, mask); |
3405 | if (dest == BAD_APICID) | |
54168ed7 IM |
3406 | return; |
3407 | ||
54168ed7 IM |
3408 | irte.vector = cfg->vector; |
3409 | irte.dest_id = IRTE_DEST(dest); | |
3410 | ||
3411 | /* | |
3412 | * atomically update the IRTE with the new destination and vector. | |
3413 | */ | |
3414 | modify_irte(irq, &irte); | |
3415 | ||
3416 | /* | |
3417 | * After this point, all the interrupts will start arriving | |
3418 | * at the new destination. So, time to cleanup the previous | |
3419 | * vector allocation. | |
3420 | */ | |
22f65d31 MT |
3421 | if (cfg->move_in_progress) |
3422 | send_cleanup_vector(cfg); | |
54168ed7 | 3423 | } |
3145e941 | 3424 | |
54168ed7 | 3425 | #endif |
3b7d1921 | 3426 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3427 | |
3b7d1921 EB |
3428 | /* |
3429 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3430 | * which implement the MSI or MSI-X Capability Structure. | |
3431 | */ | |
3432 | static struct irq_chip msi_chip = { | |
3433 | .name = "PCI-MSI", | |
3434 | .unmask = unmask_msi_irq, | |
3435 | .mask = mask_msi_irq, | |
1d025192 | 3436 | .ack = ack_apic_edge, |
3b7d1921 EB |
3437 | #ifdef CONFIG_SMP |
3438 | .set_affinity = set_msi_irq_affinity, | |
3439 | #endif | |
3440 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3441 | }; |
3442 | ||
54168ed7 IM |
3443 | static struct irq_chip msi_ir_chip = { |
3444 | .name = "IR-PCI-MSI", | |
3445 | .unmask = unmask_msi_irq, | |
3446 | .mask = mask_msi_irq, | |
a1e38ca5 | 3447 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3448 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3449 | #ifdef CONFIG_SMP |
3450 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3451 | #endif |
54168ed7 IM |
3452 | #endif |
3453 | .retrigger = ioapic_retrigger_irq, | |
3454 | }; | |
3455 | ||
3456 | /* | |
3457 | * Map the PCI dev to the corresponding remapping hardware unit | |
3458 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3459 | * in it. | |
3460 | */ | |
3461 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3462 | { | |
3463 | struct intel_iommu *iommu; | |
3464 | int index; | |
3465 | ||
3466 | iommu = map_dev_to_ir(dev); | |
3467 | if (!iommu) { | |
3468 | printk(KERN_ERR | |
3469 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3470 | return -ENOENT; | |
3471 | } | |
3472 | ||
3473 | index = alloc_irte(iommu, irq, nvec); | |
3474 | if (index < 0) { | |
3475 | printk(KERN_ERR | |
3476 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3477 | pci_name(dev)); |
54168ed7 IM |
3478 | return -ENOSPC; |
3479 | } | |
3480 | return index; | |
3481 | } | |
1d025192 | 3482 | |
3145e941 | 3483 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3484 | { |
3485 | int ret; | |
3486 | struct msi_msg msg; | |
3487 | ||
3488 | ret = msi_compose_msg(dev, irq, &msg); | |
3489 | if (ret < 0) | |
3490 | return ret; | |
3491 | ||
3145e941 | 3492 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3493 | write_msi_msg(irq, &msg); |
3494 | ||
54168ed7 IM |
3495 | if (irq_remapped(irq)) { |
3496 | struct irq_desc *desc = irq_to_desc(irq); | |
3497 | /* | |
3498 | * irq migration in process context | |
3499 | */ | |
3500 | desc->status |= IRQ_MOVE_PCNTXT; | |
3501 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3502 | } else | |
54168ed7 | 3503 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3504 | |
c81bba49 YL |
3505 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3506 | ||
1d025192 YL |
3507 | return 0; |
3508 | } | |
3509 | ||
047c8fdb YL |
3510 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3511 | { | |
54168ed7 IM |
3512 | unsigned int irq; |
3513 | int ret, sub_handle; | |
0b8f1efa | 3514 | struct msi_desc *msidesc; |
54168ed7 | 3515 | unsigned int irq_want; |
1cc18521 | 3516 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3517 | int index = 0; |
54168ed7 | 3518 | |
1c8d7b0a MW |
3519 | /* x86 doesn't support multiple MSI yet */ |
3520 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3521 | return 1; | |
3522 | ||
be5d5350 | 3523 | irq_want = nr_irqs_gsi; |
54168ed7 | 3524 | sub_handle = 0; |
0b8f1efa YL |
3525 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3526 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3527 | if (irq == 0) |
3528 | return -1; | |
f1ee5548 | 3529 | irq_want = irq + 1; |
54168ed7 IM |
3530 | if (!intr_remapping_enabled) |
3531 | goto no_ir; | |
3532 | ||
3533 | if (!sub_handle) { | |
3534 | /* | |
3535 | * allocate the consecutive block of IRTE's | |
3536 | * for 'nvec' | |
3537 | */ | |
3538 | index = msi_alloc_irte(dev, irq, nvec); | |
3539 | if (index < 0) { | |
3540 | ret = index; | |
3541 | goto error; | |
3542 | } | |
3543 | } else { | |
3544 | iommu = map_dev_to_ir(dev); | |
3545 | if (!iommu) { | |
3546 | ret = -ENOENT; | |
3547 | goto error; | |
3548 | } | |
3549 | /* | |
3550 | * setup the mapping between the irq and the IRTE | |
3551 | * base index, the sub_handle pointing to the | |
3552 | * appropriate interrupt remap table entry. | |
3553 | */ | |
3554 | set_irte_irq(irq, iommu, index, sub_handle); | |
3555 | } | |
3556 | no_ir: | |
0b8f1efa | 3557 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3558 | if (ret < 0) |
3559 | goto error; | |
3560 | sub_handle++; | |
3561 | } | |
3562 | return 0; | |
047c8fdb YL |
3563 | |
3564 | error: | |
54168ed7 IM |
3565 | destroy_irq(irq); |
3566 | return ret; | |
047c8fdb YL |
3567 | } |
3568 | ||
3b7d1921 EB |
3569 | void arch_teardown_msi_irq(unsigned int irq) |
3570 | { | |
f7feaca7 | 3571 | destroy_irq(irq); |
3b7d1921 EB |
3572 | } |
3573 | ||
9d783ba0 | 3574 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3575 | #ifdef CONFIG_SMP |
22f65d31 | 3576 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3577 | { |
3145e941 | 3578 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3579 | struct irq_cfg *cfg; |
3580 | struct msi_msg msg; | |
3581 | unsigned int dest; | |
54168ed7 | 3582 | |
22f65d31 MT |
3583 | dest = set_desc_affinity(desc, mask); |
3584 | if (dest == BAD_APICID) | |
54168ed7 IM |
3585 | return; |
3586 | ||
3145e941 | 3587 | cfg = desc->chip_data; |
54168ed7 IM |
3588 | |
3589 | dmar_msi_read(irq, &msg); | |
3590 | ||
3591 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3592 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3593 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3594 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3595 | ||
3596 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3597 | } |
3145e941 | 3598 | |
54168ed7 IM |
3599 | #endif /* CONFIG_SMP */ |
3600 | ||
3601 | struct irq_chip dmar_msi_type = { | |
3602 | .name = "DMAR_MSI", | |
3603 | .unmask = dmar_msi_unmask, | |
3604 | .mask = dmar_msi_mask, | |
3605 | .ack = ack_apic_edge, | |
3606 | #ifdef CONFIG_SMP | |
3607 | .set_affinity = dmar_msi_set_affinity, | |
3608 | #endif | |
3609 | .retrigger = ioapic_retrigger_irq, | |
3610 | }; | |
3611 | ||
3612 | int arch_setup_dmar_msi(unsigned int irq) | |
3613 | { | |
3614 | int ret; | |
3615 | struct msi_msg msg; | |
2d3fcc1c | 3616 | |
54168ed7 IM |
3617 | ret = msi_compose_msg(NULL, irq, &msg); |
3618 | if (ret < 0) | |
3619 | return ret; | |
3620 | dmar_msi_write(irq, &msg); | |
3621 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3622 | "edge"); | |
3623 | return 0; | |
3624 | } | |
3625 | #endif | |
3626 | ||
58ac1e76 | 3627 | #ifdef CONFIG_HPET_TIMER |
3628 | ||
3629 | #ifdef CONFIG_SMP | |
22f65d31 | 3630 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3631 | { |
3145e941 | 3632 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3633 | struct irq_cfg *cfg; |
58ac1e76 | 3634 | struct msi_msg msg; |
3635 | unsigned int dest; | |
58ac1e76 | 3636 | |
22f65d31 MT |
3637 | dest = set_desc_affinity(desc, mask); |
3638 | if (dest == BAD_APICID) | |
58ac1e76 | 3639 | return; |
3640 | ||
3145e941 | 3641 | cfg = desc->chip_data; |
58ac1e76 | 3642 | |
3643 | hpet_msi_read(irq, &msg); | |
3644 | ||
3645 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3646 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3647 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3648 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3649 | ||
3650 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3651 | } |
3145e941 | 3652 | |
58ac1e76 | 3653 | #endif /* CONFIG_SMP */ |
3654 | ||
1cc18521 | 3655 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3656 | .name = "HPET_MSI", |
3657 | .unmask = hpet_msi_unmask, | |
3658 | .mask = hpet_msi_mask, | |
3659 | .ack = ack_apic_edge, | |
3660 | #ifdef CONFIG_SMP | |
3661 | .set_affinity = hpet_msi_set_affinity, | |
3662 | #endif | |
3663 | .retrigger = ioapic_retrigger_irq, | |
3664 | }; | |
3665 | ||
3666 | int arch_setup_hpet_msi(unsigned int irq) | |
3667 | { | |
3668 | int ret; | |
3669 | struct msi_msg msg; | |
3670 | ||
3671 | ret = msi_compose_msg(NULL, irq, &msg); | |
3672 | if (ret < 0) | |
3673 | return ret; | |
3674 | ||
3675 | hpet_msi_write(irq, &msg); | |
3676 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3677 | "edge"); | |
c81bba49 | 3678 | |
58ac1e76 | 3679 | return 0; |
3680 | } | |
3681 | #endif | |
3682 | ||
54168ed7 | 3683 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3684 | /* |
3685 | * Hypertransport interrupt support | |
3686 | */ | |
3687 | #ifdef CONFIG_HT_IRQ | |
3688 | ||
3689 | #ifdef CONFIG_SMP | |
3690 | ||
497c9a19 | 3691 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3692 | { |
ec68307c EB |
3693 | struct ht_irq_msg msg; |
3694 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3695 | |
497c9a19 | 3696 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3697 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3698 | |
497c9a19 | 3699 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3700 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3701 | |
ec68307c | 3702 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3703 | } |
3704 | ||
22f65d31 | 3705 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3706 | { |
3145e941 | 3707 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3708 | struct irq_cfg *cfg; |
8b955b0d | 3709 | unsigned int dest; |
8b955b0d | 3710 | |
22f65d31 MT |
3711 | dest = set_desc_affinity(desc, mask); |
3712 | if (dest == BAD_APICID) | |
497c9a19 | 3713 | return; |
8b955b0d | 3714 | |
3145e941 | 3715 | cfg = desc->chip_data; |
8b955b0d | 3716 | |
497c9a19 | 3717 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3718 | } |
3145e941 | 3719 | |
8b955b0d EB |
3720 | #endif |
3721 | ||
c37e108d | 3722 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3723 | .name = "PCI-HT", |
3724 | .mask = mask_ht_irq, | |
3725 | .unmask = unmask_ht_irq, | |
1d025192 | 3726 | .ack = ack_apic_edge, |
8b955b0d EB |
3727 | #ifdef CONFIG_SMP |
3728 | .set_affinity = set_ht_irq_affinity, | |
3729 | #endif | |
3730 | .retrigger = ioapic_retrigger_irq, | |
3731 | }; | |
3732 | ||
3733 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3734 | { | |
497c9a19 YL |
3735 | struct irq_cfg *cfg; |
3736 | int err; | |
8b955b0d | 3737 | |
f1182638 JB |
3738 | if (disable_apic) |
3739 | return -ENXIO; | |
3740 | ||
3145e941 | 3741 | cfg = irq_cfg(irq); |
fe402e1f | 3742 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3743 | if (!err) { |
ec68307c | 3744 | struct ht_irq_msg msg; |
8b955b0d | 3745 | unsigned dest; |
8b955b0d | 3746 | |
debccb3e IM |
3747 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3748 | apic->target_cpus()); | |
8b955b0d | 3749 | |
ec68307c | 3750 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3751 | |
ec68307c EB |
3752 | msg.address_lo = |
3753 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3754 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3755 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3756 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3757 | HT_IRQ_LOW_DM_PHYSICAL : |
3758 | HT_IRQ_LOW_DM_LOGICAL) | | |
3759 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3760 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3761 | HT_IRQ_LOW_MT_FIXED : |
3762 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3763 | HT_IRQ_LOW_IRQ_MASKED; | |
3764 | ||
ec68307c | 3765 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3766 | |
a460e745 IM |
3767 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3768 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3769 | |
3770 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3771 | } |
497c9a19 | 3772 | return err; |
8b955b0d EB |
3773 | } |
3774 | #endif /* CONFIG_HT_IRQ */ | |
3775 | ||
03b48632 | 3776 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3777 | /* |
3778 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3779 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3780 | */ | |
3781 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3782 | unsigned long mmr_offset) | |
3783 | { | |
22f65d31 | 3784 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3785 | struct irq_cfg *cfg; |
3786 | int mmr_pnode; | |
3787 | unsigned long mmr_value; | |
3788 | struct uv_IO_APIC_route_entry *entry; | |
3789 | unsigned long flags; | |
3790 | int err; | |
3791 | ||
3145e941 YL |
3792 | cfg = irq_cfg(irq); |
3793 | ||
e7986739 | 3794 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3795 | if (err != 0) |
3796 | return err; | |
3797 | ||
3798 | spin_lock_irqsave(&vector_lock, flags); | |
3799 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3800 | irq_name); | |
3801 | spin_unlock_irqrestore(&vector_lock, flags); | |
3802 | ||
4173a0e7 DN |
3803 | mmr_value = 0; |
3804 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3805 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3806 | ||
3807 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3808 | entry->delivery_mode = apic->irq_delivery_mode; |
3809 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3810 | entry->polarity = 0; |
3811 | entry->trigger = 0; | |
3812 | entry->mask = 0; | |
debccb3e | 3813 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3814 | |
3815 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3816 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3817 | ||
3818 | return irq; | |
3819 | } | |
3820 | ||
3821 | /* | |
3822 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3823 | * longer allowed to be sent. | |
3824 | */ | |
3825 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3826 | { | |
3827 | unsigned long mmr_value; | |
3828 | struct uv_IO_APIC_route_entry *entry; | |
3829 | int mmr_pnode; | |
3830 | ||
3831 | mmr_value = 0; | |
3832 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3833 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3834 | ||
3835 | entry->mask = 1; | |
3836 | ||
3837 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3838 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3839 | } | |
3840 | #endif /* CONFIG_X86_64 */ | |
3841 | ||
9d6a4d08 YL |
3842 | int __init io_apic_get_redir_entries (int ioapic) |
3843 | { | |
3844 | union IO_APIC_reg_01 reg_01; | |
3845 | unsigned long flags; | |
3846 | ||
3847 | spin_lock_irqsave(&ioapic_lock, flags); | |
3848 | reg_01.raw = io_apic_read(ioapic, 1); | |
3849 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3850 | ||
3851 | return reg_01.bits.entries; | |
3852 | } | |
3853 | ||
be5d5350 | 3854 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3855 | { |
be5d5350 YL |
3856 | int nr = 0; |
3857 | ||
cc6c5006 YL |
3858 | nr = acpi_probe_gsi(); |
3859 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3860 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3861 | } else { |
3862 | /* for acpi=off or acpi is not compiled in */ | |
3863 | int idx; | |
3864 | ||
3865 | nr = 0; | |
3866 | for (idx = 0; idx < nr_ioapics; idx++) | |
3867 | nr += io_apic_get_redir_entries(idx) + 1; | |
3868 | ||
3869 | if (nr > nr_irqs_gsi) | |
3870 | nr_irqs_gsi = nr; | |
3871 | } | |
3872 | ||
3873 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3874 | } |
3875 | ||
4a046d17 YL |
3876 | #ifdef CONFIG_SPARSE_IRQ |
3877 | int __init arch_probe_nr_irqs(void) | |
3878 | { | |
3879 | int nr; | |
3880 | ||
f1ee5548 YL |
3881 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3882 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3883 | |
f1ee5548 YL |
3884 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3885 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3886 | /* | |
3887 | * for MSI and HT dyn irq | |
3888 | */ | |
3889 | nr += nr_irqs_gsi * 16; | |
3890 | #endif | |
3891 | if (nr < nr_irqs) | |
4a046d17 YL |
3892 | nr_irqs = nr; |
3893 | ||
3894 | return 0; | |
3895 | } | |
3896 | #endif | |
3897 | ||
1da177e4 | 3898 | /* -------------------------------------------------------------------------- |
54168ed7 | 3899 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3900 | -------------------------------------------------------------------------- */ |
3901 | ||
888ba6c6 | 3902 | #ifdef CONFIG_ACPI |
1da177e4 | 3903 | |
54168ed7 | 3904 | #ifdef CONFIG_X86_32 |
36062448 | 3905 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3906 | { |
3907 | union IO_APIC_reg_00 reg_00; | |
3908 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3909 | physid_mask_t tmp; | |
3910 | unsigned long flags; | |
3911 | int i = 0; | |
3912 | ||
3913 | /* | |
36062448 PC |
3914 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3915 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3916 | * supports up to 16 on one shared APIC bus. |
36062448 | 3917 | * |
1da177e4 LT |
3918 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3919 | * advantage of new APIC bus architecture. | |
3920 | */ | |
3921 | ||
3922 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3923 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3924 | |
3925 | spin_lock_irqsave(&ioapic_lock, flags); | |
3926 | reg_00.raw = io_apic_read(ioapic, 0); | |
3927 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3928 | ||
3929 | if (apic_id >= get_physical_broadcast()) { | |
3930 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3931 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3932 | apic_id = reg_00.bits.ID; | |
3933 | } | |
3934 | ||
3935 | /* | |
36062448 | 3936 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3937 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3938 | */ | |
d1d7cae8 | 3939 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3940 | |
3941 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3942 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3943 | break; |
3944 | } | |
3945 | ||
3946 | if (i == get_physical_broadcast()) | |
3947 | panic("Max apic_id exceeded!\n"); | |
3948 | ||
3949 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3950 | "trying %d\n", ioapic, apic_id, i); | |
3951 | ||
3952 | apic_id = i; | |
36062448 | 3953 | } |
1da177e4 | 3954 | |
8058714a | 3955 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3956 | physids_or(apic_id_map, apic_id_map, tmp); |
3957 | ||
3958 | if (reg_00.bits.ID != apic_id) { | |
3959 | reg_00.bits.ID = apic_id; | |
3960 | ||
3961 | spin_lock_irqsave(&ioapic_lock, flags); | |
3962 | io_apic_write(ioapic, 0, reg_00.raw); | |
3963 | reg_00.raw = io_apic_read(ioapic, 0); | |
3964 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3965 | ||
3966 | /* Sanity check */ | |
6070f9ec AD |
3967 | if (reg_00.bits.ID != apic_id) { |
3968 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3969 | return -1; | |
3970 | } | |
1da177e4 LT |
3971 | } |
3972 | ||
3973 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3974 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3975 | ||
3976 | return apic_id; | |
3977 | } | |
3978 | ||
36062448 | 3979 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3980 | { |
3981 | union IO_APIC_reg_01 reg_01; | |
3982 | unsigned long flags; | |
3983 | ||
3984 | spin_lock_irqsave(&ioapic_lock, flags); | |
3985 | reg_01.raw = io_apic_read(ioapic, 1); | |
3986 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3987 | ||
3988 | return reg_01.bits.version; | |
3989 | } | |
54168ed7 | 3990 | #endif |
1da177e4 | 3991 | |
54168ed7 | 3992 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3993 | { |
0b8f1efa YL |
3994 | struct irq_desc *desc; |
3995 | struct irq_cfg *cfg; | |
3996 | int cpu = boot_cpu_id; | |
3997 | ||
1da177e4 | 3998 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3999 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
4000 | ioapic); |
4001 | return -EINVAL; | |
4002 | } | |
4003 | ||
0b8f1efa YL |
4004 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
4005 | if (!desc) { | |
4006 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
4007 | return 0; | |
4008 | } | |
4009 | ||
1da177e4 LT |
4010 | /* |
4011 | * IRQs < 16 are already in the irq_2_pin[] map | |
4012 | */ | |
99d093d1 | 4013 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 4014 | cfg = desc->chip_data; |
3145e941 | 4015 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 4016 | } |
1da177e4 | 4017 | |
3145e941 | 4018 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
4019 | |
4020 | return 0; | |
4021 | } | |
4022 | ||
54168ed7 | 4023 | |
61fd47e0 SL |
4024 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4025 | { | |
4026 | int i; | |
4027 | ||
4028 | if (skip_ioapic_setup) | |
4029 | return -1; | |
4030 | ||
4031 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4032 | if (mp_irqs[i].irqtype == mp_INT && |
4033 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4034 | break; |
4035 | if (i >= mp_irq_entries) | |
4036 | return -1; | |
4037 | ||
4038 | *trigger = irq_trigger(i); | |
4039 | *polarity = irq_polarity(i); | |
4040 | return 0; | |
4041 | } | |
4042 | ||
888ba6c6 | 4043 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4044 | |
497c9a19 YL |
4045 | /* |
4046 | * This function currently is only a helper for the i386 smp boot process where | |
4047 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4048 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4049 | */ |
4050 | #ifdef CONFIG_SMP | |
4051 | void __init setup_ioapic_dest(void) | |
4052 | { | |
4053 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4054 | struct irq_desc *desc; |
497c9a19 | 4055 | struct irq_cfg *cfg; |
22f65d31 | 4056 | const struct cpumask *mask; |
497c9a19 YL |
4057 | |
4058 | if (skip_ioapic_setup == 1) | |
4059 | return; | |
4060 | ||
4061 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4062 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4063 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4064 | if (irq_entry == -1) | |
4065 | continue; | |
4066 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4067 | ||
4068 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4069 | * when you have too many devices, because at that time only boot | |
4070 | * cpu is online. | |
4071 | */ | |
0b8f1efa YL |
4072 | desc = irq_to_desc(irq); |
4073 | cfg = desc->chip_data; | |
6c2e9403 | 4074 | if (!cfg->vector) { |
3145e941 | 4075 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4076 | irq_trigger(irq_entry), |
4077 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4078 | continue; |
4079 | ||
4080 | } | |
4081 | ||
4082 | /* | |
4083 | * Honour affinities which have been set in early boot | |
4084 | */ | |
6c2e9403 TG |
4085 | if (desc->status & |
4086 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4087 | mask = desc->affinity; |
6c2e9403 | 4088 | else |
fe402e1f | 4089 | mask = apic->target_cpus(); |
6c2e9403 | 4090 | |
6c2e9403 | 4091 | if (intr_remapping_enabled) |
3145e941 | 4092 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4093 | else |
3145e941 | 4094 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4095 | } |
4096 | ||
4097 | } | |
4098 | } | |
4099 | #endif | |
4100 | ||
54168ed7 IM |
4101 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4102 | ||
4103 | static struct resource *ioapic_resources; | |
4104 | ||
4105 | static struct resource * __init ioapic_setup_resources(void) | |
4106 | { | |
4107 | unsigned long n; | |
4108 | struct resource *res; | |
4109 | char *mem; | |
4110 | int i; | |
4111 | ||
4112 | if (nr_ioapics <= 0) | |
4113 | return NULL; | |
4114 | ||
4115 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4116 | n *= nr_ioapics; | |
4117 | ||
4118 | mem = alloc_bootmem(n); | |
4119 | res = (void *)mem; | |
4120 | ||
4121 | if (mem != NULL) { | |
4122 | mem += sizeof(struct resource) * nr_ioapics; | |
4123 | ||
4124 | for (i = 0; i < nr_ioapics; i++) { | |
4125 | res[i].name = mem; | |
4126 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4127 | sprintf(mem, "IOAPIC %u", i); | |
4128 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4129 | } | |
4130 | } | |
4131 | ||
4132 | ioapic_resources = res; | |
4133 | ||
4134 | return res; | |
4135 | } | |
54168ed7 | 4136 | |
f3294a33 YL |
4137 | void __init ioapic_init_mappings(void) |
4138 | { | |
4139 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4140 | struct resource *ioapic_res; |
d6c88a50 | 4141 | int i; |
f3294a33 | 4142 | |
54168ed7 | 4143 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4144 | for (i = 0; i < nr_ioapics; i++) { |
4145 | if (smp_found_config) { | |
b5ba7e6d | 4146 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4147 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4148 | if (!ioapic_phys) { |
4149 | printk(KERN_ERR | |
4150 | "WARNING: bogus zero IO-APIC " | |
4151 | "address found in MPTABLE, " | |
4152 | "disabling IO/APIC support!\n"); | |
4153 | smp_found_config = 0; | |
4154 | skip_ioapic_setup = 1; | |
4155 | goto fake_ioapic_page; | |
4156 | } | |
54168ed7 | 4157 | #endif |
f3294a33 | 4158 | } else { |
54168ed7 | 4159 | #ifdef CONFIG_X86_32 |
f3294a33 | 4160 | fake_ioapic_page: |
54168ed7 | 4161 | #endif |
f3294a33 | 4162 | ioapic_phys = (unsigned long) |
54168ed7 | 4163 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4164 | ioapic_phys = __pa(ioapic_phys); |
4165 | } | |
4166 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4167 | apic_printk(APIC_VERBOSE, |
4168 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4169 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4170 | idx++; |
54168ed7 | 4171 | |
54168ed7 IM |
4172 | if (ioapic_res != NULL) { |
4173 | ioapic_res->start = ioapic_phys; | |
4174 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4175 | ioapic_res++; | |
4176 | } | |
f3294a33 YL |
4177 | } |
4178 | } | |
4179 | ||
54168ed7 IM |
4180 | static int __init ioapic_insert_resources(void) |
4181 | { | |
4182 | int i; | |
4183 | struct resource *r = ioapic_resources; | |
4184 | ||
4185 | if (!r) { | |
04c93ce4 BZ |
4186 | if (nr_ioapics > 0) { |
4187 | printk(KERN_ERR | |
4188 | "IO APIC resources couldn't be allocated.\n"); | |
4189 | return -1; | |
4190 | } | |
4191 | return 0; | |
54168ed7 IM |
4192 | } |
4193 | ||
4194 | for (i = 0; i < nr_ioapics; i++) { | |
4195 | insert_resource(&iomem_resource, r); | |
4196 | r++; | |
4197 | } | |
4198 | ||
4199 | return 0; | |
4200 | } | |
4201 | ||
4202 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4203 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4204 | late_initcall(ioapic_insert_resources); |