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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
85ac16d0 | 132 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
133 | { |
134 | struct irq_pin_list *pin; | |
0b8f1efa YL |
135 | |
136 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
137 | |
138 | return pin; | |
139 | } | |
140 | ||
a1420f39 | 141 | struct irq_cfg { |
0f978f45 | 142 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
143 | cpumask_var_t domain; |
144 | cpumask_var_t old_domain; | |
497c9a19 | 145 | unsigned move_cleanup_count; |
a1420f39 | 146 | u8 vector; |
497c9a19 | 147 | u8 move_in_progress : 1; |
a1420f39 YL |
148 | }; |
149 | ||
a1420f39 | 150 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
151 | #ifdef CONFIG_SPARSE_IRQ |
152 | static struct irq_cfg irq_cfgx[] = { | |
153 | #else | |
d6c88a50 | 154 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 155 | #endif |
22f65d31 MT |
156 | [0] = { .vector = IRQ0_VECTOR, }, |
157 | [1] = { .vector = IRQ1_VECTOR, }, | |
158 | [2] = { .vector = IRQ2_VECTOR, }, | |
159 | [3] = { .vector = IRQ3_VECTOR, }, | |
160 | [4] = { .vector = IRQ4_VECTOR, }, | |
161 | [5] = { .vector = IRQ5_VECTOR, }, | |
162 | [6] = { .vector = IRQ6_VECTOR, }, | |
163 | [7] = { .vector = IRQ7_VECTOR, }, | |
164 | [8] = { .vector = IRQ8_VECTOR, }, | |
165 | [9] = { .vector = IRQ9_VECTOR, }, | |
166 | [10] = { .vector = IRQ10_VECTOR, }, | |
167 | [11] = { .vector = IRQ11_VECTOR, }, | |
168 | [12] = { .vector = IRQ12_VECTOR, }, | |
169 | [13] = { .vector = IRQ13_VECTOR, }, | |
170 | [14] = { .vector = IRQ14_VECTOR, }, | |
171 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
172 | }; |
173 | ||
13a0c3c2 | 174 | int __init arch_early_irq_init(void) |
8f09cd20 | 175 | { |
0b8f1efa YL |
176 | struct irq_cfg *cfg; |
177 | struct irq_desc *desc; | |
178 | int count; | |
179 | int i; | |
d6c88a50 | 180 | |
0b8f1efa YL |
181 | cfg = irq_cfgx; |
182 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 183 | |
0b8f1efa YL |
184 | for (i = 0; i < count; i++) { |
185 | desc = irq_to_desc(i); | |
186 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
187 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
188 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
189 | if (i < NR_IRQS_LEGACY) | |
190 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 191 | } |
13a0c3c2 YL |
192 | |
193 | return 0; | |
0b8f1efa | 194 | } |
8f09cd20 | 195 | |
0b8f1efa | 196 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 197 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 198 | { |
0b8f1efa YL |
199 | struct irq_cfg *cfg = NULL; |
200 | struct irq_desc *desc; | |
1da177e4 | 201 | |
0b8f1efa YL |
202 | desc = irq_to_desc(irq); |
203 | if (desc) | |
204 | cfg = desc->chip_data; | |
0f978f45 | 205 | |
0b8f1efa | 206 | return cfg; |
8f09cd20 | 207 | } |
d6c88a50 | 208 | |
85ac16d0 | 209 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 210 | { |
0b8f1efa | 211 | struct irq_cfg *cfg; |
0f978f45 | 212 | |
0b8f1efa | 213 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 214 | if (cfg) { |
80855f73 | 215 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
216 | kfree(cfg); |
217 | cfg = NULL; | |
80855f73 MT |
218 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
219 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
220 | free_cpumask_var(cfg->domain); |
221 | kfree(cfg); | |
222 | cfg = NULL; | |
223 | } else { | |
224 | cpumask_clear(cfg->domain); | |
225 | cpumask_clear(cfg->old_domain); | |
226 | } | |
227 | } | |
0f978f45 | 228 | |
0b8f1efa | 229 | return cfg; |
8f09cd20 YL |
230 | } |
231 | ||
85ac16d0 | 232 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 233 | { |
0b8f1efa | 234 | struct irq_cfg *cfg; |
d6c88a50 | 235 | |
0b8f1efa YL |
236 | cfg = desc->chip_data; |
237 | if (!cfg) { | |
85ac16d0 | 238 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
239 | if (!desc->chip_data) { |
240 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
241 | BUG_ON(1); | |
242 | } | |
243 | } | |
1da177e4 | 244 | |
13a0c3c2 | 245 | return 0; |
0b8f1efa | 246 | } |
0f978f45 | 247 | |
fcef5911 | 248 | /* for move_irq_desc */ |
48a1b10a | 249 | static void |
85ac16d0 | 250 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 251 | { |
48a1b10a YL |
252 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
253 | ||
254 | cfg->irq_2_pin = NULL; | |
255 | old_entry = old_cfg->irq_2_pin; | |
256 | if (!old_entry) | |
257 | return; | |
0f978f45 | 258 | |
85ac16d0 | 259 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
260 | if (!entry) |
261 | return; | |
0f978f45 | 262 | |
48a1b10a YL |
263 | entry->apic = old_entry->apic; |
264 | entry->pin = old_entry->pin; | |
265 | head = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | while (old_entry) { | |
85ac16d0 | 269 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
270 | if (!entry) { |
271 | entry = head; | |
272 | while (entry) { | |
273 | head = entry->next; | |
274 | kfree(entry); | |
275 | entry = head; | |
276 | } | |
277 | /* still use the old one */ | |
278 | return; | |
279 | } | |
280 | entry->apic = old_entry->apic; | |
281 | entry->pin = old_entry->pin; | |
282 | tail->next = entry; | |
283 | tail = entry; | |
284 | old_entry = old_entry->next; | |
285 | } | |
0f978f45 | 286 | |
48a1b10a YL |
287 | tail->next = NULL; |
288 | cfg->irq_2_pin = head; | |
0f978f45 | 289 | } |
0f978f45 | 290 | |
48a1b10a | 291 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 292 | { |
48a1b10a | 293 | struct irq_pin_list *entry, *next; |
0f978f45 | 294 | |
48a1b10a YL |
295 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
296 | return; | |
301e6190 | 297 | |
48a1b10a | 298 | entry = old_cfg->irq_2_pin; |
0f978f45 | 299 | |
48a1b10a YL |
300 | while (entry) { |
301 | next = entry->next; | |
302 | kfree(entry); | |
303 | entry = next; | |
304 | } | |
305 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 306 | } |
0f978f45 | 307 | |
48a1b10a | 308 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 309 | struct irq_desc *desc, int node) |
0f978f45 | 310 | { |
48a1b10a YL |
311 | struct irq_cfg *cfg; |
312 | struct irq_cfg *old_cfg; | |
0f978f45 | 313 | |
85ac16d0 | 314 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 315 | |
48a1b10a YL |
316 | if (!cfg) |
317 | return; | |
318 | ||
319 | desc->chip_data = cfg; | |
320 | ||
321 | old_cfg = old_desc->chip_data; | |
322 | ||
323 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
324 | ||
85ac16d0 | 325 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 326 | } |
1da177e4 | 327 | |
48a1b10a YL |
328 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
329 | { | |
330 | kfree(old_cfg); | |
331 | } | |
332 | ||
333 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
334 | { | |
335 | struct irq_cfg *old_cfg, *cfg; | |
336 | ||
337 | old_cfg = old_desc->chip_data; | |
338 | cfg = desc->chip_data; | |
339 | ||
340 | if (old_cfg == cfg) | |
341 | return; | |
342 | ||
343 | if (old_cfg) { | |
344 | free_irq_2_pin(old_cfg, cfg); | |
345 | free_irq_cfg(old_cfg); | |
346 | old_desc->chip_data = NULL; | |
347 | } | |
348 | } | |
fcef5911 | 349 | /* end for move_irq_desc */ |
48a1b10a | 350 | |
0b8f1efa YL |
351 | #else |
352 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
353 | { | |
354 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 355 | } |
1da177e4 | 356 | |
0b8f1efa YL |
357 | #endif |
358 | ||
130fe05d LT |
359 | struct io_apic { |
360 | unsigned int index; | |
361 | unsigned int unused[3]; | |
362 | unsigned int data; | |
0280f7c4 SS |
363 | unsigned int unused2[11]; |
364 | unsigned int eoi; | |
130fe05d LT |
365 | }; |
366 | ||
367 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
368 | { | |
369 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 370 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
371 | } |
372 | ||
0280f7c4 SS |
373 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
374 | { | |
375 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
376 | writel(vector, &io_apic->eoi); | |
377 | } | |
378 | ||
130fe05d LT |
379 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
380 | { | |
381 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
382 | writel(reg, &io_apic->index); | |
383 | return readl(&io_apic->data); | |
384 | } | |
385 | ||
386 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
387 | { | |
388 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
389 | writel(reg, &io_apic->index); | |
390 | writel(value, &io_apic->data); | |
391 | } | |
392 | ||
393 | /* | |
394 | * Re-write a value: to be used for read-modify-write | |
395 | * cycles where the read already set up the index register. | |
396 | * | |
397 | * Older SiS APIC requires we rewrite the index register | |
398 | */ | |
399 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
400 | { | |
54168ed7 | 401 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
402 | |
403 | if (sis_apic_bug) | |
404 | writel(reg, &io_apic->index); | |
130fe05d LT |
405 | writel(value, &io_apic->data); |
406 | } | |
407 | ||
3145e941 | 408 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
409 | { |
410 | struct irq_pin_list *entry; | |
411 | unsigned long flags; | |
047c8fdb YL |
412 | |
413 | spin_lock_irqsave(&ioapic_lock, flags); | |
414 | entry = cfg->irq_2_pin; | |
415 | for (;;) { | |
416 | unsigned int reg; | |
417 | int pin; | |
418 | ||
419 | if (!entry) | |
420 | break; | |
421 | pin = entry->pin; | |
422 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
423 | /* Is the remote IRR bit set? */ | |
424 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
425 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
426 | return true; | |
427 | } | |
428 | if (!entry->next) | |
429 | break; | |
430 | entry = entry->next; | |
431 | } | |
432 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
433 | ||
434 | return false; | |
435 | } | |
047c8fdb | 436 | |
cf4c6a2f AK |
437 | union entry_union { |
438 | struct { u32 w1, w2; }; | |
439 | struct IO_APIC_route_entry entry; | |
440 | }; | |
441 | ||
442 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
443 | { | |
444 | union entry_union eu; | |
445 | unsigned long flags; | |
446 | spin_lock_irqsave(&ioapic_lock, flags); | |
447 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
448 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
449 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
450 | return eu.entry; | |
451 | } | |
452 | ||
f9dadfa7 LT |
453 | /* |
454 | * When we write a new IO APIC routing entry, we need to write the high | |
455 | * word first! If the mask bit in the low word is clear, we will enable | |
456 | * the interrupt, and we need to make sure the entry is fully populated | |
457 | * before that happens. | |
458 | */ | |
d15512f4 AK |
459 | static void |
460 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 461 | { |
cf4c6a2f AK |
462 | union entry_union eu; |
463 | eu.entry = e; | |
f9dadfa7 LT |
464 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
465 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
466 | } |
467 | ||
ca97ab90 | 468 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
469 | { |
470 | unsigned long flags; | |
471 | spin_lock_irqsave(&ioapic_lock, flags); | |
472 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
473 | spin_unlock_irqrestore(&ioapic_lock, flags); |
474 | } | |
475 | ||
476 | /* | |
477 | * When we mask an IO APIC routing entry, we need to write the low | |
478 | * word first, in order to set the mask bit before we change the | |
479 | * high bits! | |
480 | */ | |
481 | static void ioapic_mask_entry(int apic, int pin) | |
482 | { | |
483 | unsigned long flags; | |
484 | union entry_union eu = { .entry.mask = 1 }; | |
485 | ||
cf4c6a2f AK |
486 | spin_lock_irqsave(&ioapic_lock, flags); |
487 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
488 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
489 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
490 | } | |
491 | ||
497c9a19 | 492 | #ifdef CONFIG_SMP |
22f65d31 MT |
493 | static void send_cleanup_vector(struct irq_cfg *cfg) |
494 | { | |
495 | cpumask_var_t cleanup_mask; | |
496 | ||
497 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
498 | unsigned int i; | |
499 | cfg->move_cleanup_count = 0; | |
500 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
501 | cfg->move_cleanup_count++; | |
502 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
dac5f412 | 503 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
504 | } else { |
505 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
506 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
dac5f412 | 507 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
508 | free_cpumask_var(cleanup_mask); |
509 | } | |
510 | cfg->move_in_progress = 0; | |
511 | } | |
512 | ||
3145e941 | 513 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
514 | { |
515 | int apic, pin; | |
497c9a19 | 516 | struct irq_pin_list *entry; |
3145e941 | 517 | u8 vector = cfg->vector; |
497c9a19 | 518 | |
497c9a19 YL |
519 | entry = cfg->irq_2_pin; |
520 | for (;;) { | |
521 | unsigned int reg; | |
522 | ||
523 | if (!entry) | |
524 | break; | |
525 | ||
526 | apic = entry->apic; | |
527 | pin = entry->pin; | |
54168ed7 IM |
528 | /* |
529 | * With interrupt-remapping, destination information comes | |
530 | * from interrupt-remapping table entry. | |
531 | */ | |
532 | if (!irq_remapped(irq)) | |
533 | io_apic_write(apic, 0x11 + pin*2, dest); | |
497c9a19 YL |
534 | reg = io_apic_read(apic, 0x10 + pin*2); |
535 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
536 | reg |= vector; | |
54168ed7 | 537 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
538 | if (!entry->next) |
539 | break; | |
540 | entry = entry->next; | |
541 | } | |
542 | } | |
efa2559f | 543 | |
e7986739 MT |
544 | static int |
545 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 546 | |
22f65d31 | 547 | /* |
debccb3e IM |
548 | * Either sets desc->affinity to a valid value, and returns |
549 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
550 | * leaves desc->affinity untouched. | |
22f65d31 MT |
551 | */ |
552 | static unsigned int | |
553 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
554 | { |
555 | struct irq_cfg *cfg; | |
3145e941 | 556 | unsigned int irq; |
497c9a19 | 557 | |
0de26520 | 558 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 559 | return BAD_APICID; |
497c9a19 | 560 | |
3145e941 YL |
561 | irq = desc->irq; |
562 | cfg = desc->chip_data; | |
563 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 564 | return BAD_APICID; |
497c9a19 | 565 | |
e06b1b56 RR |
566 | cpumask_copy(desc->affinity, mask); |
567 | ||
568 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
22f65d31 | 569 | } |
3145e941 | 570 | |
d5dedd45 | 571 | static int |
22f65d31 | 572 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 YL |
573 | { |
574 | struct irq_cfg *cfg; | |
575 | unsigned long flags; | |
576 | unsigned int dest; | |
22f65d31 | 577 | unsigned int irq; |
d5dedd45 | 578 | int ret = -1; |
497c9a19 | 579 | |
22f65d31 MT |
580 | irq = desc->irq; |
581 | cfg = desc->chip_data; | |
497c9a19 | 582 | |
497c9a19 | 583 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
584 | dest = set_desc_affinity(desc, mask); |
585 | if (dest != BAD_APICID) { | |
586 | /* Only the high 8 bits are valid. */ | |
587 | dest = SET_APIC_LOGICAL_ID(dest); | |
588 | __target_IO_APIC_irq(irq, dest, cfg); | |
d5dedd45 | 589 | ret = 0; |
22f65d31 | 590 | } |
497c9a19 | 591 | spin_unlock_irqrestore(&ioapic_lock, flags); |
d5dedd45 YL |
592 | |
593 | return ret; | |
497c9a19 | 594 | } |
497c9a19 | 595 | |
d5dedd45 | 596 | static int |
22f65d31 | 597 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
3145e941 YL |
598 | { |
599 | struct irq_desc *desc; | |
497c9a19 | 600 | |
54168ed7 | 601 | desc = irq_to_desc(irq); |
3145e941 | 602 | |
d5dedd45 | 603 | return set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 | 604 | } |
497c9a19 YL |
605 | #endif /* CONFIG_SMP */ |
606 | ||
1da177e4 LT |
607 | /* |
608 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
609 | * shared ISA-space IRQs, so we have to support them. We are super | |
610 | * fast in the common case, and fast for shared ISA-space IRQs. | |
611 | */ | |
85ac16d0 | 612 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 613 | { |
0f978f45 YL |
614 | struct irq_pin_list *entry; |
615 | ||
0f978f45 YL |
616 | entry = cfg->irq_2_pin; |
617 | if (!entry) { | |
85ac16d0 | 618 | entry = get_one_free_irq_2_pin(node); |
0b8f1efa YL |
619 | if (!entry) { |
620 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
621 | apic, pin); | |
622 | return; | |
623 | } | |
0f978f45 YL |
624 | cfg->irq_2_pin = entry; |
625 | entry->apic = apic; | |
626 | entry->pin = pin; | |
0f978f45 YL |
627 | return; |
628 | } | |
1da177e4 | 629 | |
0f978f45 YL |
630 | while (entry->next) { |
631 | /* not again, please */ | |
632 | if (entry->apic == apic && entry->pin == pin) | |
633 | return; | |
1da177e4 | 634 | |
0f978f45 | 635 | entry = entry->next; |
1da177e4 | 636 | } |
0f978f45 | 637 | |
85ac16d0 | 638 | entry->next = get_one_free_irq_2_pin(node); |
0f978f45 | 639 | entry = entry->next; |
1da177e4 LT |
640 | entry->apic = apic; |
641 | entry->pin = pin; | |
642 | } | |
643 | ||
644 | /* | |
645 | * Reroute an IRQ to a different pin. | |
646 | */ | |
85ac16d0 | 647 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
1da177e4 LT |
648 | int oldapic, int oldpin, |
649 | int newapic, int newpin) | |
650 | { | |
0f978f45 YL |
651 | struct irq_pin_list *entry = cfg->irq_2_pin; |
652 | int replaced = 0; | |
1da177e4 | 653 | |
0f978f45 | 654 | while (entry) { |
1da177e4 LT |
655 | if (entry->apic == oldapic && entry->pin == oldpin) { |
656 | entry->apic = newapic; | |
657 | entry->pin = newpin; | |
0f978f45 YL |
658 | replaced = 1; |
659 | /* every one is different, right? */ | |
1da177e4 | 660 | break; |
0f978f45 YL |
661 | } |
662 | entry = entry->next; | |
1da177e4 | 663 | } |
0f978f45 YL |
664 | |
665 | /* why? call replace before add? */ | |
666 | if (!replaced) | |
85ac16d0 | 667 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
1da177e4 LT |
668 | } |
669 | ||
3145e941 | 670 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
671 | int mask_and, int mask_or, |
672 | void (*final)(struct irq_pin_list *entry)) | |
673 | { | |
674 | int pin; | |
87783be4 | 675 | struct irq_pin_list *entry; |
047c8fdb | 676 | |
87783be4 CG |
677 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
678 | unsigned int reg; | |
679 | pin = entry->pin; | |
680 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
681 | reg &= mask_and; | |
682 | reg |= mask_or; | |
683 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
684 | if (final) | |
685 | final(entry); | |
686 | } | |
687 | } | |
047c8fdb | 688 | |
3145e941 | 689 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 690 | { |
3145e941 | 691 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 692 | } |
047c8fdb | 693 | |
4e738e2f | 694 | #ifdef CONFIG_X86_64 |
7f3e632f | 695 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 696 | { |
87783be4 CG |
697 | /* |
698 | * Synchronize the IO-APIC and the CPU by doing | |
699 | * a dummy read from the IO-APIC | |
700 | */ | |
701 | struct io_apic __iomem *io_apic; | |
702 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 703 | readl(&io_apic->data); |
1da177e4 LT |
704 | } |
705 | ||
3145e941 | 706 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 707 | { |
3145e941 | 708 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
709 | } |
710 | #else /* CONFIG_X86_32 */ | |
3145e941 | 711 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 712 | { |
3145e941 | 713 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 714 | } |
1da177e4 | 715 | |
3145e941 | 716 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 717 | { |
3145e941 | 718 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
719 | IO_APIC_REDIR_MASKED, NULL); |
720 | } | |
1da177e4 | 721 | |
3145e941 | 722 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 723 | { |
3145e941 | 724 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
725 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
726 | } | |
727 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 728 | |
3145e941 | 729 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 730 | { |
3145e941 | 731 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
732 | unsigned long flags; |
733 | ||
3145e941 YL |
734 | BUG_ON(!cfg); |
735 | ||
1da177e4 | 736 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 737 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
738 | spin_unlock_irqrestore(&ioapic_lock, flags); |
739 | } | |
740 | ||
3145e941 | 741 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 742 | { |
3145e941 | 743 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
744 | unsigned long flags; |
745 | ||
746 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 747 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
748 | spin_unlock_irqrestore(&ioapic_lock, flags); |
749 | } | |
750 | ||
3145e941 YL |
751 | static void mask_IO_APIC_irq(unsigned int irq) |
752 | { | |
753 | struct irq_desc *desc = irq_to_desc(irq); | |
754 | ||
755 | mask_IO_APIC_irq_desc(desc); | |
756 | } | |
757 | static void unmask_IO_APIC_irq(unsigned int irq) | |
758 | { | |
759 | struct irq_desc *desc = irq_to_desc(irq); | |
760 | ||
761 | unmask_IO_APIC_irq_desc(desc); | |
762 | } | |
763 | ||
1da177e4 LT |
764 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
765 | { | |
766 | struct IO_APIC_route_entry entry; | |
36062448 | 767 | |
1da177e4 | 768 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 769 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
770 | if (entry.delivery_mode == dest_SMI) |
771 | return; | |
1da177e4 LT |
772 | /* |
773 | * Disable it in the IO-APIC irq-routing table: | |
774 | */ | |
f9dadfa7 | 775 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
776 | } |
777 | ||
54168ed7 | 778 | static void clear_IO_APIC (void) |
1da177e4 LT |
779 | { |
780 | int apic, pin; | |
781 | ||
782 | for (apic = 0; apic < nr_ioapics; apic++) | |
783 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
784 | clear_IO_APIC_pin(apic, pin); | |
785 | } | |
786 | ||
54168ed7 | 787 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
788 | /* |
789 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
790 | * specific CPU-side IRQs. | |
791 | */ | |
792 | ||
793 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
794 | static int pirq_entries[MAX_PIRQS] = { |
795 | [0 ... MAX_PIRQS - 1] = -1 | |
796 | }; | |
1da177e4 | 797 | |
1da177e4 LT |
798 | static int __init ioapic_pirq_setup(char *str) |
799 | { | |
800 | int i, max; | |
801 | int ints[MAX_PIRQS+1]; | |
802 | ||
803 | get_options(str, ARRAY_SIZE(ints), ints); | |
804 | ||
1da177e4 LT |
805 | apic_printk(APIC_VERBOSE, KERN_INFO |
806 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
807 | max = MAX_PIRQS; | |
808 | if (ints[0] < MAX_PIRQS) | |
809 | max = ints[0]; | |
810 | ||
811 | for (i = 0; i < max; i++) { | |
812 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
813 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
814 | /* | |
815 | * PIRQs are mapped upside down, usually. | |
816 | */ | |
817 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
818 | } | |
819 | return 1; | |
820 | } | |
821 | ||
822 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
823 | #endif /* CONFIG_X86_32 */ |
824 | ||
825 | #ifdef CONFIG_INTR_REMAP | |
b24696bc FY |
826 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
827 | { | |
828 | int apic; | |
829 | struct IO_APIC_route_entry **ioapic_entries; | |
830 | ||
831 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
832 | GFP_ATOMIC); | |
833 | if (!ioapic_entries) | |
834 | return 0; | |
835 | ||
836 | for (apic = 0; apic < nr_ioapics; apic++) { | |
837 | ioapic_entries[apic] = | |
838 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
839 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
840 | if (!ioapic_entries[apic]) | |
841 | goto nomem; | |
842 | } | |
843 | ||
844 | return ioapic_entries; | |
845 | ||
846 | nomem: | |
847 | while (--apic >= 0) | |
848 | kfree(ioapic_entries[apic]); | |
849 | kfree(ioapic_entries); | |
850 | ||
851 | return 0; | |
852 | } | |
54168ed7 IM |
853 | |
854 | /* | |
05c3dc2c | 855 | * Saves all the IO-APIC RTE's |
54168ed7 | 856 | */ |
b24696bc | 857 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 858 | { |
54168ed7 IM |
859 | int apic, pin; |
860 | ||
b24696bc FY |
861 | if (!ioapic_entries) |
862 | return -ENOMEM; | |
54168ed7 IM |
863 | |
864 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
865 | if (!ioapic_entries[apic]) |
866 | return -ENOMEM; | |
54168ed7 | 867 | |
05c3dc2c | 868 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 869 | ioapic_entries[apic][pin] = |
54168ed7 | 870 | ioapic_read_entry(apic, pin); |
b24696bc | 871 | } |
5ffa4eb2 | 872 | |
54168ed7 IM |
873 | return 0; |
874 | } | |
875 | ||
b24696bc FY |
876 | /* |
877 | * Mask all IO APIC entries. | |
878 | */ | |
879 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
880 | { |
881 | int apic, pin; | |
882 | ||
b24696bc FY |
883 | if (!ioapic_entries) |
884 | return; | |
885 | ||
05c3dc2c | 886 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 887 | if (!ioapic_entries[apic]) |
05c3dc2c | 888 | break; |
b24696bc | 889 | |
05c3dc2c SS |
890 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
891 | struct IO_APIC_route_entry entry; | |
892 | ||
b24696bc | 893 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
894 | if (!entry.mask) { |
895 | entry.mask = 1; | |
896 | ioapic_write_entry(apic, pin, entry); | |
897 | } | |
898 | } | |
899 | } | |
900 | } | |
901 | ||
b24696bc FY |
902 | /* |
903 | * Restore IO APIC entries which was saved in ioapic_entries. | |
904 | */ | |
905 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
906 | { |
907 | int apic, pin; | |
908 | ||
b24696bc FY |
909 | if (!ioapic_entries) |
910 | return -ENOMEM; | |
911 | ||
5ffa4eb2 | 912 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
913 | if (!ioapic_entries[apic]) |
914 | return -ENOMEM; | |
915 | ||
54168ed7 IM |
916 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
917 | ioapic_write_entry(apic, pin, | |
b24696bc | 918 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 919 | } |
b24696bc | 920 | return 0; |
54168ed7 IM |
921 | } |
922 | ||
b24696bc FY |
923 | void reinit_intr_remapped_IO_APIC(int intr_remapping, |
924 | struct IO_APIC_route_entry **ioapic_entries) | |
925 | ||
54168ed7 IM |
926 | { |
927 | /* | |
928 | * for now plain restore of previous settings. | |
929 | * TBD: In the case of OS enabling interrupt-remapping, | |
930 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
931 | * table entries. for now, do a plain restore, and wait for | |
932 | * the setup_IO_APIC_irqs() to do proper initialization. | |
933 | */ | |
b24696bc FY |
934 | restore_IO_APIC_setup(ioapic_entries); |
935 | } | |
936 | ||
937 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) | |
938 | { | |
939 | int apic; | |
940 | ||
941 | for (apic = 0; apic < nr_ioapics; apic++) | |
942 | kfree(ioapic_entries[apic]); | |
943 | ||
944 | kfree(ioapic_entries); | |
54168ed7 IM |
945 | } |
946 | #endif | |
1da177e4 LT |
947 | |
948 | /* | |
949 | * Find the IRQ entry number of a certain pin. | |
950 | */ | |
951 | static int find_irq_entry(int apic, int pin, int type) | |
952 | { | |
953 | int i; | |
954 | ||
955 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
956 | if (mp_irqs[i].irqtype == type && |
957 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
958 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
959 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
960 | return i; |
961 | ||
962 | return -1; | |
963 | } | |
964 | ||
965 | /* | |
966 | * Find the pin to which IRQ[irq] (ISA) is connected | |
967 | */ | |
fcfd636a | 968 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
969 | { |
970 | int i; | |
971 | ||
972 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 973 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 974 | |
d27e2b8e | 975 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
976 | (mp_irqs[i].irqtype == type) && |
977 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 978 | |
c2c21745 | 979 | return mp_irqs[i].dstirq; |
1da177e4 LT |
980 | } |
981 | return -1; | |
982 | } | |
983 | ||
fcfd636a EB |
984 | static int __init find_isa_irq_apic(int irq, int type) |
985 | { | |
986 | int i; | |
987 | ||
988 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 989 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 990 | |
73b2961b | 991 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
992 | (mp_irqs[i].irqtype == type) && |
993 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
994 | break; |
995 | } | |
996 | if (i < mp_irq_entries) { | |
997 | int apic; | |
54168ed7 | 998 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 999 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
1000 | return apic; |
1001 | } | |
1002 | } | |
1003 | ||
1004 | return -1; | |
1005 | } | |
1006 | ||
1da177e4 LT |
1007 | /* |
1008 | * Find a specific PCI IRQ entry. | |
1009 | * Not an __init, possibly needed by modules | |
1010 | */ | |
1011 | static int pin_2_irq(int idx, int apic, int pin); | |
1012 | ||
1013 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1014 | { | |
1015 | int apic, i, best_guess = -1; | |
1016 | ||
54168ed7 IM |
1017 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1018 | bus, slot, pin); | |
ce6444d3 | 1019 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1020 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1021 | return -1; |
1022 | } | |
1023 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1024 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
1025 | |
1026 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
1027 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
1028 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1029 | break; |
1030 | ||
47cab822 | 1031 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 1032 | !mp_irqs[i].irqtype && |
1da177e4 | 1033 | (bus == lbus) && |
c2c21745 JSR |
1034 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
1035 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
1036 | |
1037 | if (!(apic || IO_APIC_IRQ(irq))) | |
1038 | continue; | |
1039 | ||
c2c21745 | 1040 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
1041 | return irq; |
1042 | /* | |
1043 | * Use the first all-but-pin matching entry as a | |
1044 | * best-guess fuzzy result for broken mptables. | |
1045 | */ | |
1046 | if (best_guess < 0) | |
1047 | best_guess = irq; | |
1048 | } | |
1049 | } | |
1050 | return best_guess; | |
1051 | } | |
54168ed7 | 1052 | |
129f6946 | 1053 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1054 | |
c0a282c2 | 1055 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1056 | /* |
1057 | * EISA Edge/Level control register, ELCR | |
1058 | */ | |
1059 | static int EISA_ELCR(unsigned int irq) | |
1060 | { | |
99d093d1 | 1061 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1062 | unsigned int port = 0x4d0 + (irq >> 3); |
1063 | return (inb(port) >> (irq & 7)) & 1; | |
1064 | } | |
1065 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1066 | "Broken MPtable reports ISA irq %d\n", irq); | |
1067 | return 0; | |
1068 | } | |
54168ed7 | 1069 | |
c0a282c2 | 1070 | #endif |
1da177e4 | 1071 | |
6728801d AS |
1072 | /* ISA interrupts are always polarity zero edge triggered, |
1073 | * when listed as conforming in the MP table. */ | |
1074 | ||
1075 | #define default_ISA_trigger(idx) (0) | |
1076 | #define default_ISA_polarity(idx) (0) | |
1077 | ||
1da177e4 LT |
1078 | /* EISA interrupts are always polarity zero and can be edge or level |
1079 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1080 | * EISA conforming in the MP table, that means its trigger type must | |
1081 | * be read in from the ELCR */ | |
1082 | ||
c2c21745 | 1083 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 1084 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1085 | |
1086 | /* PCI interrupts are always polarity one level triggered, | |
1087 | * when listed as conforming in the MP table. */ | |
1088 | ||
1089 | #define default_PCI_trigger(idx) (1) | |
1090 | #define default_PCI_polarity(idx) (1) | |
1091 | ||
1092 | /* MCA interrupts are always polarity zero level triggered, | |
1093 | * when listed as conforming in the MP table. */ | |
1094 | ||
1095 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1096 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1097 | |
61fd47e0 | 1098 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1099 | { |
c2c21745 | 1100 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1101 | int polarity; |
1102 | ||
1103 | /* | |
1104 | * Determine IRQ line polarity (high active or low active): | |
1105 | */ | |
c2c21745 | 1106 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 1107 | { |
54168ed7 IM |
1108 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1109 | if (test_bit(bus, mp_bus_not_pci)) | |
1110 | polarity = default_ISA_polarity(idx); | |
1111 | else | |
1112 | polarity = default_PCI_polarity(idx); | |
1113 | break; | |
1114 | case 1: /* high active */ | |
1115 | { | |
1116 | polarity = 0; | |
1117 | break; | |
1118 | } | |
1119 | case 2: /* reserved */ | |
1120 | { | |
1121 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1122 | polarity = 1; | |
1123 | break; | |
1124 | } | |
1125 | case 3: /* low active */ | |
1126 | { | |
1127 | polarity = 1; | |
1128 | break; | |
1129 | } | |
1130 | default: /* invalid */ | |
1131 | { | |
1132 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1133 | polarity = 1; | |
1134 | break; | |
1135 | } | |
1da177e4 LT |
1136 | } |
1137 | return polarity; | |
1138 | } | |
1139 | ||
1140 | static int MPBIOS_trigger(int idx) | |
1141 | { | |
c2c21745 | 1142 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1143 | int trigger; |
1144 | ||
1145 | /* | |
1146 | * Determine IRQ trigger mode (edge or level sensitive): | |
1147 | */ | |
c2c21745 | 1148 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1149 | { |
54168ed7 IM |
1150 | case 0: /* conforms, ie. bus-type dependent */ |
1151 | if (test_bit(bus, mp_bus_not_pci)) | |
1152 | trigger = default_ISA_trigger(idx); | |
1153 | else | |
1154 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1155 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1156 | switch (mp_bus_id_to_type[bus]) { |
1157 | case MP_BUS_ISA: /* ISA pin */ | |
1158 | { | |
1159 | /* set before the switch */ | |
1160 | break; | |
1161 | } | |
1162 | case MP_BUS_EISA: /* EISA pin */ | |
1163 | { | |
1164 | trigger = default_EISA_trigger(idx); | |
1165 | break; | |
1166 | } | |
1167 | case MP_BUS_PCI: /* PCI pin */ | |
1168 | { | |
1169 | /* set before the switch */ | |
1170 | break; | |
1171 | } | |
1172 | case MP_BUS_MCA: /* MCA pin */ | |
1173 | { | |
1174 | trigger = default_MCA_trigger(idx); | |
1175 | break; | |
1176 | } | |
1177 | default: | |
1178 | { | |
1179 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1180 | trigger = 1; | |
1181 | break; | |
1182 | } | |
1183 | } | |
1184 | #endif | |
1da177e4 | 1185 | break; |
54168ed7 | 1186 | case 1: /* edge */ |
1da177e4 | 1187 | { |
54168ed7 | 1188 | trigger = 0; |
1da177e4 LT |
1189 | break; |
1190 | } | |
54168ed7 | 1191 | case 2: /* reserved */ |
1da177e4 | 1192 | { |
54168ed7 IM |
1193 | printk(KERN_WARNING "broken BIOS!!\n"); |
1194 | trigger = 1; | |
1da177e4 LT |
1195 | break; |
1196 | } | |
54168ed7 | 1197 | case 3: /* level */ |
1da177e4 | 1198 | { |
54168ed7 | 1199 | trigger = 1; |
1da177e4 LT |
1200 | break; |
1201 | } | |
54168ed7 | 1202 | default: /* invalid */ |
1da177e4 LT |
1203 | { |
1204 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1205 | trigger = 0; |
1da177e4 LT |
1206 | break; |
1207 | } | |
1208 | } | |
1209 | return trigger; | |
1210 | } | |
1211 | ||
1212 | static inline int irq_polarity(int idx) | |
1213 | { | |
1214 | return MPBIOS_polarity(idx); | |
1215 | } | |
1216 | ||
1217 | static inline int irq_trigger(int idx) | |
1218 | { | |
1219 | return MPBIOS_trigger(idx); | |
1220 | } | |
1221 | ||
efa2559f | 1222 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1223 | static int pin_2_irq(int idx, int apic, int pin) |
1224 | { | |
1225 | int irq, i; | |
c2c21745 | 1226 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1227 | |
1228 | /* | |
1229 | * Debugging check, we are in big trouble if this message pops up! | |
1230 | */ | |
c2c21745 | 1231 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1232 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1233 | ||
54168ed7 | 1234 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1235 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1236 | } else { |
643befed AS |
1237 | /* |
1238 | * PCI IRQs are mapped in order | |
1239 | */ | |
1240 | i = irq = 0; | |
1241 | while (i < apic) | |
1242 | irq += nr_ioapic_registers[i++]; | |
1243 | irq += pin; | |
d6c88a50 | 1244 | /* |
54168ed7 IM |
1245 | * For MPS mode, so far only needed by ES7000 platform |
1246 | */ | |
d6c88a50 TG |
1247 | if (ioapic_renumber_irq) |
1248 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1249 | } |
1250 | ||
54168ed7 | 1251 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1252 | /* |
1253 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1254 | */ | |
1255 | if ((pin >= 16) && (pin <= 23)) { | |
1256 | if (pirq_entries[pin-16] != -1) { | |
1257 | if (!pirq_entries[pin-16]) { | |
1258 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1259 | "disabling PIRQ%d\n", pin-16); | |
1260 | } else { | |
1261 | irq = pirq_entries[pin-16]; | |
1262 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1263 | "using PIRQ%d -> IRQ %d\n", | |
1264 | pin-16, irq); | |
1265 | } | |
1266 | } | |
1267 | } | |
54168ed7 IM |
1268 | #endif |
1269 | ||
1da177e4 LT |
1270 | return irq; |
1271 | } | |
1272 | ||
497c9a19 YL |
1273 | void lock_vector_lock(void) |
1274 | { | |
1275 | /* Used to the online set of cpus does not change | |
1276 | * during assign_irq_vector. | |
1277 | */ | |
1278 | spin_lock(&vector_lock); | |
1279 | } | |
1da177e4 | 1280 | |
497c9a19 | 1281 | void unlock_vector_lock(void) |
1da177e4 | 1282 | { |
497c9a19 YL |
1283 | spin_unlock(&vector_lock); |
1284 | } | |
1da177e4 | 1285 | |
e7986739 MT |
1286 | static int |
1287 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1288 | { |
047c8fdb YL |
1289 | /* |
1290 | * NOTE! The local APIC isn't very good at handling | |
1291 | * multiple interrupts at the same interrupt level. | |
1292 | * As the interrupt level is determined by taking the | |
1293 | * vector number and shifting that right by 4, we | |
1294 | * want to spread these out a bit so that they don't | |
1295 | * all fall in the same interrupt level. | |
1296 | * | |
1297 | * Also, we've got to be careful not to trash gate | |
1298 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1299 | */ | |
54168ed7 IM |
1300 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1301 | unsigned int old_vector; | |
22f65d31 MT |
1302 | int cpu, err; |
1303 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1304 | |
54168ed7 IM |
1305 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1306 | return -EBUSY; | |
0a1ad60d | 1307 | |
22f65d31 MT |
1308 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1309 | return -ENOMEM; | |
ace80ab7 | 1310 | |
54168ed7 IM |
1311 | old_vector = cfg->vector; |
1312 | if (old_vector) { | |
22f65d31 MT |
1313 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1314 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1315 | if (!cpumask_empty(tmp_mask)) { | |
1316 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1317 | return 0; |
22f65d31 | 1318 | } |
54168ed7 | 1319 | } |
497c9a19 | 1320 | |
e7986739 | 1321 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1322 | err = -ENOSPC; |
1323 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1324 | int new_cpu; |
1325 | int vector, offset; | |
497c9a19 | 1326 | |
e2d40b18 | 1327 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1328 | |
54168ed7 IM |
1329 | vector = current_vector; |
1330 | offset = current_offset; | |
497c9a19 | 1331 | next: |
54168ed7 IM |
1332 | vector += 8; |
1333 | if (vector >= first_system_vector) { | |
e7986739 | 1334 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1335 | offset = (offset + 1) % 8; |
1336 | vector = FIRST_DEVICE_VECTOR + offset; | |
1337 | } | |
1338 | if (unlikely(current_vector == vector)) | |
1339 | continue; | |
b77b881f YL |
1340 | |
1341 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1342 | goto next; |
b77b881f | 1343 | |
22f65d31 | 1344 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1345 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1346 | goto next; | |
1347 | /* Found one! */ | |
1348 | current_vector = vector; | |
1349 | current_offset = offset; | |
1350 | if (old_vector) { | |
1351 | cfg->move_in_progress = 1; | |
22f65d31 | 1352 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1353 | } |
22f65d31 | 1354 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1355 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1356 | cfg->vector = vector; | |
22f65d31 MT |
1357 | cpumask_copy(cfg->domain, tmp_mask); |
1358 | err = 0; | |
1359 | break; | |
54168ed7 | 1360 | } |
22f65d31 MT |
1361 | free_cpumask_var(tmp_mask); |
1362 | return err; | |
497c9a19 YL |
1363 | } |
1364 | ||
e7986739 MT |
1365 | static int |
1366 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1367 | { |
1368 | int err; | |
ace80ab7 | 1369 | unsigned long flags; |
ace80ab7 EB |
1370 | |
1371 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1372 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1373 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1374 | return err; |
1375 | } | |
1376 | ||
3145e941 | 1377 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1378 | { |
497c9a19 YL |
1379 | int cpu, vector; |
1380 | ||
497c9a19 YL |
1381 | BUG_ON(!cfg->vector); |
1382 | ||
1383 | vector = cfg->vector; | |
22f65d31 | 1384 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1385 | per_cpu(vector_irq, cpu)[vector] = -1; |
1386 | ||
1387 | cfg->vector = 0; | |
22f65d31 | 1388 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1389 | |
1390 | if (likely(!cfg->move_in_progress)) | |
1391 | return; | |
22f65d31 | 1392 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1393 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1394 | vector++) { | |
1395 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1396 | continue; | |
1397 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1398 | break; | |
1399 | } | |
1400 | } | |
1401 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1402 | } |
1403 | ||
1404 | void __setup_vector_irq(int cpu) | |
1405 | { | |
1406 | /* Initialize vector_irq on a new cpu */ | |
1407 | /* This function must be called with vector_lock held */ | |
1408 | int irq, vector; | |
1409 | struct irq_cfg *cfg; | |
0b8f1efa | 1410 | struct irq_desc *desc; |
497c9a19 YL |
1411 | |
1412 | /* Mark the inuse vectors */ | |
0b8f1efa | 1413 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1414 | cfg = desc->chip_data; |
22f65d31 | 1415 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1416 | continue; |
1417 | vector = cfg->vector; | |
497c9a19 YL |
1418 | per_cpu(vector_irq, cpu)[vector] = irq; |
1419 | } | |
1420 | /* Mark the free vectors */ | |
1421 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1422 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1423 | if (irq < 0) | |
1424 | continue; | |
1425 | ||
1426 | cfg = irq_cfg(irq); | |
22f65d31 | 1427 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1428 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1429 | } |
1da177e4 | 1430 | } |
3fde6900 | 1431 | |
f5b9ed7a | 1432 | static struct irq_chip ioapic_chip; |
54168ed7 | 1433 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1434 | |
54168ed7 IM |
1435 | #define IOAPIC_AUTO -1 |
1436 | #define IOAPIC_EDGE 0 | |
1437 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1438 | |
047c8fdb | 1439 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1440 | static inline int IO_APIC_irq_trigger(int irq) |
1441 | { | |
d6c88a50 | 1442 | int apic, idx, pin; |
1d025192 | 1443 | |
d6c88a50 TG |
1444 | for (apic = 0; apic < nr_ioapics; apic++) { |
1445 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1446 | idx = find_irq_entry(apic, pin, mp_INT); | |
1447 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1448 | return irq_trigger(idx); | |
1449 | } | |
1450 | } | |
1451 | /* | |
54168ed7 IM |
1452 | * nonexistent IRQs are edge default |
1453 | */ | |
d6c88a50 | 1454 | return 0; |
1d025192 | 1455 | } |
047c8fdb YL |
1456 | #else |
1457 | static inline int IO_APIC_irq_trigger(int irq) | |
1458 | { | |
54168ed7 | 1459 | return 1; |
047c8fdb YL |
1460 | } |
1461 | #endif | |
1d025192 | 1462 | |
3145e941 | 1463 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1464 | { |
199751d7 | 1465 | |
6ebcc00e | 1466 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1467 | trigger == IOAPIC_LEVEL) |
08678b08 | 1468 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1469 | else |
1470 | desc->status &= ~IRQ_LEVEL; | |
1471 | ||
54168ed7 IM |
1472 | if (irq_remapped(irq)) { |
1473 | desc->status |= IRQ_MOVE_PCNTXT; | |
1474 | if (trigger) | |
1475 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1476 | handle_fasteoi_irq, | |
1477 | "fasteoi"); | |
1478 | else | |
1479 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1480 | handle_edge_irq, "edge"); | |
1481 | return; | |
1482 | } | |
29b61be6 | 1483 | |
047c8fdb YL |
1484 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1485 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1486 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1487 | handle_fasteoi_irq, |
1488 | "fasteoi"); | |
047c8fdb | 1489 | else |
a460e745 | 1490 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1491 | handle_edge_irq, "edge"); |
1da177e4 LT |
1492 | } |
1493 | ||
ca97ab90 JF |
1494 | int setup_ioapic_entry(int apic_id, int irq, |
1495 | struct IO_APIC_route_entry *entry, | |
1496 | unsigned int destination, int trigger, | |
0280f7c4 | 1497 | int polarity, int vector, int pin) |
1da177e4 | 1498 | { |
497c9a19 YL |
1499 | /* |
1500 | * add it to the IO-APIC irq-routing table: | |
1501 | */ | |
1502 | memset(entry,0,sizeof(*entry)); | |
1503 | ||
54168ed7 | 1504 | if (intr_remapping_enabled) { |
c8d46cf0 | 1505 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1506 | struct irte irte; |
1507 | struct IR_IO_APIC_route_entry *ir_entry = | |
1508 | (struct IR_IO_APIC_route_entry *) entry; | |
1509 | int index; | |
1510 | ||
1511 | if (!iommu) | |
c8d46cf0 | 1512 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1513 | |
1514 | index = alloc_irte(iommu, irq, 1); | |
1515 | if (index < 0) | |
c8d46cf0 | 1516 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1517 | |
1518 | memset(&irte, 0, sizeof(irte)); | |
1519 | ||
1520 | irte.present = 1; | |
9b5bc8dc | 1521 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1522 | /* |
1523 | * Trigger mode in the IRTE will always be edge, and the | |
1524 | * actual level or edge trigger will be setup in the IO-APIC | |
1525 | * RTE. This will help simplify level triggered irq migration. | |
1526 | * For more details, see the comments above explainig IO-APIC | |
1527 | * irq migration in the presence of interrupt-remapping. | |
1528 | */ | |
1529 | irte.trigger_mode = 0; | |
9b5bc8dc | 1530 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1531 | irte.vector = vector; |
1532 | irte.dest_id = IRTE_DEST(destination); | |
1533 | ||
1534 | modify_irte(irq, &irte); | |
1535 | ||
1536 | ir_entry->index2 = (index >> 15) & 0x1; | |
1537 | ir_entry->zero = 0; | |
1538 | ir_entry->format = 1; | |
1539 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1540 | /* |
1541 | * IO-APIC RTE will be configured with virtual vector. | |
1542 | * irq handler will do the explicit EOI to the io-apic. | |
1543 | */ | |
1544 | ir_entry->vector = pin; | |
29b61be6 | 1545 | } else { |
9b5bc8dc IM |
1546 | entry->delivery_mode = apic->irq_delivery_mode; |
1547 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1548 | entry->dest = destination; |
0280f7c4 | 1549 | entry->vector = vector; |
54168ed7 | 1550 | } |
497c9a19 | 1551 | |
54168ed7 | 1552 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1553 | entry->trigger = trigger; |
1554 | entry->polarity = polarity; | |
497c9a19 YL |
1555 | |
1556 | /* Mask level triggered irqs. | |
1557 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1558 | */ | |
1559 | if (trigger) | |
1560 | entry->mask = 1; | |
497c9a19 YL |
1561 | return 0; |
1562 | } | |
1563 | ||
c8d46cf0 | 1564 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1565 | int trigger, int polarity) |
497c9a19 YL |
1566 | { |
1567 | struct irq_cfg *cfg; | |
1da177e4 | 1568 | struct IO_APIC_route_entry entry; |
22f65d31 | 1569 | unsigned int dest; |
497c9a19 YL |
1570 | |
1571 | if (!IO_APIC_IRQ(irq)) | |
1572 | return; | |
1573 | ||
3145e941 | 1574 | cfg = desc->chip_data; |
497c9a19 | 1575 | |
fe402e1f | 1576 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1577 | return; |
1578 | ||
debccb3e | 1579 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1580 | |
1581 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1582 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1583 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1584 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1585 | irq, trigger, polarity); |
1586 | ||
1587 | ||
c8d46cf0 | 1588 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1589 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1590 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1591 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1592 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1593 | return; |
1594 | } | |
1595 | ||
3145e941 | 1596 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1597 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1598 | disable_8259A_irq(irq); |
1599 | ||
c8d46cf0 | 1600 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1601 | } |
1602 | ||
1603 | static void __init setup_IO_APIC_irqs(void) | |
1604 | { | |
c8d46cf0 | 1605 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1606 | int notcon = 0; |
0b8f1efa | 1607 | struct irq_desc *desc; |
3145e941 | 1608 | struct irq_cfg *cfg; |
85ac16d0 | 1609 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1610 | |
1611 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1612 | ||
c8d46cf0 IM |
1613 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1614 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1615 | |
c8d46cf0 | 1616 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1617 | if (idx == -1) { |
2a554fb1 | 1618 | if (!notcon) { |
3c2cbd24 | 1619 | notcon = 1; |
2a554fb1 CG |
1620 | apic_printk(APIC_VERBOSE, |
1621 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1622 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1623 | } else |
1624 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1625 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1626 | continue; |
1627 | } | |
56ffa1a0 CG |
1628 | if (notcon) { |
1629 | apic_printk(APIC_VERBOSE, | |
1630 | " (apicid-pin) not connected\n"); | |
1631 | notcon = 0; | |
1632 | } | |
3c2cbd24 | 1633 | |
c8d46cf0 | 1634 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa IM |
1635 | |
1636 | /* | |
1637 | * Skip the timer IRQ if there's a quirk handler | |
1638 | * installed and if it returns 1: | |
1639 | */ | |
1640 | if (apic->multi_timer_check && | |
1641 | apic->multi_timer_check(apic_id, irq)) | |
3c2cbd24 | 1642 | continue; |
33a201fa | 1643 | |
85ac16d0 | 1644 | desc = irq_to_desc_alloc_node(irq, node); |
0b8f1efa YL |
1645 | if (!desc) { |
1646 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1647 | continue; | |
1648 | } | |
3145e941 | 1649 | cfg = desc->chip_data; |
85ac16d0 | 1650 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
36062448 | 1651 | |
c8d46cf0 | 1652 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1653 | irq_trigger(idx), irq_polarity(idx)); |
1654 | } | |
1da177e4 LT |
1655 | } |
1656 | ||
3c2cbd24 CG |
1657 | if (notcon) |
1658 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1659 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1660 | } |
1661 | ||
1662 | /* | |
f7633ce5 | 1663 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1664 | */ |
c8d46cf0 | 1665 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1666 | int vector) |
1da177e4 LT |
1667 | { |
1668 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1669 | |
54168ed7 IM |
1670 | if (intr_remapping_enabled) |
1671 | return; | |
54168ed7 | 1672 | |
36062448 | 1673 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1674 | |
1675 | /* | |
1676 | * We use logical delivery to get the timer IRQ | |
1677 | * to the first CPU. | |
1678 | */ | |
9b5bc8dc | 1679 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1680 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1681 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1682 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1683 | entry.polarity = 0; |
1684 | entry.trigger = 0; | |
1685 | entry.vector = vector; | |
1686 | ||
1687 | /* | |
1688 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1689 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1690 | */ |
54168ed7 | 1691 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1692 | |
1693 | /* | |
1694 | * Add it to the IO-APIC irq-routing table: | |
1695 | */ | |
c8d46cf0 | 1696 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1697 | } |
1698 | ||
32f71aff MR |
1699 | |
1700 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1701 | { |
1702 | int apic, i; | |
1703 | union IO_APIC_reg_00 reg_00; | |
1704 | union IO_APIC_reg_01 reg_01; | |
1705 | union IO_APIC_reg_02 reg_02; | |
1706 | union IO_APIC_reg_03 reg_03; | |
1707 | unsigned long flags; | |
0f978f45 | 1708 | struct irq_cfg *cfg; |
0b8f1efa | 1709 | struct irq_desc *desc; |
8f09cd20 | 1710 | unsigned int irq; |
1da177e4 LT |
1711 | |
1712 | if (apic_verbosity == APIC_QUIET) | |
1713 | return; | |
1714 | ||
36062448 | 1715 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1716 | for (i = 0; i < nr_ioapics; i++) |
1717 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1718 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1719 | |
1720 | /* | |
1721 | * We are a bit conservative about what we expect. We have to | |
1722 | * know about every hardware change ASAP. | |
1723 | */ | |
1724 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1725 | ||
1726 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1727 | ||
1728 | spin_lock_irqsave(&ioapic_lock, flags); | |
1729 | reg_00.raw = io_apic_read(apic, 0); | |
1730 | reg_01.raw = io_apic_read(apic, 1); | |
1731 | if (reg_01.bits.version >= 0x10) | |
1732 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1733 | if (reg_01.bits.version >= 0x20) |
1734 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1735 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1736 | ||
54168ed7 | 1737 | printk("\n"); |
b5ba7e6d | 1738 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1739 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1740 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1741 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1742 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1743 | |
54168ed7 | 1744 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1745 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1746 | |
1747 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1748 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1749 | |
1750 | /* | |
1751 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1752 | * but the value of reg_02 is read as the previous read register | |
1753 | * value, so ignore it if reg_02 == reg_01. | |
1754 | */ | |
1755 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1756 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1757 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1758 | } |
1759 | ||
1760 | /* | |
1761 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1762 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1763 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1764 | */ | |
1765 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1766 | reg_03.raw != reg_01.raw) { | |
1767 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1768 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1769 | } |
1770 | ||
1771 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1772 | ||
d83e94ac YL |
1773 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1774 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1775 | |
1776 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1777 | struct IO_APIC_route_entry entry; | |
1778 | ||
cf4c6a2f | 1779 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1780 | |
54168ed7 IM |
1781 | printk(KERN_DEBUG " %02x %03X ", |
1782 | i, | |
1783 | entry.dest | |
1784 | ); | |
1da177e4 LT |
1785 | |
1786 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1787 | entry.mask, | |
1788 | entry.trigger, | |
1789 | entry.irr, | |
1790 | entry.polarity, | |
1791 | entry.delivery_status, | |
1792 | entry.dest_mode, | |
1793 | entry.delivery_mode, | |
1794 | entry.vector | |
1795 | ); | |
1796 | } | |
1797 | } | |
1da177e4 | 1798 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1799 | for_each_irq_desc(irq, desc) { |
1800 | struct irq_pin_list *entry; | |
1801 | ||
0b8f1efa YL |
1802 | cfg = desc->chip_data; |
1803 | entry = cfg->irq_2_pin; | |
0f978f45 | 1804 | if (!entry) |
1da177e4 | 1805 | continue; |
8f09cd20 | 1806 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1807 | for (;;) { |
1808 | printk("-> %d:%d", entry->apic, entry->pin); | |
1809 | if (!entry->next) | |
1810 | break; | |
0f978f45 | 1811 | entry = entry->next; |
1da177e4 LT |
1812 | } |
1813 | printk("\n"); | |
1814 | } | |
1815 | ||
1816 | printk(KERN_INFO ".................................... done.\n"); | |
1817 | ||
1818 | return; | |
1819 | } | |
1820 | ||
32f71aff | 1821 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1822 | { |
1823 | unsigned int v; | |
1824 | int i, j; | |
1825 | ||
1826 | if (apic_verbosity == APIC_QUIET) | |
1827 | return; | |
1828 | ||
1829 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1830 | for (i = 0; i < 8; i++) { | |
1831 | v = apic_read(base + i*0x10); | |
1832 | for (j = 0; j < 32; j++) { | |
1833 | if (v & (1<<j)) | |
1834 | printk("1"); | |
1835 | else | |
1836 | printk("0"); | |
1837 | } | |
1838 | printk("\n"); | |
1839 | } | |
1840 | } | |
1841 | ||
32f71aff | 1842 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1843 | { |
1844 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1845 | u64 icr; |
1da177e4 LT |
1846 | |
1847 | if (apic_verbosity == APIC_QUIET) | |
1848 | return; | |
1849 | ||
1850 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1851 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1852 | v = apic_read(APIC_ID); |
54168ed7 | 1853 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1854 | v = apic_read(APIC_LVR); |
1855 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1856 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1857 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1858 | |
1859 | v = apic_read(APIC_TASKPRI); | |
1860 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1861 | ||
54168ed7 | 1862 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1863 | if (!APIC_XAPIC(ver)) { |
1864 | v = apic_read(APIC_ARBPRI); | |
1865 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1866 | v & APIC_ARBPRI_MASK); | |
1867 | } | |
1da177e4 LT |
1868 | v = apic_read(APIC_PROCPRI); |
1869 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1870 | } | |
1871 | ||
a11b5abe YL |
1872 | /* |
1873 | * Remote read supported only in the 82489DX and local APIC for | |
1874 | * Pentium processors. | |
1875 | */ | |
1876 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1877 | v = apic_read(APIC_RRR); | |
1878 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1879 | } | |
1880 | ||
1da177e4 LT |
1881 | v = apic_read(APIC_LDR); |
1882 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1883 | if (!x2apic_enabled()) { |
1884 | v = apic_read(APIC_DFR); | |
1885 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1886 | } | |
1da177e4 LT |
1887 | v = apic_read(APIC_SPIV); |
1888 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1889 | ||
1890 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1891 | print_APIC_bitfield(APIC_ISR); | |
1892 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1893 | print_APIC_bitfield(APIC_TMR); | |
1894 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1895 | print_APIC_bitfield(APIC_IRR); | |
1896 | ||
54168ed7 IM |
1897 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1898 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1899 | apic_write(APIC_ESR, 0); |
54168ed7 | 1900 | |
1da177e4 LT |
1901 | v = apic_read(APIC_ESR); |
1902 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1903 | } | |
1904 | ||
7ab6af7a | 1905 | icr = apic_icr_read(); |
0c425cec IM |
1906 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1907 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1908 | |
1909 | v = apic_read(APIC_LVTT); | |
1910 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1911 | ||
1912 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1913 | v = apic_read(APIC_LVTPC); | |
1914 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1915 | } | |
1916 | v = apic_read(APIC_LVT0); | |
1917 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1918 | v = apic_read(APIC_LVT1); | |
1919 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1920 | ||
1921 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1922 | v = apic_read(APIC_LVTERR); | |
1923 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1924 | } | |
1925 | ||
1926 | v = apic_read(APIC_TMICT); | |
1927 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1928 | v = apic_read(APIC_TMCCT); | |
1929 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1930 | v = apic_read(APIC_TDCR); | |
1931 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1932 | printk("\n"); | |
1933 | } | |
1934 | ||
32f71aff | 1935 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1936 | { |
ffd5aae7 YL |
1937 | int cpu; |
1938 | ||
1939 | preempt_disable(); | |
1940 | for_each_online_cpu(cpu) | |
1941 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1942 | preempt_enable(); | |
1da177e4 LT |
1943 | } |
1944 | ||
32f71aff | 1945 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1946 | { |
1da177e4 LT |
1947 | unsigned int v; |
1948 | unsigned long flags; | |
1949 | ||
1950 | if (apic_verbosity == APIC_QUIET) | |
1951 | return; | |
1952 | ||
1953 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1954 | ||
1955 | spin_lock_irqsave(&i8259A_lock, flags); | |
1956 | ||
1957 | v = inb(0xa1) << 8 | inb(0x21); | |
1958 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1959 | ||
1960 | v = inb(0xa0) << 8 | inb(0x20); | |
1961 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1962 | ||
54168ed7 IM |
1963 | outb(0x0b,0xa0); |
1964 | outb(0x0b,0x20); | |
1da177e4 | 1965 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1966 | outb(0x0a,0xa0); |
1967 | outb(0x0a,0x20); | |
1da177e4 LT |
1968 | |
1969 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1970 | ||
1971 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1972 | ||
1973 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1974 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1975 | } | |
1976 | ||
32f71aff MR |
1977 | __apicdebuginit(int) print_all_ICs(void) |
1978 | { | |
1979 | print_PIC(); | |
1980 | print_all_local_APICs(); | |
1981 | print_IO_APIC(); | |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
1986 | fs_initcall(print_all_ICs); | |
1987 | ||
1da177e4 | 1988 | |
efa2559f YL |
1989 | /* Where if anywhere is the i8259 connect in external int mode */ |
1990 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1991 | ||
54168ed7 | 1992 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1993 | { |
1994 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1995 | int i8259_apic, i8259_pin; |
54168ed7 | 1996 | int apic; |
1da177e4 LT |
1997 | unsigned long flags; |
1998 | ||
1da177e4 LT |
1999 | /* |
2000 | * The number of IO-APIC IRQ registers (== #pins): | |
2001 | */ | |
fcfd636a | 2002 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 2003 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 2004 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 2005 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
2006 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
2007 | } | |
54168ed7 | 2008 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2009 | int pin; |
2010 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2011 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2012 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2013 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2014 | |
fcfd636a EB |
2015 | /* If the interrupt line is enabled and in ExtInt mode |
2016 | * I have found the pin where the i8259 is connected. | |
2017 | */ | |
2018 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2019 | ioapic_i8259.apic = apic; | |
2020 | ioapic_i8259.pin = pin; | |
2021 | goto found_i8259; | |
2022 | } | |
2023 | } | |
2024 | } | |
2025 | found_i8259: | |
2026 | /* Look to see what if the MP table has reported the ExtINT */ | |
2027 | /* If we could not find the appropriate pin by looking at the ioapic | |
2028 | * the i8259 probably is not connected the ioapic but give the | |
2029 | * mptable a chance anyway. | |
2030 | */ | |
2031 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2032 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2033 | /* Trust the MP table if nothing is setup in the hardware */ | |
2034 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2035 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2036 | ioapic_i8259.pin = i8259_pin; | |
2037 | ioapic_i8259.apic = i8259_apic; | |
2038 | } | |
2039 | /* Complain if the MP table and the hardware disagree */ | |
2040 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2041 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2042 | { | |
2043 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2044 | } |
2045 | ||
2046 | /* | |
2047 | * Do not trust the IO-APIC being empty at bootup | |
2048 | */ | |
2049 | clear_IO_APIC(); | |
2050 | } | |
2051 | ||
2052 | /* | |
2053 | * Not an __init, needed by the reboot code | |
2054 | */ | |
2055 | void disable_IO_APIC(void) | |
2056 | { | |
2057 | /* | |
2058 | * Clear the IO-APIC before rebooting: | |
2059 | */ | |
2060 | clear_IO_APIC(); | |
2061 | ||
650927ef | 2062 | /* |
0b968d23 | 2063 | * If the i8259 is routed through an IOAPIC |
650927ef | 2064 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2065 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2066 | * |
2067 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2068 | * as virtual wire B is little complex (need to configure both | |
2069 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2070 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2071 | */ |
7c6d9f97 | 2072 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2073 | struct IO_APIC_route_entry entry; |
650927ef EB |
2074 | |
2075 | memset(&entry, 0, sizeof(entry)); | |
2076 | entry.mask = 0; /* Enabled */ | |
2077 | entry.trigger = 0; /* Edge */ | |
2078 | entry.irr = 0; | |
2079 | entry.polarity = 0; /* High */ | |
2080 | entry.delivery_status = 0; | |
2081 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2082 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2083 | entry.vector = 0; |
54168ed7 | 2084 | entry.dest = read_apic_id(); |
650927ef EB |
2085 | |
2086 | /* | |
2087 | * Add it to the IO-APIC irq-routing table: | |
2088 | */ | |
cf4c6a2f | 2089 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2090 | } |
54168ed7 | 2091 | |
7c6d9f97 SS |
2092 | /* |
2093 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2094 | */ | |
2095 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
2096 | } |
2097 | ||
54168ed7 | 2098 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2099 | /* |
2100 | * function to set the IO-APIC physical IDs based on the | |
2101 | * values stored in the MPC table. | |
2102 | * | |
2103 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2104 | */ | |
2105 | ||
1da177e4 LT |
2106 | static void __init setup_ioapic_ids_from_mpc(void) |
2107 | { | |
2108 | union IO_APIC_reg_00 reg_00; | |
2109 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2110 | int apic_id; |
1da177e4 LT |
2111 | int i; |
2112 | unsigned char old_id; | |
2113 | unsigned long flags; | |
2114 | ||
a4dbc34d | 2115 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2116 | return; |
d49c4288 | 2117 | |
ca05fea6 NP |
2118 | /* |
2119 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2120 | * no meaning without the serial APIC bus. | |
2121 | */ | |
7c5c1e42 SL |
2122 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2123 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2124 | return; |
1da177e4 LT |
2125 | /* |
2126 | * This is broken; anything with a real cpu count has to | |
2127 | * circumvent this idiocy regardless. | |
2128 | */ | |
d190cb87 | 2129 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2130 | |
2131 | /* | |
2132 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2133 | */ | |
c8d46cf0 | 2134 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2135 | |
2136 | /* Read the register 0 value */ | |
2137 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2138 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2139 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2140 | |
c8d46cf0 | 2141 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2142 | |
c8d46cf0 | 2143 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2144 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2145 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2146 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2147 | reg_00.bits.ID); | |
c8d46cf0 | 2148 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2149 | } |
2150 | ||
1da177e4 LT |
2151 | /* |
2152 | * Sanity check, is the ID really free? Every APIC in a | |
2153 | * system must have a unique ID or we get lots of nice | |
2154 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2155 | */ | |
d1d7cae8 | 2156 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2157 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2158 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2159 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2160 | for (i = 0; i < get_physical_broadcast(); i++) |
2161 | if (!physid_isset(i, phys_id_present_map)) | |
2162 | break; | |
2163 | if (i >= get_physical_broadcast()) | |
2164 | panic("Max APIC ID exceeded!\n"); | |
2165 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2166 | i); | |
2167 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2168 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2169 | } else { |
2170 | physid_mask_t tmp; | |
8058714a | 2171 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2172 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2173 | "phys_id_present_map\n", | |
c8d46cf0 | 2174 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2175 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2176 | } | |
2177 | ||
2178 | ||
2179 | /* | |
2180 | * We need to adjust the IRQ routing table | |
2181 | * if the ID changed. | |
2182 | */ | |
c8d46cf0 | 2183 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2184 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2185 | if (mp_irqs[i].dstapic == old_id) |
2186 | mp_irqs[i].dstapic | |
c8d46cf0 | 2187 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2188 | |
2189 | /* | |
2190 | * Read the right value from the MPC table and | |
2191 | * write it into the ID register. | |
36062448 | 2192 | */ |
1da177e4 LT |
2193 | apic_printk(APIC_VERBOSE, KERN_INFO |
2194 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2195 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2196 | |
c8d46cf0 | 2197 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2198 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2199 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2200 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2201 | |
2202 | /* | |
2203 | * Sanity check | |
2204 | */ | |
2205 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2206 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2207 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2208 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2209 | printk("could not set ID!\n"); |
2210 | else | |
2211 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2212 | } | |
2213 | } | |
54168ed7 | 2214 | #endif |
1da177e4 | 2215 | |
7ce0bcfd | 2216 | int no_timer_check __initdata; |
8542b200 ZA |
2217 | |
2218 | static int __init notimercheck(char *s) | |
2219 | { | |
2220 | no_timer_check = 1; | |
2221 | return 1; | |
2222 | } | |
2223 | __setup("no_timer_check", notimercheck); | |
2224 | ||
1da177e4 LT |
2225 | /* |
2226 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2227 | * about the timer IRQ. We do the following to work around the situation: | |
2228 | * | |
2229 | * - timer IRQ defaults to IO-APIC IRQ | |
2230 | * - if this function detects that timer IRQs are defunct, then we fall | |
2231 | * back to ISA timer IRQs | |
2232 | */ | |
f0a7a5c9 | 2233 | static int __init timer_irq_works(void) |
1da177e4 LT |
2234 | { |
2235 | unsigned long t1 = jiffies; | |
4aae0702 | 2236 | unsigned long flags; |
1da177e4 | 2237 | |
8542b200 ZA |
2238 | if (no_timer_check) |
2239 | return 1; | |
2240 | ||
4aae0702 | 2241 | local_save_flags(flags); |
1da177e4 LT |
2242 | local_irq_enable(); |
2243 | /* Let ten ticks pass... */ | |
2244 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2245 | local_irq_restore(flags); |
1da177e4 LT |
2246 | |
2247 | /* | |
2248 | * Expect a few ticks at least, to be sure some possible | |
2249 | * glue logic does not lock up after one or two first | |
2250 | * ticks in a non-ExtINT mode. Also the local APIC | |
2251 | * might have cached one ExtINT interrupt. Finally, at | |
2252 | * least one tick may be lost due to delays. | |
2253 | */ | |
54168ed7 IM |
2254 | |
2255 | /* jiffies wrap? */ | |
1d16b53e | 2256 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2257 | return 1; |
1da177e4 LT |
2258 | return 0; |
2259 | } | |
2260 | ||
2261 | /* | |
2262 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2263 | * number of pending IRQ events unhandled. These cases are very rare, | |
2264 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2265 | * better to do it this way as thus we do not have to be aware of | |
2266 | * 'pending' interrupts in the IRQ path, except at this point. | |
2267 | */ | |
2268 | /* | |
2269 | * Edge triggered needs to resend any interrupt | |
2270 | * that was delayed but this is now handled in the device | |
2271 | * independent code. | |
2272 | */ | |
2273 | ||
2274 | /* | |
2275 | * Starting up a edge-triggered IO-APIC interrupt is | |
2276 | * nasty - we need to make sure that we get the edge. | |
2277 | * If it is already asserted for some reason, we need | |
2278 | * return 1 to indicate that is was pending. | |
2279 | * | |
2280 | * This is not complete - we should be able to fake | |
2281 | * an edge even if it isn't on the 8259A... | |
2282 | */ | |
54168ed7 | 2283 | |
f5b9ed7a | 2284 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2285 | { |
2286 | int was_pending = 0; | |
2287 | unsigned long flags; | |
0b8f1efa | 2288 | struct irq_cfg *cfg; |
1da177e4 LT |
2289 | |
2290 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2291 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2292 | disable_8259A_irq(irq); |
2293 | if (i8259A_irq_pending(irq)) | |
2294 | was_pending = 1; | |
2295 | } | |
0b8f1efa | 2296 | cfg = irq_cfg(irq); |
3145e941 | 2297 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2298 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2299 | ||
2300 | return was_pending; | |
2301 | } | |
2302 | ||
54168ed7 | 2303 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2304 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2305 | { |
54168ed7 IM |
2306 | |
2307 | struct irq_cfg *cfg = irq_cfg(irq); | |
2308 | unsigned long flags; | |
2309 | ||
2310 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2311 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2312 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2313 | |
2314 | return 1; | |
2315 | } | |
54168ed7 IM |
2316 | #else |
2317 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2318 | { |
dac5f412 | 2319 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2320 | |
d6c88a50 | 2321 | return 1; |
54168ed7 IM |
2322 | } |
2323 | #endif | |
497c9a19 | 2324 | |
54168ed7 IM |
2325 | /* |
2326 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2327 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2328 | * handled with the level-triggered descriptor, but that one has slightly | |
2329 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2330 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2331 | * races. | |
2332 | */ | |
497c9a19 | 2333 | |
54168ed7 | 2334 | #ifdef CONFIG_SMP |
497c9a19 | 2335 | |
54168ed7 | 2336 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2337 | |
54168ed7 IM |
2338 | /* |
2339 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2340 | * | |
0280f7c4 SS |
2341 | * For both level and edge triggered, irq migration is a simple atomic |
2342 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2343 | * |
0280f7c4 SS |
2344 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2345 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2346 | * Real vector that is used for interrupting cpu will be coming from | |
2347 | * the interrupt-remapping table entry. | |
54168ed7 | 2348 | */ |
d5dedd45 | 2349 | static int |
e7986739 | 2350 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2351 | { |
54168ed7 | 2352 | struct irq_cfg *cfg; |
54168ed7 | 2353 | struct irte irte; |
54168ed7 | 2354 | unsigned int dest; |
3145e941 | 2355 | unsigned int irq; |
d5dedd45 | 2356 | int ret = -1; |
497c9a19 | 2357 | |
22f65d31 | 2358 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2359 | return ret; |
497c9a19 | 2360 | |
3145e941 | 2361 | irq = desc->irq; |
54168ed7 | 2362 | if (get_irte(irq, &irte)) |
d5dedd45 | 2363 | return ret; |
497c9a19 | 2364 | |
3145e941 YL |
2365 | cfg = desc->chip_data; |
2366 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2367 | return ret; |
54168ed7 | 2368 | |
debccb3e | 2369 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2370 | |
54168ed7 IM |
2371 | irte.vector = cfg->vector; |
2372 | irte.dest_id = IRTE_DEST(dest); | |
2373 | ||
2374 | /* | |
2375 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2376 | */ | |
2377 | modify_irte(irq, &irte); | |
2378 | ||
22f65d31 MT |
2379 | if (cfg->move_in_progress) |
2380 | send_cleanup_vector(cfg); | |
54168ed7 | 2381 | |
7f7ace0c | 2382 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2383 | |
2384 | return 0; | |
54168ed7 IM |
2385 | } |
2386 | ||
54168ed7 IM |
2387 | /* |
2388 | * Migrates the IRQ destination in the process context. | |
2389 | */ | |
d5dedd45 | 2390 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2391 | const struct cpumask *mask) |
54168ed7 | 2392 | { |
d5dedd45 | 2393 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2394 | } |
d5dedd45 | 2395 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2396 | const struct cpumask *mask) |
3145e941 YL |
2397 | { |
2398 | struct irq_desc *desc = irq_to_desc(irq); | |
2399 | ||
d5dedd45 | 2400 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2401 | } |
29b61be6 | 2402 | #else |
d5dedd45 | 2403 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2404 | const struct cpumask *mask) |
2405 | { | |
d5dedd45 | 2406 | return 0; |
29b61be6 | 2407 | } |
54168ed7 IM |
2408 | #endif |
2409 | ||
2410 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2411 | { | |
2412 | unsigned vector, me; | |
8f2466f4 | 2413 | |
54168ed7 | 2414 | ack_APIC_irq(); |
54168ed7 | 2415 | exit_idle(); |
54168ed7 IM |
2416 | irq_enter(); |
2417 | ||
2418 | me = smp_processor_id(); | |
2419 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2420 | unsigned int irq; | |
68a8ca59 | 2421 | unsigned int irr; |
54168ed7 IM |
2422 | struct irq_desc *desc; |
2423 | struct irq_cfg *cfg; | |
2424 | irq = __get_cpu_var(vector_irq)[vector]; | |
2425 | ||
0b8f1efa YL |
2426 | if (irq == -1) |
2427 | continue; | |
2428 | ||
54168ed7 IM |
2429 | desc = irq_to_desc(irq); |
2430 | if (!desc) | |
2431 | continue; | |
2432 | ||
2433 | cfg = irq_cfg(irq); | |
2434 | spin_lock(&desc->lock); | |
2435 | if (!cfg->move_cleanup_count) | |
2436 | goto unlock; | |
2437 | ||
22f65d31 | 2438 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2439 | goto unlock; |
2440 | ||
68a8ca59 SS |
2441 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2442 | /* | |
2443 | * Check if the vector that needs to be cleanedup is | |
2444 | * registered at the cpu's IRR. If so, then this is not | |
2445 | * the best time to clean it up. Lets clean it up in the | |
2446 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2447 | * to myself. | |
2448 | */ | |
2449 | if (irr & (1 << (vector % 32))) { | |
2450 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2451 | goto unlock; | |
2452 | } | |
54168ed7 IM |
2453 | __get_cpu_var(vector_irq)[vector] = -1; |
2454 | cfg->move_cleanup_count--; | |
2455 | unlock: | |
2456 | spin_unlock(&desc->lock); | |
2457 | } | |
2458 | ||
2459 | irq_exit(); | |
2460 | } | |
2461 | ||
3145e941 | 2462 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2463 | { |
3145e941 YL |
2464 | struct irq_desc *desc = *descp; |
2465 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2466 | unsigned vector, me; |
2467 | ||
fcef5911 | 2468 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2469 | return; |
2470 | ||
2471 | vector = ~get_irq_regs()->orig_ax; | |
2472 | me = smp_processor_id(); | |
10b888d6 | 2473 | |
fcef5911 | 2474 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2475 | send_cleanup_vector(cfg); |
497c9a19 YL |
2476 | } |
2477 | #else | |
3145e941 | 2478 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2479 | #endif |
3145e941 | 2480 | |
0280f7c4 SS |
2481 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2482 | { | |
2483 | int apic, pin; | |
2484 | struct irq_pin_list *entry; | |
2485 | ||
2486 | entry = cfg->irq_2_pin; | |
2487 | for (;;) { | |
2488 | ||
2489 | if (!entry) | |
2490 | break; | |
2491 | ||
2492 | apic = entry->apic; | |
2493 | pin = entry->pin; | |
2494 | io_apic_eoi(apic, pin); | |
2495 | entry = entry->next; | |
2496 | } | |
2497 | } | |
2498 | ||
2499 | static void | |
2500 | eoi_ioapic_irq(struct irq_desc *desc) | |
2501 | { | |
2502 | struct irq_cfg *cfg; | |
2503 | unsigned long flags; | |
2504 | unsigned int irq; | |
2505 | ||
2506 | irq = desc->irq; | |
2507 | cfg = desc->chip_data; | |
2508 | ||
2509 | spin_lock_irqsave(&ioapic_lock, flags); | |
2510 | __eoi_ioapic_irq(irq, cfg); | |
2511 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2512 | } | |
2513 | ||
746cddd3 | 2514 | #ifdef CONFIG_X86_X2APIC |
54168ed7 IM |
2515 | static void ack_x2apic_level(unsigned int irq) |
2516 | { | |
0280f7c4 | 2517 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 | 2518 | ack_x2APIC_irq(); |
0280f7c4 | 2519 | eoi_ioapic_irq(desc); |
54168ed7 IM |
2520 | } |
2521 | ||
2522 | static void ack_x2apic_edge(unsigned int irq) | |
2523 | { | |
2524 | ack_x2APIC_irq(); | |
2525 | } | |
2526 | #endif | |
497c9a19 | 2527 | |
1d025192 YL |
2528 | static void ack_apic_edge(unsigned int irq) |
2529 | { | |
3145e941 YL |
2530 | struct irq_desc *desc = irq_to_desc(irq); |
2531 | ||
2532 | irq_complete_move(&desc); | |
1d025192 YL |
2533 | move_native_irq(irq); |
2534 | ack_APIC_irq(); | |
2535 | } | |
2536 | ||
3eb2cce8 | 2537 | atomic_t irq_mis_count; |
3eb2cce8 | 2538 | |
047c8fdb YL |
2539 | static void ack_apic_level(unsigned int irq) |
2540 | { | |
3145e941 YL |
2541 | struct irq_desc *desc = irq_to_desc(irq); |
2542 | ||
3eb2cce8 YL |
2543 | #ifdef CONFIG_X86_32 |
2544 | unsigned long v; | |
2545 | int i; | |
2546 | #endif | |
3145e941 | 2547 | struct irq_cfg *cfg; |
54168ed7 | 2548 | int do_unmask_irq = 0; |
047c8fdb | 2549 | |
3145e941 | 2550 | irq_complete_move(&desc); |
047c8fdb | 2551 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2552 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2553 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2554 | do_unmask_irq = 1; |
3145e941 | 2555 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2556 | } |
047c8fdb YL |
2557 | #endif |
2558 | ||
3eb2cce8 YL |
2559 | #ifdef CONFIG_X86_32 |
2560 | /* | |
2561 | * It appears there is an erratum which affects at least version 0x11 | |
2562 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2563 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2564 | * erroneously delivered as edge-triggered one but the respective IRR | |
2565 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2566 | * message but it will never arrive and further interrupts are blocked | |
2567 | * from the source. The exact reason is so far unknown, but the | |
2568 | * phenomenon was observed when two consecutive interrupt requests | |
2569 | * from a given source get delivered to the same CPU and the source is | |
2570 | * temporarily disabled in between. | |
2571 | * | |
2572 | * A workaround is to simulate an EOI message manually. We achieve it | |
2573 | * by setting the trigger mode to edge and then to level when the edge | |
2574 | * trigger mode gets detected in the TMR of a local APIC for a | |
2575 | * level-triggered interrupt. We mask the source for the time of the | |
2576 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2577 | * The idea is from Manfred Spraul. --macro | |
2578 | */ | |
3145e941 YL |
2579 | cfg = desc->chip_data; |
2580 | i = cfg->vector; | |
3eb2cce8 YL |
2581 | |
2582 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2583 | #endif | |
2584 | ||
54168ed7 IM |
2585 | /* |
2586 | * We must acknowledge the irq before we move it or the acknowledge will | |
2587 | * not propagate properly. | |
2588 | */ | |
2589 | ack_APIC_irq(); | |
2590 | ||
746cddd3 WH |
2591 | if (irq_remapped(irq)) |
2592 | eoi_ioapic_irq(desc); | |
2593 | ||
54168ed7 IM |
2594 | /* Now we can move and renable the irq */ |
2595 | if (unlikely(do_unmask_irq)) { | |
2596 | /* Only migrate the irq if the ack has been received. | |
2597 | * | |
2598 | * On rare occasions the broadcast level triggered ack gets | |
2599 | * delayed going to ioapics, and if we reprogram the | |
2600 | * vector while Remote IRR is still set the irq will never | |
2601 | * fire again. | |
2602 | * | |
2603 | * To prevent this scenario we read the Remote IRR bit | |
2604 | * of the ioapic. This has two effects. | |
2605 | * - On any sane system the read of the ioapic will | |
2606 | * flush writes (and acks) going to the ioapic from | |
2607 | * this cpu. | |
2608 | * - We get to see if the ACK has actually been delivered. | |
2609 | * | |
2610 | * Based on failed experiments of reprogramming the | |
2611 | * ioapic entry from outside of irq context starting | |
2612 | * with masking the ioapic entry and then polling until | |
2613 | * Remote IRR was clear before reprogramming the | |
2614 | * ioapic I don't trust the Remote IRR bit to be | |
2615 | * completey accurate. | |
2616 | * | |
2617 | * However there appears to be no other way to plug | |
2618 | * this race, so if the Remote IRR bit is not | |
2619 | * accurate and is causing problems then it is a hardware bug | |
2620 | * and you can go talk to the chipset vendor about it. | |
2621 | */ | |
3145e941 YL |
2622 | cfg = desc->chip_data; |
2623 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2624 | move_masked_irq(irq); |
3145e941 | 2625 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2626 | } |
1d025192 | 2627 | |
3eb2cce8 | 2628 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2629 | if (!(v & (1 << (i & 0x1f)))) { |
2630 | atomic_inc(&irq_mis_count); | |
2631 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2632 | __mask_and_edge_IO_APIC_irq(cfg); |
2633 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2634 | spin_unlock(&ioapic_lock); |
2635 | } | |
047c8fdb | 2636 | #endif |
3eb2cce8 | 2637 | } |
1d025192 | 2638 | |
d0b03bd1 HW |
2639 | #ifdef CONFIG_INTR_REMAP |
2640 | static void ir_ack_apic_edge(unsigned int irq) | |
2641 | { | |
2642 | #ifdef CONFIG_X86_X2APIC | |
2643 | if (x2apic_enabled()) | |
2644 | return ack_x2apic_edge(irq); | |
2645 | #endif | |
2646 | return ack_apic_edge(irq); | |
2647 | } | |
2648 | ||
2649 | static void ir_ack_apic_level(unsigned int irq) | |
2650 | { | |
2651 | #ifdef CONFIG_X86_X2APIC | |
2652 | if (x2apic_enabled()) | |
2653 | return ack_x2apic_level(irq); | |
2654 | #endif | |
2655 | return ack_apic_level(irq); | |
2656 | } | |
2657 | #endif /* CONFIG_INTR_REMAP */ | |
2658 | ||
f5b9ed7a | 2659 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2660 | .name = "IO-APIC", |
2661 | .startup = startup_ioapic_irq, | |
2662 | .mask = mask_IO_APIC_irq, | |
2663 | .unmask = unmask_IO_APIC_irq, | |
2664 | .ack = ack_apic_edge, | |
2665 | .eoi = ack_apic_level, | |
54d5d424 | 2666 | #ifdef CONFIG_SMP |
d6c88a50 | 2667 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2668 | #endif |
ace80ab7 | 2669 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2670 | }; |
2671 | ||
54168ed7 | 2672 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2673 | .name = "IR-IO-APIC", |
2674 | .startup = startup_ioapic_irq, | |
2675 | .mask = mask_IO_APIC_irq, | |
2676 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2677 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2678 | .ack = ir_ack_apic_edge, |
2679 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2680 | #ifdef CONFIG_SMP |
d6c88a50 | 2681 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2682 | #endif |
54168ed7 IM |
2683 | #endif |
2684 | .retrigger = ioapic_retrigger_irq, | |
2685 | }; | |
1da177e4 LT |
2686 | |
2687 | static inline void init_IO_APIC_traps(void) | |
2688 | { | |
2689 | int irq; | |
08678b08 | 2690 | struct irq_desc *desc; |
da51a821 | 2691 | struct irq_cfg *cfg; |
1da177e4 LT |
2692 | |
2693 | /* | |
2694 | * NOTE! The local APIC isn't very good at handling | |
2695 | * multiple interrupts at the same interrupt level. | |
2696 | * As the interrupt level is determined by taking the | |
2697 | * vector number and shifting that right by 4, we | |
2698 | * want to spread these out a bit so that they don't | |
2699 | * all fall in the same interrupt level. | |
2700 | * | |
2701 | * Also, we've got to be careful not to trash gate | |
2702 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2703 | */ | |
0b8f1efa | 2704 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2705 | cfg = desc->chip_data; |
2706 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2707 | /* |
2708 | * Hmm.. We don't have an entry for this, | |
2709 | * so default to an old-fashioned 8259 | |
2710 | * interrupt if we can.. | |
2711 | */ | |
99d093d1 | 2712 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2713 | make_8259A_irq(irq); |
0b8f1efa | 2714 | else |
1da177e4 | 2715 | /* Strange. Oh, well.. */ |
08678b08 | 2716 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2717 | } |
2718 | } | |
2719 | } | |
2720 | ||
f5b9ed7a IM |
2721 | /* |
2722 | * The local APIC irq-chip implementation: | |
2723 | */ | |
1da177e4 | 2724 | |
36062448 | 2725 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2726 | { |
2727 | unsigned long v; | |
2728 | ||
2729 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2730 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2731 | } |
2732 | ||
36062448 | 2733 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2734 | { |
f5b9ed7a | 2735 | unsigned long v; |
1da177e4 | 2736 | |
f5b9ed7a | 2737 | v = apic_read(APIC_LVT0); |
593f4a78 | 2738 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2739 | } |
1da177e4 | 2740 | |
3145e941 | 2741 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2742 | { |
2743 | ack_APIC_irq(); | |
2744 | } | |
2745 | ||
f5b9ed7a | 2746 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2747 | .name = "local-APIC", |
f5b9ed7a IM |
2748 | .mask = mask_lapic_irq, |
2749 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2750 | .ack = ack_lapic_irq, |
1da177e4 LT |
2751 | }; |
2752 | ||
3145e941 | 2753 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2754 | { |
08678b08 | 2755 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2756 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2757 | "edge"); | |
c88ac1df MR |
2758 | } |
2759 | ||
e9427101 | 2760 | static void __init setup_nmi(void) |
1da177e4 LT |
2761 | { |
2762 | /* | |
36062448 | 2763 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2764 | * We put the 8259A master into AEOI mode and |
2765 | * unmask on all local APICs LVT0 as NMI. | |
2766 | * | |
2767 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2768 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2769 | * the NMI handler or the timer interrupt. | |
36062448 | 2770 | */ |
1da177e4 LT |
2771 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2772 | ||
e9427101 | 2773 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2774 | |
2775 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2776 | } | |
2777 | ||
2778 | /* | |
2779 | * This looks a bit hackish but it's about the only one way of sending | |
2780 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2781 | * not support the ExtINT mode, unfortunately. We need to send these | |
2782 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2783 | * 8259A interrupt line asserted until INTA. --macro | |
2784 | */ | |
28acf285 | 2785 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2786 | { |
fcfd636a | 2787 | int apic, pin, i; |
1da177e4 LT |
2788 | struct IO_APIC_route_entry entry0, entry1; |
2789 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2790 | |
fcfd636a | 2791 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2792 | if (pin == -1) { |
2793 | WARN_ON_ONCE(1); | |
2794 | return; | |
2795 | } | |
fcfd636a | 2796 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2797 | if (apic == -1) { |
2798 | WARN_ON_ONCE(1); | |
1da177e4 | 2799 | return; |
956fb531 | 2800 | } |
1da177e4 | 2801 | |
cf4c6a2f | 2802 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2803 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2804 | |
2805 | memset(&entry1, 0, sizeof(entry1)); | |
2806 | ||
2807 | entry1.dest_mode = 0; /* physical delivery */ | |
2808 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2809 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2810 | entry1.delivery_mode = dest_ExtINT; |
2811 | entry1.polarity = entry0.polarity; | |
2812 | entry1.trigger = 0; | |
2813 | entry1.vector = 0; | |
2814 | ||
cf4c6a2f | 2815 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2816 | |
2817 | save_control = CMOS_READ(RTC_CONTROL); | |
2818 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2819 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2820 | RTC_FREQ_SELECT); | |
2821 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2822 | ||
2823 | i = 100; | |
2824 | while (i-- > 0) { | |
2825 | mdelay(10); | |
2826 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2827 | i -= 10; | |
2828 | } | |
2829 | ||
2830 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2831 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2832 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2833 | |
cf4c6a2f | 2834 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2835 | } |
2836 | ||
efa2559f | 2837 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2838 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2839 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2840 | { |
2841 | disable_timer_pin_1 = 1; | |
2842 | return 0; | |
2843 | } | |
54168ed7 | 2844 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2845 | |
2846 | int timer_through_8259 __initdata; | |
2847 | ||
1da177e4 LT |
2848 | /* |
2849 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2850 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2851 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2852 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2853 | * |
2854 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2855 | */ |
8542b200 | 2856 | static inline void __init check_timer(void) |
1da177e4 | 2857 | { |
3145e941 YL |
2858 | struct irq_desc *desc = irq_to_desc(0); |
2859 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2860 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2861 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2862 | unsigned long flags; |
047c8fdb | 2863 | int no_pin1 = 0; |
4aae0702 IM |
2864 | |
2865 | local_irq_save(flags); | |
d4d25dec | 2866 | |
1da177e4 LT |
2867 | /* |
2868 | * get/set the timer IRQ vector: | |
2869 | */ | |
2870 | disable_8259A_irq(0); | |
fe402e1f | 2871 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2872 | |
2873 | /* | |
d11d5794 MR |
2874 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2875 | * wire has to be disabled in the local APIC. Also | |
2876 | * timer interrupts need to be acknowledged manually in | |
2877 | * the 8259A for the i82489DX when using the NMI | |
2878 | * watchdog as that APIC treats NMIs as level-triggered. | |
2879 | * The AEOI mode will finish them in the 8259A | |
2880 | * automatically. | |
1da177e4 | 2881 | */ |
593f4a78 | 2882 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2883 | init_8259A(1); |
54168ed7 | 2884 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2885 | { |
2886 | unsigned int ver; | |
2887 | ||
2888 | ver = apic_read(APIC_LVR); | |
2889 | ver = GET_APIC_VERSION(ver); | |
2890 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2891 | } | |
54168ed7 | 2892 | #endif |
1da177e4 | 2893 | |
fcfd636a EB |
2894 | pin1 = find_isa_irq_pin(0, mp_INT); |
2895 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2896 | pin2 = ioapic_i8259.pin; | |
2897 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2898 | |
49a66a0b MR |
2899 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2900 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2901 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2902 | |
691874fa MR |
2903 | /* |
2904 | * Some BIOS writers are clueless and report the ExtINTA | |
2905 | * I/O APIC input from the cascaded 8259A as the timer | |
2906 | * interrupt input. So just in case, if only one pin | |
2907 | * was found above, try it both directly and through the | |
2908 | * 8259A. | |
2909 | */ | |
2910 | if (pin1 == -1) { | |
54168ed7 IM |
2911 | if (intr_remapping_enabled) |
2912 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2913 | pin1 = pin2; |
2914 | apic1 = apic2; | |
2915 | no_pin1 = 1; | |
2916 | } else if (pin2 == -1) { | |
2917 | pin2 = pin1; | |
2918 | apic2 = apic1; | |
2919 | } | |
2920 | ||
1da177e4 LT |
2921 | if (pin1 != -1) { |
2922 | /* | |
2923 | * Ok, does IRQ0 through the IOAPIC work? | |
2924 | */ | |
691874fa | 2925 | if (no_pin1) { |
85ac16d0 | 2926 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2927 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2928 | } else { |
2929 | /* for edge trigger, setup_IO_APIC_irq already | |
2930 | * leave it unmasked. | |
2931 | * so only need to unmask if it is level-trigger | |
2932 | * do we really have level trigger timer? | |
2933 | */ | |
2934 | int idx; | |
2935 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2936 | if (idx != -1 && irq_trigger(idx)) | |
2937 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2938 | } |
1da177e4 LT |
2939 | if (timer_irq_works()) { |
2940 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2941 | setup_nmi(); |
2942 | enable_8259A_irq(0); | |
1da177e4 | 2943 | } |
66759a01 CE |
2944 | if (disable_timer_pin_1 > 0) |
2945 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2946 | goto out; |
1da177e4 | 2947 | } |
54168ed7 IM |
2948 | if (intr_remapping_enabled) |
2949 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2950 | local_irq_disable(); |
fcfd636a | 2951 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2952 | if (!no_pin1) |
49a66a0b MR |
2953 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2954 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2955 | |
49a66a0b MR |
2956 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2957 | "(IRQ0) through the 8259A ...\n"); | |
2958 | apic_printk(APIC_QUIET, KERN_INFO | |
2959 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2960 | /* |
2961 | * legacy devices should be connected to IO APIC #0 | |
2962 | */ | |
85ac16d0 | 2963 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2964 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2965 | enable_8259A_irq(0); |
1da177e4 | 2966 | if (timer_irq_works()) { |
49a66a0b | 2967 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2968 | timer_through_8259 = 1; |
1da177e4 | 2969 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2970 | disable_8259A_irq(0); |
1da177e4 | 2971 | setup_nmi(); |
60134ebe | 2972 | enable_8259A_irq(0); |
1da177e4 | 2973 | } |
4aae0702 | 2974 | goto out; |
1da177e4 LT |
2975 | } |
2976 | /* | |
2977 | * Cleanup, just in case ... | |
2978 | */ | |
f72dccac | 2979 | local_irq_disable(); |
ecd29476 | 2980 | disable_8259A_irq(0); |
fcfd636a | 2981 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2982 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2983 | } |
1da177e4 LT |
2984 | |
2985 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2986 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2987 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2988 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2989 | } |
54168ed7 | 2990 | #ifdef CONFIG_X86_32 |
d11d5794 | 2991 | timer_ack = 0; |
54168ed7 | 2992 | #endif |
1da177e4 | 2993 | |
49a66a0b MR |
2994 | apic_printk(APIC_QUIET, KERN_INFO |
2995 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2996 | |
3145e941 | 2997 | lapic_register_intr(0, desc); |
497c9a19 | 2998 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2999 | enable_8259A_irq(0); |
3000 | ||
3001 | if (timer_irq_works()) { | |
49a66a0b | 3002 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3003 | goto out; |
1da177e4 | 3004 | } |
f72dccac | 3005 | local_irq_disable(); |
e67465f1 | 3006 | disable_8259A_irq(0); |
497c9a19 | 3007 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3008 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3009 | |
49a66a0b MR |
3010 | apic_printk(APIC_QUIET, KERN_INFO |
3011 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3012 | |
1da177e4 LT |
3013 | init_8259A(0); |
3014 | make_8259A_irq(0); | |
593f4a78 | 3015 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3016 | |
3017 | unlock_ExtINT_logic(); | |
3018 | ||
3019 | if (timer_irq_works()) { | |
49a66a0b | 3020 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3021 | goto out; |
1da177e4 | 3022 | } |
f72dccac | 3023 | local_irq_disable(); |
49a66a0b | 3024 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3025 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3026 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3027 | out: |
3028 | local_irq_restore(flags); | |
1da177e4 LT |
3029 | } |
3030 | ||
3031 | /* | |
af174783 MR |
3032 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3033 | * to devices. However there may be an I/O APIC pin available for | |
3034 | * this interrupt regardless. The pin may be left unconnected, but | |
3035 | * typically it will be reused as an ExtINT cascade interrupt for | |
3036 | * the master 8259A. In the MPS case such a pin will normally be | |
3037 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3038 | * there is no provision for ExtINT interrupts, and in the absence | |
3039 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3040 | * interrupt, that is edge-triggered and unmasked by default. We | |
3041 | * used to do this, but it caused problems on some systems because | |
3042 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3043 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3044 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3045 | * the I/O APIC in all cases now. No actual device should request | |
3046 | * it anyway. --macro | |
1da177e4 LT |
3047 | */ |
3048 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3049 | ||
3050 | void __init setup_IO_APIC(void) | |
3051 | { | |
54168ed7 | 3052 | |
54168ed7 IM |
3053 | /* |
3054 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3055 | */ | |
1da177e4 | 3056 | |
af174783 | 3057 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3058 | |
54168ed7 | 3059 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3060 | /* |
54168ed7 IM |
3061 | * Set up IO-APIC IRQ routing. |
3062 | */ | |
3063 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3064 | if (!acpi_ioapic) |
3065 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3066 | #endif |
1da177e4 LT |
3067 | sync_Arb_IDs(); |
3068 | setup_IO_APIC_irqs(); | |
3069 | init_IO_APIC_traps(); | |
1e4c85f9 | 3070 | check_timer(); |
1da177e4 LT |
3071 | } |
3072 | ||
3073 | /* | |
54168ed7 IM |
3074 | * Called after all the initialization is done. If we didnt find any |
3075 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3076 | */ |
36062448 | 3077 | |
1da177e4 LT |
3078 | static int __init io_apic_bug_finalize(void) |
3079 | { | |
d6c88a50 TG |
3080 | if (sis_apic_bug == -1) |
3081 | sis_apic_bug = 0; | |
3082 | return 0; | |
1da177e4 LT |
3083 | } |
3084 | ||
3085 | late_initcall(io_apic_bug_finalize); | |
3086 | ||
3087 | struct sysfs_ioapic_data { | |
3088 | struct sys_device dev; | |
3089 | struct IO_APIC_route_entry entry[0]; | |
3090 | }; | |
54168ed7 | 3091 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3092 | |
438510f6 | 3093 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3094 | { |
3095 | struct IO_APIC_route_entry *entry; | |
3096 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3097 | int i; |
36062448 | 3098 | |
1da177e4 LT |
3099 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3100 | entry = data->entry; | |
54168ed7 IM |
3101 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3102 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3103 | |
3104 | return 0; | |
3105 | } | |
3106 | ||
3107 | static int ioapic_resume(struct sys_device *dev) | |
3108 | { | |
3109 | struct IO_APIC_route_entry *entry; | |
3110 | struct sysfs_ioapic_data *data; | |
3111 | unsigned long flags; | |
3112 | union IO_APIC_reg_00 reg_00; | |
3113 | int i; | |
36062448 | 3114 | |
1da177e4 LT |
3115 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3116 | entry = data->entry; | |
3117 | ||
3118 | spin_lock_irqsave(&ioapic_lock, flags); | |
3119 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3120 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3121 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3122 | io_apic_write(dev->id, 0, reg_00.raw); |
3123 | } | |
1da177e4 | 3124 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3125 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3126 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3127 | |
3128 | return 0; | |
3129 | } | |
3130 | ||
3131 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3132 | .name = "ioapic", |
1da177e4 LT |
3133 | .suspend = ioapic_suspend, |
3134 | .resume = ioapic_resume, | |
3135 | }; | |
3136 | ||
3137 | static int __init ioapic_init_sysfs(void) | |
3138 | { | |
54168ed7 IM |
3139 | struct sys_device * dev; |
3140 | int i, size, error; | |
1da177e4 LT |
3141 | |
3142 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3143 | if (error) | |
3144 | return error; | |
3145 | ||
54168ed7 | 3146 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3147 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3148 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3149 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3150 | if (!mp_ioapic_data[i]) { |
3151 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3152 | continue; | |
3153 | } | |
1da177e4 | 3154 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3155 | dev->id = i; |
1da177e4 LT |
3156 | dev->cls = &ioapic_sysdev_class; |
3157 | error = sysdev_register(dev); | |
3158 | if (error) { | |
3159 | kfree(mp_ioapic_data[i]); | |
3160 | mp_ioapic_data[i] = NULL; | |
3161 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3162 | continue; | |
3163 | } | |
3164 | } | |
3165 | ||
3166 | return 0; | |
3167 | } | |
3168 | ||
3169 | device_initcall(ioapic_init_sysfs); | |
3170 | ||
abcaa2b8 | 3171 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3172 | /* |
95d77884 | 3173 | * Dynamic irq allocate and deallocation |
3fc471ed | 3174 | */ |
d047f53a | 3175 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3176 | { |
ace80ab7 | 3177 | /* Allocate an unused irq */ |
54168ed7 IM |
3178 | unsigned int irq; |
3179 | unsigned int new; | |
3fc471ed | 3180 | unsigned long flags; |
0b8f1efa | 3181 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3182 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3183 | |
3184 | irq = 0; | |
abcaa2b8 YL |
3185 | if (irq_want < nr_irqs_gsi) |
3186 | irq_want = nr_irqs_gsi; | |
3187 | ||
ace80ab7 | 3188 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3189 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3190 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3191 | if (!desc_new) { |
3192 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3193 | continue; |
0b8f1efa YL |
3194 | } |
3195 | cfg_new = desc_new->chip_data; | |
3196 | ||
3197 | if (cfg_new->vector != 0) | |
ace80ab7 | 3198 | continue; |
d047f53a | 3199 | |
15e957d0 | 3200 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3201 | |
fe402e1f | 3202 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3203 | irq = new; |
3204 | break; | |
3205 | } | |
3206 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3207 | |
199751d7 | 3208 | if (irq > 0) { |
3fc471ed | 3209 | dynamic_irq_init(irq); |
0b8f1efa YL |
3210 | /* restore it, in case dynamic_irq_init clear it */ |
3211 | if (desc_new) | |
3212 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3213 | } |
3214 | return irq; | |
3215 | } | |
3216 | ||
199751d7 YL |
3217 | int create_irq(void) |
3218 | { | |
d047f53a | 3219 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3220 | unsigned int irq_want; |
54168ed7 IM |
3221 | int irq; |
3222 | ||
be5d5350 | 3223 | irq_want = nr_irqs_gsi; |
d047f53a | 3224 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3225 | |
3226 | if (irq == 0) | |
3227 | irq = -1; | |
3228 | ||
3229 | return irq; | |
199751d7 YL |
3230 | } |
3231 | ||
3fc471ed EB |
3232 | void destroy_irq(unsigned int irq) |
3233 | { | |
3234 | unsigned long flags; | |
0b8f1efa YL |
3235 | struct irq_cfg *cfg; |
3236 | struct irq_desc *desc; | |
3fc471ed | 3237 | |
0b8f1efa YL |
3238 | /* store it, in case dynamic_irq_cleanup clear it */ |
3239 | desc = irq_to_desc(irq); | |
3240 | cfg = desc->chip_data; | |
3fc471ed | 3241 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3242 | /* connect back irq_cfg */ |
3243 | if (desc) | |
3244 | desc->chip_data = cfg; | |
3fc471ed | 3245 | |
54168ed7 | 3246 | free_irte(irq); |
3fc471ed | 3247 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3248 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3249 | spin_unlock_irqrestore(&vector_lock, flags); |
3250 | } | |
3fc471ed | 3251 | |
2d3fcc1c | 3252 | /* |
27b46d76 | 3253 | * MSI message composition |
2d3fcc1c EB |
3254 | */ |
3255 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3256 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3257 | { |
497c9a19 YL |
3258 | struct irq_cfg *cfg; |
3259 | int err; | |
2d3fcc1c EB |
3260 | unsigned dest; |
3261 | ||
f1182638 JB |
3262 | if (disable_apic) |
3263 | return -ENXIO; | |
3264 | ||
3145e941 | 3265 | cfg = irq_cfg(irq); |
fe402e1f | 3266 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3267 | if (err) |
3268 | return err; | |
2d3fcc1c | 3269 | |
debccb3e | 3270 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3271 | |
54168ed7 IM |
3272 | if (irq_remapped(irq)) { |
3273 | struct irte irte; | |
3274 | int ir_index; | |
3275 | u16 sub_handle; | |
3276 | ||
3277 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3278 | BUG_ON(ir_index == -1); | |
3279 | ||
3280 | memset (&irte, 0, sizeof(irte)); | |
3281 | ||
3282 | irte.present = 1; | |
9b5bc8dc | 3283 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3284 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3285 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3286 | irte.vector = cfg->vector; |
3287 | irte.dest_id = IRTE_DEST(dest); | |
3288 | ||
3289 | modify_irte(irq, &irte); | |
3290 | ||
3291 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3292 | msg->data = sub_handle; | |
3293 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3294 | MSI_ADDR_IR_SHV | | |
3295 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3296 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3297 | } else { |
9d783ba0 SS |
3298 | if (x2apic_enabled()) |
3299 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3300 | MSI_ADDR_EXT_DEST_ID(dest); | |
3301 | else | |
3302 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3303 | ||
54168ed7 IM |
3304 | msg->address_lo = |
3305 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3306 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3307 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3308 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3309 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3310 | MSI_ADDR_REDIRECTION_CPU: |
3311 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3312 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3313 | |
54168ed7 IM |
3314 | msg->data = |
3315 | MSI_DATA_TRIGGER_EDGE | | |
3316 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3317 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3318 | MSI_DATA_DELIVERY_FIXED: |
3319 | MSI_DATA_DELIVERY_LOWPRI) | | |
3320 | MSI_DATA_VECTOR(cfg->vector); | |
3321 | } | |
497c9a19 | 3322 | return err; |
2d3fcc1c EB |
3323 | } |
3324 | ||
3b7d1921 | 3325 | #ifdef CONFIG_SMP |
d5dedd45 | 3326 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3327 | { |
3145e941 | 3328 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3329 | struct irq_cfg *cfg; |
3b7d1921 EB |
3330 | struct msi_msg msg; |
3331 | unsigned int dest; | |
3b7d1921 | 3332 | |
22f65d31 MT |
3333 | dest = set_desc_affinity(desc, mask); |
3334 | if (dest == BAD_APICID) | |
d5dedd45 | 3335 | return -1; |
2d3fcc1c | 3336 | |
3145e941 | 3337 | cfg = desc->chip_data; |
2d3fcc1c | 3338 | |
3145e941 | 3339 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3340 | |
3341 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3342 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3343 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3344 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3345 | ||
3145e941 | 3346 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3347 | |
3348 | return 0; | |
2d3fcc1c | 3349 | } |
54168ed7 IM |
3350 | #ifdef CONFIG_INTR_REMAP |
3351 | /* | |
3352 | * Migrate the MSI irq to another cpumask. This migration is | |
3353 | * done in the process context using interrupt-remapping hardware. | |
3354 | */ | |
d5dedd45 | 3355 | static int |
e7986739 | 3356 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3357 | { |
3145e941 | 3358 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3359 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3360 | unsigned int dest; |
54168ed7 | 3361 | struct irte irte; |
54168ed7 IM |
3362 | |
3363 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3364 | return -1; |
54168ed7 | 3365 | |
22f65d31 MT |
3366 | dest = set_desc_affinity(desc, mask); |
3367 | if (dest == BAD_APICID) | |
d5dedd45 | 3368 | return -1; |
54168ed7 | 3369 | |
54168ed7 IM |
3370 | irte.vector = cfg->vector; |
3371 | irte.dest_id = IRTE_DEST(dest); | |
3372 | ||
3373 | /* | |
3374 | * atomically update the IRTE with the new destination and vector. | |
3375 | */ | |
3376 | modify_irte(irq, &irte); | |
3377 | ||
3378 | /* | |
3379 | * After this point, all the interrupts will start arriving | |
3380 | * at the new destination. So, time to cleanup the previous | |
3381 | * vector allocation. | |
3382 | */ | |
22f65d31 MT |
3383 | if (cfg->move_in_progress) |
3384 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3385 | |
3386 | return 0; | |
54168ed7 | 3387 | } |
3145e941 | 3388 | |
54168ed7 | 3389 | #endif |
3b7d1921 | 3390 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3391 | |
3b7d1921 EB |
3392 | /* |
3393 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3394 | * which implement the MSI or MSI-X Capability Structure. | |
3395 | */ | |
3396 | static struct irq_chip msi_chip = { | |
3397 | .name = "PCI-MSI", | |
3398 | .unmask = unmask_msi_irq, | |
3399 | .mask = mask_msi_irq, | |
1d025192 | 3400 | .ack = ack_apic_edge, |
3b7d1921 EB |
3401 | #ifdef CONFIG_SMP |
3402 | .set_affinity = set_msi_irq_affinity, | |
3403 | #endif | |
3404 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3405 | }; |
3406 | ||
54168ed7 IM |
3407 | static struct irq_chip msi_ir_chip = { |
3408 | .name = "IR-PCI-MSI", | |
3409 | .unmask = unmask_msi_irq, | |
3410 | .mask = mask_msi_irq, | |
a1e38ca5 | 3411 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3412 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3413 | #ifdef CONFIG_SMP |
3414 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3415 | #endif |
54168ed7 IM |
3416 | #endif |
3417 | .retrigger = ioapic_retrigger_irq, | |
3418 | }; | |
3419 | ||
3420 | /* | |
3421 | * Map the PCI dev to the corresponding remapping hardware unit | |
3422 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3423 | * in it. | |
3424 | */ | |
3425 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3426 | { | |
3427 | struct intel_iommu *iommu; | |
3428 | int index; | |
3429 | ||
3430 | iommu = map_dev_to_ir(dev); | |
3431 | if (!iommu) { | |
3432 | printk(KERN_ERR | |
3433 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3434 | return -ENOENT; | |
3435 | } | |
3436 | ||
3437 | index = alloc_irte(iommu, irq, nvec); | |
3438 | if (index < 0) { | |
3439 | printk(KERN_ERR | |
3440 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3441 | pci_name(dev)); |
54168ed7 IM |
3442 | return -ENOSPC; |
3443 | } | |
3444 | return index; | |
3445 | } | |
1d025192 | 3446 | |
3145e941 | 3447 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3448 | { |
3449 | int ret; | |
3450 | struct msi_msg msg; | |
3451 | ||
3452 | ret = msi_compose_msg(dev, irq, &msg); | |
3453 | if (ret < 0) | |
3454 | return ret; | |
3455 | ||
3145e941 | 3456 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3457 | write_msi_msg(irq, &msg); |
3458 | ||
54168ed7 IM |
3459 | if (irq_remapped(irq)) { |
3460 | struct irq_desc *desc = irq_to_desc(irq); | |
3461 | /* | |
3462 | * irq migration in process context | |
3463 | */ | |
3464 | desc->status |= IRQ_MOVE_PCNTXT; | |
3465 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3466 | } else | |
54168ed7 | 3467 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3468 | |
c81bba49 YL |
3469 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3470 | ||
1d025192 YL |
3471 | return 0; |
3472 | } | |
3473 | ||
047c8fdb YL |
3474 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3475 | { | |
54168ed7 IM |
3476 | unsigned int irq; |
3477 | int ret, sub_handle; | |
0b8f1efa | 3478 | struct msi_desc *msidesc; |
54168ed7 | 3479 | unsigned int irq_want; |
1cc18521 | 3480 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3481 | int index = 0; |
d047f53a | 3482 | int node; |
54168ed7 | 3483 | |
1c8d7b0a MW |
3484 | /* x86 doesn't support multiple MSI yet */ |
3485 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3486 | return 1; | |
3487 | ||
d047f53a | 3488 | node = dev_to_node(&dev->dev); |
be5d5350 | 3489 | irq_want = nr_irqs_gsi; |
54168ed7 | 3490 | sub_handle = 0; |
0b8f1efa | 3491 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3492 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3493 | if (irq == 0) |
3494 | return -1; | |
f1ee5548 | 3495 | irq_want = irq + 1; |
54168ed7 IM |
3496 | if (!intr_remapping_enabled) |
3497 | goto no_ir; | |
3498 | ||
3499 | if (!sub_handle) { | |
3500 | /* | |
3501 | * allocate the consecutive block of IRTE's | |
3502 | * for 'nvec' | |
3503 | */ | |
3504 | index = msi_alloc_irte(dev, irq, nvec); | |
3505 | if (index < 0) { | |
3506 | ret = index; | |
3507 | goto error; | |
3508 | } | |
3509 | } else { | |
3510 | iommu = map_dev_to_ir(dev); | |
3511 | if (!iommu) { | |
3512 | ret = -ENOENT; | |
3513 | goto error; | |
3514 | } | |
3515 | /* | |
3516 | * setup the mapping between the irq and the IRTE | |
3517 | * base index, the sub_handle pointing to the | |
3518 | * appropriate interrupt remap table entry. | |
3519 | */ | |
3520 | set_irte_irq(irq, iommu, index, sub_handle); | |
3521 | } | |
3522 | no_ir: | |
0b8f1efa | 3523 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3524 | if (ret < 0) |
3525 | goto error; | |
3526 | sub_handle++; | |
3527 | } | |
3528 | return 0; | |
047c8fdb YL |
3529 | |
3530 | error: | |
54168ed7 IM |
3531 | destroy_irq(irq); |
3532 | return ret; | |
047c8fdb YL |
3533 | } |
3534 | ||
3b7d1921 EB |
3535 | void arch_teardown_msi_irq(unsigned int irq) |
3536 | { | |
f7feaca7 | 3537 | destroy_irq(irq); |
3b7d1921 EB |
3538 | } |
3539 | ||
9d783ba0 | 3540 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3541 | #ifdef CONFIG_SMP |
d5dedd45 | 3542 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3543 | { |
3145e941 | 3544 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3545 | struct irq_cfg *cfg; |
3546 | struct msi_msg msg; | |
3547 | unsigned int dest; | |
54168ed7 | 3548 | |
22f65d31 MT |
3549 | dest = set_desc_affinity(desc, mask); |
3550 | if (dest == BAD_APICID) | |
d5dedd45 | 3551 | return -1; |
54168ed7 | 3552 | |
3145e941 | 3553 | cfg = desc->chip_data; |
54168ed7 IM |
3554 | |
3555 | dmar_msi_read(irq, &msg); | |
3556 | ||
3557 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3558 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3559 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3560 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3561 | ||
3562 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3563 | |
3564 | return 0; | |
54168ed7 | 3565 | } |
3145e941 | 3566 | |
54168ed7 IM |
3567 | #endif /* CONFIG_SMP */ |
3568 | ||
3569 | struct irq_chip dmar_msi_type = { | |
3570 | .name = "DMAR_MSI", | |
3571 | .unmask = dmar_msi_unmask, | |
3572 | .mask = dmar_msi_mask, | |
3573 | .ack = ack_apic_edge, | |
3574 | #ifdef CONFIG_SMP | |
3575 | .set_affinity = dmar_msi_set_affinity, | |
3576 | #endif | |
3577 | .retrigger = ioapic_retrigger_irq, | |
3578 | }; | |
3579 | ||
3580 | int arch_setup_dmar_msi(unsigned int irq) | |
3581 | { | |
3582 | int ret; | |
3583 | struct msi_msg msg; | |
2d3fcc1c | 3584 | |
54168ed7 IM |
3585 | ret = msi_compose_msg(NULL, irq, &msg); |
3586 | if (ret < 0) | |
3587 | return ret; | |
3588 | dmar_msi_write(irq, &msg); | |
3589 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3590 | "edge"); | |
3591 | return 0; | |
3592 | } | |
3593 | #endif | |
3594 | ||
58ac1e76 | 3595 | #ifdef CONFIG_HPET_TIMER |
3596 | ||
3597 | #ifdef CONFIG_SMP | |
d5dedd45 | 3598 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3599 | { |
3145e941 | 3600 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3601 | struct irq_cfg *cfg; |
58ac1e76 | 3602 | struct msi_msg msg; |
3603 | unsigned int dest; | |
58ac1e76 | 3604 | |
22f65d31 MT |
3605 | dest = set_desc_affinity(desc, mask); |
3606 | if (dest == BAD_APICID) | |
d5dedd45 | 3607 | return -1; |
58ac1e76 | 3608 | |
3145e941 | 3609 | cfg = desc->chip_data; |
58ac1e76 | 3610 | |
3611 | hpet_msi_read(irq, &msg); | |
3612 | ||
3613 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3614 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3615 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3616 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3617 | ||
3618 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3619 | |
3620 | return 0; | |
58ac1e76 | 3621 | } |
3145e941 | 3622 | |
58ac1e76 | 3623 | #endif /* CONFIG_SMP */ |
3624 | ||
1cc18521 | 3625 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3626 | .name = "HPET_MSI", |
3627 | .unmask = hpet_msi_unmask, | |
3628 | .mask = hpet_msi_mask, | |
3629 | .ack = ack_apic_edge, | |
3630 | #ifdef CONFIG_SMP | |
3631 | .set_affinity = hpet_msi_set_affinity, | |
3632 | #endif | |
3633 | .retrigger = ioapic_retrigger_irq, | |
3634 | }; | |
3635 | ||
3636 | int arch_setup_hpet_msi(unsigned int irq) | |
3637 | { | |
3638 | int ret; | |
3639 | struct msi_msg msg; | |
6ec3cfec | 3640 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3641 | |
3642 | ret = msi_compose_msg(NULL, irq, &msg); | |
3643 | if (ret < 0) | |
3644 | return ret; | |
3645 | ||
3646 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3647 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3648 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3649 | "edge"); | |
c81bba49 | 3650 | |
58ac1e76 | 3651 | return 0; |
3652 | } | |
3653 | #endif | |
3654 | ||
54168ed7 | 3655 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3656 | /* |
3657 | * Hypertransport interrupt support | |
3658 | */ | |
3659 | #ifdef CONFIG_HT_IRQ | |
3660 | ||
3661 | #ifdef CONFIG_SMP | |
3662 | ||
497c9a19 | 3663 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3664 | { |
ec68307c EB |
3665 | struct ht_irq_msg msg; |
3666 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3667 | |
497c9a19 | 3668 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3669 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3670 | |
497c9a19 | 3671 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3672 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3673 | |
ec68307c | 3674 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3675 | } |
3676 | ||
d5dedd45 | 3677 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3678 | { |
3145e941 | 3679 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3680 | struct irq_cfg *cfg; |
8b955b0d | 3681 | unsigned int dest; |
8b955b0d | 3682 | |
22f65d31 MT |
3683 | dest = set_desc_affinity(desc, mask); |
3684 | if (dest == BAD_APICID) | |
d5dedd45 | 3685 | return -1; |
8b955b0d | 3686 | |
3145e941 | 3687 | cfg = desc->chip_data; |
8b955b0d | 3688 | |
497c9a19 | 3689 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3690 | |
3691 | return 0; | |
8b955b0d | 3692 | } |
3145e941 | 3693 | |
8b955b0d EB |
3694 | #endif |
3695 | ||
c37e108d | 3696 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3697 | .name = "PCI-HT", |
3698 | .mask = mask_ht_irq, | |
3699 | .unmask = unmask_ht_irq, | |
1d025192 | 3700 | .ack = ack_apic_edge, |
8b955b0d EB |
3701 | #ifdef CONFIG_SMP |
3702 | .set_affinity = set_ht_irq_affinity, | |
3703 | #endif | |
3704 | .retrigger = ioapic_retrigger_irq, | |
3705 | }; | |
3706 | ||
3707 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3708 | { | |
497c9a19 YL |
3709 | struct irq_cfg *cfg; |
3710 | int err; | |
8b955b0d | 3711 | |
f1182638 JB |
3712 | if (disable_apic) |
3713 | return -ENXIO; | |
3714 | ||
3145e941 | 3715 | cfg = irq_cfg(irq); |
fe402e1f | 3716 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3717 | if (!err) { |
ec68307c | 3718 | struct ht_irq_msg msg; |
8b955b0d | 3719 | unsigned dest; |
8b955b0d | 3720 | |
debccb3e IM |
3721 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3722 | apic->target_cpus()); | |
8b955b0d | 3723 | |
ec68307c | 3724 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3725 | |
ec68307c EB |
3726 | msg.address_lo = |
3727 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3728 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3729 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3730 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3731 | HT_IRQ_LOW_DM_PHYSICAL : |
3732 | HT_IRQ_LOW_DM_LOGICAL) | | |
3733 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3734 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3735 | HT_IRQ_LOW_MT_FIXED : |
3736 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3737 | HT_IRQ_LOW_IRQ_MASKED; | |
3738 | ||
ec68307c | 3739 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3740 | |
a460e745 IM |
3741 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3742 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3743 | |
3744 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3745 | } |
497c9a19 | 3746 | return err; |
8b955b0d EB |
3747 | } |
3748 | #endif /* CONFIG_HT_IRQ */ | |
3749 | ||
03b48632 | 3750 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3751 | /* |
3752 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3753 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3754 | */ | |
3755 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3756 | unsigned long mmr_offset) | |
3757 | { | |
22f65d31 | 3758 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3759 | struct irq_cfg *cfg; |
3760 | int mmr_pnode; | |
3761 | unsigned long mmr_value; | |
3762 | struct uv_IO_APIC_route_entry *entry; | |
3763 | unsigned long flags; | |
3764 | int err; | |
3765 | ||
3145e941 YL |
3766 | cfg = irq_cfg(irq); |
3767 | ||
e7986739 | 3768 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3769 | if (err != 0) |
3770 | return err; | |
3771 | ||
3772 | spin_lock_irqsave(&vector_lock, flags); | |
3773 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3774 | irq_name); | |
3775 | spin_unlock_irqrestore(&vector_lock, flags); | |
3776 | ||
4173a0e7 DN |
3777 | mmr_value = 0; |
3778 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3779 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3780 | ||
3781 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3782 | entry->delivery_mode = apic->irq_delivery_mode; |
3783 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3784 | entry->polarity = 0; |
3785 | entry->trigger = 0; | |
3786 | entry->mask = 0; | |
debccb3e | 3787 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3788 | |
3789 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3790 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3791 | ||
3792 | return irq; | |
3793 | } | |
3794 | ||
3795 | /* | |
3796 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3797 | * longer allowed to be sent. | |
3798 | */ | |
3799 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3800 | { | |
3801 | unsigned long mmr_value; | |
3802 | struct uv_IO_APIC_route_entry *entry; | |
3803 | int mmr_pnode; | |
3804 | ||
3805 | mmr_value = 0; | |
3806 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3807 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3808 | ||
3809 | entry->mask = 1; | |
3810 | ||
3811 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3812 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3813 | } | |
3814 | #endif /* CONFIG_X86_64 */ | |
3815 | ||
9d6a4d08 YL |
3816 | int __init io_apic_get_redir_entries (int ioapic) |
3817 | { | |
3818 | union IO_APIC_reg_01 reg_01; | |
3819 | unsigned long flags; | |
3820 | ||
3821 | spin_lock_irqsave(&ioapic_lock, flags); | |
3822 | reg_01.raw = io_apic_read(ioapic, 1); | |
3823 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3824 | ||
3825 | return reg_01.bits.entries; | |
3826 | } | |
3827 | ||
be5d5350 | 3828 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3829 | { |
be5d5350 YL |
3830 | int nr = 0; |
3831 | ||
cc6c5006 YL |
3832 | nr = acpi_probe_gsi(); |
3833 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3834 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3835 | } else { |
3836 | /* for acpi=off or acpi is not compiled in */ | |
3837 | int idx; | |
3838 | ||
3839 | nr = 0; | |
3840 | for (idx = 0; idx < nr_ioapics; idx++) | |
3841 | nr += io_apic_get_redir_entries(idx) + 1; | |
3842 | ||
3843 | if (nr > nr_irqs_gsi) | |
3844 | nr_irqs_gsi = nr; | |
3845 | } | |
3846 | ||
3847 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3848 | } |
3849 | ||
4a046d17 YL |
3850 | #ifdef CONFIG_SPARSE_IRQ |
3851 | int __init arch_probe_nr_irqs(void) | |
3852 | { | |
3853 | int nr; | |
3854 | ||
f1ee5548 YL |
3855 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3856 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3857 | |
f1ee5548 YL |
3858 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3859 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3860 | /* | |
3861 | * for MSI and HT dyn irq | |
3862 | */ | |
3863 | nr += nr_irqs_gsi * 16; | |
3864 | #endif | |
3865 | if (nr < nr_irqs) | |
4a046d17 YL |
3866 | nr_irqs = nr; |
3867 | ||
3868 | return 0; | |
3869 | } | |
3870 | #endif | |
3871 | ||
1da177e4 | 3872 | /* -------------------------------------------------------------------------- |
54168ed7 | 3873 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3874 | -------------------------------------------------------------------------- */ |
3875 | ||
888ba6c6 | 3876 | #ifdef CONFIG_ACPI |
1da177e4 | 3877 | |
54168ed7 | 3878 | #ifdef CONFIG_X86_32 |
36062448 | 3879 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3880 | { |
3881 | union IO_APIC_reg_00 reg_00; | |
3882 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3883 | physid_mask_t tmp; | |
3884 | unsigned long flags; | |
3885 | int i = 0; | |
3886 | ||
3887 | /* | |
36062448 PC |
3888 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3889 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3890 | * supports up to 16 on one shared APIC bus. |
36062448 | 3891 | * |
1da177e4 LT |
3892 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3893 | * advantage of new APIC bus architecture. | |
3894 | */ | |
3895 | ||
3896 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3897 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3898 | |
3899 | spin_lock_irqsave(&ioapic_lock, flags); | |
3900 | reg_00.raw = io_apic_read(ioapic, 0); | |
3901 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3902 | ||
3903 | if (apic_id >= get_physical_broadcast()) { | |
3904 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3905 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3906 | apic_id = reg_00.bits.ID; | |
3907 | } | |
3908 | ||
3909 | /* | |
36062448 | 3910 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3911 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3912 | */ | |
d1d7cae8 | 3913 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3914 | |
3915 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3916 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3917 | break; |
3918 | } | |
3919 | ||
3920 | if (i == get_physical_broadcast()) | |
3921 | panic("Max apic_id exceeded!\n"); | |
3922 | ||
3923 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3924 | "trying %d\n", ioapic, apic_id, i); | |
3925 | ||
3926 | apic_id = i; | |
36062448 | 3927 | } |
1da177e4 | 3928 | |
8058714a | 3929 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3930 | physids_or(apic_id_map, apic_id_map, tmp); |
3931 | ||
3932 | if (reg_00.bits.ID != apic_id) { | |
3933 | reg_00.bits.ID = apic_id; | |
3934 | ||
3935 | spin_lock_irqsave(&ioapic_lock, flags); | |
3936 | io_apic_write(ioapic, 0, reg_00.raw); | |
3937 | reg_00.raw = io_apic_read(ioapic, 0); | |
3938 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3939 | ||
3940 | /* Sanity check */ | |
6070f9ec AD |
3941 | if (reg_00.bits.ID != apic_id) { |
3942 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3943 | return -1; | |
3944 | } | |
1da177e4 LT |
3945 | } |
3946 | ||
3947 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3948 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3949 | ||
3950 | return apic_id; | |
3951 | } | |
3952 | ||
36062448 | 3953 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3954 | { |
3955 | union IO_APIC_reg_01 reg_01; | |
3956 | unsigned long flags; | |
3957 | ||
3958 | spin_lock_irqsave(&ioapic_lock, flags); | |
3959 | reg_01.raw = io_apic_read(ioapic, 1); | |
3960 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3961 | ||
3962 | return reg_01.bits.version; | |
3963 | } | |
54168ed7 | 3964 | #endif |
1da177e4 | 3965 | |
a2f809b0 YL |
3966 | int io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq, |
3967 | int triggering, int polarity) | |
1da177e4 | 3968 | { |
0b8f1efa YL |
3969 | struct irq_desc *desc; |
3970 | struct irq_cfg *cfg; | |
024154cf | 3971 | int node; |
0b8f1efa | 3972 | |
1da177e4 | 3973 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3974 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3975 | ioapic); |
3976 | return -EINVAL; | |
3977 | } | |
3978 | ||
024154cf YL |
3979 | if (dev) |
3980 | node = dev_to_node(dev); | |
3981 | else | |
3982 | node = cpu_to_node(boot_cpu_id); | |
3983 | ||
85ac16d0 | 3984 | desc = irq_to_desc_alloc_node(irq, node); |
0b8f1efa YL |
3985 | if (!desc) { |
3986 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3987 | return 0; | |
3988 | } | |
3989 | ||
1da177e4 LT |
3990 | /* |
3991 | * IRQs < 16 are already in the irq_2_pin[] map | |
3992 | */ | |
99d093d1 | 3993 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3994 | cfg = desc->chip_data; |
85ac16d0 | 3995 | add_pin_to_irq_node(cfg, node, ioapic, pin); |
0b8f1efa | 3996 | } |
1da177e4 | 3997 | |
3145e941 | 3998 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3999 | |
4000 | return 0; | |
4001 | } | |
4002 | ||
54168ed7 | 4003 | |
61fd47e0 SL |
4004 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4005 | { | |
4006 | int i; | |
4007 | ||
4008 | if (skip_ioapic_setup) | |
4009 | return -1; | |
4010 | ||
4011 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4012 | if (mp_irqs[i].irqtype == mp_INT && |
4013 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4014 | break; |
4015 | if (i >= mp_irq_entries) | |
4016 | return -1; | |
4017 | ||
4018 | *trigger = irq_trigger(i); | |
4019 | *polarity = irq_polarity(i); | |
4020 | return 0; | |
4021 | } | |
4022 | ||
888ba6c6 | 4023 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4024 | |
497c9a19 YL |
4025 | /* |
4026 | * This function currently is only a helper for the i386 smp boot process where | |
4027 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4028 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4029 | */ |
4030 | #ifdef CONFIG_SMP | |
4031 | void __init setup_ioapic_dest(void) | |
4032 | { | |
4033 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4034 | struct irq_desc *desc; |
497c9a19 | 4035 | struct irq_cfg *cfg; |
22f65d31 | 4036 | const struct cpumask *mask; |
497c9a19 YL |
4037 | |
4038 | if (skip_ioapic_setup == 1) | |
4039 | return; | |
4040 | ||
4041 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4042 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4043 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4044 | if (irq_entry == -1) | |
4045 | continue; | |
4046 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4047 | ||
4048 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4049 | * when you have too many devices, because at that time only boot | |
4050 | * cpu is online. | |
4051 | */ | |
0b8f1efa YL |
4052 | desc = irq_to_desc(irq); |
4053 | cfg = desc->chip_data; | |
6c2e9403 | 4054 | if (!cfg->vector) { |
3145e941 | 4055 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4056 | irq_trigger(irq_entry), |
4057 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4058 | continue; |
4059 | ||
4060 | } | |
4061 | ||
4062 | /* | |
4063 | * Honour affinities which have been set in early boot | |
4064 | */ | |
6c2e9403 TG |
4065 | if (desc->status & |
4066 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4067 | mask = desc->affinity; |
6c2e9403 | 4068 | else |
fe402e1f | 4069 | mask = apic->target_cpus(); |
6c2e9403 | 4070 | |
6c2e9403 | 4071 | if (intr_remapping_enabled) |
3145e941 | 4072 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4073 | else |
3145e941 | 4074 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4075 | } |
4076 | ||
4077 | } | |
4078 | } | |
4079 | #endif | |
4080 | ||
54168ed7 IM |
4081 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4082 | ||
4083 | static struct resource *ioapic_resources; | |
4084 | ||
4085 | static struct resource * __init ioapic_setup_resources(void) | |
4086 | { | |
4087 | unsigned long n; | |
4088 | struct resource *res; | |
4089 | char *mem; | |
4090 | int i; | |
4091 | ||
4092 | if (nr_ioapics <= 0) | |
4093 | return NULL; | |
4094 | ||
4095 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4096 | n *= nr_ioapics; | |
4097 | ||
4098 | mem = alloc_bootmem(n); | |
4099 | res = (void *)mem; | |
4100 | ||
4101 | if (mem != NULL) { | |
4102 | mem += sizeof(struct resource) * nr_ioapics; | |
4103 | ||
4104 | for (i = 0; i < nr_ioapics; i++) { | |
4105 | res[i].name = mem; | |
4106 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4107 | sprintf(mem, "IOAPIC %u", i); | |
4108 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4109 | } | |
4110 | } | |
4111 | ||
4112 | ioapic_resources = res; | |
4113 | ||
4114 | return res; | |
4115 | } | |
54168ed7 | 4116 | |
f3294a33 YL |
4117 | void __init ioapic_init_mappings(void) |
4118 | { | |
4119 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4120 | struct resource *ioapic_res; |
d6c88a50 | 4121 | int i; |
f3294a33 | 4122 | |
54168ed7 | 4123 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4124 | for (i = 0; i < nr_ioapics; i++) { |
4125 | if (smp_found_config) { | |
b5ba7e6d | 4126 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4127 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4128 | if (!ioapic_phys) { |
4129 | printk(KERN_ERR | |
4130 | "WARNING: bogus zero IO-APIC " | |
4131 | "address found in MPTABLE, " | |
4132 | "disabling IO/APIC support!\n"); | |
4133 | smp_found_config = 0; | |
4134 | skip_ioapic_setup = 1; | |
4135 | goto fake_ioapic_page; | |
4136 | } | |
54168ed7 | 4137 | #endif |
f3294a33 | 4138 | } else { |
54168ed7 | 4139 | #ifdef CONFIG_X86_32 |
f3294a33 | 4140 | fake_ioapic_page: |
54168ed7 | 4141 | #endif |
f3294a33 | 4142 | ioapic_phys = (unsigned long) |
54168ed7 | 4143 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4144 | ioapic_phys = __pa(ioapic_phys); |
4145 | } | |
4146 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4147 | apic_printk(APIC_VERBOSE, |
4148 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4149 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4150 | idx++; |
54168ed7 | 4151 | |
54168ed7 IM |
4152 | if (ioapic_res != NULL) { |
4153 | ioapic_res->start = ioapic_phys; | |
4154 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4155 | ioapic_res++; | |
4156 | } | |
f3294a33 YL |
4157 | } |
4158 | } | |
4159 | ||
54168ed7 IM |
4160 | static int __init ioapic_insert_resources(void) |
4161 | { | |
4162 | int i; | |
4163 | struct resource *r = ioapic_resources; | |
4164 | ||
4165 | if (!r) { | |
04c93ce4 BZ |
4166 | if (nr_ioapics > 0) { |
4167 | printk(KERN_ERR | |
4168 | "IO APIC resources couldn't be allocated.\n"); | |
4169 | return -1; | |
4170 | } | |
4171 | return 0; | |
54168ed7 IM |
4172 | } |
4173 | ||
4174 | for (i = 0; i < nr_ioapics; i++) { | |
4175 | insert_resource(&iomem_resource, r); | |
4176 | r++; | |
4177 | } | |
4178 | ||
4179 | return 0; | |
4180 | } | |
4181 | ||
4182 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4183 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4184 | late_initcall(ioapic_insert_resources); |