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Commit | Line | Data |
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952cf6d7 JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV architectural definitions | |
7 | * | |
9f5314fb | 8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. |
952cf6d7 JS |
9 | */ |
10 | ||
05e4d316 PA |
11 | #ifndef _ASM_X86_UV_UV_HUB_H |
12 | #define _ASM_X86_UV_UV_HUB_H | |
952cf6d7 | 13 | |
bc5d9940 | 14 | #ifdef CONFIG_X86_64 |
952cf6d7 JS |
15 | #include <linux/numa.h> |
16 | #include <linux/percpu.h> | |
c08b6acc | 17 | #include <linux/timer.h> |
8dc579e8 | 18 | #include <linux/io.h> |
952cf6d7 JS |
19 | #include <asm/types.h> |
20 | #include <asm/percpu.h> | |
66666e50 | 21 | #include <asm/uv/uv_mmrs.h> |
952cf6d7 JS |
22 | |
23 | ||
24 | /* | |
25 | * Addressing Terminology | |
26 | * | |
9f5314fb JS |
27 | * M - The low M bits of a physical address represent the offset |
28 | * into the blade local memory. RAM memory on a blade is physically | |
29 | * contiguous (although various IO spaces may punch holes in | |
30 | * it).. | |
952cf6d7 | 31 | * |
9f5314fb JS |
32 | * N - Number of bits in the node portion of a socket physical |
33 | * address. | |
34 | * | |
35 | * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of | |
36 | * routers always have low bit of 1, C/MBricks have low bit | |
37 | * equal to 0. Most addressing macros that target UV hub chips | |
38 | * right shift the NASID by 1 to exclude the always-zero bit. | |
39 | * NASIDs contain up to 15 bits. | |
40 | * | |
41 | * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead | |
42 | * of nasids. | |
43 | * | |
44 | * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant | |
45 | * of the nasid for socket usage. | |
46 | * | |
47 | * | |
48 | * NumaLink Global Physical Address Format: | |
49 | * +--------------------------------+---------------------+ | |
50 | * |00..000| GNODE | NodeOffset | | |
51 | * +--------------------------------+---------------------+ | |
52 | * |<-------53 - M bits --->|<--------M bits -----> | |
53 | * | |
54 | * M - number of node offset bits (35 .. 40) | |
952cf6d7 JS |
55 | * |
56 | * | |
57 | * Memory/UV-HUB Processor Socket Address Format: | |
9f5314fb JS |
58 | * +----------------+---------------+---------------------+ |
59 | * |00..000000000000| PNODE | NodeOffset | | |
60 | * +----------------+---------------+---------------------+ | |
61 | * <--- N bits --->|<--------M bits -----> | |
952cf6d7 | 62 | * |
9f5314fb JS |
63 | * M - number of node offset bits (35 .. 40) |
64 | * N - number of PNODE bits (0 .. 10) | |
952cf6d7 JS |
65 | * |
66 | * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | |
67 | * The actual values are configuration dependent and are set at | |
9f5314fb JS |
68 | * boot time. M & N values are set by the hardware/BIOS at boot. |
69 | * | |
952cf6d7 JS |
70 | * |
71 | * APICID format | |
72 | * NOTE!!!!!! This is the current format of the APICID. However, code | |
73 | * should assume that this will change in the future. Use functions | |
74 | * in this file for all APICID bit manipulations and conversion. | |
75 | * | |
76 | * 1111110000000000 | |
77 | * 5432109876543210 | |
9f5314fb | 78 | * pppppppppplc0cch |
952cf6d7 JS |
79 | * sssssssssss |
80 | * | |
9f5314fb | 81 | * p = pnode bits |
952cf6d7 JS |
82 | * l = socket number on board |
83 | * c = core | |
84 | * h = hyperthread | |
9f5314fb | 85 | * s = bits that are in the SOCKET_ID CSR |
952cf6d7 JS |
86 | * |
87 | * Note: Processor only supports 12 bits in the APICID register. The ACPI | |
88 | * tables hold all 16 bits. Software needs to be aware of this. | |
89 | * | |
90 | * Unless otherwise specified, all references to APICID refer to | |
91 | * the FULL value contained in ACPI tables, not the subset in the | |
92 | * processor APICID register. | |
93 | */ | |
94 | ||
95 | ||
96 | /* | |
97 | * Maximum number of bricks in all partitions and in all coherency domains. | |
98 | * This is the total number of bricks accessible in the numalink fabric. It | |
99 | * includes all C & M bricks. Routers are NOT included. | |
100 | * | |
101 | * This value is also the value of the maximum number of non-router NASIDs | |
102 | * in the numalink fabric. | |
103 | * | |
9f5314fb | 104 | * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
952cf6d7 JS |
105 | */ |
106 | #define UV_MAX_NUMALINK_BLADES 16384 | |
107 | ||
108 | /* | |
109 | * Maximum number of C/Mbricks within a software SSI (hardware may support | |
110 | * more). | |
111 | */ | |
112 | #define UV_MAX_SSI_BLADES 256 | |
113 | ||
114 | /* | |
115 | * The largest possible NASID of a C or M brick (+ 2) | |
116 | */ | |
1d21e6e3 | 117 | #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) |
952cf6d7 | 118 | |
7f1baa06 MT |
119 | struct uv_scir_s { |
120 | struct timer_list timer; | |
121 | unsigned long offset; | |
122 | unsigned long last; | |
123 | unsigned long idle_on; | |
124 | unsigned long idle_off; | |
125 | unsigned char state; | |
126 | unsigned char enabled; | |
127 | }; | |
128 | ||
952cf6d7 JS |
129 | /* |
130 | * The following defines attributes of the HUB chip. These attributes are | |
131 | * frequently referenced and are kept in the per-cpu data areas of each cpu. | |
132 | * They are kept together in a struct to minimize cache misses. | |
133 | */ | |
134 | struct uv_hub_info_s { | |
69a72a0e MT |
135 | unsigned long global_mmr_base; |
136 | unsigned long gpa_mask; | |
c4ed3f04 | 137 | unsigned int gnode_extra; |
69a72a0e MT |
138 | unsigned long gnode_upper; |
139 | unsigned long lowmem_remap_top; | |
140 | unsigned long lowmem_remap_base; | |
141 | unsigned short pnode; | |
142 | unsigned short pnode_mask; | |
143 | unsigned short coherency_domain_number; | |
144 | unsigned short numa_blade_id; | |
145 | unsigned char blade_processor_id; | |
146 | unsigned char m_val; | |
147 | unsigned char n_val; | |
148 | struct uv_scir_s scir; | |
952cf6d7 | 149 | }; |
7f1baa06 | 150 | |
952cf6d7 JS |
151 | DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
152 | #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) | |
153 | #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) | |
154 | ||
155 | /* | |
156 | * Local & Global MMR space macros. | |
157 | * Note: macros are intended to be used ONLY by inline functions | |
158 | * in this file - not by other kernel code. | |
9f5314fb JS |
159 | * n - NASID (full 15-bit global nasid) |
160 | * g - GNODE (full 15-bit global nasid, right shifted 1) | |
161 | * p - PNODE (local part of nsids, right shifted 1) | |
952cf6d7 | 162 | */ |
9f5314fb | 163 | #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) |
c4ed3f04 JS |
164 | #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) |
165 | #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) | |
952cf6d7 JS |
166 | |
167 | #define UV_LOCAL_MMR_BASE 0xf4000000UL | |
168 | #define UV_GLOBAL_MMR32_BASE 0xf8000000UL | |
169 | #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) | |
83f5d894 JS |
170 | #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) |
171 | #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) | |
952cf6d7 | 172 | |
9f5314fb JS |
173 | #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
174 | #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 | |
952cf6d7 | 175 | |
9f5314fb | 176 | #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
952cf6d7 | 177 | |
9f5314fb | 178 | #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
67e83f30 | 179 | (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
9f5314fb JS |
180 | |
181 | #define UV_APIC_PNODE_SHIFT 6 | |
182 | ||
7f1baa06 MT |
183 | /* Local Bus from cpu's perspective */ |
184 | #define LOCAL_BUS_BASE 0x1c00000 | |
185 | #define LOCAL_BUS_SIZE (4 * 1024 * 1024) | |
186 | ||
187 | /* | |
188 | * System Controller Interface Reg | |
189 | * | |
190 | * Note there are NO leds on a UV system. This register is only | |
191 | * used by the system controller to monitor system-wide operation. | |
192 | * There are 64 regs per node. With Nahelem cpus (2 cores per node, | |
193 | * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on | |
194 | * a node. | |
195 | * | |
196 | * The window is located at top of ACPI MMR space | |
197 | */ | |
198 | #define SCIR_WINDOW_COUNT 64 | |
199 | #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ | |
200 | LOCAL_BUS_SIZE - \ | |
201 | SCIR_WINDOW_COUNT) | |
202 | ||
203 | #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ | |
204 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ | |
205 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ | |
206 | ||
8661984f DS |
207 | /* Loop through all installed blades */ |
208 | #define for_each_possible_blade(bid) \ | |
209 | for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) | |
210 | ||
9f5314fb JS |
211 | /* |
212 | * Macros for converting between kernel virtual addresses, socket local physical | |
213 | * addresses, and UV global physical addresses. | |
214 | * Note: use the standard __pa() & __va() macros for converting | |
215 | * between socket virtual and socket physical addresses. | |
216 | */ | |
217 | ||
218 | /* socket phys RAM --> UV global physical address */ | |
219 | static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) | |
220 | { | |
221 | if (paddr < uv_hub_info->lowmem_remap_top) | |
189f67c4 | 222 | paddr |= uv_hub_info->lowmem_remap_base; |
9f5314fb JS |
223 | return paddr | uv_hub_info->gnode_upper; |
224 | } | |
225 | ||
226 | ||
227 | /* socket virtual --> UV global physical address */ | |
228 | static inline unsigned long uv_gpa(void *v) | |
229 | { | |
189f67c4 | 230 | return uv_soc_phys_ram_to_gpa(__pa(v)); |
9f5314fb | 231 | } |
1d21e6e3 RH |
232 | |
233 | /* gnode -> pnode */ | |
234 | static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) | |
235 | { | |
236 | return gpa >> uv_hub_info->m_val; | |
237 | } | |
238 | ||
239 | /* gpa -> pnode */ | |
240 | static inline int uv_gpa_to_pnode(unsigned long gpa) | |
241 | { | |
242 | unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; | |
243 | ||
244 | return uv_gpa_to_gnode(gpa) & n_mask; | |
245 | } | |
9f5314fb JS |
246 | |
247 | /* pnode, offset --> socket virtual */ | |
248 | static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) | |
249 | { | |
250 | return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); | |
251 | } | |
952cf6d7 | 252 | |
952cf6d7 JS |
253 | |
254 | /* | |
9f5314fb | 255 | * Extract a PNODE from an APICID (full apicid, not processor subset) |
952cf6d7 | 256 | */ |
9f5314fb | 257 | static inline int uv_apicid_to_pnode(int apicid) |
952cf6d7 | 258 | { |
9f5314fb | 259 | return (apicid >> UV_APIC_PNODE_SHIFT); |
952cf6d7 JS |
260 | } |
261 | ||
262 | /* | |
263 | * Access global MMRs using the low memory MMR32 space. This region supports | |
264 | * faster MMR access but not all MMRs are accessible in this space. | |
265 | */ | |
9f5314fb | 266 | static inline unsigned long *uv_global_mmr32_address(int pnode, |
952cf6d7 JS |
267 | unsigned long offset) |
268 | { | |
269 | return __va(UV_GLOBAL_MMR32_BASE | | |
9f5314fb | 270 | UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
271 | } |
272 | ||
9f5314fb | 273 | static inline void uv_write_global_mmr32(int pnode, unsigned long offset, |
952cf6d7 JS |
274 | unsigned long val) |
275 | { | |
8dc579e8 | 276 | writeq(val, uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
277 | } |
278 | ||
9f5314fb | 279 | static inline unsigned long uv_read_global_mmr32(int pnode, |
952cf6d7 JS |
280 | unsigned long offset) |
281 | { | |
8dc579e8 | 282 | return readq(uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
283 | } |
284 | ||
285 | /* | |
286 | * Access Global MMR space using the MMR space located at the top of physical | |
287 | * memory. | |
288 | */ | |
9f5314fb | 289 | static inline unsigned long *uv_global_mmr64_address(int pnode, |
952cf6d7 JS |
290 | unsigned long offset) |
291 | { | |
292 | return __va(UV_GLOBAL_MMR64_BASE | | |
9f5314fb | 293 | UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
294 | } |
295 | ||
9f5314fb | 296 | static inline void uv_write_global_mmr64(int pnode, unsigned long offset, |
952cf6d7 JS |
297 | unsigned long val) |
298 | { | |
8dc579e8 | 299 | writeq(val, uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
300 | } |
301 | ||
9f5314fb | 302 | static inline unsigned long uv_read_global_mmr64(int pnode, |
952cf6d7 JS |
303 | unsigned long offset) |
304 | { | |
8dc579e8 | 305 | return readq(uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
306 | } |
307 | ||
308 | /* | |
9f5314fb | 309 | * Access hub local MMRs. Faster than using global space but only local MMRs |
952cf6d7 JS |
310 | * are accessible. |
311 | */ | |
312 | static inline unsigned long *uv_local_mmr_address(unsigned long offset) | |
313 | { | |
314 | return __va(UV_LOCAL_MMR_BASE | offset); | |
315 | } | |
316 | ||
317 | static inline unsigned long uv_read_local_mmr(unsigned long offset) | |
318 | { | |
8dc579e8 | 319 | return readq(uv_local_mmr_address(offset)); |
952cf6d7 JS |
320 | } |
321 | ||
322 | static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | |
323 | { | |
8dc579e8 | 324 | writeq(val, uv_local_mmr_address(offset)); |
952cf6d7 JS |
325 | } |
326 | ||
7f1baa06 MT |
327 | static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
328 | { | |
8dc579e8 | 329 | return readb(uv_local_mmr_address(offset)); |
7f1baa06 MT |
330 | } |
331 | ||
332 | static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) | |
333 | { | |
8dc579e8 | 334 | writeb(val, uv_local_mmr_address(offset)); |
7f1baa06 MT |
335 | } |
336 | ||
8400def8 | 337 | /* |
9f5314fb | 338 | * Structures and definitions for converting between cpu, node, pnode, and blade |
8400def8 JS |
339 | * numbers. |
340 | */ | |
341 | struct uv_blade_info { | |
9f5314fb | 342 | unsigned short nr_possible_cpus; |
8400def8 | 343 | unsigned short nr_online_cpus; |
9f5314fb | 344 | unsigned short pnode; |
6c7184b7 | 345 | short memory_nid; |
8400def8 | 346 | }; |
9f5314fb | 347 | extern struct uv_blade_info *uv_blade_info; |
8400def8 JS |
348 | extern short *uv_node_to_blade; |
349 | extern short *uv_cpu_to_blade; | |
350 | extern short uv_possible_blades; | |
351 | ||
352 | /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ | |
353 | static inline int uv_blade_processor_id(void) | |
354 | { | |
355 | return uv_hub_info->blade_processor_id; | |
356 | } | |
357 | ||
358 | /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ | |
359 | static inline int uv_numa_blade_id(void) | |
360 | { | |
361 | return uv_hub_info->numa_blade_id; | |
362 | } | |
363 | ||
364 | /* Convert a cpu number to the the UV blade number */ | |
365 | static inline int uv_cpu_to_blade_id(int cpu) | |
366 | { | |
367 | return uv_cpu_to_blade[cpu]; | |
368 | } | |
369 | ||
370 | /* Convert linux node number to the UV blade number */ | |
371 | static inline int uv_node_to_blade_id(int nid) | |
372 | { | |
373 | return uv_node_to_blade[nid]; | |
374 | } | |
375 | ||
9f5314fb JS |
376 | /* Convert a blade id to the PNODE of the blade */ |
377 | static inline int uv_blade_to_pnode(int bid) | |
8400def8 | 378 | { |
9f5314fb | 379 | return uv_blade_info[bid].pnode; |
8400def8 JS |
380 | } |
381 | ||
6c7184b7 JS |
382 | /* Nid of memory node on blade. -1 if no blade-local memory */ |
383 | static inline int uv_blade_to_memory_nid(int bid) | |
384 | { | |
385 | return uv_blade_info[bid].memory_nid; | |
386 | } | |
387 | ||
8400def8 JS |
388 | /* Determine the number of possible cpus on a blade */ |
389 | static inline int uv_blade_nr_possible_cpus(int bid) | |
390 | { | |
9f5314fb | 391 | return uv_blade_info[bid].nr_possible_cpus; |
8400def8 JS |
392 | } |
393 | ||
394 | /* Determine the number of online cpus on a blade */ | |
395 | static inline int uv_blade_nr_online_cpus(int bid) | |
396 | { | |
397 | return uv_blade_info[bid].nr_online_cpus; | |
398 | } | |
399 | ||
9f5314fb JS |
400 | /* Convert a cpu id to the PNODE of the blade containing the cpu */ |
401 | static inline int uv_cpu_to_pnode(int cpu) | |
8400def8 | 402 | { |
9f5314fb | 403 | return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; |
8400def8 JS |
404 | } |
405 | ||
9f5314fb JS |
406 | /* Convert a linux node number to the PNODE of the blade */ |
407 | static inline int uv_node_to_pnode(int nid) | |
8400def8 | 408 | { |
9f5314fb | 409 | return uv_blade_info[uv_node_to_blade_id(nid)].pnode; |
8400def8 JS |
410 | } |
411 | ||
412 | /* Maximum possible number of blades */ | |
413 | static inline int uv_num_possible_blades(void) | |
414 | { | |
415 | return uv_possible_blades; | |
416 | } | |
417 | ||
7f1baa06 MT |
418 | /* Update SCIR state */ |
419 | static inline void uv_set_scir_bits(unsigned char value) | |
420 | { | |
421 | if (uv_hub_info->scir.state != value) { | |
422 | uv_hub_info->scir.state = value; | |
423 | uv_write_local_mmr8(uv_hub_info->scir.offset, value); | |
424 | } | |
425 | } | |
66666e50 | 426 | |
7f1baa06 MT |
427 | static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) |
428 | { | |
429 | if (uv_cpu_hub_info(cpu)->scir.state != value) { | |
430 | uv_cpu_hub_info(cpu)->scir.state = value; | |
431 | uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); | |
432 | } | |
433 | } | |
952cf6d7 | 434 | |
66666e50 JS |
435 | static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) |
436 | { | |
437 | unsigned long val; | |
438 | ||
439 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
d2374aec | 440 | ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | |
66666e50 JS |
441 | (vector << UVH_IPI_INT_VECTOR_SHFT); |
442 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); | |
443 | } | |
444 | ||
bc5d9940 | 445 | #endif /* CONFIG_X86_64 */ |
7f1baa06 | 446 | #endif /* _ASM_X86_UV_UV_HUB_H */ |