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1965aae3 PA |
1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H | |
be7baf80 TG |
3 | |
4 | #include <asm/msr-index.h> | |
5 | ||
8f12dea6 | 6 | #ifndef __ASSEMBLY__ |
c210d249 | 7 | |
8fa62ad9 | 8 | #include <linux/types.h> |
ff55df53 PA |
9 | #include <linux/ioctl.h> |
10 | ||
11 | #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) | |
12 | #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) | |
13 | ||
14 | #ifdef __KERNEL__ | |
15 | ||
c210d249 GOC |
16 | #include <asm/asm.h> |
17 | #include <asm/errno.h> | |
6bc1096d BP |
18 | #include <asm/cpumask.h> |
19 | ||
20 | struct msr { | |
21 | union { | |
22 | struct { | |
23 | u32 l; | |
24 | u32 h; | |
25 | }; | |
26 | u64 q; | |
27 | }; | |
28 | }; | |
c210d249 | 29 | |
1e160cc3 | 30 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
8f12dea6 GOC |
31 | { |
32 | unsigned long low, high; | |
abb0ade0 JP |
33 | asm volatile(".byte 0x0f,0x01,0xf9" |
34 | : "=a" (low), "=d" (high), "=c" (*aux)); | |
41aefdcc | 35 | return low | ((u64)high << 32); |
8f12dea6 GOC |
36 | } |
37 | ||
c210d249 | 38 | /* |
d4f1b103 JS |
39 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
40 | * constraint has different meanings. For i386, "A" means exactly | |
41 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, | |
42 | * it means rax *or* rdx. | |
c210d249 GOC |
43 | */ |
44 | #ifdef CONFIG_X86_64 | |
45 | #define DECLARE_ARGS(val, low, high) unsigned low, high | |
abb0ade0 | 46 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
c210d249 GOC |
47 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
48 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) | |
49 | #else | |
50 | #define DECLARE_ARGS(val, low, high) unsigned long long val | |
51 | #define EAX_EDX_VAL(val, low, high) (val) | |
52 | #define EAX_EDX_ARGS(val, low, high) "A" (val) | |
53 | #define EAX_EDX_RET(val, low, high) "=A" (val) | |
8f12dea6 GOC |
54 | #endif |
55 | ||
be7baf80 TG |
56 | static inline unsigned long long native_read_msr(unsigned int msr) |
57 | { | |
c210d249 | 58 | DECLARE_ARGS(val, low, high); |
be7baf80 | 59 | |
c210d249 GOC |
60 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
61 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
62 | } |
63 | ||
64 | static inline unsigned long long native_read_msr_safe(unsigned int msr, | |
65 | int *err) | |
66 | { | |
c210d249 | 67 | DECLARE_ARGS(val, low, high); |
be7baf80 | 68 | |
08970fc4 | 69 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
70 | "1:\n\t" |
71 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 72 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 73 | ".previous\n\t" |
abb0ade0 | 74 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 75 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
0cc0213e | 76 | : "c" (msr), [fault] "i" (-EIO)); |
c210d249 | 77 | return EAX_EDX_VAL(val, low, high); |
be7baf80 TG |
78 | } |
79 | ||
c9dcda5c GOC |
80 | static inline void native_write_msr(unsigned int msr, |
81 | unsigned low, unsigned high) | |
be7baf80 | 82 | { |
af2b1c60 | 83 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
be7baf80 TG |
84 | } |
85 | ||
0ca59dd9 FW |
86 | /* Can be uninlined because referenced by paravirt */ |
87 | notrace static inline int native_write_msr_safe(unsigned int msr, | |
c9dcda5c | 88 | unsigned low, unsigned high) |
be7baf80 TG |
89 | { |
90 | int err; | |
08970fc4 | 91 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
92 | "1:\n\t" |
93 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 94 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 95 | ".previous\n\t" |
abb0ade0 | 96 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 97 | : [err] "=a" (err) |
c9dcda5c | 98 | : "c" (msr), "0" (low), "d" (high), |
0cc0213e | 99 | [fault] "i" (-EIO) |
af2b1c60 | 100 | : "memory"); |
be7baf80 TG |
101 | return err; |
102 | } | |
103 | ||
cdc7957d | 104 | extern unsigned long long native_read_tsc(void); |
be7baf80 | 105 | |
8b956bf1 PA |
106 | extern int native_rdmsr_safe_regs(u32 regs[8]); |
107 | extern int native_wrmsr_safe_regs(u32 regs[8]); | |
132ec92f | 108 | |
92767af0 IM |
109 | static __always_inline unsigned long long __native_read_tsc(void) |
110 | { | |
111 | DECLARE_ARGS(val, low, high); | |
112 | ||
92767af0 | 113 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
92767af0 IM |
114 | |
115 | return EAX_EDX_VAL(val, low, high); | |
116 | } | |
117 | ||
b8d1fae7 | 118 | static inline unsigned long long native_read_pmc(int counter) |
be7baf80 | 119 | { |
c210d249 GOC |
120 | DECLARE_ARGS(val, low, high); |
121 | ||
122 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); | |
123 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
124 | } |
125 | ||
126 | #ifdef CONFIG_PARAVIRT | |
127 | #include <asm/paravirt.h> | |
96a388de | 128 | #else |
be7baf80 TG |
129 | #include <linux/errno.h> |
130 | /* | |
131 | * Access to machine-specific registers (available on 586 and better only) | |
132 | * Note: the rd* operations modify the parameters directly (without using | |
133 | * pointer indirection), this allows gcc to optimize better | |
134 | */ | |
135 | ||
abb0ade0 JP |
136 | #define rdmsr(msr, val1, val2) \ |
137 | do { \ | |
138 | u64 __val = native_read_msr((msr)); \ | |
139 | (val1) = (u32)__val; \ | |
140 | (val2) = (u32)(__val >> 32); \ | |
141 | } while (0) | |
be7baf80 | 142 | |
c9dcda5c | 143 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 144 | { |
c9dcda5c | 145 | native_write_msr(msr, low, high); |
be7baf80 TG |
146 | } |
147 | ||
abb0ade0 JP |
148 | #define rdmsrl(msr, val) \ |
149 | ((val) = native_read_msr((msr))) | |
be7baf80 | 150 | |
c210d249 | 151 | #define wrmsrl(msr, val) \ |
abb0ade0 | 152 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
be7baf80 TG |
153 | |
154 | /* wrmsr with exception handling */ | |
c9dcda5c | 155 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 156 | { |
c9dcda5c | 157 | return native_write_msr_safe(msr, low, high); |
be7baf80 TG |
158 | } |
159 | ||
160 | /* rdmsr with exception handling */ | |
abb0ade0 JP |
161 | #define rdmsr_safe(msr, p1, p2) \ |
162 | ({ \ | |
163 | int __err; \ | |
164 | u64 __val = native_read_msr_safe((msr), &__err); \ | |
165 | (*p1) = (u32)__val; \ | |
166 | (*p2) = (u32)(__val >> 32); \ | |
167 | __err; \ | |
168 | }) | |
be7baf80 | 169 | |
1de87bd4 AK |
170 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
171 | { | |
172 | int err; | |
173 | ||
174 | *p = native_read_msr_safe(msr, &err); | |
175 | return err; | |
176 | } | |
177fed1e | 177 | |
b05f78f5 YL |
178 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
179 | { | |
177fed1e | 180 | u32 gprs[8] = { 0 }; |
b05f78f5 YL |
181 | int err; |
182 | ||
177fed1e BP |
183 | gprs[1] = msr; |
184 | gprs[7] = 0x9c5a203a; | |
185 | ||
186 | err = native_rdmsr_safe_regs(gprs); | |
187 | ||
188 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
189 | ||
b05f78f5 YL |
190 | return err; |
191 | } | |
1de87bd4 | 192 | |
177fed1e BP |
193 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) |
194 | { | |
195 | u32 gprs[8] = { 0 }; | |
196 | ||
197 | gprs[0] = (u32)val; | |
198 | gprs[1] = msr; | |
199 | gprs[2] = val >> 32; | |
200 | gprs[7] = 0x9c5a203a; | |
201 | ||
202 | return native_wrmsr_safe_regs(gprs); | |
203 | } | |
204 | ||
8b956bf1 | 205 | static inline int rdmsr_safe_regs(u32 regs[8]) |
132ec92f BP |
206 | { |
207 | return native_rdmsr_safe_regs(regs); | |
208 | } | |
209 | ||
8b956bf1 | 210 | static inline int wrmsr_safe_regs(u32 regs[8]) |
132ec92f BP |
211 | { |
212 | return native_wrmsr_safe_regs(regs); | |
213 | } | |
214 | ||
be7baf80 | 215 | #define rdtscl(low) \ |
205516c1 | 216 | ((low) = (u32)__native_read_tsc()) |
be7baf80 TG |
217 | |
218 | #define rdtscll(val) \ | |
205516c1 | 219 | ((val) = __native_read_tsc()) |
be7baf80 | 220 | |
abb0ade0 JP |
221 | #define rdpmc(counter, low, high) \ |
222 | do { \ | |
223 | u64 _l = native_read_pmc((counter)); \ | |
224 | (low) = (u32)_l; \ | |
225 | (high) = (u32)(_l >> 32); \ | |
226 | } while (0) | |
be7baf80 | 227 | |
abb0ade0 JP |
228 | #define rdtscp(low, high, aux) \ |
229 | do { \ | |
230 | unsigned long long _val = native_read_tscp(&(aux)); \ | |
231 | (low) = (u32)_val; \ | |
232 | (high) = (u32)(_val >> 32); \ | |
233 | } while (0) | |
be7baf80 | 234 | |
c210d249 | 235 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
be7baf80 | 236 | |
c210d249 | 237 | #endif /* !CONFIG_PARAVIRT */ |
be7baf80 | 238 | |
be7baf80 | 239 | |
abb0ade0 JP |
240 | #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ |
241 | (u32)((val) >> 32)) | |
be7baf80 | 242 | |
abb0ade0 | 243 | #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) |
be7baf80 | 244 | |
abb0ade0 | 245 | #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) |
be7baf80 | 246 | |
be7baf80 | 247 | #ifdef CONFIG_SMP |
c6f31932 PA |
248 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
249 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
b8a47541 BP |
250 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
251 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); | |
be7baf80 TG |
252 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
253 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
8b956bf1 PA |
254 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
255 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); | |
be7baf80 | 256 | #else /* CONFIG_SMP */ |
c6f31932 | 257 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
be7baf80 TG |
258 | { |
259 | rdmsr(msr_no, *l, *h); | |
c6f31932 | 260 | return 0; |
be7baf80 | 261 | } |
c6f31932 | 262 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
be7baf80 TG |
263 | { |
264 | wrmsr(msr_no, l, h); | |
c6f31932 | 265 | return 0; |
be7baf80 | 266 | } |
0d0fbbdd | 267 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
268 | struct msr *msrs) |
269 | { | |
270 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); | |
271 | } | |
0d0fbbdd | 272 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
273 | struct msr *msrs) |
274 | { | |
275 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); | |
276 | } | |
abb0ade0 JP |
277 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
278 | u32 *l, u32 *h) | |
be7baf80 TG |
279 | { |
280 | return rdmsr_safe(msr_no, l, h); | |
281 | } | |
282 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |
283 | { | |
284 | return wrmsr_safe(msr_no, l, h); | |
285 | } | |
8b956bf1 PA |
286 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
287 | { | |
288 | return rdmsr_safe_regs(regs); | |
289 | } | |
290 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) | |
291 | { | |
292 | return wrmsr_safe_regs(regs); | |
293 | } | |
be7baf80 | 294 | #endif /* CONFIG_SMP */ |
c210d249 | 295 | #endif /* __KERNEL__ */ |
ff55df53 | 296 | #endif /* __ASSEMBLY__ */ |
1965aae3 | 297 | #endif /* _ASM_X86_MSR_H */ |