[net-next-2.6.git] / arch / x86 / include / asm / io_apic.h

#ifndef _ASM_X86_IO_APIC_H
#define _ASM_X86_IO_APIC_H

#include <linux/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>
#include <asm/irq_vectors.h>

/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

/* I/O Unit Redirection Table */
#define IO_APIC_REDIR_VECTOR_MASK	0x000FF
#define IO_APIC_REDIR_DEST_LOGICAL	0x00800
#define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
#define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
#define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
#define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
#define IO_APIC_REDIR_MASKED		(1 << 16)

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
			__reserved_2	:  7,
			PRQ		:  1,
			entries		:  8,
			__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
			arbitration	:  4,
			__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

enum ioapic_irq_destination_types {
	dest_Fixed = 0,
	dest_LowestPrio = 1,
	dest_SMI = 2,
	dest__reserved_1 = 3,
	dest_NMI = 4,
	dest_INIT = 5,
	dest__reserved_2 = 6,
	dest_ExtINT = 7
};

struct IO_APIC_route_entry {
	__u32	vector		:  8,
		delivery_mode	:  3,	/* 000: FIXED
					 * 001: lowest prio
					 * 111: ExtINT
					 */
		dest_mode	:  1,	/* 0: physical, 1: logical */
		delivery_status	:  1,
		polarity	:  1,
		irr		:  1,
		trigger		:  1,	/* 0: edge, 1: level */
		mask		:  1,	/* 0: enabled, 1: disabled */
		__reserved_2	: 15;

	__u32	__reserved_3	: 24,
		dest		:  8;
} __attribute__ ((packed));

struct IR_IO_APIC_route_entry {
	__u64	vector		: 8,
		zero		: 3,
		index2		: 1,
		delivery_status : 1,
		polarity	: 1,
		irr		: 1,
		trigger		: 1,
		mask		: 1,
		reserved	: 31,
		format		: 1,
		index		: 15;
} __attribute__ ((packed));

#ifdef CONFIG_X86_IO_APIC

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;
extern int nr_ioapic_registers[MAX_IO_APICS];

#define MP_MAX_IOAPIC_PIN 127

/* I/O APIC entries */
extern struct mpc_ioapic mp_ioapics[MAX_IO_APICS];

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* non-0 if default (table-less) MP configuration */
extern int mpc_default_type;

/* Older SiS APIC requires we rewrite the index register */
extern int sis_apic_bug;

/* 1 if "noapic" boot option passed */
extern int skip_ioapic_setup;

/* 1 if "noapic" boot option passed */
extern int noioapicquirk;

/* -1 if "noapic" boot option passed */
extern int noioapicreroute;

/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
extern int timer_through_8259;

/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs \
	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)

extern u8 io_apic_unique_id(u8 id);
extern int io_apic_get_unique_id(int ioapic, int apic_id);
extern int io_apic_get_version(int ioapic);
extern int io_apic_get_redir_entries(int ioapic);

struct io_apic_irq_attr;
extern int io_apic_set_pci_routing(struct device *dev, int irq,
		 struct io_apic_irq_attr *irq_attr);
void setup_IO_APIC_irq_extra(u32 gsi);
extern void ioapic_init_mappings(void);
extern void ioapic_insert_resources(void);

extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);

extern void probe_nr_irqs_gsi(void);

extern int setup_ioapic_entry(int apic, int irq,
			      struct IO_APIC_route_entry *entry,
			      unsigned int destination, int trigger,
			      int polarity, int vector, int pin);
extern void ioapic_write_entry(int apic, int pin,
			       struct IO_APIC_route_entry e);
extern void setup_ioapic_ids_from_mpc(void);

struct mp_ioapic_gsi{
	u32 gsi_base;
	u32 gsi_end;
};
extern struct mp_ioapic_gsi  mp_gsi_routing[];
extern u32 gsi_top;
int mp_find_ioapic(u32 gsi);
int mp_find_ioapic_pin(int ioapic, u32 gsi);
void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
extern void __init pre_init_apic_IRQ0(void);

#else  /* !CONFIG_X86_IO_APIC */

#define io_apic_assign_pci_irqs 0
#define setup_ioapic_ids_from_mpc x86_init_noop
static const int timer_through_8259 = 0;
static inline void ioapic_init_mappings(void)	{ }
static inline void ioapic_insert_resources(void) { }
static inline void probe_nr_irqs_gsi(void)	{ }
#define gsi_top (NR_IRQS_LEGACY)
static inline int mp_find_ioapic(u32 gsi) { return 0; }

struct io_apic_irq_attr;
static inline int io_apic_set_pci_routing(struct device *dev, int irq,
		 struct io_apic_irq_attr *irq_attr) { return 0; }
#endif

#endif /* _ASM_X86_IO_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_IO_APIC_H
1965aae3 PA	2	#define _ASM_X86_IO_APIC_H
e1d91978	3
a1a33fa3	4	#include <linux/types.h>
e1d91978 TG	5	#include <asm/mpspec.h>
e1d91978 TG	6	#include <asm/apicdef.h>
9d6a4d08	7	#include <asm/irq_vectors.h>
e1d91978 TG	8
	9	/*
	10	* Intel IO-APIC support for SMP and UP systems.
	11	*
	12	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	13	*/
	14
d3f020d2 CG	15	/* I/O Unit Redirection Table */
	16	#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
	17	#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
	18	#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
	19	#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
	20	#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
	21	#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
	22	#define IO_APIC_REDIR_MASKED (1 << 16)
	23
e1d91978 TG	24	/*
	25	* The structure of the IO-APIC:
	26	*/
	27	union IO_APIC_reg_00 {
	28	u32 raw;
	29	struct {
	30	u32 __reserved_2 : 14,
	31	LTS : 1,
	32	delivery_type : 1,
	33	__reserved_1 : 8,
	34	ID : 8;
	35	} __attribute__ ((packed)) bits;
	36	};
	37
	38	union IO_APIC_reg_01 {
	39	u32 raw;
	40	struct {
	41	u32 version : 8,
	42	__reserved_2 : 7,
	43	PRQ : 1,
	44	entries : 8,
	45	__reserved_1 : 8;
	46	} __attribute__ ((packed)) bits;
	47	};
	48
	49	union IO_APIC_reg_02 {
	50	u32 raw;
	51	struct {
	52	u32 __reserved_2 : 24,
	53	arbitration : 4,
	54	__reserved_1 : 4;
	55	} __attribute__ ((packed)) bits;
	56	};
	57
	58	union IO_APIC_reg_03 {
	59	u32 raw;
	60	struct {
	61	u32 boot_DT : 1,
	62	__reserved_1 : 31;
	63	} __attribute__ ((packed)) bits;
	64	};
	65
	66	enum ioapic_irq_destination_types {
	67	dest_Fixed = 0,
	68	dest_LowestPrio = 1,
	69	dest_SMI = 2,
	70	dest__reserved_1 = 3,
	71	dest_NMI = 4,
	72	dest_INIT = 5,
	73	dest__reserved_2 = 6,
	74	dest_ExtINT = 7
	75	};
	76
	77	struct IO_APIC_route_entry {
	78	__u32 vector : 8,
	79	delivery_mode : 3, /* 000: FIXED
	80	* 001: lowest prio
	81	* 111: ExtINT
	82	*/
	83	dest_mode : 1, /* 0: physical, 1: logical */
	84	delivery_status : 1,
	85	polarity : 1,
	86	irr : 1,
	87	trigger : 1, /* 0: edge, 1: level */
88	mask : 1, /* 0: enabled, 1: disabled */
89	__reserved_2 : 15;
90
e1d91978 TG	91	__u32 __reserved_3 : 24,
e1d91978 TG	92	dest : 8;
e1d91978	93	} __attribute__ ((packed));
e1d91978	94
89027d35 SS	95	struct IR_IO_APIC_route_entry {
	96	__u64 vector : 8,
	97	zero : 3,
	98	index2 : 1,
	99	delivery_status : 1,
	100	polarity : 1,
	101	irr : 1,
	102	trigger : 1,
	103	mask : 1,
	104	reserved : 31,
	105	format : 1,
	106	index : 15;
e1d91978 TG	107	} __attribute__ ((packed));
	108
	109	#ifdef CONFIG_X86_IO_APIC
	110
	111	/*
	112	* # of IO-APICs and # of IRQ routing registers
	113	*/
	114	extern int nr_ioapics;
	115	extern int nr_ioapic_registers[MAX_IO_APICS];
	116
a1a33fa3 AM	117	#define MP_MAX_IOAPIC_PIN 127
a1a33fa3 AM	118
e1d91978	119	/* I/O APIC entries */
b5ba7e6d	120	extern struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
e1d91978 TG	121
	122	/* # of MP IRQ source entries */
	123	extern int mp_irq_entries;
	124
	125	/* MP IRQ source entries */
c2c21745	126	extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
e1d91978 TG	127
	128	/* non-0 if default (table-less) MP configuration */
	129	extern int mpc_default_type;
	130
	131	/* Older SiS APIC requires we rewrite the index register */
	132	extern int sis_apic_bug;
	133
	134	/* 1 if "noapic" boot option passed */
	135	extern int skip_ioapic_setup;
	136
a9322f64 SA	137	/* 1 if "noapic" boot option passed */
	138	extern int noioapicquirk;
	139
9197979b SA	140	/* -1 if "noapic" boot option passed */
	141	extern int noioapicreroute;
	142
35542c5e MR	143	/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
	144	extern int timer_through_8259;
	145
e1d91978 TG	146	/*
	147	* If we use the IO-APIC for IRQ routing, disable automatic
	148	* assignment of PCI IRQ's.
	149	*/
	150	#define io_apic_assign_pci_irqs \
	151	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
	152
2a4ab640	153	extern u8 io_apic_unique_id(u8 id);
e1d91978 TG	154	extern int io_apic_get_unique_id(int ioapic, int apic_id);
	155	extern int io_apic_get_version(int ioapic);
	156	extern int io_apic_get_redir_entries(int ioapic);
e1d91978	157
e5198075 YL	158	struct io_apic_irq_attr;
	159	extern int io_apic_set_pci_routing(struct device *dev, int irq,
	160	struct io_apic_irq_attr *irq_attr);
18dce6ba	161	void setup_IO_APIC_irq_extra(u32 gsi);
e1d91978	162	extern void ioapic_init_mappings(void);
857fdc53	163	extern void ioapic_insert_resources(void);
e1d91978	164
b24696bc FY	165	extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
	166	extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
	167	extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
	168	extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
	169	extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
4dc2f96c	170
be5d5350	171	extern void probe_nr_irqs_gsi(void);
9d6a4d08	172
ca97ab90 JF	173	extern int setup_ioapic_entry(int apic, int irq,
	174	struct IO_APIC_route_entry *entry,
	175	unsigned int destination, int trigger,
0280f7c4	176	int polarity, int vector, int pin);
ca97ab90 JF	177	extern void ioapic_write_entry(int apic, int pin,
ca97ab90 JF	178	struct IO_APIC_route_entry e);
de934103	179	extern void setup_ioapic_ids_from_mpc(void);
2a4ab640 FT	180
2a4ab640 FT	181	struct mp_ioapic_gsi{
eddb0c55 EB	182	u32 gsi_base;
eddb0c55 EB	183	u32 gsi_end;
2a4ab640 FT	184	};
2a4ab640 FT	185	extern struct mp_ioapic_gsi mp_gsi_routing[];
a4384df3	186	extern u32 gsi_top;
eddb0c55 EB	187	int mp_find_ioapic(u32 gsi);
eddb0c55 EB	188	int mp_find_ioapic_pin(int ioapic, u32 gsi);
2a4ab640	189	void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
05ddafb1	190	extern void __init pre_init_apic_IRQ0(void);
2a4ab640	191
e1d91978	192	#else /* !CONFIG_X86_IO_APIC */
78f28b7c	193
e1d91978	194	#define io_apic_assign_pci_irqs 0
de934103	195	#define setup_ioapic_ids_from_mpc x86_init_noop
35542c5e	196	static const int timer_through_8259 = 0;
50dd94e0	197	static inline void ioapic_init_mappings(void) { }
857fdc53	198	static inline void ioapic_insert_resources(void) { }
50dd94e0	199	static inline void probe_nr_irqs_gsi(void) { }
a4384df3	200	#define gsi_top (NR_IRQS_LEGACY)
eddb0c55	201	static inline int mp_find_ioapic(u32 gsi) { return 0; }
78f28b7c	202
4966e1af JP	203	struct io_apic_irq_attr;
	204	static inline int io_apic_set_pci_routing(struct device *dev, int irq,
	205	struct io_apic_irq_attr *irq_attr) { return 0; }
96a388de	206	#endif
e1d91978	207
1965aae3	208	#endif /* _ASM_X86_IO_APIC_H */