[net-next-2.6.git] / arch / x86 / include / asm / cpufeature.h

/*
 * Defines x86 CPU feature bits
 */
#ifndef _ASM_X86_CPUFEATURE_H
#define _ASM_X86_CPUFEATURE_H

#include <asm/required-features.h>

#define NCAPINTS	10	/* N 32-bit words worth of info */

/*
 * Note: If the comment begins with a quoted string, that string is used
 * in /proc/cpuinfo instead of the macro name.  If the string is "",
 * this feature bit is not displayed in /proc/cpuinfo at all.
 */

/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
#define X86_FEATURE_FPU		(0*32+ 0) /* Onboard FPU */
#define X86_FEATURE_VME		(0*32+ 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE		(0*32+ 2) /* Debugging Extensions */
#define X86_FEATURE_PSE		(0*32+ 3) /* Page Size Extensions */
#define X86_FEATURE_TSC		(0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR		(0*32+ 5) /* Model-Specific Registers */
#define X86_FEATURE_PAE		(0*32+ 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Exception */
#define X86_FEATURE_CX8		(0*32+ 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC	(0*32+ 9) /* Onboard APIC */
#define X86_FEATURE_SEP		(0*32+11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR	(0*32+12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE		(0*32+13) /* Page Global Enable */
#define X86_FEATURE_MCA		(0*32+14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV	(0*32+15) /* CMOV instructions */
					  /* (plus FCMOVcc, FCOMI with FPU) */
#define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */
#define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN		(0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLSH	(0*32+19) /* "clflush" CLFLUSH instruction */
#define X86_FEATURE_DS		(0*32+21) /* "dts" Debug Store */
#define X86_FEATURE_ACPI	(0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR	(0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
#define X86_FEATURE_XMM		(0*32+25) /* "sse" */
#define X86_FEATURE_XMM2	(0*32+26) /* "sse2" */
#define X86_FEATURE_SELFSNOOP	(0*32+27) /* "ss" CPU self snoop */
#define X86_FEATURE_HT		(0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC		(0*32+29) /* "tm" Automatic clock control */
#define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */
#define X86_FEATURE_PBE		(0*32+31) /* Pending Break Enable */

/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
#define X86_FEATURE_SYSCALL	(1*32+11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP		(1*32+19) /* MP Capable. */
#define X86_FEATURE_NX		(1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
#define X86_FEATURE_FXSR_OPT	(1*32+25) /* FXSAVE/FXRSTOR optimizations */
#define X86_FEATURE_GBPAGES	(1*32+26) /* "pdpe1gb" GB pages */
#define X86_FEATURE_RDTSCP	(1*32+27) /* RDTSCP */
#define X86_FEATURE_LM		(1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT	(1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW	(1*32+31) /* 3DNow! */

/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
#define X86_FEATURE_RECOVERY	(2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN	(2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI	(2*32+ 3) /* LongRun table interface */

/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
#define X86_FEATURE_CXMMX	(3*32+ 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR	(3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR	(3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR	(3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* cpu types for specific tunings: */
#define X86_FEATURE_K8		(3*32+ 4) /* "" Opteron, Athlon64 */
#define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
#define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
#define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS	(3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS		(3*32+13) /* Branch Trace Store */
#define X86_FEATURE_SYSCALL32	(3*32+14) /* "" syscall in ia32 userspace */
#define X86_FEATURE_SYSENTER32	(3*32+15) /* "" sysenter in ia32 userspace */
#define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */
#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
					  /* 21 available, was AMD_C1E */
#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
#define X86_FEATURE_EXTD_APICID	(3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF	(3*32+28) /* APERFMPERF */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* PCLMULQDQ instruction */
#define X86_FEATURE_DTES64	(4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT	(4*32+ 3) /* "monitor" Monitor/Mwait support */
#define X86_FEATURE_DSCPL	(4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
#define X86_FEATURE_VMX		(4*32+ 5) /* Hardware virtualization */
#define X86_FEATURE_SMX		(4*32+ 6) /* Safer mode */
#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3	(4*32+ 9) /* Supplemental SSE-3 */
#define X86_FEATURE_CID		(4*32+10) /* Context ID */
#define X86_FEATURE_FMA		(4*32+12) /* Fused multiply-add */
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM	(4*32+15) /* Performance Capabilities */
#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */
#define X86_FEATURE_XMM4_1	(4*32+19) /* "sse4_1" SSE-4.1 */
#define X86_FEATURE_XMM4_2	(4*32+20) /* "sse4_2" SSE-4.2 */
#define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */
#define X86_FEATURE_MOVBE	(4*32+22) /* MOVBE instruction */
#define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
#define X86_FEATURE_AES		(4*32+25) /* AES instructions */
#define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
#define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */
#define X86_FEATURE_RDRND	(4*32+30) /* The RDRAND instruction */
#define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE	(5*32+ 2) /* "rng" RNG present (xstore) */
#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* "rng_en" RNG enabled */
#define X86_FEATURE_XCRYPT	(5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* "ace_en" on-CPU crypto enabled */
#define X86_FEATURE_ACE2	(5*32+ 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN	(5*32+ 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE		(5*32+10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN	(5*32+11) /* PHE enabled */
#define X86_FEATURE_PMM		(5*32+12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN	(5*32+13) /* PMM enabled */

/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVM		(6*32+ 2) /* Secure virtual machine */
#define X86_FEATURE_EXTAPIC	(6*32+ 3) /* Extended APIC space */
#define X86_FEATURE_CR8_LEGACY	(6*32+ 4) /* CR8 in 32-bit mode */
#define X86_FEATURE_ABM		(6*32+ 5) /* Advanced bit manipulation */
#define X86_FEATURE_SSE4A	(6*32+ 6) /* SSE-4A */
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
#define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */
#define X86_FEATURE_SSE5	(6*32+11) /* SSE-5 */
#define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */
#define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */
#define X86_FEATURE_NODEID_MSR	(6*32+19) /* NodeId MSR */

/*
 * Auxiliary flags: Linux defined - For features scattered in various
 * CPUID levels like 0x6, 0xA etc, word 7
 */
#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
#define X86_FEATURE_CPB		(7*32+ 2) /* AMD Core Performance Boost */
#define X86_FEATURE_EPB		(7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
#define X86_FEATURE_XSAVEOPT	(7*32+ 4) /* Optimized Xsave */
#define X86_FEATURE_PLN		(7*32+ 5) /* Intel Power Limit Notification */
#define X86_FEATURE_PTS		(7*32+ 6) /* Intel Package Thermal Status */
#define X86_FEATURE_DTS		(7*32+ 7) /* Digital Thermal Sensor */

/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
#define X86_FEATURE_NPT		(8*32+ 5) /* AMD Nested Page Table support */
#define X86_FEATURE_LBRV	(8*32+ 6) /* AMD LBR Virtualization support */
#define X86_FEATURE_SVML	(8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
#define X86_FEATURE_NRIPS	(8*32+ 8) /* "nrip_save" AMD SVM next_rip save */

/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
#define X86_FEATURE_FSGSBASE	(9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#include <asm/asm.h>
#include <linux/bitops.h>

extern const char * const x86_cap_flags[NCAPINTS*32];
extern const char * const x86_power_flags[32];

#define test_cpu_cap(c, bit)						\
	 test_bit(bit, (unsigned long *)((c)->x86_capability))

#define cpu_has(c, bit)							\
	(__builtin_constant_p(bit) &&					\
	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||	\
	   (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||	\
	   (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )	\
	  ? 1 :								\
	 test_cpu_cap(c, bit))

#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)

#define set_cpu_cap(c, bit)	set_bit(bit, (unsigned long *)((c)->x86_capability))
#define clear_cpu_cap(c, bit)	clear_bit(bit, (unsigned long *)((c)->x86_capability))
#define setup_clear_cpu_cap(bit) do { \
	clear_cpu_cap(&boot_cpu_data, bit);	\
	set_bit(bit, (unsigned long *)cpu_caps_cleared); \
} while (0)
#define setup_force_cpu_cap(bit) do { \
	set_cpu_cap(&boot_cpu_data, bit);	\
	set_bit(bit, (unsigned long *)cpu_caps_set);	\
} while (0)

#define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)
#define cpu_has_vme		boot_cpu_has(X86_FEATURE_VME)
#define cpu_has_de		boot_cpu_has(X86_FEATURE_DE)
#define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)
#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
#define cpu_has_pae		boot_cpu_has(X86_FEATURE_PAE)
#define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
#define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
#define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
#define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)
#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)
#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
#define cpu_has_centaur_mcr	boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
#define cpu_has_xstore		boot_cpu_has(X86_FEATURE_XSTORE)
#define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)
#define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)
#define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)
#define cpu_has_ace2		boot_cpu_has(X86_FEATURE_ACE2)
#define cpu_has_ace2_enabled	boot_cpu_has(X86_FEATURE_ACE2_EN)
#define cpu_has_phe		boot_cpu_has(X86_FEATURE_PHE)
#define cpu_has_phe_enabled	boot_cpu_has(X86_FEATURE_PHE_EN)
#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)
#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)
#define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)
#define cpu_has_pebs		boot_cpu_has(X86_FEATURE_PEBS)
#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
#define cpu_has_bts		boot_cpu_has(X86_FEATURE_BTS)
#define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)
#define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
#define cpu_has_xmm4_1		boot_cpu_has(X86_FEATURE_XMM4_1)
#define cpu_has_xmm4_2		boot_cpu_has(X86_FEATURE_XMM4_2)
#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
#define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)

#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
# define cpu_has_invlpg		1
#else
# define cpu_has_invlpg		(boot_cpu_data.x86 > 3)
#endif

#ifdef CONFIG_X86_64

#undef  cpu_has_vme
#define cpu_has_vme		0

#undef  cpu_has_pae
#define cpu_has_pae		___BUG___

#undef  cpu_has_mp
#define cpu_has_mp		1

#undef  cpu_has_k6_mtrr
#define cpu_has_k6_mtrr		0

#undef  cpu_has_cyrix_arr
#define cpu_has_cyrix_arr	0

#undef  cpu_has_centaur_mcr
#define cpu_has_centaur_mcr	0

#endif /* CONFIG_X86_64 */

#if __GNUC__ >= 4
/*
 * Static testing of CPU features.  Used the same as boot_cpu_has().
 * These are only valid after alternatives have run, but will statically
 * patch the target code for additional performance.
 *
 */
static __always_inline __pure bool __static_cpu_has(u16 bit)
{
#if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
		asm goto("1: jmp %l[t_no]\n"
			 "2:\n"
			 ".section .altinstructions,\"a\"\n"
			 _ASM_ALIGN "\n"
			 _ASM_PTR "1b\n"
			 _ASM_PTR "0\n" 	/* no replacement */
			 " .word %P0\n"		/* feature bit */
			 " .byte 2b - 1b\n"	/* source len */
			 " .byte 0\n"		/* replacement len */
			 ".previous\n"
			 /* skipping size check since replacement size = 0 */
			 : : "i" (bit) : : t_no);
		return true;
	t_no:
		return false;
#else
		u8 flag;
		/* Open-coded due to __stringify() in ALTERNATIVE() */
		asm volatile("1: movb $0,%0\n"
			     "2:\n"
			     ".section .altinstructions,\"a\"\n"
			     _ASM_ALIGN "\n"
			     _ASM_PTR "1b\n"
			     _ASM_PTR "3f\n"
			     " .word %P1\n"		/* feature bit */
			     " .byte 2b - 1b\n"		/* source len */
			     " .byte 4f - 3f\n"		/* replacement len */
			     ".previous\n"
			     ".section .discard,\"aw\",@progbits\n"
			     " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
			     ".previous\n"
			     ".section .altinstr_replacement,\"ax\"\n"
			     "3: movb $1,%0\n"
			     "4:\n"
			     ".previous\n"
			     : "=qm" (flag) : "i" (bit));
		return flag;
#endif
}

#define static_cpu_has(bit)					\
(								\
	__builtin_constant_p(boot_cpu_has(bit)) ?		\
		boot_cpu_has(bit) :				\
	__builtin_constant_p(bit) ?				\
		__static_cpu_has(bit) :				\
		boot_cpu_has(bit)				\
)
#else
/*
 * gcc 3.x is too stupid to do the static test; fall back to dynamic.
 */
#define static_cpu_has(bit) boot_cpu_has(bit)
#endif

#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */

#endif /* _ASM_X86_CPUFEATURE_H */
Commit	Line	Data
7b11fb51 PA	1	/*
	2	* Defines x86 CPU feature bits
	3	*/
1965aae3 PA	4	#ifndef _ASM_X86_CPUFEATURE_H
1965aae3 PA	5	#define _ASM_X86_CPUFEATURE_H
7b11fb51	6
7b11fb51 PA	7	#include <asm/required-features.h>
7b11fb51 PA	8
bdc802dc	9	#define NCAPINTS 10 /* N 32-bit words worth of info */
7b11fb51	10
7414aa41 PA	11	/*
	12	* Note: If the comment begins with a quoted string, that string is used
	13	* in /proc/cpuinfo instead of the macro name. If the string is "",
	14	* this feature bit is not displayed in /proc/cpuinfo at all.
	15	*/
7b11fb51 PA	16
	17	/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
	18	#define X86_FEATURE_FPU (032+ 0) / Onboard FPU */
	19	#define X86_FEATURE_VME (032+ 1) / Virtual Mode Extensions */
	20	#define X86_FEATURE_DE (032+ 2) / Debugging Extensions */
	21	#define X86_FEATURE_PSE (032+ 3) / Page Size Extensions */
	22	#define X86_FEATURE_TSC (032+ 4) / Time Stamp Counter */
2798c63e	23	#define X86_FEATURE_MSR (032+ 5) / Model-Specific Registers */
7b11fb51	24	#define X86_FEATURE_PAE (032+ 6) / Physical Address Extensions */
3969c52d	25	#define X86_FEATURE_MCE (032+ 7) / Machine Check Exception */
7b11fb51 PA	26	#define X86_FEATURE_CX8 (032+ 8) / CMPXCHG8 instruction */
	27	#define X86_FEATURE_APIC (032+ 9) / Onboard APIC */
	28	#define X86_FEATURE_SEP (032+11) / SYSENTER/SYSEXIT */
	29	#define X86_FEATURE_MTRR (032+12) / Memory Type Range Registers */
	30	#define X86_FEATURE_PGE (032+13) / Page Global Enable */
	31	#define X86_FEATURE_MCA (032+14) / Machine Check Architecture */
2798c63e PA	32	#define X86_FEATURE_CMOV (032+15) / CMOV instructions */
2798c63e PA	33	/* (plus FCMOVcc, FCOMI with FPU) */
7b11fb51 PA	34	#define X86_FEATURE_PAT (032+16) / Page Attribute Table */
	35	#define X86_FEATURE_PSE36 (032+17) / 36-bit PSEs */
	36	#define X86_FEATURE_PN (032+18) / Processor serial number */
2798c63e	37	#define X86_FEATURE_CLFLSH (032+19) / "clflush" CLFLUSH instruction */
7414aa41	38	#define X86_FEATURE_DS (032+21) / "dts" Debug Store */
7b11fb51 PA	39	#define X86_FEATURE_ACPI (032+22) / ACPI via MSR */
7b11fb51 PA	40	#define X86_FEATURE_MMX (032+23) / Multimedia Extensions */
7414aa41 PA	41	#define X86_FEATURE_FXSR (032+24) / FXSAVE/FXRSTOR, CR4.OSFXSR */
	42	#define X86_FEATURE_XMM (032+25) / "sse" */
	43	#define X86_FEATURE_XMM2 (032+26) / "sse2" */
	44	#define X86_FEATURE_SELFSNOOP (032+27) / "ss" CPU self snoop */
7b11fb51	45	#define X86_FEATURE_HT (032+28) / Hyper-Threading */
7414aa41	46	#define X86_FEATURE_ACC (032+29) / "tm" Automatic clock control */
7b11fb51	47	#define X86_FEATURE_IA64 (032+30) / IA-64 processor */
7414aa41	48	#define X86_FEATURE_PBE (032+31) / Pending Break Enable */
7b11fb51 PA	49
	50	/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
	51	/* Don't duplicate feature flags which are redundant with Intel! */
	52	#define X86_FEATURE_SYSCALL (132+11) / SYSCALL/SYSRET */
	53	#define X86_FEATURE_MP (132+19) / MP Capable. */
	54	#define X86_FEATURE_NX (132+20) / Execute Disable */
	55	#define X86_FEATURE_MMXEXT (132+22) / AMD MMX extensions */
7414aa41 PA	56	#define X86_FEATURE_FXSR_OPT (132+25) / FXSAVE/FXRSTOR optimizations */
7414aa41 PA	57	#define X86_FEATURE_GBPAGES (132+26) / "pdpe1gb" GB pages */
7b11fb51 PA	58	#define X86_FEATURE_RDTSCP (132+27) / RDTSCP */
	59	#define X86_FEATURE_LM (132+29) / Long Mode (x86-64) */
	60	#define X86_FEATURE_3DNOWEXT (132+30) / AMD 3DNow! extensions */
	61	#define X86_FEATURE_3DNOW (132+31) / 3DNow! */
	62
	63	/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
	64	#define X86_FEATURE_RECOVERY (232+ 0) / CPU in recovery mode */
	65	#define X86_FEATURE_LONGRUN (232+ 1) / Longrun power control */
	66	#define X86_FEATURE_LRTI (232+ 3) / LongRun table interface */
	67
	68	/* Other features, Linux-defined mapping, word 3 */
	69	/* This range is used for feature bits which conflict or are synthesized */
	70	#define X86_FEATURE_CXMMX (332+ 0) / Cyrix MMX extensions */
	71	#define X86_FEATURE_K6_MTRR (332+ 1) / AMD K6 nonstandard MTRRs */
	72	#define X86_FEATURE_CYRIX_ARR (332+ 2) / Cyrix ARRs (= MTRRs) */
	73	#define X86_FEATURE_CENTAUR_MCR (332+ 3) / Centaur MCRs (= MTRRs) */
	74	/* cpu types for specific tunings: */
7414aa41 PA	75	#define X86_FEATURE_K8 (332+ 4) / "" Opteron, Athlon64 */
	76	#define X86_FEATURE_K7 (332+ 5) / "" Athlon */
	77	#define X86_FEATURE_P3 (332+ 6) / "" P3 */
	78	#define X86_FEATURE_P4 (332+ 7) / "" P4 */
7b11fb51 PA	79	#define X86_FEATURE_CONSTANT_TSC (332+ 8) / TSC ticks at a constant rate */
7b11fb51 PA	80	#define X86_FEATURE_UP (332+ 9) / smp kernel running on up */
7414aa41	81	#define X86_FEATURE_FXSAVE_LEAK (332+10) / "" FXSAVE leaks FOP/FIP/FOP */
7b11fb51	82	#define X86_FEATURE_ARCH_PERFMON (332+11) / Intel Architectural PerfMon */
b6734c35 PA	83	#define X86_FEATURE_PEBS (332+12) / Precise-Event Based Sampling */
b6734c35 PA	84	#define X86_FEATURE_BTS (332+13) / Branch Trace Store */
7414aa41 PA	85	#define X86_FEATURE_SYSCALL32 (332+14) / "" syscall in ia32 userspace */
7414aa41 PA	86	#define X86_FEATURE_SYSENTER32 (332+15) / "" sysenter in ia32 userspace */
2798c63e	87	#define X86_FEATURE_REP_GOOD (332+16) / rep microcode works well */
7414aa41 PA	88	#define X86_FEATURE_MFENCE_RDTSC (332+17) / "" Mfence synchronizes RDTSC */
	89	#define X86_FEATURE_LFENCE_RDTSC (332+18) / "" Lfence synchronizes RDTSC */
	90	#define X86_FEATURE_11AP (332+19) / "" Bad local APIC aka 11AP */
b6734c35	91	#define X86_FEATURE_NOPL (332+20) / The NOPL (0F 1F) instructions */
e8c534ec	92	/* 21 available, was AMD_C1E */
2576c999	93	#define X86_FEATURE_XTOPOLOGY (332+22) / cpu topology enum extensions */
b2bcc7b2	94	#define X86_FEATURE_TSC_RELIABLE (332+23) / TSC is known to be reliable */
d4377974	95	#define X86_FEATURE_NONSTOP_TSC (332+24) / TSC does not stop in C states */
e736ad54	96	#define X86_FEATURE_CLFLUSH_MONITOR (332+25) / "" clflush reqd with monitor */
42937e81	97	#define X86_FEATURE_EXTD_APICID (332+26) / has extended APICID (8 bits) */
4a376ec3	98	#define X86_FEATURE_AMD_DCM (332+27) / multi-node processor */
a8303aaf	99	#define X86_FEATURE_APERFMPERF (332+28) / APERFMPERF */
7b11fb51 PA	100
7b11fb51 PA	101	/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
7414aa41	102	#define X86_FEATURE_XMM3 (432+ 0) / "pni" SSE-3 */
f1240c00 PA	103	#define X86_FEATURE_PCLMULQDQ (432+ 1) / PCLMULQDQ instruction */
f1240c00 PA	104	#define X86_FEATURE_DTES64 (432+ 2) / 64-bit Debug Store */
7414aa41 PA	105	#define X86_FEATURE_MWAIT (432+ 3) / "monitor" Monitor/Mwait support */
	106	#define X86_FEATURE_DSCPL (432+ 4) / "ds_cpl" CPL Qual. Debug Store */
	107	#define X86_FEATURE_VMX (432+ 5) / Hardware virtualization */
af2e1f27	108	#define X86_FEATURE_SMX (432+ 6) / Safer mode */
7b11fb51 PA	109	#define X86_FEATURE_EST (432+ 7) / Enhanced SpeedStep */
7b11fb51 PA	110	#define X86_FEATURE_TM2 (432+ 8) / Thermal Monitor 2 */
7414aa41	111	#define X86_FEATURE_SSSE3 (432+ 9) / Supplemental SSE-3 */
7b11fb51	112	#define X86_FEATURE_CID (432+10) / Context ID */
f1240c00	113	#define X86_FEATURE_FMA (432+12) / Fused multiply-add */
7b11fb51 PA	114	#define X86_FEATURE_CX16 (432+13) / CMPXCHG16B */
7b11fb51 PA	115	#define X86_FEATURE_XTPR (432+14) / Send Task Priority Messages */
f1240c00	116	#define X86_FEATURE_PDCM (432+15) / Performance Capabilities */
7b11fb51	117	#define X86_FEATURE_DCA (432+18) / Direct Cache Access */
7414aa41 PA	118	#define X86_FEATURE_XMM4_1 (432+19) / "sse4_1" SSE-4.1 */
7414aa41 PA	119	#define X86_FEATURE_XMM4_2 (432+20) / "sse4_2" SSE-4.2 */
32e1d0a0	120	#define X86_FEATURE_X2APIC (432+21) / x2APIC */
069ebaa4 AK	121	#define X86_FEATURE_MOVBE (432+22) / MOVBE instruction */
069ebaa4 AK	122	#define X86_FEATURE_POPCNT (432+23) / POPCNT instruction */
f1240c00 PA	123	#define X86_FEATURE_AES (432+25) / AES instructions */
	124	#define X86_FEATURE_XSAVE (432+26) / XSAVE/XRSTOR/XSETBV/XGETBV */
	125	#define X86_FEATURE_OSXSAVE (432+27) / "" XSAVE enabled in the OS */
	126	#define X86_FEATURE_AVX (432+28) / Advanced Vector Extensions */
24da9c26 PA	127	#define X86_FEATURE_F16C (432+29) / 16-bit fp conversions */
24da9c26 PA	128	#define X86_FEATURE_RDRND (432+30) / The RDRAND instruction */
49ab56ac	129	#define X86_FEATURE_HYPERVISOR (432+31) / Running on a hypervisor */
7b11fb51 PA	130
7b11fb51 PA	131	/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
7414aa41 PA	132	#define X86_FEATURE_XSTORE (532+ 2) / "rng" RNG present (xstore) */
	133	#define X86_FEATURE_XSTORE_EN (532+ 3) / "rng_en" RNG enabled */
	134	#define X86_FEATURE_XCRYPT (532+ 6) / "ace" on-CPU crypto (xcrypt) */
	135	#define X86_FEATURE_XCRYPT_EN (532+ 7) / "ace_en" on-CPU crypto enabled */
7b11fb51 PA	136	#define X86_FEATURE_ACE2 (532+ 8) / Advanced Cryptography Engine v2 */
7b11fb51 PA	137	#define X86_FEATURE_ACE2_EN (532+ 9) / ACE v2 enabled */
7414aa41 PA	138	#define X86_FEATURE_PHE (532+10) / PadLock Hash Engine */
	139	#define X86_FEATURE_PHE_EN (532+11) / PHE enabled */
	140	#define X86_FEATURE_PMM (532+12) / PadLock Montgomery Multiplier */
	141	#define X86_FEATURE_PMM_EN (532+13) / PMM enabled */
7b11fb51 PA	142
	143	/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
	144	#define X86_FEATURE_LAHF_LM (632+ 0) / LAHF/SAHF in long mode */
	145	#define X86_FEATURE_CMP_LEGACY (632+ 1) / If yes HyperThreading not valid */
7414aa41 PA	146	#define X86_FEATURE_SVM (632+ 2) / Secure virtual machine */
	147	#define X86_FEATURE_EXTAPIC (632+ 3) / Extended APIC space */
	148	#define X86_FEATURE_CR8_LEGACY (632+ 4) / CR8 in 32-bit mode */
	149	#define X86_FEATURE_ABM (632+ 5) / Advanced bit manipulation */
	150	#define X86_FEATURE_SSE4A (632+ 6) / SSE-4A */
	151	#define X86_FEATURE_MISALIGNSSE (632+ 7) / Misaligned SSE mode */
	152	#define X86_FEATURE_3DNOWPREFETCH (632+ 8) / 3DNow prefetch instructions */
	153	#define X86_FEATURE_OSVW (632+ 9) / OS Visible Workaround */
	154	#define X86_FEATURE_IBS (632+10) / Instruction Based Sampling */
	155	#define X86_FEATURE_SSE5 (632+11) / SSE-5 */
	156	#define X86_FEATURE_SKINIT (632+12) / SKINIT/STGI instructions */
	157	#define X86_FEATURE_WDT (632+13) / Watchdog timer */
9d260ebc	158	#define X86_FEATURE_NODEID_MSR (632+19) / NodeId MSR */
7b11fb51 PA	159
	160	/*
	161	* Auxiliary flags: Linux defined - For features scattered in various
bdc802dc	162	* CPUID levels like 0x6, 0xA etc, word 7
7b11fb51 PA	163	*/
7b11fb51 PA	164	#define X86_FEATURE_IDA (732+ 0) / Intel Dynamic Acceleration */
db954b58	165	#define X86_FEATURE_ARAT (732+ 1) / Always Running APIC Timer */
5958f1d5	166	#define X86_FEATURE_CPB (732+ 2) / AMD Core Performance Boost */
23016bf0	167	#define X86_FEATURE_EPB (732+ 3) / IA32_ENERGY_PERF_BIAS support */
278bc5f6	168	#define X86_FEATURE_XSAVEOPT (732+ 4) / Optimized Xsave */
9792db61 FY	169	#define X86_FEATURE_PLN (732+ 5) / Intel Power Limit Notification */
9792db61 FY	170	#define X86_FEATURE_PTS (732+ 6) / Intel Package Thermal Status */
a4659053	171	#define X86_FEATURE_DTS (732+ 7) / Digital Thermal Sensor */
7b11fb51	172
bdc802dc	173	/* Virtualization flags: Linux defined, word 8 */
e38e05a8 SY	174	#define X86_FEATURE_TPR_SHADOW (832+ 0) / Intel TPR Shadow */
	175	#define X86_FEATURE_VNMI (832+ 1) / Intel Virtual NMI */
	176	#define X86_FEATURE_FLEXPRIORITY (832+ 2) / Intel FlexPriority */
	177	#define X86_FEATURE_EPT (832+ 3) / Intel Extended Page Table */
	178	#define X86_FEATURE_VPID (832+ 4) / Intel Virtual Processor ID */
278bc5f6 PA	179	#define X86_FEATURE_NPT (832+ 5) / AMD Nested Page Table support */
	180	#define X86_FEATURE_LBRV (832+ 6) / AMD LBR Virtualization support */
	181	#define X86_FEATURE_SVML (832+ 7) / "svm_lock" AMD SVM locking MSR */
	182	#define X86_FEATURE_NRIPS (832+ 8) / "nrip_save" AMD SVM next_rip save */
e38e05a8	183
bdc802dc	184	/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
278bc5f6	185	#define X86_FEATURE_FSGSBASE (932+ 0) / {RD/WR}{FS/GS}BASE instructions*/
bdc802dc	186
fa1408e4 PA	187	#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
fa1408e4 PA	188
a3c8acd0	189	#include <asm/asm.h>
fa1408e4 PA	190	#include <linux/bitops.h>
	191
	192	extern const char * const x86_cap_flags[NCAPINTS*32];
	193	extern const char * const x86_power_flags[32];
	194
0f8d2b92 IM	195	#define test_cpu_cap(c, bit) \
	196	test_bit(bit, (unsigned long *)((c)->x86_capability))
	197
7b11fb51 PA	198	#define cpu_has(c, bit) \
	199	(__builtin_constant_p(bit) && \
	200	( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) \|\| \
	201	(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) \|\| \
	202	(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) \|\| \
	203	(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) \|\| \
	204	(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) \|\| \
	205	(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) \|\| \
	206	(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) \|\| \
bdc802dc PA	207	(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) \|\| \
	208	(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) \|\| \
	209	(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) \
7b11fb51	210	? 1 : \
0f8d2b92 IM	211	test_cpu_cap(c, bit))
0f8d2b92 IM	212
7b11fb51 PA	213	#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
7b11fb51 PA	214
53756d37 JF	215	#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
53756d37 JF	216	#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
7d851c8d AK	217	#define setup_clear_cpu_cap(bit) do { \
7d851c8d AK	218	clear_cpu_cap(&boot_cpu_data, bit); \
3e0c3737	219	set_bit(bit, (unsigned long *)cpu_caps_cleared); \
7d851c8d	220	} while (0)
404ee5b1 AK	221	#define setup_force_cpu_cap(bit) do { \
404ee5b1 AK	222	set_cpu_cap(&boot_cpu_data, bit); \
3e0c3737	223	set_bit(bit, (unsigned long *)cpu_caps_set); \
404ee5b1	224	} while (0)
53756d37	225
7b11fb51 PA	226	#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
	227	#define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
	228	#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
	229	#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
	230	#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
	231	#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
	232	#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
	233	#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
	234	#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
	235	#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
	236	#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
	237	#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
	238	#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
	239	#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
	240	#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
54b6a1bd	241	#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
7b11fb51 PA	242	#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
	243	#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
	244	#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
	245	#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
	246	#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
	247	#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
	248	#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
	249	#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
	250	#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
	251	#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
	252	#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
	253	#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
	254	#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
	255	#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
	256	#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
	257	#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
	258	#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
	259	#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
	260	#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
	261	#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
019c3e7c	262	#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
86975101	263	#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
2e5d9c85	264	#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
f1240c00	265	#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
2a61812a	266	#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
32e1d0a0	267	#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
f1240c00	268	#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
49ab56ac	269	#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
0e1227d3	270	#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
7b11fb51	271
0b9c99b6 TG	272	#if defined(CONFIG_X86_INVLPG) \|\| defined(CONFIG_X86_64)
	273	# define cpu_has_invlpg 1
	274	#else
	275	# define cpu_has_invlpg (boot_cpu_data.x86 > 3)
	276	#endif
	277
7b11fb51 PA	278	#ifdef CONFIG_X86_64
	279
	280	#undef cpu_has_vme
	281	#define cpu_has_vme 0
	282
	283	#undef cpu_has_pae
	284	#define cpu_has_pae ___BUG___
	285
	286	#undef cpu_has_mp
	287	#define cpu_has_mp 1
	288
	289	#undef cpu_has_k6_mtrr
	290	#define cpu_has_k6_mtrr 0
	291
	292	#undef cpu_has_cyrix_arr
	293	#define cpu_has_cyrix_arr 0
	294
	295	#undef cpu_has_centaur_mcr
	296	#define cpu_has_centaur_mcr 0
	297
	298	#endif /* CONFIG_X86_64 */
	299
2fd81864	300	#if __GNUC__ >= 4
a3c8acd0 PA	301	/*
	302	* Static testing of CPU features. Used the same as boot_cpu_has().
	303	* These are only valid after alternatives have run, but will statically
	304	* patch the target code for additional performance.
	305	*
	306	*/
83a7a2ad	307	static __always_inline __pure bool __static_cpu_has(u16 bit)
a3c8acd0	308	{
2fd81864	309	#if __GNUC__ > 4 \|\| __GNUC_MINOR__ >= 5
a3c8acd0 PA	310	asm goto("1: jmp %l[t_no]\n"
	311	"2:\n"
	312	".section .altinstructions,\"a\"\n"
	313	_ASM_ALIGN "\n"
	314	_ASM_PTR "1b\n"
	315	_ASM_PTR "0\n" /* no replacement */
83a7a2ad	316	" .word %P0\n" /* feature bit */
a3c8acd0 PA	317	" .byte 2b - 1b\n" /* source len */
a3c8acd0 PA	318	" .byte 0\n" /* replacement len */
a3c8acd0	319	".previous\n"
83a7a2ad	320	/* skipping size check since replacement size = 0 */
a3c8acd0 PA	321	: : "i" (bit) : : t_no);
	322	return true;
	323	t_no:
	324	return false;
	325	#else
	326	u8 flag;
	327	/* Open-coded due to __stringify() in ALTERNATIVE() */
	328	asm volatile("1: movb $0,%0\n"
	329	"2:\n"
	330	".section .altinstructions,\"a\"\n"
	331	_ASM_ALIGN "\n"
	332	_ASM_PTR "1b\n"
	333	_ASM_PTR "3f\n"
83a7a2ad	334	" .word %P1\n" /* feature bit */
a3c8acd0 PA	335	" .byte 2b - 1b\n" /* source len */
a3c8acd0 PA	336	" .byte 4f - 3f\n" /* replacement len */
83a7a2ad PA	337	".previous\n"
	338	".section .discard,\"aw\",@progbits\n"
	339	" .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
a3c8acd0 PA	340	".previous\n"
	341	".section .altinstr_replacement,\"ax\"\n"
	342	"3: movb $1,%0\n"
	343	"4:\n"
	344	".previous\n"
	345	: "=qm" (flag) : "i" (bit));
	346	return flag;
	347	#endif
	348	}
	349
	350	#define static_cpu_has(bit) \
	351	( \
	352	__builtin_constant_p(boot_cpu_has(bit)) ? \
	353	boot_cpu_has(bit) : \
83a7a2ad	354	__builtin_constant_p(bit) ? \
a3c8acd0 PA	355	__static_cpu_has(bit) : \
	356	boot_cpu_has(bit) \
	357	)
1ba4f22c PA	358	#else
	359	/*
	360	* gcc 3.x is too stupid to do the static test; fall back to dynamic.
	361	*/
	362	#define static_cpu_has(bit) boot_cpu_has(bit)
	363	#endif
a3c8acd0	364
fa1408e4 PA	365	#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
fa1408e4 PA	366
1965aae3	367	#endif /* _ASM_X86_CPUFEATURE_H */