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8d283c35 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
8d283c35 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1965aae3 PA |
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
22 | |
23 | #include <linux/types.h> | |
24 | #include <linux/list.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
bb52777e JR |
27 | /* |
28 | * Maximum number of IOMMUs supported | |
29 | */ | |
30 | #define MAX_IOMMUS 32 | |
31 | ||
8d283c35 JR |
32 | /* |
33 | * some size calculation constants | |
34 | */ | |
83f5aac1 | 35 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
36 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
37 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
38 | ||
8d283c35 JR |
39 | /* Length of the MMIO region for the AMD IOMMU */ |
40 | #define MMIO_REGION_LENGTH 0x4000 | |
41 | ||
42 | /* Capability offsets used by the driver */ | |
43 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
44 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 45 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
46 | |
47 | /* Masks, shifts and macros to parse the device range capability */ | |
48 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
49 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
50 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
51 | #define MMIO_RANGE_LD_SHIFT 24 | |
52 | #define MMIO_RANGE_FD_SHIFT 16 | |
53 | #define MMIO_RANGE_BUS_SHIFT 8 | |
54 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
55 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
56 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 57 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
58 | |
59 | /* Flag masks for the AMD IOMMU exclusion range */ | |
60 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
61 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
62 | ||
63 | /* Used offsets into the MMIO space */ | |
64 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
65 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
66 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
67 | #define MMIO_CONTROL_OFFSET 0x0018 | |
68 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
69 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
70 | #define MMIO_CMD_HEAD_OFFSET 0x2000 | |
71 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
72 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
73 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
74 | #define MMIO_STATUS_OFFSET 0x2020 | |
75 | ||
519c31ba JR |
76 | /* MMIO status bits */ |
77 | #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 | |
78 | ||
90008ee4 JR |
79 | /* event logging constants */ |
80 | #define EVENT_ENTRY_SIZE 0x10 | |
81 | #define EVENT_TYPE_SHIFT 28 | |
82 | #define EVENT_TYPE_MASK 0xf | |
83 | #define EVENT_TYPE_ILL_DEV 0x1 | |
84 | #define EVENT_TYPE_IO_FAULT 0x2 | |
85 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
86 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
87 | #define EVENT_TYPE_ILL_CMD 0x5 | |
88 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
89 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
90 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
91 | #define EVENT_DEVID_MASK 0xffff | |
92 | #define EVENT_DEVID_SHIFT 0 | |
93 | #define EVENT_DOMID_MASK 0xffff | |
94 | #define EVENT_DOMID_SHIFT 0 | |
95 | #define EVENT_FLAGS_MASK 0xfff | |
96 | #define EVENT_FLAGS_SHIFT 0x10 | |
97 | ||
8d283c35 JR |
98 | /* feature control bits */ |
99 | #define CONTROL_IOMMU_EN 0x00ULL | |
100 | #define CONTROL_HT_TUN_EN 0x01ULL | |
101 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
102 | #define CONTROL_EVT_INT_EN 0x03ULL | |
103 | #define CONTROL_COMWAIT_EN 0x04ULL | |
104 | #define CONTROL_PASSPW_EN 0x08ULL | |
105 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
106 | #define CONTROL_COHERENT_EN 0x0aULL | |
107 | #define CONTROL_ISOC_EN 0x0bULL | |
108 | #define CONTROL_CMDBUF_EN 0x0cULL | |
109 | #define CONTROL_PPFLOG_EN 0x0dULL | |
110 | #define CONTROL_PPFINT_EN 0x0eULL | |
111 | ||
112 | /* command specific defines */ | |
113 | #define CMD_COMPL_WAIT 0x01 | |
114 | #define CMD_INV_DEV_ENTRY 0x02 | |
115 | #define CMD_INV_IOMMU_PAGES 0x03 | |
116 | ||
117 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 118 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
119 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
120 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
121 | ||
999ba417 JR |
122 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
123 | ||
8d283c35 JR |
124 | /* macros and definitions for device table entries */ |
125 | #define DEV_ENTRY_VALID 0x00 | |
126 | #define DEV_ENTRY_TRANSLATION 0x01 | |
127 | #define DEV_ENTRY_IR 0x3d | |
128 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 129 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
130 | #define DEV_ENTRY_EX 0x67 |
131 | #define DEV_ENTRY_SYSMGT1 0x68 | |
132 | #define DEV_ENTRY_SYSMGT2 0x69 | |
133 | #define DEV_ENTRY_INIT_PASS 0xb8 | |
134 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
135 | #define DEV_ENTRY_NMI_PASS 0xba | |
136 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
137 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
138 | #define DEV_ENTRY_MODE_MASK 0x07 |
139 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 JR |
140 | |
141 | /* constants to configure the command buffer */ | |
142 | #define CMD_BUFFER_SIZE 8192 | |
143 | #define CMD_BUFFER_ENTRIES 512 | |
144 | #define MMIO_CMD_SIZE_SHIFT 56 | |
145 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
146 | ||
335503e5 JR |
147 | /* constants for event buffer handling */ |
148 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
149 | #define EVT_LEN_MASK (0x9ULL << 56) | |
150 | ||
0feae533 | 151 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
152 | #define PAGE_MODE_1_LEVEL 0x01 |
153 | #define PAGE_MODE_2_LEVEL 0x02 | |
154 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
155 | #define PAGE_MODE_4_LEVEL 0x04 |
156 | #define PAGE_MODE_5_LEVEL 0x05 | |
157 | #define PAGE_MODE_6_LEVEL 0x06 | |
8d283c35 | 158 | |
9355a081 JR |
159 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
160 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
161 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
162 | (0xffffffffffffffffULL)) | |
163 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
164 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
165 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
166 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) | |
a6b256b4 | 167 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 168 | |
abdc5eb3 JR |
169 | #define PM_MAP_4k 0 |
170 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
171 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
172 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
173 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 JR |
174 | |
175 | #define IOMMU_PTE_P (1ULL << 0) | |
38ddf41b | 176 | #define IOMMU_PTE_TV (1ULL << 1) |
8d283c35 JR |
177 | #define IOMMU_PTE_U (1ULL << 59) |
178 | #define IOMMU_PTE_FC (1ULL << 60) | |
179 | #define IOMMU_PTE_IR (1ULL << 61) | |
180 | #define IOMMU_PTE_IW (1ULL << 62) | |
181 | ||
8d283c35 JR |
182 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
183 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) | |
184 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) | |
185 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) | |
186 | ||
187 | #define IOMMU_PROT_MASK 0x03 | |
188 | #define IOMMU_PROT_IR 0x01 | |
189 | #define IOMMU_PROT_IW 0x02 | |
190 | ||
191 | /* IOMMU capabilities */ | |
192 | #define IOMMU_CAP_IOTLB 24 | |
193 | #define IOMMU_CAP_NPCACHE 26 | |
194 | ||
195 | #define MAX_DOMAIN_ID 65536 | |
196 | ||
90008ee4 JR |
197 | /* FIXME: move this macro to <linux/pci.h> */ |
198 | #define PCI_BUS(x) (((x) >> 8) & 0xff) | |
199 | ||
9fdb19d6 JR |
200 | /* Protection domain flags */ |
201 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
202 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
203 | domain for an IOMMU */ | |
0feae533 JR |
204 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
205 | translation */ | |
206 | ||
fefda117 JR |
207 | extern bool amd_iommu_dump; |
208 | #define DUMP_printk(format, arg...) \ | |
209 | do { \ | |
210 | if (amd_iommu_dump) \ | |
4c6f40d4 | 211 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 212 | } while(0); |
9fdb19d6 | 213 | |
318afd41 JR |
214 | /* global flag if IOMMUs cache non-present entries */ |
215 | extern bool amd_iommu_np_cache; | |
216 | ||
3bd22172 JR |
217 | /* |
218 | * Make iterating over all IOMMUs easier | |
219 | */ | |
220 | #define for_each_iommu(iommu) \ | |
221 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
222 | #define for_each_iommu_safe(iommu, next) \ | |
223 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
224 | ||
384de729 JR |
225 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
226 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
227 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
228 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
229 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
230 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 231 | |
5694703f JR |
232 | /* |
233 | * This structure contains generic data for IOMMU protection domains | |
234 | * independent of their use. | |
235 | */ | |
8d283c35 | 236 | struct protection_domain { |
aeb26f55 | 237 | struct list_head list; /* for list of all protection domains */ |
7c392cbe | 238 | struct list_head dev_list; /* List of all devices in this domain */ |
9fdb19d6 JR |
239 | spinlock_t lock; /* mostly used to lock the page table*/ |
240 | u16 id; /* the domain id written to the device table */ | |
241 | int mode; /* paging mode (0-6 levels) */ | |
242 | u64 *pt_root; /* page table root pointer */ | |
243 | unsigned long flags; /* flags to find out type of domain */ | |
04bfdd84 | 244 | bool updated; /* complete domain flush required */ |
863c74eb | 245 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 246 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
9fdb19d6 | 247 | void *priv; /* private data */ |
c4596114 | 248 | |
8d283c35 JR |
249 | }; |
250 | ||
657cbb6b JR |
251 | /* |
252 | * This struct contains device specific data for the IOMMU | |
253 | */ | |
254 | struct iommu_dev_data { | |
7c392cbe | 255 | struct list_head list; /* For domain->dev_list */ |
657cbb6b JR |
256 | struct device *alias; /* The Alias Device */ |
257 | struct protection_domain *domain; /* Domain the device is bound to */ | |
24100055 | 258 | atomic_t bind; /* Domain attach reverent count */ |
657cbb6b JR |
259 | }; |
260 | ||
c3239567 JR |
261 | /* |
262 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
263 | * DMA address space each. This struct represents one such range. | |
264 | */ | |
265 | struct aperture_range { | |
266 | ||
267 | /* address allocation bitmap */ | |
268 | unsigned long *bitmap; | |
269 | ||
270 | /* | |
271 | * Array of PTE pages for the aperture. In this array we save all the | |
272 | * leaf pages of the domain page table used for the aperture. This way | |
273 | * we don't need to walk the page table to find a specific PTE. We can | |
274 | * just calculate its address in constant time. | |
275 | */ | |
276 | u64 *pte_pages[64]; | |
384de729 JR |
277 | |
278 | unsigned long offset; | |
c3239567 JR |
279 | }; |
280 | ||
5694703f JR |
281 | /* |
282 | * Data container for a dma_ops specific protection domain | |
283 | */ | |
8d283c35 JR |
284 | struct dma_ops_domain { |
285 | struct list_head list; | |
5694703f JR |
286 | |
287 | /* generic protection domain information */ | |
8d283c35 | 288 | struct protection_domain domain; |
5694703f JR |
289 | |
290 | /* size of the aperture for the mappings */ | |
8d283c35 | 291 | unsigned long aperture_size; |
5694703f JR |
292 | |
293 | /* address we start to search for free addresses */ | |
803b8cb4 | 294 | unsigned long next_address; |
5694703f | 295 | |
c3239567 | 296 | /* address space relevant data */ |
384de729 | 297 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; |
1c655773 JR |
298 | |
299 | /* This will be set to true when TLB needs to be flushed */ | |
300 | bool need_flush; | |
bd60b735 JR |
301 | |
302 | /* | |
303 | * if this is a preallocated domain, keep the device for which it was | |
304 | * preallocated in this variable | |
305 | */ | |
306 | u16 target_dev; | |
8d283c35 JR |
307 | }; |
308 | ||
5694703f JR |
309 | /* |
310 | * Structure where we save information about one hardware AMD IOMMU in the | |
311 | * system. | |
312 | */ | |
8d283c35 JR |
313 | struct amd_iommu { |
314 | struct list_head list; | |
5694703f | 315 | |
bb52777e JR |
316 | /* Index within the IOMMU array */ |
317 | int index; | |
318 | ||
5694703f | 319 | /* locks the accesses to the hardware */ |
8d283c35 JR |
320 | spinlock_t lock; |
321 | ||
3eaf28a1 JR |
322 | /* Pointer to PCI device of this IOMMU */ |
323 | struct pci_dev *dev; | |
324 | ||
5694703f | 325 | /* physical address of MMIO space */ |
8d283c35 | 326 | u64 mmio_phys; |
5694703f | 327 | /* virtual address of MMIO space */ |
8d283c35 | 328 | u8 *mmio_base; |
5694703f JR |
329 | |
330 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 331 | u32 cap; |
5694703f | 332 | |
eac9fbc6 RK |
333 | /* |
334 | * Capability pointer. There could be more than one IOMMU per PCI | |
335 | * device function if there are more than one AMD IOMMU capability | |
336 | * pointers. | |
337 | */ | |
338 | u16 cap_ptr; | |
339 | ||
ee893c24 JR |
340 | /* pci domain of this IOMMU */ |
341 | u16 pci_seg; | |
342 | ||
5694703f | 343 | /* first device this IOMMU handles. read from PCI */ |
8d283c35 | 344 | u16 first_device; |
5694703f | 345 | /* last device this IOMMU handles. read from PCI */ |
8d283c35 | 346 | u16 last_device; |
5694703f JR |
347 | |
348 | /* start of exclusion range of that IOMMU */ | |
8d283c35 | 349 | u64 exclusion_start; |
5694703f | 350 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
351 | u64 exclusion_length; |
352 | ||
5694703f | 353 | /* command buffer virtual address */ |
8d283c35 | 354 | u8 *cmd_buf; |
5694703f | 355 | /* size of command buffer */ |
8d283c35 JR |
356 | u32 cmd_buf_size; |
357 | ||
335503e5 JR |
358 | /* size of event buffer */ |
359 | u32 evt_buf_size; | |
eac9fbc6 RK |
360 | /* event buffer virtual address */ |
361 | u8 *evt_buf; | |
a80dc3e0 JR |
362 | /* MSI number for event interrupt */ |
363 | u16 evt_msi_num; | |
335503e5 | 364 | |
a80dc3e0 JR |
365 | /* true if interrupts for this IOMMU are already enabled */ |
366 | bool int_enabled; | |
367 | ||
eac9fbc6 | 368 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 369 | bool need_sync; |
eac9fbc6 | 370 | |
b26e81b8 JR |
371 | /* becomes true if a command buffer reset is running */ |
372 | bool reset_in_progress; | |
373 | ||
5694703f | 374 | /* default dma_ops domain for that IOMMU */ |
8d283c35 JR |
375 | struct dma_ops_domain *default_dom; |
376 | }; | |
377 | ||
5694703f JR |
378 | /* |
379 | * List with all IOMMUs in the system. This list is not locked because it is | |
380 | * only written and read at driver initialization or suspend time | |
381 | */ | |
8d283c35 JR |
382 | extern struct list_head amd_iommu_list; |
383 | ||
bb52777e JR |
384 | /* |
385 | * Array with pointers to each IOMMU struct | |
386 | * The indices are referenced in the protection domains | |
387 | */ | |
388 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
389 | ||
390 | /* Number of IOMMUs present in the system */ | |
391 | extern int amd_iommus_present; | |
392 | ||
aeb26f55 JR |
393 | /* |
394 | * Declarations for the global list of all protection domains | |
395 | */ | |
396 | extern spinlock_t amd_iommu_pd_lock; | |
397 | extern struct list_head amd_iommu_pd_list; | |
398 | ||
5694703f JR |
399 | /* |
400 | * Structure defining one entry in the device table | |
401 | */ | |
8d283c35 JR |
402 | struct dev_table_entry { |
403 | u32 data[8]; | |
404 | }; | |
405 | ||
5694703f JR |
406 | /* |
407 | * One entry for unity mappings parsed out of the ACPI table. | |
408 | */ | |
8d283c35 JR |
409 | struct unity_map_entry { |
410 | struct list_head list; | |
5694703f JR |
411 | |
412 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 413 | u16 devid_start; |
5694703f | 414 | /* end device id this entry is used for (including) */ |
8d283c35 | 415 | u16 devid_end; |
5694703f JR |
416 | |
417 | /* start address to unity map (including) */ | |
8d283c35 | 418 | u64 address_start; |
5694703f | 419 | /* end address to unity map (including) */ |
8d283c35 | 420 | u64 address_end; |
5694703f JR |
421 | |
422 | /* required protection */ | |
8d283c35 JR |
423 | int prot; |
424 | }; | |
425 | ||
5694703f JR |
426 | /* |
427 | * List of all unity mappings. It is not locked because as runtime it is only | |
428 | * read. It is created at ACPI table parsing time. | |
429 | */ | |
8d283c35 JR |
430 | extern struct list_head amd_iommu_unity_map; |
431 | ||
5694703f JR |
432 | /* |
433 | * Data structures for device handling | |
434 | */ | |
435 | ||
436 | /* | |
437 | * Device table used by hardware. Read and write accesses by software are | |
438 | * locked with the amd_iommu_pd_table lock. | |
439 | */ | |
8d283c35 | 440 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
441 | |
442 | /* | |
443 | * Alias table to find requestor ids to device ids. Not locked because only | |
444 | * read on runtime. | |
445 | */ | |
8d283c35 | 446 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
447 | |
448 | /* | |
449 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
450 | */ | |
8d283c35 JR |
451 | extern struct amd_iommu **amd_iommu_rlookup_table; |
452 | ||
5694703f | 453 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
454 | extern unsigned amd_iommu_aperture_order; |
455 | ||
5694703f | 456 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
457 | extern u16 amd_iommu_last_bdf; |
458 | ||
459 | /* data structures for protection domain handling */ | |
460 | extern struct protection_domain **amd_iommu_pd_table; | |
5694703f JR |
461 | |
462 | /* allocation bitmap for domain ids */ | |
8d283c35 JR |
463 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
464 | ||
afa9fdc2 FT |
465 | /* |
466 | * If true, the addresses will be flushed on unmap time, not when | |
467 | * they are reused | |
468 | */ | |
469 | extern bool amd_iommu_unmap_flush; | |
470 | ||
d591b0a3 JR |
471 | /* takes bus and device/function and returns the device id |
472 | * FIXME: should that be in generic PCI code? */ | |
473 | static inline u16 calc_devid(u8 bus, u8 devfn) | |
474 | { | |
475 | return (((u16)bus) << 8) | devfn; | |
476 | } | |
477 | ||
a9dddbe0 JR |
478 | #ifdef CONFIG_AMD_IOMMU_STATS |
479 | ||
480 | struct __iommu_counter { | |
481 | char *name; | |
482 | struct dentry *dent; | |
483 | u64 value; | |
484 | }; | |
485 | ||
486 | #define DECLARE_STATS_COUNTER(nm) \ | |
487 | static struct __iommu_counter nm = { \ | |
488 | .name = #nm, \ | |
489 | } | |
490 | ||
491 | #define INC_STATS_COUNTER(name) name.value += 1 | |
492 | #define ADD_STATS_COUNTER(name, x) name.value += (x) | |
493 | #define SUB_STATS_COUNTER(name, x) name.value -= (x) | |
494 | ||
495 | #else /* CONFIG_AMD_IOMMU_STATS */ | |
496 | ||
497 | #define DECLARE_STATS_COUNTER(name) | |
498 | #define INC_STATS_COUNTER(name) | |
499 | #define ADD_STATS_COUNTER(name, x) | |
500 | #define SUB_STATS_COUNTER(name, x) | |
501 | ||
502 | #endif /* CONFIG_AMD_IOMMU_STATS */ | |
503 | ||
1965aae3 | 504 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |