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[net-next-2.6.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
1da177e4
LT		 25
26#include <asm/head.h>
27#include <asm/system.h>
28#include <asm/page.h>
29#include <asm/pgalloc.h>
30#include <asm/pgtable.h>
31#include <asm/oplib.h>
32#include <asm/iommu.h>
33#include <asm/io.h>
34#include <asm/uaccess.h>
35#include <asm/mmu_context.h>
36#include <asm/tlbflush.h>
37#include <asm/dma.h>
38#include <asm/starfire.h>
39#include <asm/tlb.h>
40#include <asm/spitfire.h>
41#include <asm/sections.h>
42
43extern void device_scan(void);
44
13edad7a
DM		 45#define MAX_BANKS 32
46
47static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
48static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
49static int pavail_ents __initdata;
50static int pavail_rescan_ents __initdata;
51
52static int cmp_p64(const void *a, const void *b)
53{
54 const struct linux_prom64_registers *x = a, *y = b;
55
56 if (x->phys_addr > y->phys_addr)
57 return 1;
58 if (x->phys_addr < y->phys_addr)
59 return -1;
60 return 0;
61}
62
63static void __init read_obp_memory(const char *property,
64 struct linux_prom64_registers *regs,
65 int *num_ents)
66{
67 int node = prom_finddevice("/memory");
68 int prop_size = prom_getproplen(node, property);
69 int ents, ret, i;
70
71 ents = prop_size / sizeof(struct linux_prom64_registers);
72 if (ents > MAX_BANKS) {
73 prom_printf("The machine has more %s property entries than "
74 "this kernel can support (%d).\n",
75 property, MAX_BANKS);
76 prom_halt();
77 }
78
79 ret = prom_getproperty(node, property, (char *) regs, prop_size);
80 if (ret == -1) {
81 prom_printf("Couldn't get %s property from /memory.\n");
82 prom_halt();
83 }
84
85 *num_ents = ents;
10147570 86
13edad7a
DM		 87 /* Sanitize what we got from the firmware, by page aligning
88 * everything.
89 */
90 for (i = 0; i < ents; i++) {
91 unsigned long base, size;
92
93 base = regs[i].phys_addr;
94 size = regs[i].reg_size;
10147570 95
13edad7a
DM		 96 size &= PAGE_MASK;
97 if (base & ~PAGE_MASK) {
98 unsigned long new_base = PAGE_ALIGN(base);
99
100 size -= new_base - base;
101 if ((long) size < 0L)
102 size = 0UL;
103 base = new_base;
104 }
105 regs[i].phys_addr = base;
106 regs[i].reg_size = size;
107 }
108 sort(regs, ents, sizeof(struct linux_prom64_registers),
109 cmp_p64, NULL);
110}
1da177e4 111
2bdb3cb2 112unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4
LT		 113
114/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 115unsigned long phys_base __read_mostly;
116unsigned long kern_base __read_mostly;
117unsigned long kern_size __read_mostly;
118unsigned long pfn_base __read_mostly;
1da177e4 119
1da177e4
LT		 120/* get_new_mmu_context() uses "cache + 1". */
121DEFINE_SPINLOCK(ctx_alloc_lock);
122unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
123#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
124unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
125
126/* References to special section boundaries */
127extern char _start[], _end[];
128
129/* Initial ramdisk setup */
130extern unsigned long sparc_ramdisk_image64;
131extern unsigned int sparc_ramdisk_image;
132extern unsigned int sparc_ramdisk_size;
133
1ac4f5eb 134struct page *mem_map_zero __read_mostly;
1da177e4
LT		 135
136int bigkernel = 0;
137
138/* XXX Tune this... */
139#define PGT_CACHE_LOW 25
140#define PGT_CACHE_HIGH 50
141
142void check_pgt_cache(void)
143{
144 preempt_disable();
145 if (pgtable_cache_size > PGT_CACHE_HIGH) {
146 do {
147 if (pgd_quicklist)
148 free_pgd_slow(get_pgd_fast());
149 if (pte_quicklist[0])
150 free_pte_slow(pte_alloc_one_fast(NULL, 0));
151 if (pte_quicklist[1])
152 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
153 } while (pgtable_cache_size > PGT_CACHE_LOW);
154 }
155 preempt_enable();
156}
157
158#ifdef CONFIG_DEBUG_DCFLUSH
159atomic_t dcpage_flushes = ATOMIC_INIT(0);
160#ifdef CONFIG_SMP
161atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
162#endif
163#endif
164
165__inline__ void flush_dcache_page_impl(struct page *page)
166{
167#ifdef CONFIG_DEBUG_DCFLUSH
168 atomic_inc(&dcpage_flushes);
169#endif
170
171#ifdef DCACHE_ALIASING_POSSIBLE
172 __flush_dcache_page(page_address(page),
173 ((tlb_type == spitfire) &&
174 page_mapping(page) != NULL));
175#else
176 if (page_mapping(page) != NULL &&
177 tlb_type == spitfire)
178 __flush_icache_page(__pa(page_address(page)));
179#endif
180}
181
182#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 183#define PG_dcache_cpu_shift 24
184#define PG_dcache_cpu_mask (256 - 1)
185
186#if NR_CPUS > 256
187#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
188#endif
1da177e4
LT		 189
190#define dcache_dirty_cpu(page) \
48b0e548 191 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 192
193static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
194{
195 unsigned long mask = this_cpu;
48b0e548
DM		 196 unsigned long non_cpu_bits;
197
198 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
199 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
200
1da177e4
LT		 201 __asm__ __volatile__("1:\n\t"
202 "ldx [%2], %%g7\n\t"
203 "and %%g7, %1, %%g1\n\t"
204 "or %%g1, %0, %%g1\n\t"
205 "casx [%2], %%g7, %%g1\n\t"
206 "cmp %%g7, %%g1\n\t"
b445e26c 207 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 208 "bne,pn %%xcc, 1b\n\t"
b445e26c 209 " nop"
1da177e4
LT		 210 : /* no outputs */
211 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
212 : "g1", "g7");
213}
214
215static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
216{
217 unsigned long mask = (1UL << PG_dcache_dirty);
218
219 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
220 "1:\n\t"
221 "ldx [%2], %%g7\n\t"
48b0e548 222 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 223 "and %%g1, %3, %%g1\n\t"
224 "cmp %%g1, %0\n\t"
225 "bne,pn %%icc, 2f\n\t"
226 " andn %%g7, %1, %%g1\n\t"
227 "casx [%2], %%g7, %%g1\n\t"
228 "cmp %%g7, %%g1\n\t"
b445e26c 229 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 230 "bne,pn %%xcc, 1b\n\t"
b445e26c 231 " nop\n"
1da177e4
LT		 232 "2:"
233 : /* no outputs */
234 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 235 "i" (PG_dcache_cpu_mask),
236 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 237 : "g1", "g7");
238}
239
1da177e4
LT		 240void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
241{
242 struct page *page;
243 unsigned long pfn;
244 unsigned long pg_flags;
245
246 pfn = pte_pfn(pte);
247 if (pfn_valid(pfn) &&
248 (page = pfn_to_page(pfn), page_mapping(page)) &&
249 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 250 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
251 PG_dcache_cpu_mask);
1da177e4
LT		 252 int this_cpu = get_cpu();
253
254 /* This is just to optimize away some function calls
255 * in the SMP case.
256 */
257 if (cpu == this_cpu)
258 flush_dcache_page_impl(page);
259 else
260 smp_flush_dcache_page_impl(page, cpu);
261
262 clear_dcache_dirty_cpu(page, cpu);
263
264 put_cpu();
265 }
1da177e4
LT		 266}
267
268void flush_dcache_page(struct page *page)
269{
a9546f59
DM		 270 struct address_space *mapping;
271 int this_cpu;
1da177e4 272
a9546f59
DM		 273 /* Do not bother with the expensive D-cache flush if it
274 * is merely the zero page. The 'bigcore' testcase in GDB
275 * causes this case to run millions of times.
276 */
277 if (page == ZERO_PAGE(0))
278 return;
279
280 this_cpu = get_cpu();
281
282 mapping = page_mapping(page);
1da177e4 283 if (mapping && !mapping_mapped(mapping)) {
a9546f59 284 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 285 if (dirty) {
a9546f59
DM		 286 int dirty_cpu = dcache_dirty_cpu(page);
287
1da177e4
LT		 288 if (dirty_cpu == this_cpu)
289 goto out;
290 smp_flush_dcache_page_impl(page, dirty_cpu);
291 }
292 set_dcache_dirty(page, this_cpu);
293 } else {
294 /* We could delay the flush for the !page_mapping
295 * case too. But that case is for exec env/arg
296 * pages and those are %99 certainly going to get
297 * faulted into the tlb (and thus flushed) anyways.
298 */
299 flush_dcache_page_impl(page);
300 }
301
302out:
303 put_cpu();
304}
305
05e14cb3 306void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4
LT		 307{
308 /* Cheetah has coherent I-cache. */
309 if (tlb_type == spitfire) {
310 unsigned long kaddr;
311
312 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
313 __flush_icache_page(__get_phys(kaddr));
314 }
315}
316
317unsigned long page_to_pfn(struct page *page)
318{
319 return (unsigned long) ((page - mem_map) + pfn_base);
320}
321
322struct page *pfn_to_page(unsigned long pfn)
323{
324 return (mem_map + (pfn - pfn_base));
325}
326
327void show_mem(void)
328{
329 printk("Mem-info:\n");
330 show_free_areas();
331 printk("Free swap: %6ldkB\n",
332 nr_swap_pages << (PAGE_SHIFT-10));
333 printk("%ld pages of RAM\n", num_physpages);
334 printk("%d free pages\n", nr_free_pages());
335 printk("%d pages in page table cache\n",pgtable_cache_size);
336}
337
338void mmu_info(struct seq_file *m)
339{
340 if (tlb_type == cheetah)
341 seq_printf(m, "MMU Type\t: Cheetah\n");
342 else if (tlb_type == cheetah_plus)
343 seq_printf(m, "MMU Type\t: Cheetah+\n");
344 else if (tlb_type == spitfire)
345 seq_printf(m, "MMU Type\t: Spitfire\n");
346 else
347 seq_printf(m, "MMU Type\t: ???\n");
348
349#ifdef CONFIG_DEBUG_DCFLUSH
350 seq_printf(m, "DCPageFlushes\t: %d\n",
351 atomic_read(&dcpage_flushes));
352#ifdef CONFIG_SMP
353 seq_printf(m, "DCPageFlushesXC\t: %d\n",
354 atomic_read(&dcpage_flushes_xcall));
355#endif /* CONFIG_SMP */
356#endif /* CONFIG_DEBUG_DCFLUSH */
357}
358
359struct linux_prom_translation {
360 unsigned long virt;
361 unsigned long size;
362 unsigned long data;
363};
b206fc4c 364static struct linux_prom_translation prom_trans[512] __initdata;
1da177e4
LT		 365
366extern unsigned long prom_boot_page;
367extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
368extern int prom_get_mmu_ihandle(void);
369extern void register_prom_callbacks(void);
370
371/* Exported for SMP bootup purposes. */
372unsigned long kern_locked_tte_data;
373
1ac4f5eb
DM		 374/* Exported for kernel TLB miss handling in ktlb.S */
375unsigned long prom_pmd_phys __read_mostly;
376unsigned int swapper_pgd_zero __read_mostly;
377
5085b4a5
DM		 378/* Allocate power-of-2 aligned chunks from the end of the
379 * kernel image. Return physical address.
380 */
381static inline unsigned long early_alloc_phys(unsigned long size)
1da177e4 382{
5085b4a5
DM		 383 unsigned long base;
384
385 BUILD_BUG_ON(size & (size - 1));
386
387 kern_size = (kern_size + (size - 1)) & ~(size - 1);
388 base = kern_base + kern_size;
389 kern_size += size;
390
391 return base;
392}
393
394static inline unsigned long load_phys32(unsigned long pa)
395{
396 unsigned long val;
397
398 __asm__ __volatile__("lduwa [%1] %2, %0"
399 : "=&r" (val)
400 : "r" (pa), "i" (ASI_PHYS_USE_EC));
401
402 return val;
403}
404
405static inline unsigned long load_phys64(unsigned long pa)
406{
407 unsigned long val;
408
409 __asm__ __volatile__("ldxa [%1] %2, %0"
410 : "=&r" (val)
411 : "r" (pa), "i" (ASI_PHYS_USE_EC));
412
413 return val;
414}
415
416static inline void store_phys32(unsigned long pa, unsigned long val)
417{
418 __asm__ __volatile__("stwa %0, [%1] %2"
419 : /* no outputs */
420 : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
421}
422
423static inline void store_phys64(unsigned long pa, unsigned long val)
424{
425 __asm__ __volatile__("stxa %0, [%1] %2"
426 : /* no outputs */
427 : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
1da177e4
LT		 428}
429
430#define BASE_PAGE_SIZE 8192
1da177e4
LT		 431
432/*
433 * Translate PROM's mapping we capture at boot time into physical address.
434 * The second parameter is only set from prom_callback() invocations.
435 */
436unsigned long prom_virt_to_phys(unsigned long promva, int *error)
437{
5085b4a5
DM		 438 unsigned long pmd_phys = (prom_pmd_phys +
439 ((promva >> 23) & 0x7ff) * sizeof(pmd_t));
440 unsigned long pte_phys;
441 pmd_t pmd_ent;
442 pte_t pte_ent;
1da177e4
LT		 443 unsigned long base;
444
5085b4a5
DM		 445 pmd_val(pmd_ent) = load_phys32(pmd_phys);
446 if (pmd_none(pmd_ent)) {
1da177e4
LT		 447 if (error)
448 *error = 1;
5085b4a5 449 return 0;
1da177e4 450 }
5085b4a5
DM		 451
452 pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
453 pte_phys += ((promva >> 13) & 0x3ff) * sizeof(pte_t);
454 pte_val(pte_ent) = load_phys64(pte_phys);
455 if (!pte_present(pte_ent)) {
1da177e4
LT		 456 if (error)
457 *error = 1;
5085b4a5 458 return 0;
1da177e4
LT		 459 }
460 if (error) {
461 *error = 0;
5085b4a5 462 return pte_val(pte_ent);
1da177e4 463 }
5085b4a5
DM		 464 base = pte_val(pte_ent) & _PAGE_PADDR;
465 return (base + (promva & (BASE_PAGE_SIZE - 1)));
405599bd
DM		 466}
467
468/* The obp translations are saved based on 8k pagesize, since obp can
469 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
470 * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
471 * scheme (also, see rant in inherit_locked_prom_mappings()).
472 */
898cf0ec 473static void __init build_obp_range(unsigned long start, unsigned long end, unsigned long data)
405599bd
DM		 474{
475 unsigned long vaddr;
476
477 for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
5085b4a5
DM		 478 unsigned long val, pte_phys, pmd_phys;
479 pmd_t pmd_ent;
480 int i;
481
482 pmd_phys = (prom_pmd_phys +
483 (((vaddr >> 23) & 0x7ff) * sizeof(pmd_t)));
484 pmd_val(pmd_ent) = load_phys32(pmd_phys);
485 if (pmd_none(pmd_ent)) {
486 pte_phys = early_alloc_phys(BASE_PAGE_SIZE);
487
488 for (i = 0; i < BASE_PAGE_SIZE / sizeof(pte_t); i++)
489 store_phys64(pte_phys+i*sizeof(pte_t),0);
490
491 pmd_val(pmd_ent) = pte_phys >> 11UL;
492 store_phys32(pmd_phys, pmd_val(pmd_ent));
405599bd 493 }
5085b4a5
DM		 494
495 pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
496 pte_phys += (((vaddr >> 13) & 0x3ff) * sizeof(pte_t));
405599bd
DM		 497
498 val = data;
499
500 /* Clear diag TTE bits. */
501 if (tlb_type == spitfire)
502 val &= ~0x0003fe0000000000UL;
503
5085b4a5
DM		 504 store_phys64(pte_phys, val | _PAGE_MODIFIED);
505
405599bd
DM		 506 data += BASE_PAGE_SIZE;
507 }
508}
509
5085b4a5
DM		 510static inline int in_obp_range(unsigned long vaddr)
511{
512 return (vaddr >= LOW_OBP_ADDRESS &&
513 vaddr < HI_OBP_ADDRESS);
514}
515
405599bd 516#define OBP_PMD_SIZE 2048
898cf0ec 517static void __init build_obp_pgtable(int prom_trans_ents)
405599bd 518{
5085b4a5
DM		 519 unsigned long i;
520
521 prom_pmd_phys = early_alloc_phys(OBP_PMD_SIZE);
522 for (i = 0; i < OBP_PMD_SIZE; i += 4)
523 store_phys32(prom_pmd_phys + i, 0);
405599bd 524
405599bd
DM		 525 for (i = 0; i < prom_trans_ents; i++) {
526 unsigned long start, end;
527
528 if (!in_obp_range(prom_trans[i].virt))
529 continue;
530
531 start = prom_trans[i].virt;
532 end = start + prom_trans[i].size;
533 if (end > HI_OBP_ADDRESS)
534 end = HI_OBP_ADDRESS;
535
536 build_obp_range(start, end, prom_trans[i].data);
537 }
405599bd
DM		 538}
539
540/* Read OBP translations property into 'prom_trans[]'.
541 * Return the number of entries.
542 */
898cf0ec 543static int __init read_obp_translations(void)
405599bd
DM		 544{
545 int n, node;
1da177e4
LT		 546
547 node = prom_finddevice("/virtual-memory");
548 n = prom_getproplen(node, "translations");
405599bd 549 if (unlikely(n == 0 || n == -1)) {
b206fc4c 550 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 551 prom_halt();
552 }
405599bd
DM		 553 if (unlikely(n > sizeof(prom_trans))) {
554 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 555 prom_halt();
556 }
405599bd 557
b206fc4c 558 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 559 (char *)&prom_trans[0],
560 sizeof(prom_trans))) == -1) {
b206fc4c 561 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 562 prom_halt();
563 }
b206fc4c 564 n = n / sizeof(struct linux_prom_translation);
405599bd
DM		 565 return n;
566}
1da177e4 567
898cf0ec 568static void __init remap_kernel(void)
405599bd
DM		 569{
570 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 571 int tlb_ent = sparc64_highest_locked_tlbent();
572
1da177e4 573 tte_vaddr = (unsigned long) KERNBASE;
bff06d55
DM		 574 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
575 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
576 _PAGE_CP | _PAGE_CV | _PAGE_P |
577 _PAGE_L | _PAGE_W));
1da177e4
LT		 578
579 kern_locked_tte_data = tte_data;
580
bff06d55 581 /* Now lock us into the TLBs via OBP. */
405599bd
DM		 582 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
583 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
1da177e4 584 if (bigkernel) {
405599bd
DM		 585 prom_dtlb_load(tlb_ent - 1,
586 tte_data + 0x400000,
587 tte_vaddr + 0x400000);
588 prom_itlb_load(tlb_ent - 1,
589 tte_data + 0x400000,
590 tte_vaddr + 0x400000);
1da177e4 591 }
405599bd 592}
1da177e4 593
898cf0ec 594static void __init inherit_prom_mappings(void)
405599bd
DM		 595{
596 int n;
597
598 n = read_obp_translations();
599 build_obp_pgtable(n);
600
601 /* Now fixup OBP's idea about where we really are mapped. */
602 prom_printf("Remapping the kernel... ");
603 remap_kernel();
604
1da177e4
LT		 605 prom_printf("done.\n");
606
607 register_prom_callbacks();
608}
609
610/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
611 * upwards as reserved for use by the firmware (I wonder if this
612 * will be the same on Cheetah...). We use this virtual address
613 * range for the VPTE table mappings of the nucleus so we need
614 * to zap them when we enter the PROM. -DaveM
615 */
616static void __flush_nucleus_vptes(void)
617{
618 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
619 int i;
620
621 /* Only DTLB must be checked for VPTE entries. */
622 if (tlb_type == spitfire) {
623 for (i = 0; i < 63; i++) {
624 unsigned long tag;
625
626 /* Spitfire Errata #32 workaround */
627 /* NOTE: Always runs on spitfire, so no cheetah+
628 * page size encodings.
629 */
630 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
631 "flush %%g6"
632 : /* No outputs */
633 : "r" (0),
634 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
635
636 tag = spitfire_get_dtlb_tag(i);
637 if (((tag & ~(PAGE_MASK)) == 0) &&
638 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
639 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
640 "membar #Sync"
641 : /* no outputs */
642 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
643 spitfire_put_dtlb_data(i, 0x0UL);
644 }
645 }
646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 for (i = 0; i < 512; i++) {
648 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
649
650 if ((tag & ~PAGE_MASK) == 0 &&
651 (tag & PAGE_MASK) >= prom_reserved_base) {
652 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
653 "membar #Sync"
654 : /* no outputs */
655 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
656 cheetah_put_dtlb_data(i, 0x0UL, 2);
657 }
658
659 if (tlb_type != cheetah_plus)
660 continue;
661
662 tag = cheetah_get_dtlb_tag(i, 3);
663
664 if ((tag & ~PAGE_MASK) == 0 &&
665 (tag & PAGE_MASK) >= prom_reserved_base) {
666 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
667 "membar #Sync"
668 : /* no outputs */
669 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
670 cheetah_put_dtlb_data(i, 0x0UL, 3);
671 }
672 }
673 } else {
674 /* Implement me :-) */
675 BUG();
676 }
677}
678
679static int prom_ditlb_set;
680struct prom_tlb_entry {
681 int tlb_ent;
682 unsigned long tlb_tag;
683 unsigned long tlb_data;
684};
685struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
686
687void prom_world(int enter)
688{
689 unsigned long pstate;
690 int i;
691
692 if (!enter)
693 set_fs((mm_segment_t) { get_thread_current_ds() });
694
695 if (!prom_ditlb_set)
696 return;
697
698 /* Make sure the following runs atomically. */
699 __asm__ __volatile__("flushw\n\t"
700 "rdpr %%pstate, %0\n\t"
701 "wrpr %0, %1, %%pstate"
702 : "=r" (pstate)
703 : "i" (PSTATE_IE));
704
705 if (enter) {
706 /* Kick out nucleus VPTEs. */
707 __flush_nucleus_vptes();
708
709 /* Install PROM world. */
710 for (i = 0; i < 16; i++) {
711 if (prom_dtlb[i].tlb_ent != -1) {
712 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
713 "membar #Sync"
714 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
715 "i" (ASI_DMMU));
716 if (tlb_type == spitfire)
717 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
718 prom_dtlb[i].tlb_data);
719 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
720 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
721 prom_dtlb[i].tlb_data);
722 }
723 if (prom_itlb[i].tlb_ent != -1) {
724 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
725 "membar #Sync"
726 : : "r" (prom_itlb[i].tlb_tag),
727 "r" (TLB_TAG_ACCESS),
728 "i" (ASI_IMMU));
729 if (tlb_type == spitfire)
730 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
731 prom_itlb[i].tlb_data);
732 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
733 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
734 prom_itlb[i].tlb_data);
735 }
736 }
737 } else {
738 for (i = 0; i < 16; i++) {
739 if (prom_dtlb[i].tlb_ent != -1) {
740 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
741 "membar #Sync"
742 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
743 if (tlb_type == spitfire)
744 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
745 else
746 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
747 }
748 if (prom_itlb[i].tlb_ent != -1) {
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
750 "membar #Sync"
751 : : "r" (TLB_TAG_ACCESS),
752 "i" (ASI_IMMU));
753 if (tlb_type == spitfire)
754 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
755 else
756 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
757 }
758 }
759 }
760 __asm__ __volatile__("wrpr %0, 0, %%pstate"
761 : : "r" (pstate));
762}
763
764void inherit_locked_prom_mappings(int save_p)
765{
766 int i;
767 int dtlb_seen = 0;
768 int itlb_seen = 0;
769
770 /* Fucking losing PROM has more mappings in the TLB, but
771 * it (conveniently) fails to mention any of these in the
772 * translations property. The only ones that matter are
773 * the locked PROM tlb entries, so we impose the following
774 * irrecovable rule on the PROM, it is allowed 8 locked
775 * entries in the ITLB and 8 in the DTLB.
776 *
777 * Supposedly the upper 16GB of the address space is
778 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
779 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
780 * used between the client program and the firmware on sun5
781 * systems to coordinate mmu mappings is also COMPLETELY
782 * UNDOCUMENTED!!!!!! Thanks S(t)un!
783 */
784 if (save_p) {
785 for (i = 0; i < 16; i++) {
786 prom_itlb[i].tlb_ent = -1;
787 prom_dtlb[i].tlb_ent = -1;
788 }
789 }
790 if (tlb_type == spitfire) {
791 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
792 for (i = 0; i < high; i++) {
793 unsigned long data;
794
795 /* Spitfire Errata #32 workaround */
796 /* NOTE: Always runs on spitfire, so no cheetah+
797 * page size encodings.
798 */
799 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
800 "flush %%g6"
801 : /* No outputs */
802 : "r" (0),
803 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
804
805 data = spitfire_get_dtlb_data(i);
806 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
807 unsigned long tag;
808
809 /* Spitfire Errata #32 workaround */
810 /* NOTE: Always runs on spitfire, so no
811 * cheetah+ page size encodings.
812 */
813 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
814 "flush %%g6"
815 : /* No outputs */
816 : "r" (0),
817 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
818
819 tag = spitfire_get_dtlb_tag(i);
820 if (save_p) {
821 prom_dtlb[dtlb_seen].tlb_ent = i;
822 prom_dtlb[dtlb_seen].tlb_tag = tag;
823 prom_dtlb[dtlb_seen].tlb_data = data;
824 }
825 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
826 "membar #Sync"
827 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
828 spitfire_put_dtlb_data(i, 0x0UL);
829
830 dtlb_seen++;
831 if (dtlb_seen > 15)
832 break;
833 }
834 }
835
836 for (i = 0; i < high; i++) {
837 unsigned long data;
838
839 /* Spitfire Errata #32 workaround */
840 /* NOTE: Always runs on spitfire, so no
841 * cheetah+ page size encodings.
842 */
843 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
844 "flush %%g6"
845 : /* No outputs */
846 : "r" (0),
847 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
848
849 data = spitfire_get_itlb_data(i);
850 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
851 unsigned long tag;
852
853 /* Spitfire Errata #32 workaround */
854 /* NOTE: Always runs on spitfire, so no
855 * cheetah+ page size encodings.
856 */
857 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
858 "flush %%g6"
859 : /* No outputs */
860 : "r" (0),
861 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
862
863 tag = spitfire_get_itlb_tag(i);
864 if (save_p) {
865 prom_itlb[itlb_seen].tlb_ent = i;
866 prom_itlb[itlb_seen].tlb_tag = tag;
867 prom_itlb[itlb_seen].tlb_data = data;
868 }
869 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
870 "membar #Sync"
871 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
872 spitfire_put_itlb_data(i, 0x0UL);
873
874 itlb_seen++;
875 if (itlb_seen > 15)
876 break;
877 }
878 }
879 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
880 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
881
882 for (i = 0; i < high; i++) {
883 unsigned long data;
884
885 data = cheetah_get_ldtlb_data(i);
886 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
887 unsigned long tag;
888
889 tag = cheetah_get_ldtlb_tag(i);
890 if (save_p) {
891 prom_dtlb[dtlb_seen].tlb_ent = i;
892 prom_dtlb[dtlb_seen].tlb_tag = tag;
893 prom_dtlb[dtlb_seen].tlb_data = data;
894 }
895 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
896 "membar #Sync"
897 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
898 cheetah_put_ldtlb_data(i, 0x0UL);
899
900 dtlb_seen++;
901 if (dtlb_seen > 15)
902 break;
903 }
904 }
905
906 for (i = 0; i < high; i++) {
907 unsigned long data;
908
909 data = cheetah_get_litlb_data(i);
910 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
911 unsigned long tag;
912
913 tag = cheetah_get_litlb_tag(i);
914 if (save_p) {
915 prom_itlb[itlb_seen].tlb_ent = i;
916 prom_itlb[itlb_seen].tlb_tag = tag;
917 prom_itlb[itlb_seen].tlb_data = data;
918 }
919 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
920 "membar #Sync"
921 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
922 cheetah_put_litlb_data(i, 0x0UL);
923
924 itlb_seen++;
925 if (itlb_seen > 15)
926 break;
927 }
928 }
929 } else {
930 /* Implement me :-) */
931 BUG();
932 }
933 if (save_p)
934 prom_ditlb_set = 1;
935}
936
937/* Give PROM back his world, done during reboots... */
938void prom_reload_locked(void)
939{
940 int i;
941
942 for (i = 0; i < 16; i++) {
943 if (prom_dtlb[i].tlb_ent != -1) {
944 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
945 "membar #Sync"
946 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
947 "i" (ASI_DMMU));
948 if (tlb_type == spitfire)
949 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
950 prom_dtlb[i].tlb_data);
951 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
952 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
953 prom_dtlb[i].tlb_data);
954 }
955
956 if (prom_itlb[i].tlb_ent != -1) {
957 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
958 "membar #Sync"
959 : : "r" (prom_itlb[i].tlb_tag),
960 "r" (TLB_TAG_ACCESS),
961 "i" (ASI_IMMU));
962 if (tlb_type == spitfire)
963 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
964 prom_itlb[i].tlb_data);
965 else
966 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
967 prom_itlb[i].tlb_data);
968 }
969 }
970}
971
972#ifdef DCACHE_ALIASING_POSSIBLE
973void __flush_dcache_range(unsigned long start, unsigned long end)
974{
975 unsigned long va;
976
977 if (tlb_type == spitfire) {
978 int n = 0;
979
980 for (va = start; va < end; va += 32) {
981 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
982 if (++n >= 512)
983 break;
984 }
985 } else {
986 start = __pa(start);
987 end = __pa(end);
988 for (va = start; va < end; va += 32)
989 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
990 "membar #Sync"
991 : /* no outputs */
992 : "r" (va),
993 "i" (ASI_DCACHE_INVALIDATE));
994 }
995}
996#endif /* DCACHE_ALIASING_POSSIBLE */
997
998/* If not locked, zap it. */
999void __flush_tlb_all(void)
1000{
1001 unsigned long pstate;
1002 int i;
1003
1004 __asm__ __volatile__("flushw\n\t"
1005 "rdpr %%pstate, %0\n\t"
1006 "wrpr %0, %1, %%pstate"
1007 : "=r" (pstate)
1008 : "i" (PSTATE_IE));
1009 if (tlb_type == spitfire) {
1010 for (i = 0; i < 64; i++) {
1011 /* Spitfire Errata #32 workaround */
1012 /* NOTE: Always runs on spitfire, so no
1013 * cheetah+ page size encodings.
1014 */
1015 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1016 "flush %%g6"
1017 : /* No outputs */
1018 : "r" (0),
1019 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1020
1021 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1022 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1023 "membar #Sync"
1024 : /* no outputs */
1025 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1026 spitfire_put_dtlb_data(i, 0x0UL);
1027 }
1028
1029 /* Spitfire Errata #32 workaround */
1030 /* NOTE: Always runs on spitfire, so no
1031 * cheetah+ page size encodings.
1032 */
1033 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1034 "flush %%g6"
1035 : /* No outputs */
1036 : "r" (0),
1037 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1038
1039 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1040 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1041 "membar #Sync"
1042 : /* no outputs */
1043 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1044 spitfire_put_itlb_data(i, 0x0UL);
1045 }
1046 }
1047 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1048 cheetah_flush_dtlb_all();
1049 cheetah_flush_itlb_all();
1050 }
1051 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1052 : : "r" (pstate));
1053}
1054
1055/* Caller does TLB context flushing on local CPU if necessary.
1056 * The caller also ensures that CTX_VALID(mm->context) is false.
1057 *
1058 * We must be careful about boundary cases so that we never
1059 * let the user have CTX 0 (nucleus) or we ever use a CTX
1060 * version of zero (and thus NO_CONTEXT would not be caught
1061 * by version mis-match tests in mmu_context.h).
1062 */
1063void get_new_mmu_context(struct mm_struct *mm)
1064{
1065 unsigned long ctx, new_ctx;
1066 unsigned long orig_pgsz_bits;
1067
1068
1069 spin_lock(&ctx_alloc_lock);
1070 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1071 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1072 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1073 if (new_ctx >= (1 << CTX_NR_BITS)) {
1074 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1075 if (new_ctx >= ctx) {
1076 int i;
1077 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1078 CTX_FIRST_VERSION;
1079 if (new_ctx == 1)
1080 new_ctx = CTX_FIRST_VERSION;
1081
1082 /* Don't call memset, for 16 entries that's just
1083 * plain silly...
1084 */
1085 mmu_context_bmap[0] = 3;
1086 mmu_context_bmap[1] = 0;
1087 mmu_context_bmap[2] = 0;
1088 mmu_context_bmap[3] = 0;
1089 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1090 mmu_context_bmap[i + 0] = 0;
1091 mmu_context_bmap[i + 1] = 0;
1092 mmu_context_bmap[i + 2] = 0;
1093 mmu_context_bmap[i + 3] = 0;
1094 }
1095 goto out;
1096 }
1097 }
1098 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1099 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1100out:
1101 tlb_context_cache = new_ctx;
1102 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1103 spin_unlock(&ctx_alloc_lock);
1104}
1105
1106#ifndef CONFIG_SMP
1107struct pgtable_cache_struct pgt_quicklists;
1108#endif
1109
1110/* OK, we have to color these pages. The page tables are accessed
1111 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1112 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1113 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1114 * fast handlers do not get data from old/garbage dcache lines that
1115 * correspond to an old/stale virtual address (user/kernel) that
1116 * previously mapped the pagetable page while accessing vpte range
1117 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1118 * color is the same, then when the kernel initializes the pagetable
1119 * using the later address range, accesses with the first address
1120 * range will see the newly initialized data rather than the garbage.
1121 */
1122#ifdef DCACHE_ALIASING_POSSIBLE
1123#define DC_ALIAS_SHIFT 1
1124#else
1125#define DC_ALIAS_SHIFT 0
1126#endif
8edf72eb 1127pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1da177e4
LT		 1128{
1129 struct page *page;
1130 unsigned long color;
1131
1132 {
1133 pte_t *ptep = pte_alloc_one_fast(mm, address);
1134
1135 if (ptep)
1136 return ptep;
1137 }
1138
1139 color = VPTE_COLOR(address);
1140 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1141 if (page) {
1142 unsigned long *to_free;
1143 unsigned long paddr;
1144 pte_t *pte;
1145
1146#ifdef DCACHE_ALIASING_POSSIBLE
1147 set_page_count(page, 1);
1148 ClearPageCompound(page);
1149
1150 set_page_count((page + 1), 1);
1151 ClearPageCompound(page + 1);
1152#endif
1153 paddr = (unsigned long) page_address(page);
1154 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1155
1156 if (!color) {
1157 pte = (pte_t *) paddr;
1158 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1159 } else {
1160 pte = (pte_t *) (paddr + PAGE_SIZE);
1161 to_free = (unsigned long *) paddr;
1162 }
1163
1164#ifdef DCACHE_ALIASING_POSSIBLE
1165 /* Now free the other one up, adjust cache size. */
1166 preempt_disable();
1167 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1168 pte_quicklist[color ^ 0x1] = to_free;
1169 pgtable_cache_size++;
1170 preempt_enable();
1171#endif
1172
1173 return pte;
1174 }
1175 return NULL;
1176}
1177
1178void sparc_ultra_dump_itlb(void)
1179{
1180 int slot;
1181
1182 if (tlb_type == spitfire) {
1183 printk ("Contents of itlb: ");
1184 for (slot = 0; slot < 14; slot++) printk (" ");
1185 printk ("%2x:%016lx,%016lx\n",
1186 0,
1187 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1188 for (slot = 1; slot < 64; slot+=3) {
1189 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1190 slot,
1191 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1192 slot+1,
1193 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1194 slot+2,
1195 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1196 }
1197 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1198 printk ("Contents of itlb0:\n");
1199 for (slot = 0; slot < 16; slot+=2) {
1200 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1201 slot,
1202 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1203 slot+1,
1204 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1205 }
1206 printk ("Contents of itlb2:\n");
1207 for (slot = 0; slot < 128; slot+=2) {
1208 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1209 slot,
1210 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1211 slot+1,
1212 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1213 }
1214 }
1215}
1216
1217void sparc_ultra_dump_dtlb(void)
1218{
1219 int slot;
1220
1221 if (tlb_type == spitfire) {
1222 printk ("Contents of dtlb: ");
1223 for (slot = 0; slot < 14; slot++) printk (" ");
1224 printk ("%2x:%016lx,%016lx\n", 0,
1225 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1226 for (slot = 1; slot < 64; slot+=3) {
1227 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1228 slot,
1229 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1230 slot+1,
1231 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1232 slot+2,
1233 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1234 }
1235 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1236 printk ("Contents of dtlb0:\n");
1237 for (slot = 0; slot < 16; slot+=2) {
1238 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1239 slot,
1240 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1241 slot+1,
1242 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1243 }
1244 printk ("Contents of dtlb2:\n");
1245 for (slot = 0; slot < 512; slot+=2) {
1246 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1247 slot,
1248 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1249 slot+1,
1250 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1251 }
1252 if (tlb_type == cheetah_plus) {
1253 printk ("Contents of dtlb3:\n");
1254 for (slot = 0; slot < 512; slot+=2) {
1255 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1256 slot,
1257 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1258 slot+1,
1259 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1260 }
1261 }
1262 }
1263}
1264
1265extern unsigned long cmdline_memory_size;
1266
1267unsigned long __init bootmem_init(unsigned long *pages_avail)
1268{
1269 unsigned long bootmap_size, start_pfn, end_pfn;
1270 unsigned long end_of_phys_memory = 0UL;
1271 unsigned long bootmap_pfn, bytes_avail, size;
1272 int i;
1273
1274#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 1275 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 1276#endif
1277
1278 bytes_avail = 0UL;
13edad7a
DM		 1279 for (i = 0; i < pavail_ents; i++) {
1280 end_of_phys_memory = pavail[i].phys_addr +
1281 pavail[i].reg_size;
1282 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 1283 if (cmdline_memory_size) {
1284 if (bytes_avail > cmdline_memory_size) {
1285 unsigned long slack = bytes_avail - cmdline_memory_size;
1286
1287 bytes_avail -= slack;
1288 end_of_phys_memory -= slack;
1289
13edad7a
DM		 1290 pavail[i].reg_size -= slack;
1291 if ((long)pavail[i].reg_size <= 0L) {
1292 pavail[i].phys_addr = 0xdeadbeefUL;
1293 pavail[i].reg_size = 0UL;
1294 pavail_ents = i;
1da177e4 1295 } else {
13edad7a
DM		 1296 pavail[i+1].reg_size = 0Ul;
1297 pavail[i+1].phys_addr = 0xdeadbeefUL;
1298 pavail_ents = i + 1;
1da177e4
LT		 1299 }
1300 break;
1301 }
1302 }
1303 }
1304
1305 *pages_avail = bytes_avail >> PAGE_SHIFT;
1306
1307 /* Start with page aligned address of last symbol in kernel
1308 * image. The kernel is hard mapped below PAGE_OFFSET in a
1309 * 4MB locked TLB translation.
1310 */
1311 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1312
1313 bootmap_pfn = start_pfn;
1314
1315 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1316
1317#ifdef CONFIG_BLK_DEV_INITRD
1318 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1319 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1320 unsigned long ramdisk_image = sparc_ramdisk_image ?
1321 sparc_ramdisk_image : sparc_ramdisk_image64;
1322 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1323 ramdisk_image -= KERNBASE;
1324 initrd_start = ramdisk_image + phys_base;
1325 initrd_end = initrd_start + sparc_ramdisk_size;
1326 if (initrd_end > end_of_phys_memory) {
1327 printk(KERN_CRIT "initrd extends beyond end of memory "
1328 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1329 initrd_end, end_of_phys_memory);
1330 initrd_start = 0;
1331 }
1332 if (initrd_start) {
1333 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1334 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1335 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1336 }
1337 }
1338#endif
1339 /* Initialize the boot-time allocator. */
1340 max_pfn = max_low_pfn = end_pfn;
1341 min_low_pfn = pfn_base;
1342
1343#ifdef CONFIG_DEBUG_BOOTMEM
1344 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1345 min_low_pfn, bootmap_pfn, max_low_pfn);
1346#endif
1347 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1348
1da177e4
LT		 1349 /* Now register the available physical memory with the
1350 * allocator.
1351 */
13edad7a 1352 for (i = 0; i < pavail_ents; i++) {
1da177e4 1353#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 1354 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1355 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 1356#endif
13edad7a 1357 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 1358 }
1359
1360#ifdef CONFIG_BLK_DEV_INITRD
1361 if (initrd_start) {
1362 size = initrd_end - initrd_start;
1363
1364 /* Resert the initrd image area. */
1365#ifdef CONFIG_DEBUG_BOOTMEM
1366 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1367 initrd_start, initrd_end);
1368#endif
1369 reserve_bootmem(initrd_start, size);
1370 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1371
1372 initrd_start += PAGE_OFFSET;
1373 initrd_end += PAGE_OFFSET;
1374 }
1375#endif
1376 /* Reserve the kernel text/data/bss. */
1377#ifdef CONFIG_DEBUG_BOOTMEM
1378 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1379#endif
1380 reserve_bootmem(kern_base, kern_size);
1381 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1382
1383 /* Reserve the bootmem map. We do not account for it
1384 * in pages_avail because we will release that memory
1385 * in free_all_bootmem.
1386 */
1387 size = bootmap_size;
1388#ifdef CONFIG_DEBUG_BOOTMEM
1389 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1390 (bootmap_pfn << PAGE_SHIFT), size);
1391#endif
1392 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1393 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1394
1395 return end_pfn;
1396}
1397
56425306
DM		 1398#ifdef CONFIG_DEBUG_PAGEALLOC
1399static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1400{
1401 unsigned long vstart = PAGE_OFFSET + pstart;
1402 unsigned long vend = PAGE_OFFSET + pend;
1403 unsigned long alloc_bytes = 0UL;
1404
1405 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1406 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1407 vstart, vend);
1408 prom_halt();
1409 }
1410
1411 while (vstart < vend) {
1412 unsigned long this_end, paddr = __pa(vstart);
1413 pgd_t *pgd = pgd_offset_k(vstart);
1414 pud_t *pud;
1415 pmd_t *pmd;
1416 pte_t *pte;
1417
1418 pud = pud_offset(pgd, vstart);
1419 if (pud_none(*pud)) {
1420 pmd_t *new;
1421
1422 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1423 alloc_bytes += PAGE_SIZE;
1424 pud_populate(&init_mm, pud, new);
1425 }
1426
1427 pmd = pmd_offset(pud, vstart);
1428 if (!pmd_present(*pmd)) {
1429 pte_t *new;
1430
1431 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1432 alloc_bytes += PAGE_SIZE;
1433 pmd_populate_kernel(&init_mm, pmd, new);
1434 }
1435
1436 pte = pte_offset_kernel(pmd, vstart);
1437 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1438 if (this_end > vend)
1439 this_end = vend;
1440
1441 while (vstart < this_end) {
1442 pte_val(*pte) = (paddr | pgprot_val(prot));
1443
1444 vstart += PAGE_SIZE;
1445 paddr += PAGE_SIZE;
1446 pte++;
1447 }
1448 }
1449
1450 return alloc_bytes;
1451}
1452
13edad7a
DM		 1453static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1454static int pall_ents __initdata;
1455
56425306
DM		 1456extern unsigned int kvmap_linear_patch[1];
1457
1458static void __init kernel_physical_mapping_init(void)
1459{
13edad7a 1460 unsigned long i, mem_alloced = 0UL;
56425306 1461
13edad7a
DM		 1462 read_obp_memory("reg", &pall[0], &pall_ents);
1463
1464 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1465 unsigned long phys_start, phys_end;
1466
13edad7a
DM		 1467 phys_start = pall[i].phys_addr;
1468 phys_end = phys_start + pall[i].reg_size;
56425306
DM		 1469 mem_alloced += kernel_map_range(phys_start, phys_end,
1470 PAGE_KERNEL);
56425306
DM		 1471 }
1472
1473 printk("Allocated %ld bytes for kernel page tables.\n",
1474 mem_alloced);
1475
1476 kvmap_linear_patch[0] = 0x01000000; /* nop */
1477 flushi(&kvmap_linear_patch[0]);
1478
1479 __flush_tlb_all();
1480}
1481
1482void kernel_map_pages(struct page *page, int numpages, int enable)
1483{
1484 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1485 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1486
1487 kernel_map_range(phys_start, phys_end,
1488 (enable ? PAGE_KERNEL : __pgprot(0)));
1489
1490 /* we should perform an IPI and flush all tlbs,
1491 * but that can deadlock->flush only current cpu.
1492 */
1493 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1494 PAGE_OFFSET + phys_end);
1495}
1496#endif
1497
10147570
DM		 1498unsigned long __init find_ecache_flush_span(unsigned long size)
1499{
0836a0eb
DM		 1500 int i;
1501
13edad7a
DM		 1502 for (i = 0; i < pavail_ents; i++) {
1503 if (pavail[i].reg_size >= size)
1504 return pavail[i].phys_addr;
0836a0eb
DM		 1505 }
1506
13edad7a 1507 return ~0UL;
0836a0eb
DM		 1508}
1509
1da177e4
LT		 1510/* paging_init() sets up the page tables */
1511
1512extern void cheetah_ecache_flush_init(void);
1513
1514static unsigned long last_valid_pfn;
56425306 1515pgd_t swapper_pg_dir[2048];
1da177e4
LT		 1516
1517void __init paging_init(void)
1518{
2bdb3cb2 1519 unsigned long end_pfn, pages_avail, shift;
0836a0eb
DM		 1520 unsigned long real_end, i;
1521
13edad7a
DM		 1522 /* Find available physical memory... */
1523 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1524
1525 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1526 for (i = 0; i < pavail_ents; i++)
1527 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1528
0836a0eb
DM		 1529 pfn_base = phys_base >> PAGE_SHIFT;
1530
1531 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1532 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1da177e4
LT		 1533
1534 set_bit(0, mmu_context_bmap);
1535
2bdb3cb2
DM		 1536 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1537
1da177e4
LT		 1538 real_end = (unsigned long)_end;
1539 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1540 bigkernel = 1;
2bdb3cb2
DM		 1541 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1542 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1543 prom_halt();
1da177e4 1544 }
2bdb3cb2
DM		 1545
1546 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1547 * work.
1548 */
1549 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1550
56425306 1551 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1552
1553 /* Now can init the kernel/bad page tables. */
1554 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1555 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1556
2bdb3cb2 1557 swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1da177e4 1558
5085b4a5
DM		 1559 /* Inherit non-locked OBP mappings. */
1560 inherit_prom_mappings();
1561
1da177e4
LT		 1562 /* Ok, we can use our TLB miss and window trap handlers safely.
1563 * We need to do a quick peek here to see if we are on StarFire
1564 * or not, so setup_tba can setup the IRQ globals correctly (it
1565 * needs to get the hard smp processor id correctly).
1566 */
1567 {
1568 extern void setup_tba(int);
1569 setup_tba(this_is_starfire);
1570 }
1571
1572 inherit_locked_prom_mappings(1);
1573
1da177e4
LT		 1574 __flush_tlb_all();
1575
2bdb3cb2
DM		 1576 /* Setup bootmem... */
1577 pages_avail = 0;
1578 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1579
56425306
DM		 1580#ifdef CONFIG_DEBUG_PAGEALLOC
1581 kernel_physical_mapping_init();
1582#endif
1583
1da177e4
LT		 1584 {
1585 unsigned long zones_size[MAX_NR_ZONES];
1586 unsigned long zholes_size[MAX_NR_ZONES];
1587 unsigned long npages;
1588 int znum;
1589
1590 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1591 zones_size[znum] = zholes_size[znum] = 0;
1592
1593 npages = end_pfn - pfn_base;
1594 zones_size[ZONE_DMA] = npages;
1595 zholes_size[ZONE_DMA] = npages - pages_avail;
1596
1597 free_area_init_node(0, &contig_page_data, zones_size,
1598 phys_base >> PAGE_SHIFT, zholes_size);
1599 }
1600
1601 device_scan();
1602}
1603
1da177e4
LT		 1604static void __init taint_real_pages(void)
1605{
1da177e4
LT		 1606 int i;
1607
13edad7a 1608 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1609
13edad7a 1610 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1611 * reserve the lost portions in the bootmem maps.
1612 */
13edad7a 1613 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1614 unsigned long old_start, old_end;
1615
13edad7a 1616 old_start = pavail[i].phys_addr;
1da177e4 1617 old_end = old_start +
13edad7a 1618 pavail[i].reg_size;
1da177e4
LT		 1619 while (old_start < old_end) {
1620 int n;
1621
13edad7a 1622 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1623 unsigned long new_start, new_end;
1624
13edad7a
DM		 1625 new_start = pavail_rescan[n].phys_addr;
1626 new_end = new_start +
1627 pavail_rescan[n].reg_size;
1da177e4
LT		 1628
1629 if (new_start <= old_start &&
1630 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1631 set_bit(old_start >> 22,
1632 sparc64_valid_addr_bitmap);
1da177e4
LT		 1633 goto do_next_page;
1634 }
1635 }
1636 reserve_bootmem(old_start, PAGE_SIZE);
1637
1638 do_next_page:
1639 old_start += PAGE_SIZE;
1640 }
1641 }
1642}
1643
1644void __init mem_init(void)
1645{
1646 unsigned long codepages, datapages, initpages;
1647 unsigned long addr, last;
1648 int i;
1649
1650 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1651 i += 1;
2bdb3cb2 1652 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1653 if (sparc64_valid_addr_bitmap == NULL) {
1654 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1655 prom_halt();
1656 }
1657 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1658
1659 addr = PAGE_OFFSET + kern_base;
1660 last = PAGE_ALIGN(kern_size) + addr;
1661 while (addr < last) {
1662 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1663 addr += PAGE_SIZE;
1664 }
1665
1666 taint_real_pages();
1667
1668 max_mapnr = last_valid_pfn - pfn_base;
1669 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1670
1671#ifdef CONFIG_DEBUG_BOOTMEM
1672 prom_printf("mem_init: Calling free_all_bootmem().\n");
1673#endif
1674 totalram_pages = num_physpages = free_all_bootmem() - 1;
1675
1676 /*
1677 * Set up the zero page, mark it reserved, so that page count
1678 * is not manipulated when freeing the page from user ptes.
1679 */
1680 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1681 if (mem_map_zero == NULL) {
1682 prom_printf("paging_init: Cannot alloc zero page.\n");
1683 prom_halt();
1684 }
1685 SetPageReserved(mem_map_zero);
1686
1687 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1688 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1689 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1690 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1691 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1692 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1693
1694 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1695 nr_free_pages() << (PAGE_SHIFT-10),
1696 codepages << (PAGE_SHIFT-10),
1697 datapages << (PAGE_SHIFT-10),
1698 initpages << (PAGE_SHIFT-10),
1699 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1700
1701 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1702 cheetah_ecache_flush_init();
1703}
1704
898cf0ec 1705void free_initmem(void)
1da177e4
LT		 1706{
1707 unsigned long addr, initend;
1708
1709 /*
1710 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1711 */
1712 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1713 initend = (unsigned long)(__init_end) & PAGE_MASK;
1714 for (; addr < initend; addr += PAGE_SIZE) {
1715 unsigned long page;
1716 struct page *p;
1717
1718 page = (addr +
1719 ((unsigned long) __va(kern_base)) -
1720 ((unsigned long) KERNBASE));
1721 memset((void *)addr, 0xcc, PAGE_SIZE);
1722 p = virt_to_page(page);
1723
1724 ClearPageReserved(p);
1725 set_page_count(p, 1);
1726 __free_page(p);
1727 num_physpages++;
1728 totalram_pages++;
1729 }
1730}
1731
1732#ifdef CONFIG_BLK_DEV_INITRD
1733void free_initrd_mem(unsigned long start, unsigned long end)
1734{
1735 if (start < end)
1736 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1737 for (; start < end; start += PAGE_SIZE) {
1738 struct page *p = virt_to_page(start);
1739
1740 ClearPageReserved(p);
1741 set_page_count(p, 1);
1742 __free_page(p);
1743 num_physpages++;
1744 totalram_pages++;
1745 }
1746}
1747#endif
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