]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/sparc64/mm/init.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SPARC64]: Break up inherit_prom_mappings() into it's constituent parts.
[net-next-2.6.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
1da177e4
LT		 24
25#include <asm/head.h>
26#include <asm/system.h>
27#include <asm/page.h>
28#include <asm/pgalloc.h>
29#include <asm/pgtable.h>
30#include <asm/oplib.h>
31#include <asm/iommu.h>
32#include <asm/io.h>
33#include <asm/uaccess.h>
34#include <asm/mmu_context.h>
35#include <asm/tlbflush.h>
36#include <asm/dma.h>
37#include <asm/starfire.h>
38#include <asm/tlb.h>
39#include <asm/spitfire.h>
40#include <asm/sections.h>
41
42extern void device_scan(void);
43
44struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
45
46unsigned long *sparc64_valid_addr_bitmap;
47
48/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 49unsigned long phys_base __read_mostly;
50unsigned long kern_base __read_mostly;
51unsigned long kern_size __read_mostly;
52unsigned long pfn_base __read_mostly;
1da177e4
LT		 53
54/* This is even uglier. We have a problem where the kernel may not be
55 * located at phys_base. However, initial __alloc_bootmem() calls need to
56 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
57 * those page mappings wont work. Things are ok after inherit_prom_mappings
58 * is called though. Dave says he'll clean this up some other time.
59 * -- BenC
60 */
61static unsigned long bootmap_base;
62
63/* get_new_mmu_context() uses "cache + 1". */
64DEFINE_SPINLOCK(ctx_alloc_lock);
65unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
66#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
67unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
68
69/* References to special section boundaries */
70extern char _start[], _end[];
71
72/* Initial ramdisk setup */
73extern unsigned long sparc_ramdisk_image64;
74extern unsigned int sparc_ramdisk_image;
75extern unsigned int sparc_ramdisk_size;
76
1ac4f5eb 77struct page *mem_map_zero __read_mostly;
1da177e4
LT		 78
79int bigkernel = 0;
80
81/* XXX Tune this... */
82#define PGT_CACHE_LOW 25
83#define PGT_CACHE_HIGH 50
84
85void check_pgt_cache(void)
86{
87 preempt_disable();
88 if (pgtable_cache_size > PGT_CACHE_HIGH) {
89 do {
90 if (pgd_quicklist)
91 free_pgd_slow(get_pgd_fast());
92 if (pte_quicklist[0])
93 free_pte_slow(pte_alloc_one_fast(NULL, 0));
94 if (pte_quicklist[1])
95 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
96 } while (pgtable_cache_size > PGT_CACHE_LOW);
97 }
98 preempt_enable();
99}
100
101#ifdef CONFIG_DEBUG_DCFLUSH
102atomic_t dcpage_flushes = ATOMIC_INIT(0);
103#ifdef CONFIG_SMP
104atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
105#endif
106#endif
107
108__inline__ void flush_dcache_page_impl(struct page *page)
109{
110#ifdef CONFIG_DEBUG_DCFLUSH
111 atomic_inc(&dcpage_flushes);
112#endif
113
114#ifdef DCACHE_ALIASING_POSSIBLE
115 __flush_dcache_page(page_address(page),
116 ((tlb_type == spitfire) &&
117 page_mapping(page) != NULL));
118#else
119 if (page_mapping(page) != NULL &&
120 tlb_type == spitfire)
121 __flush_icache_page(__pa(page_address(page)));
122#endif
123}
124
125#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 126#define PG_dcache_cpu_shift 24
127#define PG_dcache_cpu_mask (256 - 1)
128
129#if NR_CPUS > 256
130#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
131#endif
1da177e4
LT		 132
133#define dcache_dirty_cpu(page) \
48b0e548 134 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 135
136static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
137{
138 unsigned long mask = this_cpu;
48b0e548
DM		 139 unsigned long non_cpu_bits;
140
141 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
142 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
143
1da177e4
LT		 144 __asm__ __volatile__("1:\n\t"
145 "ldx [%2], %%g7\n\t"
146 "and %%g7, %1, %%g1\n\t"
147 "or %%g1, %0, %%g1\n\t"
148 "casx [%2], %%g7, %%g1\n\t"
149 "cmp %%g7, %%g1\n\t"
b445e26c 150 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 151 "bne,pn %%xcc, 1b\n\t"
b445e26c 152 " nop"
1da177e4
LT		 153 : /* no outputs */
154 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
155 : "g1", "g7");
156}
157
158static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
159{
160 unsigned long mask = (1UL << PG_dcache_dirty);
161
162 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
163 "1:\n\t"
164 "ldx [%2], %%g7\n\t"
48b0e548 165 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 166 "and %%g1, %3, %%g1\n\t"
167 "cmp %%g1, %0\n\t"
168 "bne,pn %%icc, 2f\n\t"
169 " andn %%g7, %1, %%g1\n\t"
170 "casx [%2], %%g7, %%g1\n\t"
171 "cmp %%g7, %%g1\n\t"
b445e26c 172 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 173 "bne,pn %%xcc, 1b\n\t"
b445e26c 174 " nop\n"
1da177e4
LT		 175 "2:"
176 : /* no outputs */
177 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 178 "i" (PG_dcache_cpu_mask),
179 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 180 : "g1", "g7");
181}
182
183extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
184
185void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
186{
187 struct page *page;
188 unsigned long pfn;
189 unsigned long pg_flags;
190
191 pfn = pte_pfn(pte);
192 if (pfn_valid(pfn) &&
193 (page = pfn_to_page(pfn), page_mapping(page)) &&
194 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 195 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
196 PG_dcache_cpu_mask);
1da177e4
LT		 197 int this_cpu = get_cpu();
198
199 /* This is just to optimize away some function calls
200 * in the SMP case.
201 */
202 if (cpu == this_cpu)
203 flush_dcache_page_impl(page);
204 else
205 smp_flush_dcache_page_impl(page, cpu);
206
207 clear_dcache_dirty_cpu(page, cpu);
208
209 put_cpu();
210 }
211
212 if (get_thread_fault_code())
213 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
214 address, pte, get_thread_fault_code());
215}
216
217void flush_dcache_page(struct page *page)
218{
a9546f59
DM		 219 struct address_space *mapping;
220 int this_cpu;
1da177e4 221
a9546f59
DM		 222 /* Do not bother with the expensive D-cache flush if it
223 * is merely the zero page. The 'bigcore' testcase in GDB
224 * causes this case to run millions of times.
225 */
226 if (page == ZERO_PAGE(0))
227 return;
228
229 this_cpu = get_cpu();
230
231 mapping = page_mapping(page);
1da177e4 232 if (mapping && !mapping_mapped(mapping)) {
a9546f59 233 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 234 if (dirty) {
a9546f59
DM		 235 int dirty_cpu = dcache_dirty_cpu(page);
236
1da177e4
LT		 237 if (dirty_cpu == this_cpu)
238 goto out;
239 smp_flush_dcache_page_impl(page, dirty_cpu);
240 }
241 set_dcache_dirty(page, this_cpu);
242 } else {
243 /* We could delay the flush for the !page_mapping
244 * case too. But that case is for exec env/arg
245 * pages and those are %99 certainly going to get
246 * faulted into the tlb (and thus flushed) anyways.
247 */
248 flush_dcache_page_impl(page);
249 }
250
251out:
252 put_cpu();
253}
254
05e14cb3 255void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4
LT		 256{
257 /* Cheetah has coherent I-cache. */
258 if (tlb_type == spitfire) {
259 unsigned long kaddr;
260
261 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
262 __flush_icache_page(__get_phys(kaddr));
263 }
264}
265
266unsigned long page_to_pfn(struct page *page)
267{
268 return (unsigned long) ((page - mem_map) + pfn_base);
269}
270
271struct page *pfn_to_page(unsigned long pfn)
272{
273 return (mem_map + (pfn - pfn_base));
274}
275
276void show_mem(void)
277{
278 printk("Mem-info:\n");
279 show_free_areas();
280 printk("Free swap: %6ldkB\n",
281 nr_swap_pages << (PAGE_SHIFT-10));
282 printk("%ld pages of RAM\n", num_physpages);
283 printk("%d free pages\n", nr_free_pages());
284 printk("%d pages in page table cache\n",pgtable_cache_size);
285}
286
287void mmu_info(struct seq_file *m)
288{
289 if (tlb_type == cheetah)
290 seq_printf(m, "MMU Type\t: Cheetah\n");
291 else if (tlb_type == cheetah_plus)
292 seq_printf(m, "MMU Type\t: Cheetah+\n");
293 else if (tlb_type == spitfire)
294 seq_printf(m, "MMU Type\t: Spitfire\n");
295 else
296 seq_printf(m, "MMU Type\t: ???\n");
297
298#ifdef CONFIG_DEBUG_DCFLUSH
299 seq_printf(m, "DCPageFlushes\t: %d\n",
300 atomic_read(&dcpage_flushes));
301#ifdef CONFIG_SMP
302 seq_printf(m, "DCPageFlushesXC\t: %d\n",
303 atomic_read(&dcpage_flushes_xcall));
304#endif /* CONFIG_SMP */
305#endif /* CONFIG_DEBUG_DCFLUSH */
306}
307
308struct linux_prom_translation {
309 unsigned long virt;
310 unsigned long size;
311 unsigned long data;
312};
b206fc4c 313static struct linux_prom_translation prom_trans[512] __initdata;
1da177e4
LT		 314
315extern unsigned long prom_boot_page;
316extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
317extern int prom_get_mmu_ihandle(void);
318extern void register_prom_callbacks(void);
319
320/* Exported for SMP bootup purposes. */
321unsigned long kern_locked_tte_data;
322
1ac4f5eb
DM		 323/* Exported for kernel TLB miss handling in ktlb.S */
324unsigned long prom_pmd_phys __read_mostly;
325unsigned int swapper_pgd_zero __read_mostly;
326
1da177e4
LT		 327void __init early_pgtable_allocfail(char *type)
328{
329 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
330 prom_halt();
331}
332
333#define BASE_PAGE_SIZE 8192
334static pmd_t *prompmd;
335
336/*
337 * Translate PROM's mapping we capture at boot time into physical address.
338 * The second parameter is only set from prom_callback() invocations.
339 */
340unsigned long prom_virt_to_phys(unsigned long promva, int *error)
341{
342 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
343 pte_t *ptep;
344 unsigned long base;
345
346 if (pmd_none(*pmdp)) {
347 if (error)
348 *error = 1;
349 return(0);
350 }
351 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
352 if (!pte_present(*ptep)) {
353 if (error)
354 *error = 1;
355 return(0);
356 }
357 if (error) {
358 *error = 0;
359 return(pte_val(*ptep));
360 }
361 base = pte_val(*ptep) & _PAGE_PADDR;
362 return(base + (promva & (BASE_PAGE_SIZE - 1)));
363}
364
405599bd 365static inline int in_obp_range(unsigned long vaddr)
1da177e4 366{
405599bd
DM		 367 return (vaddr >= LOW_OBP_ADDRESS &&
368 vaddr < HI_OBP_ADDRESS);
369}
370
371/* The obp translations are saved based on 8k pagesize, since obp can
372 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
373 * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
374 * scheme (also, see rant in inherit_locked_prom_mappings()).
375 */
376static void build_obp_range(unsigned long start, unsigned long end, unsigned long data)
377{
378 unsigned long vaddr;
379
380 for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
381 unsigned long val;
382 pmd_t *pmdp;
383 pte_t *ptep;
384
385 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
386 if (pmd_none(*pmdp)) {
387 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
388 BASE_PAGE_SIZE,
389 bootmap_base);
390 if (ptep == NULL)
391 early_pgtable_allocfail("pte");
392 memset(ptep, 0, BASE_PAGE_SIZE);
393 pmd_set(pmdp, ptep);
394 }
395 ptep = (pte_t *)__pmd_page(*pmdp) +
396 ((vaddr >> 13) & 0x3ff);
397
398 val = data;
399
400 /* Clear diag TTE bits. */
401 if (tlb_type == spitfire)
402 val &= ~0x0003fe0000000000UL;
403
404 set_pte_at(&init_mm, vaddr,
405 ptep, __pte(val | _PAGE_MODIFIED));
406 data += BASE_PAGE_SIZE;
407 }
408}
409
410#define OBP_PMD_SIZE 2048
411static void build_obp_pgtable(int prom_trans_ents)
412{
413 int i;
414
415 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE,
416 bootmap_base);
417 if (prompmd == NULL)
418 early_pgtable_allocfail("pmd");
419 memset(prompmd, 0, OBP_PMD_SIZE);
420 for (i = 0; i < prom_trans_ents; i++) {
421 unsigned long start, end;
422
423 if (!in_obp_range(prom_trans[i].virt))
424 continue;
425
426 start = prom_trans[i].virt;
427 end = start + prom_trans[i].size;
428 if (end > HI_OBP_ADDRESS)
429 end = HI_OBP_ADDRESS;
430
431 build_obp_range(start, end, prom_trans[i].data);
432 }
433 prom_pmd_phys = __pa(prompmd);
434}
435
436/* Read OBP translations property into 'prom_trans[]'.
437 * Return the number of entries.
438 */
439static int read_obp_translations(void)
440{
441 int n, node;
1da177e4
LT		 442
443 node = prom_finddevice("/virtual-memory");
444 n = prom_getproplen(node, "translations");
405599bd 445 if (unlikely(n == 0 || n == -1)) {
b206fc4c 446 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 447 prom_halt();
448 }
405599bd
DM		 449 if (unlikely(n > sizeof(prom_trans))) {
450 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 451 prom_halt();
452 }
405599bd 453
b206fc4c 454 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 455 (char *)&prom_trans[0],
456 sizeof(prom_trans))) == -1) {
b206fc4c 457 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 458 prom_halt();
459 }
b206fc4c 460 n = n / sizeof(struct linux_prom_translation);
405599bd
DM		 461 return n;
462}
1da177e4 463
405599bd
DM		 464static inline void early_spitfire_errata32(void)
465{
1da177e4
LT		 466 /* Spitfire Errata #32 workaround */
467 /* NOTE: Using plain zero for the context value is
468 * correct here, we are not using the Linux trap
469 * tables yet so we should not use the special
470 * UltraSPARC-III+ page size encodings yet.
471 */
472 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
473 "flush %%g6"
474 : /* No outputs */
405599bd
DM		 475 : "r" (0), "r" (PRIMARY_CONTEXT),
476 "i" (ASI_DMMU));
477}
1da177e4 478
405599bd
DM		 479static void lock_remap_func_page(unsigned long phys_page)
480{
481 unsigned long tte_data = (phys_page | pgprot_val(PAGE_KERNEL));
1da177e4
LT		 482
483 if (tlb_type == spitfire) {
484 /* Lock this into i/d tlb entry 59 */
485 __asm__ __volatile__(
486 "stxa %%g0, [%2] %3\n\t"
487 "stxa %0, [%1] %4\n\t"
488 "membar #Sync\n\t"
489 "flush %%g6\n\t"
490 "stxa %%g0, [%2] %5\n\t"
491 "stxa %0, [%1] %6\n\t"
492 "membar #Sync\n\t"
493 "flush %%g6"
405599bd
DM		 494 : /* no outputs */
495 : "r" (tte_data), "r" (59 << 3), "r" (TLB_TAG_ACCESS),
496 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
497 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
498 : "memory");
499 } else {
1da177e4
LT		 500 /* Lock this into i/d tlb-0 entry 11 */
501 __asm__ __volatile__(
502 "stxa %%g0, [%2] %3\n\t"
503 "stxa %0, [%1] %4\n\t"
504 "membar #Sync\n\t"
505 "flush %%g6\n\t"
506 "stxa %%g0, [%2] %5\n\t"
507 "stxa %0, [%1] %6\n\t"
508 "membar #Sync\n\t"
509 "flush %%g6"
405599bd
DM		 510 : /* no outputs */
511 : "r" (tte_data), "r" ((0 << 16) | (11 << 3)),
512 "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU),
513 "i" (ASI_DTLB_DATA_ACCESS), "i" (ASI_IMMU),
514 "i" (ASI_ITLB_DATA_ACCESS)
1da177e4 515 : "memory");
1da177e4 516 }
405599bd
DM		 517}
518
519static void remap_kernel(void)
520{
521 unsigned long phys_page, tte_vaddr, tte_data;
522 void (*remap_func)(unsigned long, unsigned long, int);
523 int tlb_ent = sparc64_highest_locked_tlbent();
524
525 early_spitfire_errata32();
526
527 if (tlb_type == spitfire)
528 phys_page = spitfire_get_dtlb_data(tlb_ent);
529 else
530 phys_page = cheetah_get_ldtlb_data(tlb_ent);
531
532 phys_page &= _PAGE_PADDR;
533 phys_page += ((unsigned long)&prom_boot_page -
534 (unsigned long)KERNBASE);
535
536 lock_remap_func_page(phys_page);
1da177e4
LT		 537
538 tte_vaddr = (unsigned long) KERNBASE;
539
405599bd 540 early_spitfire_errata32();
1da177e4
LT		 541
542 if (tlb_type == spitfire)
405599bd 543 tte_data = spitfire_get_dtlb_data(tlb_ent);
1da177e4 544 else
405599bd 545 tte_data = cheetah_get_ldtlb_data(tlb_ent);
1da177e4
LT		 546
547 kern_locked_tte_data = tte_data;
548
549 remap_func = (void *) ((unsigned long) &prom_remap -
550 (unsigned long) &prom_boot_page);
551
405599bd 552 early_spitfire_errata32();
1da177e4 553
405599bd
DM		 554 phys_page = tte_data & _PAGE_PADDR;
555 remap_func(phys_page, KERNBASE, prom_get_mmu_ihandle());
1da177e4 556 if (bigkernel)
405599bd
DM		 557 remap_func(phys_page + 0x400000,
558 KERNBASE + 0x400000,
559 prom_get_mmu_ihandle());
1da177e4
LT		 560
561 /* Flush out that temporary mapping. */
562 spitfire_flush_dtlb_nucleus_page(0x0);
563 spitfire_flush_itlb_nucleus_page(0x0);
564
565 /* Now lock us back into the TLBs via OBP. */
405599bd
DM		 566 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
567 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
1da177e4 568 if (bigkernel) {
405599bd
DM		 569 prom_dtlb_load(tlb_ent - 1,
570 tte_data + 0x400000,
571 tte_vaddr + 0x400000);
572 prom_itlb_load(tlb_ent - 1,
573 tte_data + 0x400000,
574 tte_vaddr + 0x400000);
1da177e4 575 }
405599bd 576}
1da177e4 577
405599bd
DM		 578static void readjust_prom_translations(void)
579{
580 int nents, i;
1da177e4 581
405599bd
DM		 582 nents = read_obp_translations();
583 for (i = 0; i < nents; i++) {
b206fc4c
DM		 584 unsigned long vaddr = prom_trans[i].virt;
585 unsigned long size = prom_trans[i].size;
1da177e4
LT		 586
587 if (vaddr < 0xf0000000UL) {
588 unsigned long avoid_start = (unsigned long) KERNBASE;
589 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
590
591 if (bigkernel)
592 avoid_end += (4 * 1024 * 1024);
593 if (vaddr < avoid_start) {
594 unsigned long top = vaddr + size;
595
596 if (top > avoid_start)
597 top = avoid_start;
598 prom_unmap(top - vaddr, vaddr);
599 }
600 if ((vaddr + size) > avoid_end) {
601 unsigned long bottom = vaddr;
602
603 if (bottom < avoid_end)
604 bottom = avoid_end;
605 prom_unmap((vaddr + size) - bottom, bottom);
606 }
607 }
608 }
405599bd
DM		 609}
610
611static void inherit_prom_mappings(void)
612{
613 int n;
614
615 n = read_obp_translations();
616 build_obp_pgtable(n);
617
618 /* Now fixup OBP's idea about where we really are mapped. */
619 prom_printf("Remapping the kernel... ");
620 remap_kernel();
621
622 readjust_prom_translations();
1da177e4
LT		 623
624 prom_printf("done.\n");
625
626 register_prom_callbacks();
627}
628
629/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
630 * upwards as reserved for use by the firmware (I wonder if this
631 * will be the same on Cheetah...). We use this virtual address
632 * range for the VPTE table mappings of the nucleus so we need
633 * to zap them when we enter the PROM. -DaveM
634 */
635static void __flush_nucleus_vptes(void)
636{
637 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
638 int i;
639
640 /* Only DTLB must be checked for VPTE entries. */
641 if (tlb_type == spitfire) {
642 for (i = 0; i < 63; i++) {
643 unsigned long tag;
644
645 /* Spitfire Errata #32 workaround */
646 /* NOTE: Always runs on spitfire, so no cheetah+
647 * page size encodings.
648 */
649 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
650 "flush %%g6"
651 : /* No outputs */
652 : "r" (0),
653 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
654
655 tag = spitfire_get_dtlb_tag(i);
656 if (((tag & ~(PAGE_MASK)) == 0) &&
657 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
658 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
659 "membar #Sync"
660 : /* no outputs */
661 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
662 spitfire_put_dtlb_data(i, 0x0UL);
663 }
664 }
665 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
666 for (i = 0; i < 512; i++) {
667 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
668
669 if ((tag & ~PAGE_MASK) == 0 &&
670 (tag & PAGE_MASK) >= prom_reserved_base) {
671 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
672 "membar #Sync"
673 : /* no outputs */
674 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
675 cheetah_put_dtlb_data(i, 0x0UL, 2);
676 }
677
678 if (tlb_type != cheetah_plus)
679 continue;
680
681 tag = cheetah_get_dtlb_tag(i, 3);
682
683 if ((tag & ~PAGE_MASK) == 0 &&
684 (tag & PAGE_MASK) >= prom_reserved_base) {
685 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
686 "membar #Sync"
687 : /* no outputs */
688 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
689 cheetah_put_dtlb_data(i, 0x0UL, 3);
690 }
691 }
692 } else {
693 /* Implement me :-) */
694 BUG();
695 }
696}
697
698static int prom_ditlb_set;
699struct prom_tlb_entry {
700 int tlb_ent;
701 unsigned long tlb_tag;
702 unsigned long tlb_data;
703};
704struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
705
706void prom_world(int enter)
707{
708 unsigned long pstate;
709 int i;
710
711 if (!enter)
712 set_fs((mm_segment_t) { get_thread_current_ds() });
713
714 if (!prom_ditlb_set)
715 return;
716
717 /* Make sure the following runs atomically. */
718 __asm__ __volatile__("flushw\n\t"
719 "rdpr %%pstate, %0\n\t"
720 "wrpr %0, %1, %%pstate"
721 : "=r" (pstate)
722 : "i" (PSTATE_IE));
723
724 if (enter) {
725 /* Kick out nucleus VPTEs. */
726 __flush_nucleus_vptes();
727
728 /* Install PROM world. */
729 for (i = 0; i < 16; i++) {
730 if (prom_dtlb[i].tlb_ent != -1) {
731 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
732 "membar #Sync"
733 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
734 "i" (ASI_DMMU));
735 if (tlb_type == spitfire)
736 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
737 prom_dtlb[i].tlb_data);
738 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
739 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
740 prom_dtlb[i].tlb_data);
741 }
742 if (prom_itlb[i].tlb_ent != -1) {
743 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
744 "membar #Sync"
745 : : "r" (prom_itlb[i].tlb_tag),
746 "r" (TLB_TAG_ACCESS),
747 "i" (ASI_IMMU));
748 if (tlb_type == spitfire)
749 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
750 prom_itlb[i].tlb_data);
751 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
752 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
753 prom_itlb[i].tlb_data);
754 }
755 }
756 } else {
757 for (i = 0; i < 16; i++) {
758 if (prom_dtlb[i].tlb_ent != -1) {
759 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
760 "membar #Sync"
761 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
762 if (tlb_type == spitfire)
763 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
764 else
765 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
766 }
767 if (prom_itlb[i].tlb_ent != -1) {
768 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
769 "membar #Sync"
770 : : "r" (TLB_TAG_ACCESS),
771 "i" (ASI_IMMU));
772 if (tlb_type == spitfire)
773 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
774 else
775 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
776 }
777 }
778 }
779 __asm__ __volatile__("wrpr %0, 0, %%pstate"
780 : : "r" (pstate));
781}
782
783void inherit_locked_prom_mappings(int save_p)
784{
785 int i;
786 int dtlb_seen = 0;
787 int itlb_seen = 0;
788
789 /* Fucking losing PROM has more mappings in the TLB, but
790 * it (conveniently) fails to mention any of these in the
791 * translations property. The only ones that matter are
792 * the locked PROM tlb entries, so we impose the following
793 * irrecovable rule on the PROM, it is allowed 8 locked
794 * entries in the ITLB and 8 in the DTLB.
795 *
796 * Supposedly the upper 16GB of the address space is
797 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
798 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
799 * used between the client program and the firmware on sun5
800 * systems to coordinate mmu mappings is also COMPLETELY
801 * UNDOCUMENTED!!!!!! Thanks S(t)un!
802 */
803 if (save_p) {
804 for (i = 0; i < 16; i++) {
805 prom_itlb[i].tlb_ent = -1;
806 prom_dtlb[i].tlb_ent = -1;
807 }
808 }
809 if (tlb_type == spitfire) {
810 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
811 for (i = 0; i < high; i++) {
812 unsigned long data;
813
814 /* Spitfire Errata #32 workaround */
815 /* NOTE: Always runs on spitfire, so no cheetah+
816 * page size encodings.
817 */
818 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
819 "flush %%g6"
820 : /* No outputs */
821 : "r" (0),
822 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
823
824 data = spitfire_get_dtlb_data(i);
825 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
826 unsigned long tag;
827
828 /* Spitfire Errata #32 workaround */
829 /* NOTE: Always runs on spitfire, so no
830 * cheetah+ page size encodings.
831 */
832 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
833 "flush %%g6"
834 : /* No outputs */
835 : "r" (0),
836 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
837
838 tag = spitfire_get_dtlb_tag(i);
839 if (save_p) {
840 prom_dtlb[dtlb_seen].tlb_ent = i;
841 prom_dtlb[dtlb_seen].tlb_tag = tag;
842 prom_dtlb[dtlb_seen].tlb_data = data;
843 }
844 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
845 "membar #Sync"
846 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
847 spitfire_put_dtlb_data(i, 0x0UL);
848
849 dtlb_seen++;
850 if (dtlb_seen > 15)
851 break;
852 }
853 }
854
855 for (i = 0; i < high; i++) {
856 unsigned long data;
857
858 /* Spitfire Errata #32 workaround */
859 /* NOTE: Always runs on spitfire, so no
860 * cheetah+ page size encodings.
861 */
862 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
863 "flush %%g6"
864 : /* No outputs */
865 : "r" (0),
866 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
867
868 data = spitfire_get_itlb_data(i);
869 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
870 unsigned long tag;
871
872 /* Spitfire Errata #32 workaround */
873 /* NOTE: Always runs on spitfire, so no
874 * cheetah+ page size encodings.
875 */
876 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
877 "flush %%g6"
878 : /* No outputs */
879 : "r" (0),
880 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
881
882 tag = spitfire_get_itlb_tag(i);
883 if (save_p) {
884 prom_itlb[itlb_seen].tlb_ent = i;
885 prom_itlb[itlb_seen].tlb_tag = tag;
886 prom_itlb[itlb_seen].tlb_data = data;
887 }
888 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
889 "membar #Sync"
890 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
891 spitfire_put_itlb_data(i, 0x0UL);
892
893 itlb_seen++;
894 if (itlb_seen > 15)
895 break;
896 }
897 }
898 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
899 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
900
901 for (i = 0; i < high; i++) {
902 unsigned long data;
903
904 data = cheetah_get_ldtlb_data(i);
905 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
906 unsigned long tag;
907
908 tag = cheetah_get_ldtlb_tag(i);
909 if (save_p) {
910 prom_dtlb[dtlb_seen].tlb_ent = i;
911 prom_dtlb[dtlb_seen].tlb_tag = tag;
912 prom_dtlb[dtlb_seen].tlb_data = data;
913 }
914 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
915 "membar #Sync"
916 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
917 cheetah_put_ldtlb_data(i, 0x0UL);
918
919 dtlb_seen++;
920 if (dtlb_seen > 15)
921 break;
922 }
923 }
924
925 for (i = 0; i < high; i++) {
926 unsigned long data;
927
928 data = cheetah_get_litlb_data(i);
929 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
930 unsigned long tag;
931
932 tag = cheetah_get_litlb_tag(i);
933 if (save_p) {
934 prom_itlb[itlb_seen].tlb_ent = i;
935 prom_itlb[itlb_seen].tlb_tag = tag;
936 prom_itlb[itlb_seen].tlb_data = data;
937 }
938 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
939 "membar #Sync"
940 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
941 cheetah_put_litlb_data(i, 0x0UL);
942
943 itlb_seen++;
944 if (itlb_seen > 15)
945 break;
946 }
947 }
948 } else {
949 /* Implement me :-) */
950 BUG();
951 }
952 if (save_p)
953 prom_ditlb_set = 1;
954}
955
956/* Give PROM back his world, done during reboots... */
957void prom_reload_locked(void)
958{
959 int i;
960
961 for (i = 0; i < 16; i++) {
962 if (prom_dtlb[i].tlb_ent != -1) {
963 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
964 "membar #Sync"
965 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
966 "i" (ASI_DMMU));
967 if (tlb_type == spitfire)
968 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
969 prom_dtlb[i].tlb_data);
970 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
971 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
972 prom_dtlb[i].tlb_data);
973 }
974
975 if (prom_itlb[i].tlb_ent != -1) {
976 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
977 "membar #Sync"
978 : : "r" (prom_itlb[i].tlb_tag),
979 "r" (TLB_TAG_ACCESS),
980 "i" (ASI_IMMU));
981 if (tlb_type == spitfire)
982 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
983 prom_itlb[i].tlb_data);
984 else
985 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
986 prom_itlb[i].tlb_data);
987 }
988 }
989}
990
991#ifdef DCACHE_ALIASING_POSSIBLE
992void __flush_dcache_range(unsigned long start, unsigned long end)
993{
994 unsigned long va;
995
996 if (tlb_type == spitfire) {
997 int n = 0;
998
999 for (va = start; va < end; va += 32) {
1000 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
1001 if (++n >= 512)
1002 break;
1003 }
1004 } else {
1005 start = __pa(start);
1006 end = __pa(end);
1007 for (va = start; va < end; va += 32)
1008 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1009 "membar #Sync"
1010 : /* no outputs */
1011 : "r" (va),
1012 "i" (ASI_DCACHE_INVALIDATE));
1013 }
1014}
1015#endif /* DCACHE_ALIASING_POSSIBLE */
1016
1017/* If not locked, zap it. */
1018void __flush_tlb_all(void)
1019{
1020 unsigned long pstate;
1021 int i;
1022
1023 __asm__ __volatile__("flushw\n\t"
1024 "rdpr %%pstate, %0\n\t"
1025 "wrpr %0, %1, %%pstate"
1026 : "=r" (pstate)
1027 : "i" (PSTATE_IE));
1028 if (tlb_type == spitfire) {
1029 for (i = 0; i < 64; i++) {
1030 /* Spitfire Errata #32 workaround */
1031 /* NOTE: Always runs on spitfire, so no
1032 * cheetah+ page size encodings.
1033 */
1034 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1035 "flush %%g6"
1036 : /* No outputs */
1037 : "r" (0),
1038 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1039
1040 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1041 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1042 "membar #Sync"
1043 : /* no outputs */
1044 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1045 spitfire_put_dtlb_data(i, 0x0UL);
1046 }
1047
1048 /* Spitfire Errata #32 workaround */
1049 /* NOTE: Always runs on spitfire, so no
1050 * cheetah+ page size encodings.
1051 */
1052 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1053 "flush %%g6"
1054 : /* No outputs */
1055 : "r" (0),
1056 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1057
1058 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1059 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1060 "membar #Sync"
1061 : /* no outputs */
1062 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1063 spitfire_put_itlb_data(i, 0x0UL);
1064 }
1065 }
1066 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1067 cheetah_flush_dtlb_all();
1068 cheetah_flush_itlb_all();
1069 }
1070 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1071 : : "r" (pstate));
1072}
1073
1074/* Caller does TLB context flushing on local CPU if necessary.
1075 * The caller also ensures that CTX_VALID(mm->context) is false.
1076 *
1077 * We must be careful about boundary cases so that we never
1078 * let the user have CTX 0 (nucleus) or we ever use a CTX
1079 * version of zero (and thus NO_CONTEXT would not be caught
1080 * by version mis-match tests in mmu_context.h).
1081 */
1082void get_new_mmu_context(struct mm_struct *mm)
1083{
1084 unsigned long ctx, new_ctx;
1085 unsigned long orig_pgsz_bits;
1086
1087
1088 spin_lock(&ctx_alloc_lock);
1089 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1090 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1091 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1092 if (new_ctx >= (1 << CTX_NR_BITS)) {
1093 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1094 if (new_ctx >= ctx) {
1095 int i;
1096 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1097 CTX_FIRST_VERSION;
1098 if (new_ctx == 1)
1099 new_ctx = CTX_FIRST_VERSION;
1100
1101 /* Don't call memset, for 16 entries that's just
1102 * plain silly...
1103 */
1104 mmu_context_bmap[0] = 3;
1105 mmu_context_bmap[1] = 0;
1106 mmu_context_bmap[2] = 0;
1107 mmu_context_bmap[3] = 0;
1108 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1109 mmu_context_bmap[i + 0] = 0;
1110 mmu_context_bmap[i + 1] = 0;
1111 mmu_context_bmap[i + 2] = 0;
1112 mmu_context_bmap[i + 3] = 0;
1113 }
1114 goto out;
1115 }
1116 }
1117 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1118 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1119out:
1120 tlb_context_cache = new_ctx;
1121 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1122 spin_unlock(&ctx_alloc_lock);
1123}
1124
1125#ifndef CONFIG_SMP
1126struct pgtable_cache_struct pgt_quicklists;
1127#endif
1128
1129/* OK, we have to color these pages. The page tables are accessed
1130 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1131 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1132 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1133 * fast handlers do not get data from old/garbage dcache lines that
1134 * correspond to an old/stale virtual address (user/kernel) that
1135 * previously mapped the pagetable page while accessing vpte range
1136 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1137 * color is the same, then when the kernel initializes the pagetable
1138 * using the later address range, accesses with the first address
1139 * range will see the newly initialized data rather than the garbage.
1140 */
1141#ifdef DCACHE_ALIASING_POSSIBLE
1142#define DC_ALIAS_SHIFT 1
1143#else
1144#define DC_ALIAS_SHIFT 0
1145#endif
8edf72eb 1146pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1da177e4
LT		 1147{
1148 struct page *page;
1149 unsigned long color;
1150
1151 {
1152 pte_t *ptep = pte_alloc_one_fast(mm, address);
1153
1154 if (ptep)
1155 return ptep;
1156 }
1157
1158 color = VPTE_COLOR(address);
1159 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1160 if (page) {
1161 unsigned long *to_free;
1162 unsigned long paddr;
1163 pte_t *pte;
1164
1165#ifdef DCACHE_ALIASING_POSSIBLE
1166 set_page_count(page, 1);
1167 ClearPageCompound(page);
1168
1169 set_page_count((page + 1), 1);
1170 ClearPageCompound(page + 1);
1171#endif
1172 paddr = (unsigned long) page_address(page);
1173 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1174
1175 if (!color) {
1176 pte = (pte_t *) paddr;
1177 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1178 } else {
1179 pte = (pte_t *) (paddr + PAGE_SIZE);
1180 to_free = (unsigned long *) paddr;
1181 }
1182
1183#ifdef DCACHE_ALIASING_POSSIBLE
1184 /* Now free the other one up, adjust cache size. */
1185 preempt_disable();
1186 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1187 pte_quicklist[color ^ 0x1] = to_free;
1188 pgtable_cache_size++;
1189 preempt_enable();
1190#endif
1191
1192 return pte;
1193 }
1194 return NULL;
1195}
1196
1197void sparc_ultra_dump_itlb(void)
1198{
1199 int slot;
1200
1201 if (tlb_type == spitfire) {
1202 printk ("Contents of itlb: ");
1203 for (slot = 0; slot < 14; slot++) printk (" ");
1204 printk ("%2x:%016lx,%016lx\n",
1205 0,
1206 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1207 for (slot = 1; slot < 64; slot+=3) {
1208 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1209 slot,
1210 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1211 slot+1,
1212 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1213 slot+2,
1214 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1215 }
1216 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1217 printk ("Contents of itlb0:\n");
1218 for (slot = 0; slot < 16; slot+=2) {
1219 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1220 slot,
1221 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1222 slot+1,
1223 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1224 }
1225 printk ("Contents of itlb2:\n");
1226 for (slot = 0; slot < 128; slot+=2) {
1227 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1228 slot,
1229 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1230 slot+1,
1231 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1232 }
1233 }
1234}
1235
1236void sparc_ultra_dump_dtlb(void)
1237{
1238 int slot;
1239
1240 if (tlb_type == spitfire) {
1241 printk ("Contents of dtlb: ");
1242 for (slot = 0; slot < 14; slot++) printk (" ");
1243 printk ("%2x:%016lx,%016lx\n", 0,
1244 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1245 for (slot = 1; slot < 64; slot+=3) {
1246 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1247 slot,
1248 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1249 slot+1,
1250 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1251 slot+2,
1252 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1253 }
1254 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1255 printk ("Contents of dtlb0:\n");
1256 for (slot = 0; slot < 16; slot+=2) {
1257 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1258 slot,
1259 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1260 slot+1,
1261 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1262 }
1263 printk ("Contents of dtlb2:\n");
1264 for (slot = 0; slot < 512; slot+=2) {
1265 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1266 slot,
1267 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1268 slot+1,
1269 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1270 }
1271 if (tlb_type == cheetah_plus) {
1272 printk ("Contents of dtlb3:\n");
1273 for (slot = 0; slot < 512; slot+=2) {
1274 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1275 slot,
1276 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1277 slot+1,
1278 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1279 }
1280 }
1281 }
1282}
1283
1284extern unsigned long cmdline_memory_size;
1285
1286unsigned long __init bootmem_init(unsigned long *pages_avail)
1287{
1288 unsigned long bootmap_size, start_pfn, end_pfn;
1289 unsigned long end_of_phys_memory = 0UL;
1290 unsigned long bootmap_pfn, bytes_avail, size;
1291 int i;
1292
1293#ifdef CONFIG_DEBUG_BOOTMEM
1294 prom_printf("bootmem_init: Scan sp_banks, ");
1295#endif
1296
1297 bytes_avail = 0UL;
1298 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1299 end_of_phys_memory = sp_banks[i].base_addr +
1300 sp_banks[i].num_bytes;
1301 bytes_avail += sp_banks[i].num_bytes;
1302 if (cmdline_memory_size) {
1303 if (bytes_avail > cmdline_memory_size) {
1304 unsigned long slack = bytes_avail - cmdline_memory_size;
1305
1306 bytes_avail -= slack;
1307 end_of_phys_memory -= slack;
1308
1309 sp_banks[i].num_bytes -= slack;
1310 if (sp_banks[i].num_bytes == 0) {
1311 sp_banks[i].base_addr = 0xdeadbeef;
1312 } else {
1313 sp_banks[i+1].num_bytes = 0;
1314 sp_banks[i+1].base_addr = 0xdeadbeef;
1315 }
1316 break;
1317 }
1318 }
1319 }
1320
1321 *pages_avail = bytes_avail >> PAGE_SHIFT;
1322
1323 /* Start with page aligned address of last symbol in kernel
1324 * image. The kernel is hard mapped below PAGE_OFFSET in a
1325 * 4MB locked TLB translation.
1326 */
1327 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1328
1329 bootmap_pfn = start_pfn;
1330
1331 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1332
1333#ifdef CONFIG_BLK_DEV_INITRD
1334 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1335 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1336 unsigned long ramdisk_image = sparc_ramdisk_image ?
1337 sparc_ramdisk_image : sparc_ramdisk_image64;
1338 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1339 ramdisk_image -= KERNBASE;
1340 initrd_start = ramdisk_image + phys_base;
1341 initrd_end = initrd_start + sparc_ramdisk_size;
1342 if (initrd_end > end_of_phys_memory) {
1343 printk(KERN_CRIT "initrd extends beyond end of memory "
1344 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1345 initrd_end, end_of_phys_memory);
1346 initrd_start = 0;
1347 }
1348 if (initrd_start) {
1349 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1350 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1351 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1352 }
1353 }
1354#endif
1355 /* Initialize the boot-time allocator. */
1356 max_pfn = max_low_pfn = end_pfn;
1357 min_low_pfn = pfn_base;
1358
1359#ifdef CONFIG_DEBUG_BOOTMEM
1360 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1361 min_low_pfn, bootmap_pfn, max_low_pfn);
1362#endif
1363 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1364
1365 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1366
1367 /* Now register the available physical memory with the
1368 * allocator.
1369 */
1370 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1371#ifdef CONFIG_DEBUG_BOOTMEM
1372 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1373 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1374#endif
1375 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1376 }
1377
1378#ifdef CONFIG_BLK_DEV_INITRD
1379 if (initrd_start) {
1380 size = initrd_end - initrd_start;
1381
1382 /* Resert the initrd image area. */
1383#ifdef CONFIG_DEBUG_BOOTMEM
1384 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1385 initrd_start, initrd_end);
1386#endif
1387 reserve_bootmem(initrd_start, size);
1388 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1389
1390 initrd_start += PAGE_OFFSET;
1391 initrd_end += PAGE_OFFSET;
1392 }
1393#endif
1394 /* Reserve the kernel text/data/bss. */
1395#ifdef CONFIG_DEBUG_BOOTMEM
1396 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1397#endif
1398 reserve_bootmem(kern_base, kern_size);
1399 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1400
1401 /* Reserve the bootmem map. We do not account for it
1402 * in pages_avail because we will release that memory
1403 * in free_all_bootmem.
1404 */
1405 size = bootmap_size;
1406#ifdef CONFIG_DEBUG_BOOTMEM
1407 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1408 (bootmap_pfn << PAGE_SHIFT), size);
1409#endif
1410 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1411 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1412
1413 return end_pfn;
1414}
1415
1416/* paging_init() sets up the page tables */
1417
1418extern void cheetah_ecache_flush_init(void);
1419
1420static unsigned long last_valid_pfn;
1421
1422void __init paging_init(void)
1423{
1424 extern pmd_t swapper_pmd_dir[1024];
1da177e4
LT		 1425 unsigned long alias_base = kern_base + PAGE_OFFSET;
1426 unsigned long second_alias_page = 0;
1427 unsigned long pt, flags, end_pfn, pages_avail;
1428 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1429 unsigned long real_end;
1430
1431 set_bit(0, mmu_context_bmap);
1432
1433 real_end = (unsigned long)_end;
1434 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1435 bigkernel = 1;
1436#ifdef CONFIG_BLK_DEV_INITRD
1437 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1438 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1439#endif
1440
1441 /* We assume physical memory starts at some 4mb multiple,
1442 * if this were not true we wouldn't boot up to this point
1443 * anyways.
1444 */
1445 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1446 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1447 local_irq_save(flags);
1448 if (tlb_type == spitfire) {
1449 __asm__ __volatile__(
1450 " stxa %1, [%0] %3\n"
1451 " stxa %2, [%5] %4\n"
1452 " membar #Sync\n"
1453 " flush %%g6\n"
1454 " nop\n"
1455 " nop\n"
1456 " nop\n"
1457 : /* No outputs */
1458 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1459 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1460 : "memory");
1461 if (real_end >= KERNBASE + 0x340000) {
1462 second_alias_page = alias_base + 0x400000;
1463 __asm__ __volatile__(
1464 " stxa %1, [%0] %3\n"
1465 " stxa %2, [%5] %4\n"
1466 " membar #Sync\n"
1467 " flush %%g6\n"
1468 " nop\n"
1469 " nop\n"
1470 " nop\n"
1471 : /* No outputs */
1472 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1473 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1474 : "memory");
1475 }
1476 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1477 __asm__ __volatile__(
1478 " stxa %1, [%0] %3\n"
1479 " stxa %2, [%5] %4\n"
1480 " membar #Sync\n"
1481 " flush %%g6\n"
1482 " nop\n"
1483 " nop\n"
1484 " nop\n"
1485 : /* No outputs */
1486 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1487 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1488 : "memory");
1489 if (real_end >= KERNBASE + 0x340000) {
1490 second_alias_page = alias_base + 0x400000;
1491 __asm__ __volatile__(
1492 " stxa %1, [%0] %3\n"
1493 " stxa %2, [%5] %4\n"
1494 " membar #Sync\n"
1495 " flush %%g6\n"
1496 " nop\n"
1497 " nop\n"
1498 " nop\n"
1499 : /* No outputs */
1500 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1501 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1502 : "memory");
1503 }
1504 }
1505 local_irq_restore(flags);
1506
1507 /* Now set kernel pgd to upper alias so physical page computations
1508 * work.
1509 */
1510 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1511
1512 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1513
1514 /* Now can init the kernel/bad page tables. */
1515 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1516 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1517
1ac4f5eb 1518 swapper_pgd_zero = pgd_val(init_mm.pgd[0]);
1da177e4
LT		 1519
1520 /* Setup bootmem... */
1521 pages_avail = 0;
1522 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1523
1524 /* Inherit non-locked OBP mappings. */
1525 inherit_prom_mappings();
1526
1527 /* Ok, we can use our TLB miss and window trap handlers safely.
1528 * We need to do a quick peek here to see if we are on StarFire
1529 * or not, so setup_tba can setup the IRQ globals correctly (it
1530 * needs to get the hard smp processor id correctly).
1531 */
1532 {
1533 extern void setup_tba(int);
1534 setup_tba(this_is_starfire);
1535 }
1536
1537 inherit_locked_prom_mappings(1);
1538
1539 /* We only created DTLB mapping of this stuff. */
1540 spitfire_flush_dtlb_nucleus_page(alias_base);
1541 if (second_alias_page)
1542 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1543
1544 __flush_tlb_all();
1545
1546 {
1547 unsigned long zones_size[MAX_NR_ZONES];
1548 unsigned long zholes_size[MAX_NR_ZONES];
1549 unsigned long npages;
1550 int znum;
1551
1552 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1553 zones_size[znum] = zholes_size[znum] = 0;
1554
1555 npages = end_pfn - pfn_base;
1556 zones_size[ZONE_DMA] = npages;
1557 zholes_size[ZONE_DMA] = npages - pages_avail;
1558
1559 free_area_init_node(0, &contig_page_data, zones_size,
1560 phys_base >> PAGE_SHIFT, zholes_size);
1561 }
1562
1563 device_scan();
1564}
1565
1566/* Ok, it seems that the prom can allocate some more memory chunks
1567 * as a side effect of some prom calls we perform during the
1568 * boot sequence. My most likely theory is that it is from the
1569 * prom_set_traptable() call, and OBP is allocating a scratchpad
1570 * for saving client program register state etc.
1571 */
1572static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1573{
1574 int swapi = 0;
1575 int i, mitr;
1576 unsigned long tmpaddr, tmpsize;
1577 unsigned long lowest;
1578
1579 for (i = 0; thislist[i].theres_more != 0; i++) {
1580 lowest = thislist[i].start_adr;
1581 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1582 if (thislist[mitr].start_adr < lowest) {
1583 lowest = thislist[mitr].start_adr;
1584 swapi = mitr;
1585 }
1586 if (lowest == thislist[i].start_adr)
1587 continue;
1588 tmpaddr = thislist[swapi].start_adr;
1589 tmpsize = thislist[swapi].num_bytes;
1590 for (mitr = swapi; mitr > i; mitr--) {
1591 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1592 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1593 }
1594 thislist[i].start_adr = tmpaddr;
1595 thislist[i].num_bytes = tmpsize;
1596 }
1597}
1598
1599void __init rescan_sp_banks(void)
1600{
1601 struct linux_prom64_registers memlist[64];
1602 struct linux_mlist_p1275 avail[64], *mlist;
1603 unsigned long bytes, base_paddr;
1604 int num_regs, node = prom_finddevice("/memory");
1605 int i;
1606
1607 num_regs = prom_getproperty(node, "available",
1608 (char *) memlist, sizeof(memlist));
1609 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1610 for (i = 0; i < num_regs; i++) {
1611 avail[i].start_adr = memlist[i].phys_addr;
1612 avail[i].num_bytes = memlist[i].reg_size;
1613 avail[i].theres_more = &avail[i + 1];
1614 }
1615 avail[i - 1].theres_more = NULL;
1616 sort_memlist(avail);
1617
1618 mlist = &avail[0];
1619 i = 0;
1620 bytes = mlist->num_bytes;
1621 base_paddr = mlist->start_adr;
1622
1623 sp_banks[0].base_addr = base_paddr;
1624 sp_banks[0].num_bytes = bytes;
1625
1626 while (mlist->theres_more != NULL){
1627 i++;
1628 mlist = mlist->theres_more;
1629 bytes = mlist->num_bytes;
1630 if (i >= SPARC_PHYS_BANKS-1) {
1631 printk ("The machine has more banks than "
1632 "this kernel can support\n"
1633 "Increase the SPARC_PHYS_BANKS "
1634 "setting (currently %d)\n",
1635 SPARC_PHYS_BANKS);
1636 i = SPARC_PHYS_BANKS-1;
1637 break;
1638 }
1639
1640 sp_banks[i].base_addr = mlist->start_adr;
1641 sp_banks[i].num_bytes = mlist->num_bytes;
1642 }
1643
1644 i++;
1645 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1646 sp_banks[i].num_bytes = 0;
1647
1648 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1649 sp_banks[i].num_bytes &= PAGE_MASK;
1650}
1651
1652static void __init taint_real_pages(void)
1653{
1654 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1655 int i;
1656
1657 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1658 saved_sp_banks[i].base_addr =
1659 sp_banks[i].base_addr;
1660 saved_sp_banks[i].num_bytes =
1661 sp_banks[i].num_bytes;
1662 }
1663
1664 rescan_sp_banks();
1665
1666 /* Find changes discovered in the sp_bank rescan and
1667 * reserve the lost portions in the bootmem maps.
1668 */
1669 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1670 unsigned long old_start, old_end;
1671
1672 old_start = saved_sp_banks[i].base_addr;
1673 old_end = old_start +
1674 saved_sp_banks[i].num_bytes;
1675 while (old_start < old_end) {
1676 int n;
1677
1678 for (n = 0; sp_banks[n].num_bytes; n++) {
1679 unsigned long new_start, new_end;
1680
1681 new_start = sp_banks[n].base_addr;
1682 new_end = new_start + sp_banks[n].num_bytes;
1683
1684 if (new_start <= old_start &&
1685 new_end >= (old_start + PAGE_SIZE)) {
1686 set_bit (old_start >> 22,
1687 sparc64_valid_addr_bitmap);
1688 goto do_next_page;
1689 }
1690 }
1691 reserve_bootmem(old_start, PAGE_SIZE);
1692
1693 do_next_page:
1694 old_start += PAGE_SIZE;
1695 }
1696 }
1697}
1698
1699void __init mem_init(void)
1700{
1701 unsigned long codepages, datapages, initpages;
1702 unsigned long addr, last;
1703 int i;
1704
1705 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1706 i += 1;
1707 sparc64_valid_addr_bitmap = (unsigned long *)
1708 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1709 if (sparc64_valid_addr_bitmap == NULL) {
1710 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1711 prom_halt();
1712 }
1713 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1714
1715 addr = PAGE_OFFSET + kern_base;
1716 last = PAGE_ALIGN(kern_size) + addr;
1717 while (addr < last) {
1718 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1719 addr += PAGE_SIZE;
1720 }
1721
1722 taint_real_pages();
1723
1724 max_mapnr = last_valid_pfn - pfn_base;
1725 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1726
1727#ifdef CONFIG_DEBUG_BOOTMEM
1728 prom_printf("mem_init: Calling free_all_bootmem().\n");
1729#endif
1730 totalram_pages = num_physpages = free_all_bootmem() - 1;
1731
1732 /*
1733 * Set up the zero page, mark it reserved, so that page count
1734 * is not manipulated when freeing the page from user ptes.
1735 */
1736 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1737 if (mem_map_zero == NULL) {
1738 prom_printf("paging_init: Cannot alloc zero page.\n");
1739 prom_halt();
1740 }
1741 SetPageReserved(mem_map_zero);
1742
1743 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1744 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1745 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1746 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1747 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1748 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1749
1750 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1751 nr_free_pages() << (PAGE_SHIFT-10),
1752 codepages << (PAGE_SHIFT-10),
1753 datapages << (PAGE_SHIFT-10),
1754 initpages << (PAGE_SHIFT-10),
1755 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1756
1757 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1758 cheetah_ecache_flush_init();
1759}
1760
1761void free_initmem (void)
1762{
1763 unsigned long addr, initend;
1764
1765 /*
1766 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1767 */
1768 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1769 initend = (unsigned long)(__init_end) & PAGE_MASK;
1770 for (; addr < initend; addr += PAGE_SIZE) {
1771 unsigned long page;
1772 struct page *p;
1773
1774 page = (addr +
1775 ((unsigned long) __va(kern_base)) -
1776 ((unsigned long) KERNBASE));
1777 memset((void *)addr, 0xcc, PAGE_SIZE);
1778 p = virt_to_page(page);
1779
1780 ClearPageReserved(p);
1781 set_page_count(p, 1);
1782 __free_page(p);
1783 num_physpages++;
1784 totalram_pages++;
1785 }
1786}
1787
1788#ifdef CONFIG_BLK_DEV_INITRD
1789void free_initrd_mem(unsigned long start, unsigned long end)
1790{
1791 if (start < end)
1792 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1793 for (; start < end; start += PAGE_SIZE) {
1794 struct page *p = virt_to_page(start);
1795
1796 ClearPageReserved(p);
1797 set_page_count(p, 1);
1798 __free_page(p);
1799 num_physpages++;
1800 totalram_pages++;
1801 }
1802}
1803#endif
Clone of davem's net-next-2.6 tree