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Merge branch 'shrinker' of git://git.kernel.org/pub/scm/linux/kernel/git/dgc/xfsdev
[net-next-2.6.git] / arch / sparc / mm / srmmu.c
CommitLineData
1da177e4
LT		 1/*
2 * srmmu.c: SRMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
9 */
10
1da177e4
LT		 11#include <linux/kernel.h>
12#include <linux/mm.h>
1da177e4
LT		 13#include <linux/vmalloc.h>
14#include <linux/pagemap.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/bootmem.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
1eeb66a1 20#include <linux/kdebug.h>
949e8274 21#include <linux/log2.h>
5a0e3ad6 22#include <linux/gfp.h>
1da177e4
LT		 23
24#include <asm/bitext.h>
25#include <asm/page.h>
26#include <asm/pgalloc.h>
27#include <asm/pgtable.h>
28#include <asm/io.h>
1da177e4
LT		 29#include <asm/vaddrs.h>
30#include <asm/traps.h>
31#include <asm/smp.h>
32#include <asm/mbus.h>
33#include <asm/cache.h>
34#include <asm/oplib.h>
1da177e4
LT		 35#include <asm/asi.h>
36#include <asm/msi.h>
1da177e4
LT		 37#include <asm/mmu_context.h>
38#include <asm/io-unit.h>
39#include <asm/cacheflush.h>
40#include <asm/tlbflush.h>
41
42/* Now the cpu specific definitions. */
43#include <asm/viking.h>
44#include <asm/mxcc.h>
45#include <asm/ross.h>
46#include <asm/tsunami.h>
47#include <asm/swift.h>
48#include <asm/turbosparc.h>
75d9e346 49#include <asm/leon.h>
1da177e4
LT		 50
51#include <asm/btfixup.h>
52
53enum mbus_module srmmu_modtype;
50215d65 54static unsigned int hwbug_bitmask;
1da177e4
LT		 55int vac_cache_size;
56int vac_line_size;
57
58extern struct resource sparc_iomap;
59
60extern unsigned long last_valid_pfn;
61
62extern unsigned long page_kernel;
63
50215d65 64static pgd_t *srmmu_swapper_pg_dir;
1da177e4
LT		 65
66#ifdef CONFIG_SMP
67#define FLUSH_BEGIN(mm)
68#define FLUSH_END
69#else
70#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
71#define FLUSH_END }
72#endif
73
74BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
75#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
76
77int flush_page_for_dma_global = 1;
78
79#ifdef CONFIG_SMP
80BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
81#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
82#endif
83
84char *srmmu_name;
85
86ctxd_t *srmmu_ctx_table_phys;
50215d65 87static ctxd_t *srmmu_context_table;
1da177e4
LT		 88
89int viking_mxcc_present;
90static DEFINE_SPINLOCK(srmmu_context_spinlock);
91
50215d65 92static int is_hypersparc;
1da177e4
LT		 93
94/*
95 * In general all page table modifications should use the V8 atomic
96 * swap instruction. This insures the mmu and the cpu are in sync
97 * with respect to ref/mod bits in the page tables.
98 */
99static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
100{
101 __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
102 return value;
103}
104
105static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
106{
107 srmmu_swap((unsigned long *)ptep, pte_val(pteval));
108}
109
110/* The very generic SRMMU page table operations. */
111static inline int srmmu_device_memory(unsigned long x)
112{
113 return ((x & 0xF0000000) != 0);
114}
115
50215d65 116static int srmmu_cache_pagetables;
1da177e4
LT		 117
118/* these will be initialized in srmmu_nocache_calcsize() */
50215d65
AB		 119static unsigned long srmmu_nocache_size;
120static unsigned long srmmu_nocache_end;
1da177e4
LT		 121
122/* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
123#define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
124
125/* The context table is a nocache user with the biggest alignment needs. */
126#define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
127
128void *srmmu_nocache_pool;
129void *srmmu_nocache_bitmap;
130static struct bit_map srmmu_nocache_map;
131
132static unsigned long srmmu_pte_pfn(pte_t pte)
133{
134 if (srmmu_device_memory(pte_val(pte))) {
135 /* Just return something that will cause
136 * pfn_valid() to return false. This makes
137 * copy_one_pte() to just directly copy to
138 * PTE over.
139 */
140 return ~0UL;
141 }
142 return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
143}
144
145static struct page *srmmu_pmd_page(pmd_t pmd)
146{
147
148 if (srmmu_device_memory(pmd_val(pmd)))
149 BUG();
150 return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
151}
152
153static inline unsigned long srmmu_pgd_page(pgd_t pgd)
154{ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
155
156
157static inline int srmmu_pte_none(pte_t pte)
158{ return !(pte_val(pte) & 0xFFFFFFF); }
159
160static inline int srmmu_pte_present(pte_t pte)
161{ return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
162
1da177e4
LT		 163static inline void srmmu_pte_clear(pte_t *ptep)
164{ srmmu_set_pte(ptep, __pte(0)); }
165
166static inline int srmmu_pmd_none(pmd_t pmd)
167{ return !(pmd_val(pmd) & 0xFFFFFFF); }
168
169static inline int srmmu_pmd_bad(pmd_t pmd)
170{ return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
171
172static inline int srmmu_pmd_present(pmd_t pmd)
173{ return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
174
175static inline void srmmu_pmd_clear(pmd_t *pmdp) {
176 int i;
177 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
178 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
179}
180
181static inline int srmmu_pgd_none(pgd_t pgd)
182{ return !(pgd_val(pgd) & 0xFFFFFFF); }
183
184static inline int srmmu_pgd_bad(pgd_t pgd)
185{ return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
186
187static inline int srmmu_pgd_present(pgd_t pgd)
188{ return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
189
190static inline void srmmu_pgd_clear(pgd_t * pgdp)
191{ srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
192
193static inline pte_t srmmu_pte_wrprotect(pte_t pte)
194{ return __pte(pte_val(pte) & ~SRMMU_WRITE);}
195
196static inline pte_t srmmu_pte_mkclean(pte_t pte)
197{ return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
198
199static inline pte_t srmmu_pte_mkold(pte_t pte)
200{ return __pte(pte_val(pte) & ~SRMMU_REF);}
201
202static inline pte_t srmmu_pte_mkwrite(pte_t pte)
203{ return __pte(pte_val(pte) | SRMMU_WRITE);}
204
205static inline pte_t srmmu_pte_mkdirty(pte_t pte)
206{ return __pte(pte_val(pte) | SRMMU_DIRTY);}
207
208static inline pte_t srmmu_pte_mkyoung(pte_t pte)
209{ return __pte(pte_val(pte) | SRMMU_REF);}
210
211/*
212 * Conversion functions: convert a page and protection to a page entry,
213 * and a page entry and page directory to the page they refer to.
214 */
215static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
216{ return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
217
218static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
219{ return __pte(((page) >> 4) | pgprot_val(pgprot)); }
220
221static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
222{ return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
223
224/* XXX should we hyper_flush_whole_icache here - Anton */
225static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
226{ srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
227
228static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
229{ srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
230
231static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
232{
233 unsigned long ptp; /* Physical address, shifted right by 4 */
234 int i;
235
236 ptp = __nocache_pa((unsigned long) ptep) >> 4;
237 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
238 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
239 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
240 }
241}
242
243static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
244{
245 unsigned long ptp; /* Physical address, shifted right by 4 */
246 int i;
247
248 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
249 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
250 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
251 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
252 }
253}
254
255static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
256{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
257
258/* to find an entry in a top-level page table... */
3115624e 259static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
1da177e4
LT		 260{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
261
262/* Find an entry in the second-level page table.. */
263static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
264{
265 return (pmd_t *) srmmu_pgd_page(*dir) +
266 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
267}
268
269/* Find an entry in the third-level page table.. */
270static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
271{
272 void *pte;
273
274 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
275 return (pte_t *) pte +
276 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
277}
278
279static unsigned long srmmu_swp_type(swp_entry_t entry)
280{
281 return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
282}
283
284static unsigned long srmmu_swp_offset(swp_entry_t entry)
285{
286 return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
287}
288
289static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
290{
291 return (swp_entry_t) {
292 (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
293 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
294}
295
296/*
297 * size: bytes to allocate in the nocache area.
298 * align: bytes, number to align at.
299 * Returns the virtual address of the allocated area.
300 */
301static unsigned long __srmmu_get_nocache(int size, int align)
302{
303 int offset;
304
305 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
306 printk("Size 0x%x too small for nocache request\n", size);
307 size = SRMMU_NOCACHE_BITMAP_SHIFT;
308 }
309 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
310 printk("Size 0x%x unaligned int nocache request\n", size);
311 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
312 }
313 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
314
315 offset = bit_map_string_get(&srmmu_nocache_map,
316 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
317 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
318 if (offset == -1) {
319 printk("srmmu: out of nocache %d: %d/%d\n",
320 size, (int) srmmu_nocache_size,
321 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
322 return 0;
323 }
324
325 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
326}
327
50215d65 328static unsigned long srmmu_get_nocache(int size, int align)
1da177e4
LT		 329{
330 unsigned long tmp;
331
332 tmp = __srmmu_get_nocache(size, align);
333
334 if (tmp)
335 memset((void *)tmp, 0, size);
336
337 return tmp;
338}
339
50215d65 340static void srmmu_free_nocache(unsigned long vaddr, int size)
1da177e4
LT		 341{
342 int offset;
343
344 if (vaddr < SRMMU_NOCACHE_VADDR) {
345 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
346 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
347 BUG();
348 }
349 if (vaddr+size > srmmu_nocache_end) {
350 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
351 vaddr, srmmu_nocache_end);
352 BUG();
353 }
949e8274 354 if (!is_power_of_2(size)) {
1da177e4
LT		 355 printk("Size 0x%x is not a power of 2\n", size);
356 BUG();
357 }
358 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
359 printk("Size 0x%x is too small\n", size);
360 BUG();
361 }
362 if (vaddr & (size-1)) {
363 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
364 BUG();
365 }
366
367 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
368 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
369
370 bit_map_clear(&srmmu_nocache_map, offset, size);
371}
372
50215d65
AB		 373static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
374 unsigned long end);
1da177e4
LT		 375
376extern unsigned long probe_memory(void); /* in fault.c */
377
378/*
379 * Reserve nocache dynamically proportionally to the amount of
380 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
381 */
50215d65 382static void srmmu_nocache_calcsize(void)
1da177e4
LT		 383{
384 unsigned long sysmemavail = probe_memory() / 1024;
385 int srmmu_nocache_npages;
386
387 srmmu_nocache_npages =
388 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
389
390 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
391 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
392 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
393 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
394
395 /* anything above 1280 blows up */
396 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
397 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
398
399 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
400 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
401}
402
50215d65 403static void __init srmmu_nocache_init(void)
1da177e4
LT		 404{
405 unsigned int bitmap_bits;
406 pgd_t *pgd;
407 pmd_t *pmd;
408 pte_t *pte;
409 unsigned long paddr, vaddr;
410 unsigned long pteval;
411
412 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
413
414 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
415 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
416 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
417
418 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
419 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
420
421 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
422 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
423 init_mm.pgd = srmmu_swapper_pg_dir;
424
425 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
426
427 paddr = __pa((unsigned long)srmmu_nocache_pool);
428 vaddr = SRMMU_NOCACHE_VADDR;
429
430 while (vaddr < srmmu_nocache_end) {
431 pgd = pgd_offset_k(vaddr);
432 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
433 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
434
435 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
436
437 if (srmmu_cache_pagetables)
438 pteval |= SRMMU_CACHE;
439
440 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
441
442 vaddr += PAGE_SIZE;
443 paddr += PAGE_SIZE;
444 }
445
446 flush_cache_all();
447 flush_tlb_all();
448}
449
450static inline pgd_t *srmmu_get_pgd_fast(void)
451{
452 pgd_t *pgd = NULL;
453
454 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
455 if (pgd) {
456 pgd_t *init = pgd_offset_k(0);
457 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
458 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
459 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
460 }
461
462 return pgd;
463}
464
465static void srmmu_free_pgd_fast(pgd_t *pgd)
466{
467 srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
468}
469
470static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
471{
472 return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
473}
474
475static void srmmu_pmd_free(pmd_t * pmd)
476{
477 srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
478}
479
480/*
481 * Hardware needs alignment to 256 only, but we align to whole page size
482 * to reduce fragmentation problems due to the buddy principle.
483 * XXX Provide actual fragmentation statistics in /proc.
484 *
485 * Alignments up to the page size are the same for physical and virtual
486 * addresses of the nocache area.
487 */
488static pte_t *
489srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
490{
491 return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
492}
493
2f569afd 494static pgtable_t
1da177e4
LT		 495srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
496{
497 unsigned long pte;
2f569afd 498 struct page *page;
1da177e4
LT		 499
500 if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
501 return NULL;
2f569afd
MS		 502 page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
503 pgtable_page_ctor(page);
504 return page;
1da177e4
LT		 505}
506
507static void srmmu_free_pte_fast(pte_t *pte)
508{
509 srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
510}
511
2f569afd 512static void srmmu_pte_free(pgtable_t pte)
1da177e4
LT		 513{
514 unsigned long p;
515
2f569afd 516 pgtable_page_dtor(pte);
1da177e4
LT		 517 p = (unsigned long)page_address(pte); /* Cached address (for test) */
518 if (p == 0)
519 BUG();
520 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
521 p = (unsigned long) __nocache_va(p); /* Nocached virtual */
522 srmmu_free_nocache(p, PTE_SIZE);
523}
524
525/*
526 */
527static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
528{
529 struct ctx_list *ctxp;
530
531 ctxp = ctx_free.next;
532 if(ctxp != &ctx_free) {
533 remove_from_ctx_list(ctxp);
534 add_to_used_ctxlist(ctxp);
535 mm->context = ctxp->ctx_number;
536 ctxp->ctx_mm = mm;
537 return;
538 }
539 ctxp = ctx_used.next;
540 if(ctxp->ctx_mm == old_mm)
541 ctxp = ctxp->next;
542 if(ctxp == &ctx_used)
543 panic("out of mmu contexts");
544 flush_cache_mm(ctxp->ctx_mm);
545 flush_tlb_mm(ctxp->ctx_mm);
546 remove_from_ctx_list(ctxp);
547 add_to_used_ctxlist(ctxp);
548 ctxp->ctx_mm->context = NO_CONTEXT;
549 ctxp->ctx_mm = mm;
550 mm->context = ctxp->ctx_number;
551}
552
553static inline void free_context(int context)
554{
555 struct ctx_list *ctx_old;
556
557 ctx_old = ctx_list_pool + context;
558 remove_from_ctx_list(ctx_old);
559 add_to_free_ctxlist(ctx_old);
560}
561
562
563static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
564 struct task_struct *tsk, int cpu)
565{
566 if(mm->context == NO_CONTEXT) {
567 spin_lock(&srmmu_context_spinlock);
568 alloc_context(old_mm, mm);
569 spin_unlock(&srmmu_context_spinlock);
570 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
571 }
572
75d9e346
KE		 573 if (sparc_cpu_model == sparc_leon)
574 leon_switch_mm();
575
1da177e4
LT		 576 if (is_hypersparc)
577 hyper_flush_whole_icache();
578
579 srmmu_set_context(mm->context);
580}
581
582/* Low level IO area allocation on the SRMMU. */
583static inline void srmmu_mapioaddr(unsigned long physaddr,
584 unsigned long virt_addr, int bus_type)
585{
586 pgd_t *pgdp;
587 pmd_t *pmdp;
588 pte_t *ptep;
589 unsigned long tmp;
590
591 physaddr &= PAGE_MASK;
592 pgdp = pgd_offset_k(virt_addr);
593 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
594 ptep = srmmu_pte_offset(pmdp, virt_addr);
595 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
596
597 /*
598 * I need to test whether this is consistent over all
599 * sun4m's. The bus_type represents the upper 4 bits of
600 * 36-bit physical address on the I/O space lines...
601 */
602 tmp |= (bus_type << 28);
603 tmp |= SRMMU_PRIV;
604 __flush_page_to_ram(virt_addr);
605 srmmu_set_pte(ptep, __pte(tmp));
606}
607
608static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
609 unsigned long xva, unsigned int len)
610{
611 while (len != 0) {
612 len -= PAGE_SIZE;
613 srmmu_mapioaddr(xpa, xva, bus);
614 xva += PAGE_SIZE;
615 xpa += PAGE_SIZE;
616 }
617 flush_tlb_all();
618}
619
620static inline void srmmu_unmapioaddr(unsigned long virt_addr)
621{
622 pgd_t *pgdp;
623 pmd_t *pmdp;
624 pte_t *ptep;
625
626 pgdp = pgd_offset_k(virt_addr);
627 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
628 ptep = srmmu_pte_offset(pmdp, virt_addr);
629
630 /* No need to flush uncacheable page. */
631 srmmu_pte_clear(ptep);
632}
633
634static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
635{
636 while (len != 0) {
637 len -= PAGE_SIZE;
638 srmmu_unmapioaddr(virt_addr);
639 virt_addr += PAGE_SIZE;
640 }
641 flush_tlb_all();
642}
643
644/*
645 * On the SRMMU we do not have the problems with limited tlb entries
646 * for mapping kernel pages, so we just take things from the free page
647 * pool. As a side effect we are putting a little too much pressure
648 * on the gfp() subsystem. This setup also makes the logic of the
649 * iommu mapping code a lot easier as we can transparently handle
650 * mappings on the kernel stack without any special code as we did
651 * need on the sun4c.
652 */
50215d65 653static struct thread_info *srmmu_alloc_thread_info(void)
1da177e4
LT		 654{
655 struct thread_info *ret;
656
657 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
658 THREAD_INFO_ORDER);
659#ifdef CONFIG_DEBUG_STACK_USAGE
660 if (ret)
661 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
662#endif /* DEBUG_STACK_USAGE */
663
664 return ret;
665}
666
667static void srmmu_free_thread_info(struct thread_info *ti)
668{
669 free_pages((unsigned long)ti, THREAD_INFO_ORDER);
670}
671
672/* tsunami.S */
673extern void tsunami_flush_cache_all(void);
674extern void tsunami_flush_cache_mm(struct mm_struct *mm);
675extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
676extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
677extern void tsunami_flush_page_to_ram(unsigned long page);
678extern void tsunami_flush_page_for_dma(unsigned long page);
679extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
680extern void tsunami_flush_tlb_all(void);
681extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
682extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
683extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
684extern void tsunami_setup_blockops(void);
685
686/*
687 * Workaround, until we find what's going on with Swift. When low on memory,
688 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
689 * out it is already in page tables/ fault again on the same instruction.
690 * I really don't understand it, have checked it and contexts
691 * are right, flush_tlb_all is done as well, and it faults again...
692 * Strange. -jj
693 *
694 * The following code is a deadwood that may be necessary when
695 * we start to make precise page flushes again. --zaitcev
696 */
4b3073e1 697static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
1da177e4
LT		 698{
699#if 0
700 static unsigned long last;
701 unsigned int val;
702 /* unsigned int n; */
703
704 if (address == last) {
705 val = srmmu_hwprobe(address);
4b3073e1 706 if (val != 0 && pte_val(*ptep) != val) {
1da177e4
LT		 707 printk("swift_update_mmu_cache: "
708 "addr %lx put %08x probed %08x from %p\n",
4b3073e1 709 address, pte_val(*ptep), val,
1da177e4
LT		 710 __builtin_return_address(0));
711 srmmu_flush_whole_tlb();
712 }
713 }
714 last = address;
715#endif
716}
717
718/* swift.S */
719extern void swift_flush_cache_all(void);
720extern void swift_flush_cache_mm(struct mm_struct *mm);
721extern void swift_flush_cache_range(struct vm_area_struct *vma,
722 unsigned long start, unsigned long end);
723extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
724extern void swift_flush_page_to_ram(unsigned long page);
725extern void swift_flush_page_for_dma(unsigned long page);
726extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
727extern void swift_flush_tlb_all(void);
728extern void swift_flush_tlb_mm(struct mm_struct *mm);
729extern void swift_flush_tlb_range(struct vm_area_struct *vma,
730 unsigned long start, unsigned long end);
731extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
732
733#if 0 /* P3: deadwood to debug precise flushes on Swift. */
734void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
735{
736 int cctx, ctx1;
737
738 page &= PAGE_MASK;
739 if ((ctx1 = vma->vm_mm->context) != -1) {
740 cctx = srmmu_get_context();
741/* Is context # ever different from current context? P3 */
742 if (cctx != ctx1) {
743 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
744 srmmu_set_context(ctx1);
745 swift_flush_page(page);
746 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
747 "r" (page), "i" (ASI_M_FLUSH_PROBE));
748 srmmu_set_context(cctx);
749 } else {
750 /* Rm. prot. bits from virt. c. */
751 /* swift_flush_cache_all(); */
752 /* swift_flush_cache_page(vma, page); */
753 swift_flush_page(page);
754
755 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
756 "r" (page), "i" (ASI_M_FLUSH_PROBE));
757 /* same as above: srmmu_flush_tlb_page() */
758 }
759 }
760}
761#endif
762
763/*
764 * The following are all MBUS based SRMMU modules, and therefore could
765 * be found in a multiprocessor configuration. On the whole, these
766 * chips seems to be much more touchy about DVMA and page tables
767 * with respect to cache coherency.
768 */
769
770/* Cypress flushes. */
771static void cypress_flush_cache_all(void)
772{
773 volatile unsigned long cypress_sucks;
774 unsigned long faddr, tagval;
775
776 flush_user_windows();
777 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
778 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
779 "=r" (tagval) :
780 "r" (faddr), "r" (0x40000),
781 "i" (ASI_M_DATAC_TAG));
782
783 /* If modified and valid, kick it. */
784 if((tagval & 0x60) == 0x60)
785 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
786 }
787}
788
789static void cypress_flush_cache_mm(struct mm_struct *mm)
790{
791 register unsigned long a, b, c, d, e, f, g;
792 unsigned long flags, faddr;
793 int octx;
794
795 FLUSH_BEGIN(mm)
796 flush_user_windows();
797 local_irq_save(flags);
798 octx = srmmu_get_context();
799 srmmu_set_context(mm->context);
800 a = 0x20; b = 0x40; c = 0x60;
801 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
802
803 faddr = (0x10000 - 0x100);
804 goto inside;
805 do {
806 faddr -= 0x100;
807 inside:
808 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
809 "sta %%g0, [%0 + %2] %1\n\t"
810 "sta %%g0, [%0 + %3] %1\n\t"
811 "sta %%g0, [%0 + %4] %1\n\t"
812 "sta %%g0, [%0 + %5] %1\n\t"
813 "sta %%g0, [%0 + %6] %1\n\t"
814 "sta %%g0, [%0 + %7] %1\n\t"
815 "sta %%g0, [%0 + %8] %1\n\t" : :
816 "r" (faddr), "i" (ASI_M_FLUSH_CTX),
817 "r" (a), "r" (b), "r" (c), "r" (d),
818 "r" (e), "r" (f), "r" (g));
819 } while(faddr);
820 srmmu_set_context(octx);
821 local_irq_restore(flags);
822 FLUSH_END
823}
824
825static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
826{
827 struct mm_struct *mm = vma->vm_mm;
828 register unsigned long a, b, c, d, e, f, g;
829 unsigned long flags, faddr;
830 int octx;
831
832 FLUSH_BEGIN(mm)
833 flush_user_windows();
834 local_irq_save(flags);
835 octx = srmmu_get_context();
836 srmmu_set_context(mm->context);
837 a = 0x20; b = 0x40; c = 0x60;
838 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
839
840 start &= SRMMU_REAL_PMD_MASK;
841 while(start < end) {
842 faddr = (start + (0x10000 - 0x100));
843 goto inside;
844 do {
845 faddr -= 0x100;
846 inside:
847 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
848 "sta %%g0, [%0 + %2] %1\n\t"
849 "sta %%g0, [%0 + %3] %1\n\t"
850 "sta %%g0, [%0 + %4] %1\n\t"
851 "sta %%g0, [%0 + %5] %1\n\t"
852 "sta %%g0, [%0 + %6] %1\n\t"
853 "sta %%g0, [%0 + %7] %1\n\t"
854 "sta %%g0, [%0 + %8] %1\n\t" : :
855 "r" (faddr),
856 "i" (ASI_M_FLUSH_SEG),
857 "r" (a), "r" (b), "r" (c), "r" (d),
858 "r" (e), "r" (f), "r" (g));
859 } while (faddr != start);
860 start += SRMMU_REAL_PMD_SIZE;
861 }
862 srmmu_set_context(octx);
863 local_irq_restore(flags);
864 FLUSH_END
865}
866
867static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
868{
869 register unsigned long a, b, c, d, e, f, g;
870 struct mm_struct *mm = vma->vm_mm;
871 unsigned long flags, line;
872 int octx;
873
874 FLUSH_BEGIN(mm)
875 flush_user_windows();
876 local_irq_save(flags);
877 octx = srmmu_get_context();
878 srmmu_set_context(mm->context);
879 a = 0x20; b = 0x40; c = 0x60;
880 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
881
882 page &= PAGE_MASK;
883 line = (page + PAGE_SIZE) - 0x100;
884 goto inside;
885 do {
886 line -= 0x100;
887 inside:
888 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
889 "sta %%g0, [%0 + %2] %1\n\t"
890 "sta %%g0, [%0 + %3] %1\n\t"
891 "sta %%g0, [%0 + %4] %1\n\t"
892 "sta %%g0, [%0 + %5] %1\n\t"
893 "sta %%g0, [%0 + %6] %1\n\t"
894 "sta %%g0, [%0 + %7] %1\n\t"
895 "sta %%g0, [%0 + %8] %1\n\t" : :
896 "r" (line),
897 "i" (ASI_M_FLUSH_PAGE),
898 "r" (a), "r" (b), "r" (c), "r" (d),
899 "r" (e), "r" (f), "r" (g));
900 } while(line != page);
901 srmmu_set_context(octx);
902 local_irq_restore(flags);
903 FLUSH_END
904}
905
906/* Cypress is copy-back, at least that is how we configure it. */
907static void cypress_flush_page_to_ram(unsigned long page)
908{
909 register unsigned long a, b, c, d, e, f, g;
910 unsigned long line;
911
912 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
913 page &= PAGE_MASK;
914 line = (page + PAGE_SIZE) - 0x100;
915 goto inside;
916 do {
917 line -= 0x100;
918 inside:
919 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
920 "sta %%g0, [%0 + %2] %1\n\t"
921 "sta %%g0, [%0 + %3] %1\n\t"
922 "sta %%g0, [%0 + %4] %1\n\t"
923 "sta %%g0, [%0 + %5] %1\n\t"
924 "sta %%g0, [%0 + %6] %1\n\t"
925 "sta %%g0, [%0 + %7] %1\n\t"
926 "sta %%g0, [%0 + %8] %1\n\t" : :
927 "r" (line),
928 "i" (ASI_M_FLUSH_PAGE),
929 "r" (a), "r" (b), "r" (c), "r" (d),
930 "r" (e), "r" (f), "r" (g));
931 } while(line != page);
932}
933
934/* Cypress is also IO cache coherent. */
935static void cypress_flush_page_for_dma(unsigned long page)
936{
937}
938
939/* Cypress has unified L2 VIPT, from which both instructions and data
940 * are stored. It does not have an onboard icache of any sort, therefore
941 * no flush is necessary.
942 */
943static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
944{
945}
946
947static void cypress_flush_tlb_all(void)
948{
949 srmmu_flush_whole_tlb();
950}
951
952static void cypress_flush_tlb_mm(struct mm_struct *mm)
953{
954 FLUSH_BEGIN(mm)
955 __asm__ __volatile__(
956 "lda [%0] %3, %%g5\n\t"
957 "sta %2, [%0] %3\n\t"
958 "sta %%g0, [%1] %4\n\t"
959 "sta %%g5, [%0] %3\n"
960 : /* no outputs */
961 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
962 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
963 : "g5");
964 FLUSH_END
965}
966
967static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
968{
969 struct mm_struct *mm = vma->vm_mm;
970 unsigned long size;
971
972 FLUSH_BEGIN(mm)
973 start &= SRMMU_PGDIR_MASK;
974 size = SRMMU_PGDIR_ALIGN(end) - start;
975 __asm__ __volatile__(
976 "lda [%0] %5, %%g5\n\t"
977 "sta %1, [%0] %5\n"
978 "1:\n\t"
979 "subcc %3, %4, %3\n\t"
980 "bne 1b\n\t"
981 " sta %%g0, [%2 + %3] %6\n\t"
982 "sta %%g5, [%0] %5\n"
983 : /* no outputs */
984 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
985 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
986 "i" (ASI_M_FLUSH_PROBE)
987 : "g5", "cc");
988 FLUSH_END
989}
990
991static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
992{
993 struct mm_struct *mm = vma->vm_mm;
994
995 FLUSH_BEGIN(mm)
996 __asm__ __volatile__(
997 "lda [%0] %3, %%g5\n\t"
998 "sta %1, [%0] %3\n\t"
999 "sta %%g0, [%2] %4\n\t"
1000 "sta %%g5, [%0] %3\n"
1001 : /* no outputs */
1002 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
1003 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
1004 : "g5");
1005 FLUSH_END
1006}
1007
1008/* viking.S */
1009extern void viking_flush_cache_all(void);
1010extern void viking_flush_cache_mm(struct mm_struct *mm);
1011extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1012 unsigned long end);
1013extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1014extern void viking_flush_page_to_ram(unsigned long page);
1015extern void viking_flush_page_for_dma(unsigned long page);
1016extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1017extern void viking_flush_page(unsigned long page);
1018extern void viking_mxcc_flush_page(unsigned long page);
1019extern void viking_flush_tlb_all(void);
1020extern void viking_flush_tlb_mm(struct mm_struct *mm);
1021extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1022 unsigned long end);
1023extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1024 unsigned long page);
1025extern void sun4dsmp_flush_tlb_all(void);
1026extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1027extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1028 unsigned long end);
1029extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1030 unsigned long page);
1031
1032/* hypersparc.S */
1033extern void hypersparc_flush_cache_all(void);
1034extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1035extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1036extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1037extern void hypersparc_flush_page_to_ram(unsigned long page);
1038extern void hypersparc_flush_page_for_dma(unsigned long page);
1039extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1040extern void hypersparc_flush_tlb_all(void);
1041extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1042extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1043extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1044extern void hypersparc_setup_blockops(void);
1045
1046/*
1047 * NOTE: All of this startup code assumes the low 16mb (approx.) of
1048 * kernel mappings are done with one single contiguous chunk of
1049 * ram. On small ram machines (classics mainly) we only get
1050 * around 8mb mapped for us.
1051 */
1052
50215d65 1053static void __init early_pgtable_allocfail(char *type)
1da177e4
LT		 1054{
1055 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1056 prom_halt();
1057}
1058
50215d65
AB		 1059static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
1060 unsigned long end)
1da177e4
LT		 1061{
1062 pgd_t *pgdp;
1063 pmd_t *pmdp;
1064 pte_t *ptep;
1065
1066 while(start < end) {
1067 pgdp = pgd_offset_k(start);
1068 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1069 pmdp = (pmd_t *) __srmmu_get_nocache(
1070 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1071 if (pmdp == NULL)
1072 early_pgtable_allocfail("pmd");
1073 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1074 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1075 }
1076 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1077 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1078 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1079 if (ptep == NULL)
1080 early_pgtable_allocfail("pte");
1081 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1082 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1083 }
1084 if (start > (0xffffffffUL - PMD_SIZE))
1085 break;
1086 start = (start + PMD_SIZE) & PMD_MASK;
1087 }
1088}
1089
50215d65
AB		 1090static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1091 unsigned long end)
1da177e4
LT		 1092{
1093 pgd_t *pgdp;
1094 pmd_t *pmdp;
1095 pte_t *ptep;
1096
1097 while(start < end) {
1098 pgdp = pgd_offset_k(start);
1099 if(srmmu_pgd_none(*pgdp)) {
1100 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1101 if (pmdp == NULL)
1102 early_pgtable_allocfail("pmd");
1103 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1104 srmmu_pgd_set(pgdp, pmdp);
1105 }
1106 pmdp = srmmu_pmd_offset(pgdp, start);
1107 if(srmmu_pmd_none(*pmdp)) {
1108 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1109 PTE_SIZE);
1110 if (ptep == NULL)
1111 early_pgtable_allocfail("pte");
1112 memset(ptep, 0, PTE_SIZE);
1113 srmmu_pmd_set(pmdp, ptep);
1114 }
1115 if (start > (0xffffffffUL - PMD_SIZE))
1116 break;
1117 start = (start + PMD_SIZE) & PMD_MASK;
1118 }
1119}
1120
1121/*
1122 * This is much cleaner than poking around physical address space
1123 * looking at the prom's page table directly which is what most
1124 * other OS's do. Yuck... this is much better.
1125 */
50215d65
AB		 1126static void __init srmmu_inherit_prom_mappings(unsigned long start,
1127 unsigned long end)
1da177e4
LT		 1128{
1129 pgd_t *pgdp;
1130 pmd_t *pmdp;
1131 pte_t *ptep;
1132 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1133 unsigned long prompte;
1134
1135 while(start <= end) {
1136 if (start == 0)
1137 break; /* probably wrap around */
1138 if(start == 0xfef00000)
1139 start = KADB_DEBUGGER_BEGVM;
1140 if(!(prompte = srmmu_hwprobe(start))) {
1141 start += PAGE_SIZE;
1142 continue;
1143 }
1144
1145 /* A red snapper, see what it really is. */
1146 what = 0;
1147
1148 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1149 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1150 what = 1;
1151 }
1152
1153 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1154 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1155 prompte)
1156 what = 2;
1157 }
1158
1159 pgdp = pgd_offset_k(start);
1160 if(what == 2) {
1161 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1162 start += SRMMU_PGDIR_SIZE;
1163 continue;
1164 }
1165 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1166 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1167 if (pmdp == NULL)
1168 early_pgtable_allocfail("pmd");
1169 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1170 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1171 }
1172 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1173 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1174 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1175 PTE_SIZE);
1176 if (ptep == NULL)
1177 early_pgtable_allocfail("pte");
1178 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1179 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1180 }
1181 if(what == 1) {
1182 /*
1183 * We bend the rule where all 16 PTPs in a pmd_t point
1184 * inside the same PTE page, and we leak a perfectly
1185 * good hardware PTE piece. Alternatives seem worse.
1186 */
1187 unsigned int x; /* Index of HW PMD in soft cluster */
1188 x = (start >> PMD_SHIFT) & 15;
1189 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1190 start += SRMMU_REAL_PMD_SIZE;
1191 continue;
1192 }
1193 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1194 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1195 start += PAGE_SIZE;
1196 }
1197}
1198
1199#define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1200
1201/* Create a third-level SRMMU 16MB page mapping. */
1202static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1203{
1204 pgd_t *pgdp = pgd_offset_k(vaddr);
1205 unsigned long big_pte;
1206
1207 big_pte = KERNEL_PTE(phys_base >> 4);
1208 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1209}
1210
1211/* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1212static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1213{
1214 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1215 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1216 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1217 /* Map "low" memory only */
1218 const unsigned long min_vaddr = PAGE_OFFSET;
1219 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1220
1221 if (vstart < min_vaddr || vstart >= max_vaddr)
1222 return vstart;
1223
1224 if (vend > max_vaddr || vend < min_vaddr)
1225 vend = max_vaddr;
1226
1227 while(vstart < vend) {
1228 do_large_mapping(vstart, pstart);
1229 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1230 }
1231 return vstart;
1232}
1233
1234static inline void memprobe_error(char *msg)
1235{
1236 prom_printf(msg);
1237 prom_printf("Halting now...\n");
1238 prom_halt();
1239}
1240
1241static inline void map_kernel(void)
1242{
1243 int i;
1244
1245 if (phys_base > 0) {
1246 do_large_mapping(PAGE_OFFSET, phys_base);
1247 }
1248
1249 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1250 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1251 }
1252
1253 BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1254}
1255
1256/* Paging initialization on the Sparc Reference MMU. */
1257extern void sparc_context_init(int);
1258
409832f5 1259void (*poke_srmmu)(void) __cpuinitdata = NULL;
1da177e4
LT		 1260
1261extern unsigned long bootmem_init(unsigned long *pages_avail);
1262
1263void __init srmmu_paging_init(void)
1264{
1265 int i, cpunode;
1266 char node_str[128];
1267 pgd_t *pgd;
1268 pmd_t *pmd;
1269 pte_t *pte;
1270 unsigned long pages_avail;
1271
1272 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1273
1274 if (sparc_cpu_model == sun4d)
1275 num_contexts = 65536; /* We know it is Viking */
1276 else {
1277 /* Find the number of contexts on the srmmu. */
1278 cpunode = prom_getchild(prom_root_node);
1279 num_contexts = 0;
1280 while(cpunode != 0) {
1281 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1282 if(!strcmp(node_str, "cpu")) {
1283 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1284 break;
1285 }
1286 cpunode = prom_getsibling(cpunode);
1287 }
1288 }
1289
1290 if(!num_contexts) {
1291 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1292 prom_halt();
1293 }
1294
1295 pages_avail = 0;
1296 last_valid_pfn = bootmem_init(&pages_avail);
1297
1298 srmmu_nocache_calcsize();
1299 srmmu_nocache_init();
1300 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1301 map_kernel();
1302
1303 /* ctx table has to be physically aligned to its size */
1304 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1305 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1306
1307 for(i = 0; i < num_contexts; i++)
1308 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1309
1310 flush_cache_all();
1311 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
a54123e2
BB		 1312#ifdef CONFIG_SMP
1313 /* Stop from hanging here... */
1314 local_flush_tlb_all();
1315#else
1da177e4 1316 flush_tlb_all();
a54123e2 1317#endif
1da177e4
LT		 1318 poke_srmmu();
1319
1da177e4
LT		 1320 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1321 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1da177e4
LT		 1322
1323 srmmu_allocate_ptable_skeleton(
1324 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1325 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1326
1327 pgd = pgd_offset_k(PKMAP_BASE);
1328 pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1329 pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1330 pkmap_page_table = pte;
1331
1332 flush_cache_all();
1333 flush_tlb_all();
1334
1335 sparc_context_init(num_contexts);
1336
1337 kmap_init();
1338
1339 {
1340 unsigned long zones_size[MAX_NR_ZONES];
1341 unsigned long zholes_size[MAX_NR_ZONES];
1342 unsigned long npages;
1343 int znum;
1344
1345 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1346 zones_size[znum] = zholes_size[znum] = 0;
1347
1348 npages = max_low_pfn - pfn_base;
1349
1350 zones_size[ZONE_DMA] = npages;
1351 zholes_size[ZONE_DMA] = npages - pages_avail;
1352
1353 npages = highend_pfn - max_low_pfn;
1354 zones_size[ZONE_HIGHMEM] = npages;
1355 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1356
9109fb7b 1357 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1da177e4
LT		 1358 }
1359}
1360
1361static void srmmu_mmu_info(struct seq_file *m)
1362{
1363 seq_printf(m,
1364 "MMU type\t: %s\n"
1365 "contexts\t: %d\n"
1366 "nocache total\t: %ld\n"
1367 "nocache used\t: %d\n",
1368 srmmu_name,
1369 num_contexts,
1370 srmmu_nocache_size,
1371 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1372}
1373
1374static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1375{
1376}
1377
1378static void srmmu_destroy_context(struct mm_struct *mm)
1379{
1380
1381 if(mm->context != NO_CONTEXT) {
1382 flush_cache_mm(mm);
1383 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1384 flush_tlb_mm(mm);
1385 spin_lock(&srmmu_context_spinlock);
1386 free_context(mm->context);
1387 spin_unlock(&srmmu_context_spinlock);
1388 mm->context = NO_CONTEXT;
1389 }
1390}
1391
1392/* Init various srmmu chip types. */
1393static void __init srmmu_is_bad(void)
1394{
1395 prom_printf("Could not determine SRMMU chip type.\n");
1396 prom_halt();
1397}
1398
1399static void __init init_vac_layout(void)
1400{
1401 int nd, cache_lines;
1402 char node_str[128];
1403#ifdef CONFIG_SMP
1404 int cpu = 0;
1405 unsigned long max_size = 0;
1406 unsigned long min_line_size = 0x10000000;
1407#endif
1408
1409 nd = prom_getchild(prom_root_node);
1410 while((nd = prom_getsibling(nd)) != 0) {
1411 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1412 if(!strcmp(node_str, "cpu")) {
1413 vac_line_size = prom_getint(nd, "cache-line-size");
1414 if (vac_line_size == -1) {
1415 prom_printf("can't determine cache-line-size, "
1416 "halting.\n");
1417 prom_halt();
1418 }
1419 cache_lines = prom_getint(nd, "cache-nlines");
1420 if (cache_lines == -1) {
1421 prom_printf("can't determine cache-nlines, halting.\n");
1422 prom_halt();
1423 }
1424
1425 vac_cache_size = cache_lines * vac_line_size;
1426#ifdef CONFIG_SMP
1427 if(vac_cache_size > max_size)
1428 max_size = vac_cache_size;
1429 if(vac_line_size < min_line_size)
1430 min_line_size = vac_line_size;
a54123e2 1431 //FIXME: cpus not contiguous!!
1da177e4 1432 cpu++;
ec7c14bd 1433 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1da177e4
LT		 1434 break;
1435#else
1436 break;
1437#endif
1438 }
1439 }
1440 if(nd == 0) {
1441 prom_printf("No CPU nodes found, halting.\n");
1442 prom_halt();
1443 }
1444#ifdef CONFIG_SMP
1445 vac_cache_size = max_size;
1446 vac_line_size = min_line_size;
1447#endif
1448 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1449 (int)vac_cache_size, (int)vac_line_size);
1450}
1451
409832f5 1452static void __cpuinit poke_hypersparc(void)
1da177e4
LT		 1453{
1454 volatile unsigned long clear;
1455 unsigned long mreg = srmmu_get_mmureg();
1456
1457 hyper_flush_unconditional_combined();
1458
1459 mreg &= ~(HYPERSPARC_CWENABLE);
1460 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1461 mreg |= (HYPERSPARC_CMODE);
1462
1463 srmmu_set_mmureg(mreg);
1464
1465#if 0 /* XXX I think this is bad news... -DaveM */
1466 hyper_clear_all_tags();
1467#endif
1468
1469 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1470 hyper_flush_whole_icache();
1471 clear = srmmu_get_faddr();
1472 clear = srmmu_get_fstatus();
1473}
1474
1475static void __init init_hypersparc(void)
1476{
1477 srmmu_name = "ROSS HyperSparc";
1478 srmmu_modtype = HyperSparc;
1479
1480 init_vac_layout();
1481
1482 is_hypersparc = 1;
1483
1484 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1485 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1486 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1487 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1488 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1489 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1490 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1491
1492 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1493 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1494 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1495 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1496
1497 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1498 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1499 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1500
1501
1502 poke_srmmu = poke_hypersparc;
1503
1504 hypersparc_setup_blockops();
1505}
1506
409832f5 1507static void __cpuinit poke_cypress(void)
1da177e4
LT		 1508{
1509 unsigned long mreg = srmmu_get_mmureg();
1510 unsigned long faddr, tagval;
1511 volatile unsigned long cypress_sucks;
1512 volatile unsigned long clear;
1513
1514 clear = srmmu_get_faddr();
1515 clear = srmmu_get_fstatus();
1516
1517 if (!(mreg & CYPRESS_CENABLE)) {
1518 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1519 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1520 "sta %%g0, [%0] %2\n\t" : :
1521 "r" (faddr), "r" (0x40000),
1522 "i" (ASI_M_DATAC_TAG));
1523 }
1524 } else {
1525 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1526 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1527 "=r" (tagval) :
1528 "r" (faddr), "r" (0x40000),
1529 "i" (ASI_M_DATAC_TAG));
1530
1531 /* If modified and valid, kick it. */
1532 if((tagval & 0x60) == 0x60)
1533 cypress_sucks = *(unsigned long *)
1534 (0xf0020000 + faddr);
1535 }
1536 }
1537
1538 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1539 clear = srmmu_get_faddr();
1540 clear = srmmu_get_fstatus();
1541
1542 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1543 srmmu_set_mmureg(mreg);
1544}
1545
1546static void __init init_cypress_common(void)
1547{
1548 init_vac_layout();
1549
1550 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1551 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1552 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1553 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1554 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1555 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1556 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1557
1558 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1559 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1560 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1561 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1562
1563
1564 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1565 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1566 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1567
1568 poke_srmmu = poke_cypress;
1569}
1570
1571static void __init init_cypress_604(void)
1572{
1573 srmmu_name = "ROSS Cypress-604(UP)";
1574 srmmu_modtype = Cypress;
1575 init_cypress_common();
1576}
1577
1578static void __init init_cypress_605(unsigned long mrev)
1579{
1580 srmmu_name = "ROSS Cypress-605(MP)";
1581 if(mrev == 0xe) {
1582 srmmu_modtype = Cypress_vE;
1583 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1584 } else {
1585 if(mrev == 0xd) {
1586 srmmu_modtype = Cypress_vD;
1587 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1588 } else {
1589 srmmu_modtype = Cypress;
1590 }
1591 }
1592 init_cypress_common();
1593}
1594
409832f5 1595static void __cpuinit poke_swift(void)
1da177e4
LT		 1596{
1597 unsigned long mreg;
1598
1599 /* Clear any crap from the cache or else... */
1600 swift_flush_cache_all();
1601
1602 /* Enable I & D caches */
1603 mreg = srmmu_get_mmureg();
1604 mreg |= (SWIFT_IE | SWIFT_DE);
1605 /*
1606 * The Swift branch folding logic is completely broken. At
1607 * trap time, if things are just right, if can mistakenly
1608 * think that a trap is coming from kernel mode when in fact
1609 * it is coming from user mode (it mis-executes the branch in
1610 * the trap code). So you see things like crashme completely
1611 * hosing your machine which is completely unacceptable. Turn
1612 * this shit off... nice job Fujitsu.
1613 */
1614 mreg &= ~(SWIFT_BF);
1615 srmmu_set_mmureg(mreg);
1616}
1617
1618#define SWIFT_MASKID_ADDR 0x10003018
1619static void __init init_swift(void)
1620{
1621 unsigned long swift_rev;
1622
1623 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1624 "srl %0, 0x18, %0\n\t" :
1625 "=r" (swift_rev) :
1626 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1627 srmmu_name = "Fujitsu Swift";
1628 switch(swift_rev) {
1629 case 0x11:
1630 case 0x20:
1631 case 0x23:
1632 case 0x30:
1633 srmmu_modtype = Swift_lots_o_bugs;
1634 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1635 /*
1636 * Gee george, I wonder why Sun is so hush hush about
1637 * this hardware bug... really braindamage stuff going
1638 * on here. However I think we can find a way to avoid
1639 * all of the workaround overhead under Linux. Basically,
1640 * any page fault can cause kernel pages to become user
1641 * accessible (the mmu gets confused and clears some of
1642 * the ACC bits in kernel ptes). Aha, sounds pretty
1643 * horrible eh? But wait, after extensive testing it appears
1644 * that if you use pgd_t level large kernel pte's (like the
1645 * 4MB pages on the Pentium) the bug does not get tripped
1646 * at all. This avoids almost all of the major overhead.
1647 * Welcome to a world where your vendor tells you to,
1648 * "apply this kernel patch" instead of "sorry for the
1649 * broken hardware, send it back and we'll give you
1650 * properly functioning parts"
1651 */
1652 break;
1653 case 0x25:
1654 case 0x31:
1655 srmmu_modtype = Swift_bad_c;
1656 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1657 /*
1658 * You see Sun allude to this hardware bug but never
1659 * admit things directly, they'll say things like,
1660 * "the Swift chip cache problems" or similar.
1661 */
1662 break;
1663 default:
1664 srmmu_modtype = Swift_ok;
1665 break;
1666 };
1667
1668 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1669 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1670 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1671 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1672
1673
1674 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1675 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1676 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1677 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1678
1679 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1680 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1681 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1682
1683 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1684
1685 flush_page_for_dma_global = 0;
1686
1687 /*
1688 * Are you now convinced that the Swift is one of the
1689 * biggest VLSI abortions of all time? Bravo Fujitsu!
1690 * Fujitsu, the !#?!%$'d up processor people. I bet if
1691 * you examined the microcode of the Swift you'd find
1692 * XXX's all over the place.
1693 */
1694 poke_srmmu = poke_swift;
1695}
1696
1697static void turbosparc_flush_cache_all(void)
1698{
1699 flush_user_windows();
1700 turbosparc_idflash_clear();
1701}
1702
1703static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1704{
1705 FLUSH_BEGIN(mm)
1706 flush_user_windows();
1707 turbosparc_idflash_clear();
1708 FLUSH_END
1709}
1710
1711static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1712{
1713 FLUSH_BEGIN(vma->vm_mm)
1714 flush_user_windows();
1715 turbosparc_idflash_clear();
1716 FLUSH_END
1717}
1718
1719static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1720{
1721 FLUSH_BEGIN(vma->vm_mm)
1722 flush_user_windows();
1723 if (vma->vm_flags & VM_EXEC)
1724 turbosparc_flush_icache();
1725 turbosparc_flush_dcache();
1726 FLUSH_END
1727}
1728
1729/* TurboSparc is copy-back, if we turn it on, but this does not work. */
1730static void turbosparc_flush_page_to_ram(unsigned long page)
1731{
1732#ifdef TURBOSPARC_WRITEBACK
1733 volatile unsigned long clear;
1734
1735 if (srmmu_hwprobe(page))
1736 turbosparc_flush_page_cache(page);
1737 clear = srmmu_get_fstatus();
1738#endif
1739}
1740
1741static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1742{
1743}
1744
1745static void turbosparc_flush_page_for_dma(unsigned long page)
1746{
1747 turbosparc_flush_dcache();
1748}
1749
1750static void turbosparc_flush_tlb_all(void)
1751{
1752 srmmu_flush_whole_tlb();
1753}
1754
1755static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1756{
1757 FLUSH_BEGIN(mm)
1758 srmmu_flush_whole_tlb();
1759 FLUSH_END
1760}
1761
1762static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1763{
1764 FLUSH_BEGIN(vma->vm_mm)
1765 srmmu_flush_whole_tlb();
1766 FLUSH_END
1767}
1768
1769static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1770{
1771 FLUSH_BEGIN(vma->vm_mm)
1772 srmmu_flush_whole_tlb();
1773 FLUSH_END
1774}
1775
1776
409832f5 1777static void __cpuinit poke_turbosparc(void)
1da177e4
LT		 1778{
1779 unsigned long mreg = srmmu_get_mmureg();
1780 unsigned long ccreg;
1781
1782 /* Clear any crap from the cache or else... */
1783 turbosparc_flush_cache_all();
1784 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1785 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1786 srmmu_set_mmureg(mreg);
1787
1788 ccreg = turbosparc_get_ccreg();
1789
1790#ifdef TURBOSPARC_WRITEBACK
1791 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1792 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1793 /* Write-back D-cache, emulate VLSI
1794 * abortion number three, not number one */
1795#else
1796 /* For now let's play safe, optimize later */
1797 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1798 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1799 ccreg &= ~(TURBOSPARC_uS2);
1800 /* Emulate VLSI abortion number three, not number one */
1801#endif
1802
1803 switch (ccreg & 7) {
1804 case 0: /* No SE cache */
1805 case 7: /* Test mode */
1806 break;
1807 default:
1808 ccreg |= (TURBOSPARC_SCENABLE);
1809 }
1810 turbosparc_set_ccreg (ccreg);
1811
1812 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1813 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1814 srmmu_set_mmureg(mreg);
1815}
1816
1817static void __init init_turbosparc(void)
1818{
1819 srmmu_name = "Fujitsu TurboSparc";
1820 srmmu_modtype = TurboSparc;
1821
1822 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1823 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1824 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1825 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1826
1827 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1828 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1829 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1830 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1831
1832 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1833
1834 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1835 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1836
1837 poke_srmmu = poke_turbosparc;
1838}
1839
409832f5 1840static void __cpuinit poke_tsunami(void)
1da177e4
LT		 1841{
1842 unsigned long mreg = srmmu_get_mmureg();
1843
1844 tsunami_flush_icache();
1845 tsunami_flush_dcache();
1846 mreg &= ~TSUNAMI_ITD;
1847 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1848 srmmu_set_mmureg(mreg);
1849}
1850
1851static void __init init_tsunami(void)
1852{
1853 /*
1854 * Tsunami's pretty sane, Sun and TI actually got it
1855 * somewhat right this time. Fujitsu should have
1856 * taken some lessons from them.
1857 */
1858
1859 srmmu_name = "TI Tsunami";
1860 srmmu_modtype = Tsunami;
1861
1862 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1863 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1864 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1865 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1866
1867
1868 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1869 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1870 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1871 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1872
1873 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1874 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1875 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1876
1877 poke_srmmu = poke_tsunami;
1878
1879 tsunami_setup_blockops();
1880}
1881
409832f5 1882static void __cpuinit poke_viking(void)
1da177e4
LT		 1883{
1884 unsigned long mreg = srmmu_get_mmureg();
1885 static int smp_catch;
1886
1887 if(viking_mxcc_present) {
1888 unsigned long mxcc_control = mxcc_get_creg();
1889
1890 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1891 mxcc_control &= ~(MXCC_CTL_RRC);
1892 mxcc_set_creg(mxcc_control);
1893
1894 /*
1895 * We don't need memory parity checks.
1896 * XXX This is a mess, have to dig out later. ecd.
1897 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1898 */
1899
1900 /* We do cache ptables on MXCC. */
1901 mreg |= VIKING_TCENABLE;
1902 } else {
1903 unsigned long bpreg;
1904
1905 mreg &= ~(VIKING_TCENABLE);
1906 if(smp_catch++) {
1907 /* Must disable mixed-cmd mode here for other cpu's. */
1908 bpreg = viking_get_bpreg();
1909 bpreg &= ~(VIKING_ACTION_MIX);
1910 viking_set_bpreg(bpreg);
1911
1912 /* Just in case PROM does something funny. */
1913 msi_set_sync();
1914 }
1915 }
1916
1917 mreg |= VIKING_SPENABLE;
1918 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1919 mreg |= VIKING_SBENABLE;
1920 mreg &= ~(VIKING_ACENABLE);
1921 srmmu_set_mmureg(mreg);
1da177e4
LT		 1922}
1923
1924static void __init init_viking(void)
1925{
1926 unsigned long mreg = srmmu_get_mmureg();
1927
1928 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1929 if(mreg & VIKING_MMODE) {
1930 srmmu_name = "TI Viking";
1931 viking_mxcc_present = 0;
1932 msi_set_sync();
1933
1934 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1935 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1936 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1937
1938 /*
1939 * We need this to make sure old viking takes no hits
1940 * on it's cache for dma snoops to workaround the
1941 * "load from non-cacheable memory" interrupt bug.
1942 * This is only necessary because of the new way in
1943 * which we use the IOMMU.
1944 */
1945 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1946
1947 flush_page_for_dma_global = 0;
1948 } else {
1949 srmmu_name = "TI Viking/MXCC";
1950 viking_mxcc_present = 1;
1951
1952 srmmu_cache_pagetables = 1;
1953
1954 /* MXCC vikings lack the DMA snooping bug. */
1955 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1956 }
1957
1958 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1959 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1960 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1961 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1962
1963#ifdef CONFIG_SMP
1964 if (sparc_cpu_model == sun4d) {
1965 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1966 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1967 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1968 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1969 } else
1970#endif
1971 {
1972 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1973 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1974 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1975 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1976 }
1977
1978 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1979 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1980
1981 poke_srmmu = poke_viking;
1982}
1983
75d9e346
KE		 1984#ifdef CONFIG_SPARC_LEON
1985
1986void __init poke_leonsparc(void)
1987{
1988}
1989
1990void __init init_leon(void)
1991{
1992
c803ba90 1993 srmmu_name = "LEON";
75d9e346
KE		 1994
1995 BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1996 BTFIXUPCALL_NORM);
1997 BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1998 BTFIXUPCALL_NORM);
1999 BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
2000 BTFIXUPCALL_NORM);
2001 BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
2002 BTFIXUPCALL_NORM);
2003 BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
2004 BTFIXUPCALL_NORM);
2005
2006 BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2007 BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2008 BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2009 BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2010
2011 BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
2012 BTFIXUPCALL_NOP);
2013 BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
2014
2015 poke_srmmu = poke_leonsparc;
2016
2017 srmmu_cache_pagetables = 0;
2018
2019 leon_flush_during_switch = leon_flush_needed();
2020}
2021#endif
2022
1da177e4
LT		 2023/* Probe for the srmmu chip version. */
2024static void __init get_srmmu_type(void)
2025{
2026 unsigned long mreg, psr;
2027 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
2028
2029 srmmu_modtype = SRMMU_INVAL_MOD;
2030 hwbug_bitmask = 0;
2031
2032 mreg = srmmu_get_mmureg(); psr = get_psr();
2033 mod_typ = (mreg & 0xf0000000) >> 28;
2034 mod_rev = (mreg & 0x0f000000) >> 24;
2035 psr_typ = (psr >> 28) & 0xf;
2036 psr_vers = (psr >> 24) & 0xf;
2037
75d9e346
KE		 2038 /* First, check for sparc-leon. */
2039 if (sparc_cpu_model == sparc_leon) {
75d9e346
KE		 2040 init_leon();
2041 return;
2042 }
2043
2044 /* Second, check for HyperSparc or Cypress. */
1da177e4
LT		 2045 if(mod_typ == 1) {
2046 switch(mod_rev) {
2047 case 7:
2048 /* UP or MP Hypersparc */
2049 init_hypersparc();
2050 break;
2051 case 0:
2052 case 2:
2053 /* Uniprocessor Cypress */
2054 init_cypress_604();
2055 break;
2056 case 10:
2057 case 11:
2058 case 12:
2059 /* _REALLY OLD_ Cypress MP chips... */
2060 case 13:
2061 case 14:
2062 case 15:
2063 /* MP Cypress mmu/cache-controller */
2064 init_cypress_605(mod_rev);
2065 break;
2066 default:
2067 /* Some other Cypress revision, assume a 605. */
2068 init_cypress_605(mod_rev);
2069 break;
2070 };
2071 return;
2072 }
2073
2074 /*
2075 * Now Fujitsu TurboSparc. It might happen that it is
2076 * in Swift emulation mode, so we will check later...
2077 */
2078 if (psr_typ == 0 && psr_vers == 5) {
2079 init_turbosparc();
2080 return;
2081 }
2082
2083 /* Next check for Fujitsu Swift. */
2084 if(psr_typ == 0 && psr_vers == 4) {
2085 int cpunode;
2086 char node_str[128];
2087
2088 /* Look if it is not a TurboSparc emulating Swift... */
2089 cpunode = prom_getchild(prom_root_node);
2090 while((cpunode = prom_getsibling(cpunode)) != 0) {
2091 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2092 if(!strcmp(node_str, "cpu")) {
2093 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2094 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2095 init_turbosparc();
2096 return;
2097 }
2098 break;
2099 }
2100 }
2101
2102 init_swift();
2103 return;
2104 }
2105
2106 /* Now the Viking family of srmmu. */
2107 if(psr_typ == 4 &&
2108 ((psr_vers == 0) ||
2109 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2110 init_viking();
2111 return;
2112 }
2113
2114 /* Finally the Tsunami. */
2115 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2116 init_tsunami();
2117 return;
2118 }
2119
2120 /* Oh well */
2121 srmmu_is_bad();
2122}
2123
2124/* don't laugh, static pagetables */
2125static void srmmu_check_pgt_cache(int low, int high)
2126{
2127}
2128
2129extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2130 tsetup_mmu_patchme, rtrap_mmu_patchme;
2131
2132extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2133 tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2134
2135extern unsigned long srmmu_fault;
2136
2137#define PATCH_BRANCH(insn, dest) do { \
2138 iaddr = &(insn); \
2139 daddr = &(dest); \
2140 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2141 } while(0)
2142
2143static void __init patch_window_trap_handlers(void)
2144{
2145 unsigned long *iaddr, *daddr;
2146
2147 PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2148 PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2149 PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2150 PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2151 PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2152 PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2153 PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2154}
2155
2156#ifdef CONFIG_SMP
2157/* Local cross-calls. */
2158static void smp_flush_page_for_dma(unsigned long page)
2159{
2160 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2161 local_flush_page_for_dma(page);
2162}
2163
2164#endif
2165
2166static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2167{
2168 return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2169}
2170
2171static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2172{
2173 return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2174}
2175
14778d90
DM		 2176static pgprot_t srmmu_pgprot_noncached(pgprot_t prot)
2177{
2178 prot &= ~__pgprot(SRMMU_CACHE);
2179
2180 return prot;
2181}
2182
1da177e4
LT		 2183/* Load up routines and constants for sun4m and sun4d mmu */
2184void __init ld_mmu_srmmu(void)
2185{
2186 extern void ld_mmu_iommu(void);
2187 extern void ld_mmu_iounit(void);
2188 extern void ___xchg32_sun4md(void);
2189
2190 BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2191 BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2192 BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2193
2194 BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2195 BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2196
2197 BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
378e515c 2198 PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
1da177e4
LT		 2199 BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2200 BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2201 BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2202 page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
1da177e4
LT		 2203
2204 /* Functions */
14778d90 2205 BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM);
1da177e4
LT		 2206#ifndef CONFIG_SMP
2207 BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2208#endif
2209 BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2210
2211 BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2212 BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2213
2214 BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2215 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
46a82b2d 2216 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
1da177e4 2217
1da177e4
LT		 2218 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2219 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
1da177e4
LT		 2220
2221 BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2222 BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2223 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2224
2225 BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2226 BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2227 BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2228 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2229
2230 BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2231 BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2232 BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2233 BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2234 BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2235 BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2236
2237 BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2238 BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2239 BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2240
2241 BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2242 BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2243 BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2244 BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2245 BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2246 BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2247 BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2248 BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2249
2250 BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2251 BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2252 BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2253 BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2254 BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2255 BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2256 BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2257 BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2258 BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2259 BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2260 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2261 BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2262
2263 BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2264 BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2265
2266 BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2267 BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2268 BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2269
2270 BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2271
2272 BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2273 BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2274
2275 BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2276 BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2277
2278 get_srmmu_type();
2279 patch_window_trap_handlers();
2280
2281#ifdef CONFIG_SMP
2282 /* El switcheroo... */
2283
2284 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2285 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2286 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2287 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2288 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2289 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2290 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2291 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2292 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2293 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2294 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2295
2296 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2297 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2298 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2299 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
8401707f
KE		 2300 if (sparc_cpu_model != sun4d &&
2301 sparc_cpu_model != sparc_leon) {
1da177e4
LT		 2302 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2303 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2304 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2305 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2306 }
2307 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2308 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2309 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
64273d08
DM		 2310
2311 if (poke_srmmu == poke_viking) {
2312 /* Avoid unnecessary cross calls. */
2313 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2314 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2315 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2316 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2317 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2318 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2319 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2320 }
1da177e4
LT		 2321#endif
2322
2323 if (sparc_cpu_model == sun4d)
2324 ld_mmu_iounit();
2325 else
2326 ld_mmu_iommu();
2327#ifdef CONFIG_SMP
2328 if (sparc_cpu_model == sun4d)
2329 sun4d_init_smp();
8401707f
KE		 2330 else if (sparc_cpu_model == sparc_leon)
2331 leon_init_smp();
1da177e4
LT		 2332 else
2333 sun4m_init_smp();
2334#endif
2335}
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