[net-next-2.6.git] / arch / sparc / include / asm / spitfire.h

/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC64_SPITFIRE_H
#define _SPARC64_SPITFIRE_H

#ifdef CONFIG_SPARC64

#include <asm/asi.h>

/* The following register addresses are accessible via ASI_DMMU
 * and ASI_IMMU, that is there is a distinct and unique copy of
 * each these registers for each TLB.
 */
#define TSB_TAG_TARGET		0x0000000000000000 /* All chips				*/
#define TLB_SFSR		0x0000000000000018 /* All chips				*/
#define TSB_REG			0x0000000000000028 /* All chips				*/
#define TLB_TAG_ACCESS		0x0000000000000030 /* All chips				*/
#define VIRT_WATCHPOINT		0x0000000000000038 /* All chips				*/
#define PHYS_WATCHPOINT		0x0000000000000040 /* All chips				*/
#define TSB_EXTENSION_P		0x0000000000000048 /* Ultra-III and later		*/
#define TSB_EXTENSION_S		0x0000000000000050 /* Ultra-III and later, D-TLB only	*/
#define TSB_EXTENSION_N		0x0000000000000058 /* Ultra-III and later		*/
#define TLB_TAG_ACCESS_EXT	0x0000000000000060 /* Ultra-III+ and later		*/

/* These registers only exist as one entity, and are accessed
 * via ASI_DMMU only.
 */
#define PRIMARY_CONTEXT		0x0000000000000008
#define SECONDARY_CONTEXT	0x0000000000000010
#define DMMU_SFAR		0x0000000000000020
#define VIRT_WATCHPOINT		0x0000000000000038
#define PHYS_WATCHPOINT		0x0000000000000040

#define SPITFIRE_HIGHEST_LOCKED_TLBENT	(64 - 1)
#define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)

#define L1DCACHE_SIZE		0x4000

#define SUN4V_CHIP_INVALID	0x00
#define SUN4V_CHIP_NIAGARA1	0x01
#define SUN4V_CHIP_NIAGARA2	0x02
#define SUN4V_CHIP_UNKNOWN	0xff

#ifndef __ASSEMBLY__

enum ultra_tlb_layout {
	spitfire = 0,
	cheetah = 1,
	cheetah_plus = 2,
	hypervisor = 3,
};

extern enum ultra_tlb_layout tlb_type;

extern int sun4v_chip_type;

extern int cheetah_pcache_forced_on;
extern void cheetah_enable_pcache(void);

#define sparc64_highest_locked_tlbent()	\
	(tlb_type == spitfire ? \
	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
	 CHEETAH_HIGHEST_LOCKED_TLBENT)

extern int num_kernel_image_mappings;

/* The data cache is write through, so this just invalidates the
 * specified line.
 */
static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
}

/* The instruction cache lines are flushed with this, but note that
 * this does not flush the pipeline.  It is possible for a line to
 * get flushed but stale instructions to still be in the pipeline,
 * a flush instruction (to any address) is sufficient to handle
 * this issue after the line is invalidated.
 */
static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
}

static inline unsigned long spitfire_get_dtlb_data(int entry)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));

	/* Clear TTE diag bits. */
	data &= ~0x0003fe0000000000UL;

	return data;
}

static inline unsigned long spitfire_get_dtlb_tag(int entry)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
	return tag;
}

static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" (entry << 3),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline unsigned long spitfire_get_itlb_data(int entry)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));

	/* Clear TTE diag bits. */
	data &= ~0x0003fe0000000000UL;

	return data;
}

static inline unsigned long spitfire_get_itlb_tag(int entry)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
	return tag;
}

static inline void spitfire_put_itlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" (entry << 3),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
}

static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
}

/* Cheetah has "all non-locked" tlb flushes. */
static inline void cheetah_flush_dtlb_all(void)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (0x80), "i" (ASI_DMMU_DEMAP));
}

static inline void cheetah_flush_itlb_all(void)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (0x80), "i" (ASI_IMMU_DEMAP));
}

/* Cheetah has a 4-tlb layout so direct access is a bit different.
 * The first two TLBs are fully assosciative, hold 16 entries, and are
 * used only for locked and >8K sized translations.  One exists for
 * data accesses and one for instruction accesses.
 *
 * The third TLB is for data accesses to 8K non-locked translations, is
 * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
 * instruction accesses to 8K non-locked translations, is 2 way
 * assosciative, and holds 128 entries.
 *
 * Cheetah has some bug where bogus data can be returned from
 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
 * the problem for me. -DaveM
 */
static inline unsigned long cheetah_get_ldtlb_data(int entry)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_DTLB_DATA_ACCESS));

	return data;
}

static inline unsigned long cheetah_get_litlb_data(int entry)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_ITLB_DATA_ACCESS));

	return data;
}

static inline unsigned long cheetah_get_ldtlb_tag(int entry)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_DTLB_TAG_READ));

	return tag;
}

static inline unsigned long cheetah_get_litlb_tag(int entry)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_ITLB_TAG_READ));

	return tag;
}

static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((0 << 16) | (entry << 3)),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline void cheetah_put_litlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((0 << 16) | (entry << 3)),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));

	return data;
}

static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
	return tag;
}

static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((tlb << 16) | (entry << 3)),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline unsigned long cheetah_get_itlb_data(int entry)
{
	unsigned long data;

	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((2 << 16) | (entry << 3)),
                               "i" (ASI_ITLB_DATA_ACCESS));

	return data;
}

static inline unsigned long cheetah_get_itlb_tag(int entry)
{
	unsigned long tag;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
	return tag;
}

static inline void cheetah_put_itlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" ((2 << 16) | (entry << 3)),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

#endif /* !(__ASSEMBLY__) */
#endif /* CONFIG_SPARC64 */
#endif /* !(_SPARC64_SPITFIRE_H) */
Commit	Line	Data
a00736e9 SR	1	/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
	4	*/
	5
	6	#ifndef _SPARC64_SPITFIRE_H
	7	#define _SPARC64_SPITFIRE_H
	8
d34dd829 SR	9	#ifdef CONFIG_SPARC64
d34dd829 SR	10
a00736e9 SR	11	#include <asm/asi.h>
	12
	13	/* The following register addresses are accessible via ASI_DMMU
	14	* and ASI_IMMU, that is there is a distinct and unique copy of
	15	* each these registers for each TLB.
	16	*/
	17	#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
	18	#define TLB_SFSR 0x0000000000000018 /* All chips */
	19	#define TSB_REG 0x0000000000000028 /* All chips */
	20	#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
	21	#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
	22	#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
	23	#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
	24	#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
	25	#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
	26	#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
	27
	28	/* These registers only exist as one entity, and are accessed
	29	* via ASI_DMMU only.
	30	*/
	31	#define PRIMARY_CONTEXT 0x0000000000000008
	32	#define SECONDARY_CONTEXT 0x0000000000000010
	33	#define DMMU_SFAR 0x0000000000000020
	34	#define VIRT_WATCHPOINT 0x0000000000000038
	35	#define PHYS_WATCHPOINT 0x0000000000000040
	36
	37	#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
	38	#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
	39
	40	#define L1DCACHE_SIZE 0x4000
	41
	42	#define SUN4V_CHIP_INVALID 0x00
	43	#define SUN4V_CHIP_NIAGARA1 0x01
	44	#define SUN4V_CHIP_NIAGARA2 0x02
	45	#define SUN4V_CHIP_UNKNOWN 0xff
	46
	47	#ifndef __ASSEMBLY__
	48
	49	enum ultra_tlb_layout {
	50	spitfire = 0,
	51	cheetah = 1,
	52	cheetah_plus = 2,
	53	hypervisor = 3,
	54	};
	55
	56	extern enum ultra_tlb_layout tlb_type;
	57
	58	extern int sun4v_chip_type;
	59
	60	extern int cheetah_pcache_forced_on;
	61	extern void cheetah_enable_pcache(void);
	62
	63	#define sparc64_highest_locked_tlbent() \
	64	(tlb_type == spitfire ? \
	65	SPITFIRE_HIGHEST_LOCKED_TLBENT : \
	66	CHEETAH_HIGHEST_LOCKED_TLBENT)
	67
	68	extern int num_kernel_image_mappings;
	69
	70	/* The data cache is write through, so this just invalidates the
	71	* specified line.
	72	*/
	73	static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
	74	{
75	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
76	"membar #Sync"
77	: /* No outputs */
78	: "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
79	}
80
81	/* The instruction cache lines are flushed with this, but note that
82	* this does not flush the pipeline. It is possible for a line to
83	* get flushed but stale instructions to still be in the pipeline,
84	* a flush instruction (to any address) is sufficient to handle
85	* this issue after the line is invalidated.
86	*/
87	static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
88	{
89	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
90	"membar #Sync"
91	: /* No outputs */
92	: "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
93	}
94
95	static inline unsigned long spitfire_get_dtlb_data(int entry)
96	{
97	unsigned long data;
98
99	__asm__ __volatile__("ldxa [%1] %2, %0"
100	: "=r" (data)
101	: "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
102
103	/* Clear TTE diag bits. */
104	data &= ~0x0003fe0000000000UL;
105
106	return data;
107	}
108
109	static inline unsigned long spitfire_get_dtlb_tag(int entry)
110	{
111	unsigned long tag;
112
113	__asm__ __volatile__("ldxa [%1] %2, %0"
114	: "=r" (tag)
115	: "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
116	return tag;
117	}
118
119	static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
120	{
121	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
122	"membar #Sync"
123	: /* No outputs */
124	: "r" (data), "r" (entry << 3),
125	"i" (ASI_DTLB_DATA_ACCESS));
126	}
127
128	static inline unsigned long spitfire_get_itlb_data(int entry)
129	{
130	unsigned long data;
131
132	__asm__ __volatile__("ldxa [%1] %2, %0"
133	: "=r" (data)
134	: "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
135
136	/* Clear TTE diag bits. */
137	data &= ~0x0003fe0000000000UL;
138
139	return data;
140	}
141
142	static inline unsigned long spitfire_get_itlb_tag(int entry)
143	{
144	unsigned long tag;
145
146	__asm__ __volatile__("ldxa [%1] %2, %0"
147	: "=r" (tag)
148	: "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
149	return tag;
150	}
151
152	static inline void spitfire_put_itlb_data(int entry, unsigned long data)
153	{
154	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
155	"membar #Sync"
156	: /* No outputs */
157	: "r" (data), "r" (entry << 3),
158	"i" (ASI_ITLB_DATA_ACCESS));
159	}
160
161	static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
162	{
163	__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
164	"membar #Sync"
165	: /* No outputs */
166	: "r" (page \| 0x20), "i" (ASI_DMMU_DEMAP));
167	}
168
169	static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
170	{
171	__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
172	"membar #Sync"
173	: /* No outputs */
174	: "r" (page \| 0x20), "i" (ASI_IMMU_DEMAP));
175	}
176
177	/* Cheetah has "all non-locked" tlb flushes. */
178	static inline void cheetah_flush_dtlb_all(void)
179	{
180	__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
181	"membar #Sync"
182	: /* No outputs */
183	: "r" (0x80), "i" (ASI_DMMU_DEMAP));
184	}
185
186	static inline void cheetah_flush_itlb_all(void)
187	{
188	__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
189	"membar #Sync"
190	: /* No outputs */
191	: "r" (0x80), "i" (ASI_IMMU_DEMAP));
192	}
193
194	/* Cheetah has a 4-tlb layout so direct access is a bit different.
195	* The first two TLBs are fully assosciative, hold 16 entries, and are
196	* used only for locked and >8K sized translations. One exists for
197	* data accesses and one for instruction accesses.
198	*
199	* The third TLB is for data accesses to 8K non-locked translations, is
200	* 2 way assosciative, and holds 512 entries. The fourth TLB is for
201	* instruction accesses to 8K non-locked translations, is 2 way
202	* assosciative, and holds 128 entries.
203	*
204	* Cheetah has some bug where bogus data can be returned from
205	* ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
206	* the problem for me. -DaveM
207	*/
208	static inline unsigned long cheetah_get_ldtlb_data(int entry)
209	{
210	unsigned long data;
211
212	__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
213	"ldxa [%1] %2, %0"
214	: "=r" (data)
215	: "r" ((0 << 16) \| (entry << 3)),
216	"i" (ASI_DTLB_DATA_ACCESS));
217
218	return data;
219	}
220
221	static inline unsigned long cheetah_get_litlb_data(int entry)
222	{
223	unsigned long data;
224
225	__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
226	"ldxa [%1] %2, %0"
227	: "=r" (data)
228	: "r" ((0 << 16) \| (entry << 3)),
229	"i" (ASI_ITLB_DATA_ACCESS));
230
231	return data;
232	}
233
234	static inline unsigned long cheetah_get_ldtlb_tag(int entry)
235	{
236	unsigned long tag;
237
238	__asm__ __volatile__("ldxa [%1] %2, %0"
239	: "=r" (tag)
240	: "r" ((0 << 16) \| (entry << 3)),
241	"i" (ASI_DTLB_TAG_READ));
242
243	return tag;
244	}
245
246	static inline unsigned long cheetah_get_litlb_tag(int entry)
247	{
248	unsigned long tag;
249
250	__asm__ __volatile__("ldxa [%1] %2, %0"
251	: "=r" (tag)
252	: "r" ((0 << 16) \| (entry << 3)),
253	"i" (ASI_ITLB_TAG_READ));
254
255	return tag;
256	}
257
258	static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
259	{
260	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
261	"membar #Sync"
262	: /* No outputs */
263	: "r" (data),
264	"r" ((0 << 16) \| (entry << 3)),
265	"i" (ASI_DTLB_DATA_ACCESS));
266	}
267
268	static inline void cheetah_put_litlb_data(int entry, unsigned long data)
269	{
270	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
271	"membar #Sync"
272	: /* No outputs */
273	: "r" (data),
274	"r" ((0 << 16) \| (entry << 3)),
275	"i" (ASI_ITLB_DATA_ACCESS));
276	}
277
278	static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
279	{
280	unsigned long data;
281
282	__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
283	"ldxa [%1] %2, %0"
284	: "=r" (data)
285	: "r" ((tlb << 16) \| (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
286
287	return data;
288	}
289
290	static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
291	{
292	unsigned long tag;
293
294	__asm__ __volatile__("ldxa [%1] %2, %0"
295	: "=r" (tag)
296	: "r" ((tlb << 16) \| (entry << 3)), "i" (ASI_DTLB_TAG_READ));
297	return tag;
298	}
299
300	static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
301	{
302	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
303	"membar #Sync"
304	: /* No outputs */
305	: "r" (data),
306	"r" ((tlb << 16) \| (entry << 3)),
307	"i" (ASI_DTLB_DATA_ACCESS));
308	}
309
310	static inline unsigned long cheetah_get_itlb_data(int entry)
311	{
312	unsigned long data;
313
314	__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
315	"ldxa [%1] %2, %0"
316	: "=r" (data)
317	: "r" ((2 << 16) \| (entry << 3)),
318	"i" (ASI_ITLB_DATA_ACCESS));
319
320	return data;
321	}
322
323	static inline unsigned long cheetah_get_itlb_tag(int entry)
324	{
325	unsigned long tag;
326
327	__asm__ __volatile__("ldxa [%1] %2, %0"
328	: "=r" (tag)
329	: "r" ((2 << 16) \| (entry << 3)), "i" (ASI_ITLB_TAG_READ));
330	return tag;
331	}
332
333	static inline void cheetah_put_itlb_data(int entry, unsigned long data)
334	{
335	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
336	"membar #Sync"
337	: /* No outputs */
338	: "r" (data), "r" ((2 << 16) \| (entry << 3)),
339	"i" (ASI_ITLB_DATA_ACCESS));
340	}
341
342	#endif /* !(__ASSEMBLY__) */
d34dd829	343	#endif /* CONFIG_SPARC64 */
a00736e9	344	#endif /* !(_SPARC64_SPITFIRE_H) */