[net-next-2.6.git] / arch / sparc / include / asm / psrcompat.h

#ifndef _SPARC64_PSRCOMPAT_H
#define _SPARC64_PSRCOMPAT_H

#include <asm/pstate.h>

/* Old 32-bit PSR fields for the compatibility conversion code. */
#define PSR_CWP     0x0000001f         /* current window pointer     */
#define PSR_ET      0x00000020         /* enable traps field         */
#define PSR_PS      0x00000040         /* previous privilege level   */
#define PSR_S       0x00000080         /* current privilege level    */
#define PSR_PIL     0x00000f00         /* processor interrupt level  */
#define PSR_EF      0x00001000         /* enable floating point      */
#define PSR_EC      0x00002000         /* enable co-processor        */
#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
#define PSR_ICC     0x00f00000         /* integer condition codes    */
#define PSR_C       0x00100000         /* carry bit                  */
#define PSR_V       0x00200000         /* overflow bit               */
#define PSR_Z       0x00400000         /* zero bit                   */
#define PSR_N       0x00800000         /* negative bit               */
#define PSR_VERS    0x0f000000         /* cpu-version field          */
#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */

#define PSR_V8PLUS  0xff000000         /* fake impl/ver, meaning a 64bit CPU is present */
#define PSR_XCC	    0x000f0000         /* if PSR_V8PLUS, this is %xcc */

static inline unsigned int tstate_to_psr(unsigned long tstate)
{
	return ((tstate & TSTATE_CWP)			|
		PSR_S					|
		((tstate & TSTATE_ICC) >> 12)		|
		((tstate & TSTATE_XCC) >> 20)		|
		((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
		PSR_V8PLUS);
}

static inline unsigned long psr_to_tstate_icc(unsigned int psr)
{
	unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
	if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
		tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
	return tstate;
}

#endif /* !(_SPARC64_PSRCOMPAT_H) */
Commit	Line	Data
09d3e1ba SR	1	#ifndef _SPARC64_PSRCOMPAT_H
	2	#define _SPARC64_PSRCOMPAT_H
	3
	4	#include <asm/pstate.h>
	5
	6	/* Old 32-bit PSR fields for the compatibility conversion code. */
	7	#define PSR_CWP 0x0000001f /* current window pointer */
	8	#define PSR_ET 0x00000020 /* enable traps field */
	9	#define PSR_PS 0x00000040 /* previous privilege level */
	10	#define PSR_S 0x00000080 /* current privilege level */
	11	#define PSR_PIL 0x00000f00 /* processor interrupt level */
	12	#define PSR_EF 0x00001000 /* enable floating point */
	13	#define PSR_EC 0x00002000 /* enable co-processor */
	14	#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
	15	#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
	16	#define PSR_ICC 0x00f00000 /* integer condition codes */
	17	#define PSR_C 0x00100000 /* carry bit */
	18	#define PSR_V 0x00200000 /* overflow bit */
	19	#define PSR_Z 0x00400000 /* zero bit */
	20	#define PSR_N 0x00800000 /* negative bit */
	21	#define PSR_VERS 0x0f000000 /* cpu-version field */
	22	#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
	23
	24	#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
	25	#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
	26
	27	static inline unsigned int tstate_to_psr(unsigned long tstate)
	28	{
	29	return ((tstate & TSTATE_CWP) \|
	30	PSR_S \|
	31	((tstate & TSTATE_ICC) >> 12) \|
	32	((tstate & TSTATE_XCC) >> 20) \|
	33	((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) \|
	34	PSR_V8PLUS);
	35	}
	36
	37	static inline unsigned long psr_to_tstate_icc(unsigned int psr)
	38	{
	39	unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
	40	if ((psr & (PSR_VERS\|PSR_IMPL)) == PSR_V8PLUS)
	41	tstate \|= ((unsigned long)(psr & PSR_XCC)) << 20;
	42	return tstate;
	43	}
	44
	45	#endif /* !(_SPARC64_PSRCOMPAT_H) */