[net-next-2.6.git] / arch / sparc / include / asm / cache.h

/* cache.h:  Cache specific code for the Sparc.  These include flushing
 *           and direct tag/data line access.
 *
 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC_CACHE_H
#define _SPARC_CACHE_H

#define ARCH_SLAB_MINALIGN	__alignof__(unsigned long long)

#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES 32
#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))

#ifdef CONFIG_SPARC32
#define SMP_CACHE_BYTES_SHIFT 5
#else
#define SMP_CACHE_BYTES_SHIFT 6
#endif

#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)

#define __read_mostly __attribute__((__section__(".data..read_mostly")))

#ifdef CONFIG_SPARC32
#include <asm/asi.h>

/* Direct access to the instruction cache is provided through and
 * alternate address space.  The IDC bit must be off in the ICCR on
 * HyperSparcs for these accesses to work.  The code below does not do
 * any checking, the caller must do so.  These routines are for
 * diagnostics only, but could end up being useful.  Use with care.
 * Also, you are asking for trouble if you execute these in one of the
 * three instructions following a %asr/%psr access or modification.
 */

/* First, cache-tag access. */
static inline unsigned int get_icache_tag(int setnum, int tagnum)
{
	unsigned int vaddr, retval;

	vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
			     "=r" (retval) :
			     "r" (vaddr), "i" (ASI_M_TXTC_TAG));
	return retval;
}

static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
{
	unsigned int vaddr;

	vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
			     "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
			     "memory");
}

/* Second cache-data access.  The data is returned two-32bit quantities
 * at a time.
 */
static inline void get_icache_data(int setnum, int tagnum, int subblock,
				       unsigned int *data)
{
	unsigned int value1, value2, vaddr;

	vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
		((subblock&0x3) << 3);
	__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
			     "or %%g0, %%g2, %0\n\t"
			     "or %%g0, %%g3, %1\n\t" :
			     "=r" (value1), "=r" (value2) :
			     "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
			     "g2", "g3");
	data[0] = value1; data[1] = value2;
}

static inline void put_icache_data(int setnum, int tagnum, int subblock,
				       unsigned int *data)
{
	unsigned int value1, value2, vaddr;

	vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
		((subblock&0x3) << 3);
	value1 = data[0]; value2 = data[1];
	__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
			     "or %%g0, %1, %%g3\n\t"
			     "stda %%g2, [%2] %3\n\t" : :
			     "r" (value1), "r" (value2), 
			     "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
			     "g2", "g3", "memory" /* no joke */);
}

/* Different types of flushes with the ICACHE.  Some of the flushes
 * affect both the ICACHE and the external cache.  Others only clear
 * the ICACHE entries on the cpu itself.  V8's (most) allow
 * granularity of flushes on the packet (element in line), whole line,
 * and entire cache (ie. all lines) level.  The ICACHE only flushes are
 * ROSS HyperSparc specific and are in ross.h
 */

/* Flushes which clear out both the on-chip and external caches */
static inline void flush_ei_page(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
			     "memory");
}

static inline void flush_ei_seg(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_SEG) :
			     "memory");
}

static inline void flush_ei_region(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_REGION) :
			     "memory");
}

static inline void flush_ei_ctx(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_CTX) :
			     "memory");
}

static inline void flush_ei_user(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_USER) :
			     "memory");
}
#endif /* CONFIG_SPARC32 */

#endif /* !(_SPARC_CACHE_H) */
Commit	Line	Data
d113fcd9	1	/* cache.h: Cache specific code for the Sparc. These include flushing
1da177e4 LT	2	* and direct tag/data line access.
1da177e4 LT	3	*
d113fcd9	4	* Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
1da177e4 LT	5	*/
	6
	7	#ifndef _SPARC_CACHE_H
	8	#define _SPARC_CACHE_H
	9
273fca0e DM	10	#define ARCH_SLAB_MINALIGN __alignof__(unsigned long long)
273fca0e DM	11
1da177e4 LT	12	#define L1_CACHE_SHIFT 5
	13	#define L1_CACHE_BYTES 32
	14	#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
1da177e4	15
d113fcd9 DM	16	#ifdef CONFIG_SPARC32
	17	#define SMP_CACHE_BYTES_SHIFT 5
	18	#else
	19	#define SMP_CACHE_BYTES_SHIFT 6
	20	#endif
	21
	22	#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
	23
54cb27a7	24	#define __read_mostly __attribute__((__section__(".data..read_mostly")))
d113fcd9 DM	25
	26	#ifdef CONFIG_SPARC32
	27	#include <asm/asi.h>
1da177e4 LT	28
	29	/* Direct access to the instruction cache is provided through and
	30	* alternate address space. The IDC bit must be off in the ICCR on
	31	* HyperSparcs for these accesses to work. The code below does not do
	32	* any checking, the caller must do so. These routines are for
	33	* diagnostics only, but could end up being useful. Use with care.
	34	* Also, you are asking for trouble if you execute these in one of the
	35	* three instructions following a %asr/%psr access or modification.
	36	*/
	37
	38	/* First, cache-tag access. */
3115624e	39	static inline unsigned int get_icache_tag(int setnum, int tagnum)
1da177e4 LT	40	{
	41	unsigned int vaddr, retval;
	42
	43	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
	44	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
	45	"=r" (retval) :
	46	"r" (vaddr), "i" (ASI_M_TXTC_TAG));
	47	return retval;
	48	}
	49
3115624e	50	static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
1da177e4 LT	51	{
	52	unsigned int vaddr;
	53
	54	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
	55	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
	56	"r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
	57	"memory");
	58	}
	59
	60	/* Second cache-data access. The data is returned two-32bit quantities
	61	* at a time.
	62	*/
3115624e	63	static inline void get_icache_data(int setnum, int tagnum, int subblock,
1da177e4 LT	64	unsigned int *data)
	65	{
	66	unsigned int value1, value2, vaddr;
	67
	68	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
	69	((subblock&0x3) << 3);
	70	__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
	71	"or %%g0, %%g2, %0\n\t"
	72	"or %%g0, %%g3, %1\n\t" :
	73	"=r" (value1), "=r" (value2) :
	74	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
	75	"g2", "g3");
	76	data[0] = value1; data[1] = value2;
	77	}
	78
3115624e	79	static inline void put_icache_data(int setnum, int tagnum, int subblock,
1da177e4 LT	80	unsigned int *data)
	81	{
	82	unsigned int value1, value2, vaddr;
	83
	84	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
	85	((subblock&0x3) << 3);
	86	value1 = data[0]; value2 = data[1];
	87	__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
	88	"or %%g0, %1, %%g3\n\t"
	89	"stda %%g2, [%2] %3\n\t" : :
	90	"r" (value1), "r" (value2),
	91	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
	92	"g2", "g3", "memory" /* no joke */);
	93	}
	94
	95	/* Different types of flushes with the ICACHE. Some of the flushes
	96	* affect both the ICACHE and the external cache. Others only clear
	97	* the ICACHE entries on the cpu itself. V8's (most) allow
	98	* granularity of flushes on the packet (element in line), whole line,
	99	* and entire cache (ie. all lines) level. The ICACHE only flushes are
	100	* ROSS HyperSparc specific and are in ross.h
	101	*/
	102
	103	/* Flushes which clear out both the on-chip and external caches */
3115624e	104	static inline void flush_ei_page(unsigned int addr)
1da177e4 LT	105	{
	106	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	107	"r" (addr), "i" (ASI_M_FLUSH_PAGE) :
	108	"memory");
	109	}
	110
3115624e	111	static inline void flush_ei_seg(unsigned int addr)
1da177e4 LT	112	{
	113	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	114	"r" (addr), "i" (ASI_M_FLUSH_SEG) :
	115	"memory");
	116	}
	117
3115624e	118	static inline void flush_ei_region(unsigned int addr)
1da177e4 LT	119	{
	120	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	121	"r" (addr), "i" (ASI_M_FLUSH_REGION) :
	122	"memory");
	123	}
	124
3115624e	125	static inline void flush_ei_ctx(unsigned int addr)
1da177e4 LT	126	{
	127	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	128	"r" (addr), "i" (ASI_M_FLUSH_CTX) :
	129	"memory");
	130	}
	131
3115624e	132	static inline void flush_ei_user(unsigned int addr)
1da177e4 LT	133	{
	134	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	135	"r" (addr), "i" (ASI_M_FLUSH_USER) :
	136	"memory");
	137	}
d113fcd9	138	#endif /* CONFIG_SPARC32 */
1da177e4 LT	139
1da177e4 LT	140	#endif /* !(_SPARC_CACHE_H) */