[net-next-2.6.git] / arch / sh / kernel / cpu / sh4a / clock-sh7723.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
 *
 * SH7723 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7723.h>

/* SH7723 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define IRDACLKCR	0xa4150018
#define PLLCR		0xa4150024
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.name           = "rclk",
	.id             = -1,
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

/* The dll multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.name           = "dll_clk",
	.id             = -1,
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };

#define DIV4(_str, _reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
};

enum { DIV4_IRDA, DIV4_ENABLE_NR };

struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
};

enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };

struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
};
enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

static struct clk mstp_clks[] = {
	/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
	SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
	SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),

	SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),

	SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
	SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP clocks */
	CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
	CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
	CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
	CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
	CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
	CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
	CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
	CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
	CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
	CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
	CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
	{
		/* TMU0 */
		.dev_id		= "sh_tmu.0",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU0],
	}, {
		/* TMU1 */
		.dev_id		= "sh_tmu.1",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU0],
	}, {
		/* TMU2 */
		.dev_id		= "sh_tmu.2",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU0],
	},
	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
	CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
	CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
	{
		/* TMU3 */
		.dev_id		= "sh_tmu.3",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU1],
	}, {
		/* TMU4 */
		.dev_id		= "sh_tmu.4",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU1],
	}, {
		/* TMU5 */
		.dev_id		= "sh_tmu.5",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU1],
	},
	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
	{
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF0],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF1],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF2],
	}, {
		/* SCIF3 */
		.dev_id		= "sh-sci.3",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF3],
	}, {
		/* SCIF4 */
		.dev_id		= "sh-sci.4",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF4],
	}, {
		/* SCIF5 */
		.dev_id		= "sh-sci.5",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF5],
	},
	CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
	CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
	CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
	CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
	CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
	CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
	CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
	CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
	CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
	CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
	CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
	CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
	CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
	CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
	CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
	CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
	CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
	CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
	CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret |= clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_enable_register(div4_enable_clks,
					DIV4_ENABLE_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_reparent_register(div4_reparent_clks,
					DIV4_REPARENT_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);

	return ret;
}
Commit	Line	Data
c521dc02 MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7723.c
	3	*
	4	* SH7723 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
f4221802 PM	24	#include <linux/clk.h>
f4221802 PM	25	#include <asm/clkdev.h>
c521dc02	26	#include <asm/clock.h>
2094e504 MD	27	#include <asm/hwblk.h>
2094e504 MD	28	#include <cpu/sh7723.h>
c521dc02 MD	29
	30	/* SH7723 registers */
	31	#define FRQCR 0xa4150000
	32	#define VCLKCR 0xa4150004
	33	#define SCLKACR 0xa4150008
	34	#define SCLKBCR 0xa415000c
	35	#define IRDACLKCR 0xa4150018
	36	#define PLLCR 0xa4150024
c521dc02 MD	37	#define DLLFRQ 0xa4150050
	38
	39	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	40	static struct clk r_clk = {
	41	.name = "rclk",
	42	.id = -1,
	43	.rate = 32768,
	44	};
	45
	46	/*
	47	* Default rate for the root input clock, reset this with clk_set_rate()
	48	* from the platform code.
	49	*/
	50	struct clk extal_clk = {
	51	.name = "extal",
	52	.id = -1,
	53	.rate = 33333333,
	54	};
	55
	56	/* The dll multiplies the 32khz r_clk, may be used instead of extal */
	57	static unsigned long dll_recalc(struct clk *clk)
	58	{
	59	unsigned long mult;
	60
	61	if (__raw_readl(PLLCR) & 0x1000)
	62	mult = __raw_readl(DLLFRQ);
	63	else
	64	mult = 0;
	65
	66	return clk->parent->rate * mult;
	67	}
	68
	69	static struct clk_ops dll_clk_ops = {
	70	.recalc = dll_recalc,
	71	};
	72
	73	static struct clk dll_clk = {
	74	.name = "dll_clk",
	75	.id = -1,
	76	.ops = &dll_clk_ops,
	77	.parent = &r_clk,
	78	.flags = CLK_ENABLE_ON_INIT,
	79	};
	80
	81	static unsigned long pll_recalc(struct clk *clk)
	82	{
	83	unsigned long mult = 1;
	84	unsigned long div = 1;
	85
	86	if (__raw_readl(PLLCR) & 0x4000)
	87	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	88	else
	89	div = 2;
	90
	91	return (clk->parent->rate * mult) / div;
	92	}
	93
	94	static struct clk_ops pll_clk_ops = {
	95	.recalc = pll_recalc,
	96	};
	97
	98	static struct clk pll_clk = {
	99	.name = "pll_clk",
	100	.id = -1,
101	.ops = &pll_clk_ops,
102	.flags = CLK_ENABLE_ON_INIT,
103	};
104
105	struct clk *main_clks[] = {
106	&r_clk,
107	&extal_clk,
108	&dll_clk,
109	&pll_clk,
110	};
111
112	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
113	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
114
0a5f337e	115	static struct clk_div_mult_table div4_div_mult_table = {
c521dc02 MD	116	.divisors = divisors,
	117	.nr_divisors = ARRAY_SIZE(divisors),
	118	.multipliers = multipliers,
	119	.nr_multipliers = ARRAY_SIZE(multipliers),
	120	};
	121
0a5f337e MD	122	static struct clk_div4_table div4_table = {
	123	.div_mult_table = &div4_div_mult_table,
	124	};
	125
801cd56e	126	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
c521dc02 MD	127
	128	#define DIV4(_str, _reg, _bit, _mask, _flags) \
	129	SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
	130
	131	struct clk div4_clks[DIV4_NR] = {
	132	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
	133	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
	134	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
	135	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
	136	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
	137	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
801cd56e MD	138	};
	139
	140	enum { DIV4_IRDA, DIV4_ENABLE_NR };
	141
	142	struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
c521dc02 MD	143	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
	144	};
	145
801cd56e MD	146	enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
	147
	148	struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
	149	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
	150	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
	151	};
098ec49b MD	152	enum { DIV6_V, DIV6_NR };
	153
	154	struct clk div6_clks[DIV6_NR] = {
9e1985e1	155	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
c521dc02 MD	156	};
c521dc02 MD	157
c521dc02 MD	158	static struct clk mstp_clks[] = {
c521dc02 MD	159	/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
08134c3c MD	160	SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	161	SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	162	SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	163	SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
	164	SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	165	SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	166	SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
	167	SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
	168	SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
	169	SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
	170	SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
	171	SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
	172	SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
	173	SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
	174	SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
	175	SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
	176	SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
	177	SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
	178	SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
	179	SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
	180	SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
	181	SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
	182	SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
	183	SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
	184	SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
	185	SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
	186
	187	SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
	188	SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
	189
	190	SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
	191	SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
	192	SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
	193	SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
	194	SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
	195	SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
	196	SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
	197	SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
	198	SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
	199	SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
	200	SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
	201	SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
	202	SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
	203	SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
	204	SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
	205	SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
	206	SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
	207	SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
	208	SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
c521dc02 MD	209	};
c521dc02 MD	210
fd30401b MD	211	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
fd30401b MD	212
f4221802	213	static struct clk_lookup lookups[] = {
098ec49b MD	214	/* DIV6 clocks */
	215	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
	216
fd30401b MD	217	/* MSTP clocks */
	218	CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
	219	CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
	220	CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
	221	CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
	222	CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
	223	CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
	224	CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
	225	CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
	226	CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
	227	CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
	228	CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
f4221802 PM	229	{
	230	/* TMU0 */
	231	.dev_id = "sh_tmu.0",
	232	.con_id = "tmu_fck",
f3d51e13	233	.clk = &mstp_clks[HWBLK_TMU0],
f4221802 PM	234	}, {
	235	/* TMU1 */
	236	.dev_id = "sh_tmu.1",
	237	.con_id = "tmu_fck",
f3d51e13	238	.clk = &mstp_clks[HWBLK_TMU0],
f4221802 PM	239	}, {
	240	/* TMU2 */
	241	.dev_id = "sh_tmu.2",
	242	.con_id = "tmu_fck",
f3d51e13	243	.clk = &mstp_clks[HWBLK_TMU0],
fd30401b MD	244	},
	245	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
	246	CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
	247	CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
	248	{
f4221802 PM	249	/* TMU3 */
	250	.dev_id = "sh_tmu.3",
	251	.con_id = "tmu_fck",
f3d51e13	252	.clk = &mstp_clks[HWBLK_TMU1],
f4221802 PM	253	}, {
	254	/* TMU4 */
	255	.dev_id = "sh_tmu.4",
	256	.con_id = "tmu_fck",
f3d51e13	257	.clk = &mstp_clks[HWBLK_TMU1],
f4221802 PM	258	}, {
	259	/* TMU5 */
	260	.dev_id = "sh_tmu.5",
	261	.con_id = "tmu_fck",
f3d51e13	262	.clk = &mstp_clks[HWBLK_TMU1],
fd30401b MD	263	},
	264	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
	265	{
e4e06697 MD	266	/* SCIF0 */
	267	.dev_id = "sh-sci.0",
	268	.con_id = "sci_fck",
	269	.clk = &mstp_clks[HWBLK_SCIF0],
	270	}, {
	271	/* SCIF1 */
	272	.dev_id = "sh-sci.1",
	273	.con_id = "sci_fck",
	274	.clk = &mstp_clks[HWBLK_SCIF1],
	275	}, {
	276	/* SCIF2 */
	277	.dev_id = "sh-sci.2",
	278	.con_id = "sci_fck",
	279	.clk = &mstp_clks[HWBLK_SCIF2],
	280	}, {
	281	/* SCIF3 */
	282	.dev_id = "sh-sci.3",
	283	.con_id = "sci_fck",
	284	.clk = &mstp_clks[HWBLK_SCIF3],
	285	}, {
	286	/* SCIF4 */
	287	.dev_id = "sh-sci.4",
	288	.con_id = "sci_fck",
	289	.clk = &mstp_clks[HWBLK_SCIF4],
	290	}, {
	291	/* SCIF5 */
	292	.dev_id = "sh-sci.5",
	293	.con_id = "sci_fck",
	294	.clk = &mstp_clks[HWBLK_SCIF5],
f4221802	295	},
fd30401b MD	296	CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
	297	CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
	298	CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
	299	CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
	300	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
	301	CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
	302	CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
	303	CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
	304	CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
	305	CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
	306	CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
	307	CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
	308	CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
	309	CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
	310	CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
	311	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
	312	CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
	313	CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
	314	CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
	315	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
	316	CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
	317	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
	318	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
	319	CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
f4221802 PM	320	};
f4221802 PM	321
c521dc02 MD	322	int __init arch_clk_init(void)
	323	{
	324	int k, ret = 0;
	325
	326	/* autodetect extal or dll configuration */
	327	if (__raw_readl(PLLCR) & 0x1000)
	328	pll_clk.parent = &dll_clk;
	329	else
	330	pll_clk.parent = &extal_clk;
	331
	332	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
f4221802 PM	333	ret \|= clk_register(main_clks[k]);
	334
	335	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
c521dc02 MD	336
	337	if (!ret)
	338	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	339
801cd56e MD	340	if (!ret)
	341	ret = sh_clk_div4_enable_register(div4_enable_clks,
	342	DIV4_ENABLE_NR, &div4_table);
	343
	344	if (!ret)
	345	ret = sh_clk_div4_reparent_register(div4_reparent_clks,
	346	DIV4_REPARENT_NR, &div4_table);
	347
c521dc02	348	if (!ret)
098ec49b	349	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
c521dc02 MD	350
c521dc02 MD	351	if (!ret)
f3d51e13	352	ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
c521dc02 MD	353
	354	return ret;
	355	}