[net-next-2.6.git] / arch / sh / kernel / cpu / sh4a / clock-sh7366.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
 *
 * SH7366 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>

/* SH7366 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.name           = "rclk",
	.id             = -1,
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.name           = "dll_clk",
	.id             = -1,
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
       DIV4_SIUA, DIV4_SIUB, DIV4_NR };

#define DIV4(_str, _reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

#define MSTP(_str, _parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)

static struct clk mstp_clks[] = {
	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
	MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
	MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
	MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
	MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
	MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
	MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
	MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
	MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
	MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
	MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
	MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
	SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
	SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
	SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
	MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
	MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),

	MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),

	MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
	MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
	MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
	MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
	MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
	MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
	MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
	MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
	MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
	MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
	MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
	MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
	MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));

	return ret;
}
Commit	Line	Data
4ed37394 MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7366.c
	3	*
	4	* SH7366 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
098ec49b	24	#include <asm/clkdev.h>
4ed37394 MD	25	#include <asm/clock.h>
	26
	27	/* SH7366 registers */
	28	#define FRQCR 0xa4150000
	29	#define VCLKCR 0xa4150004
	30	#define SCLKACR 0xa4150008
	31	#define SCLKBCR 0xa415000c
	32	#define PLLCR 0xa4150024
	33	#define MSTPCR0 0xa4150030
	34	#define MSTPCR1 0xa4150034
	35	#define MSTPCR2 0xa4150038
	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
	40	.name = "rclk",
	41	.id = -1,
	42	.rate = 32768,
	43	};
	44
	45	/*
	46	* Default rate for the root input clock, reset this with clk_set_rate()
	47	* from the platform code.
	48	*/
	49	struct clk extal_clk = {
	50	.name = "extal",
	51	.id = -1,
	52	.rate = 33333333,
	53	};
	54
	55	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
	56	static unsigned long dll_recalc(struct clk *clk)
	57	{
	58	unsigned long mult;
	59
	60	if (__raw_readl(PLLCR) & 0x1000)
	61	mult = __raw_readl(DLLFRQ);
	62	else
	63	mult = 0;
	64
	65	return clk->parent->rate * mult;
	66	}
	67
	68	static struct clk_ops dll_clk_ops = {
	69	.recalc = dll_recalc,
	70	};
	71
	72	static struct clk dll_clk = {
	73	.name = "dll_clk",
	74	.id = -1,
	75	.ops = &dll_clk_ops,
	76	.parent = &r_clk,
	77	.flags = CLK_ENABLE_ON_INIT,
	78	};
	79
	80	static unsigned long pll_recalc(struct clk *clk)
	81	{
	82	unsigned long mult = 1;
	83	unsigned long div = 1;
	84
	85	if (__raw_readl(PLLCR) & 0x4000)
	86	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	87	else
	88	div = 2;
89
90	return (clk->parent->rate * mult) / div;
91	}
92
93	static struct clk_ops pll_clk_ops = {
94	.recalc = pll_recalc,
95	};
96
97	static struct clk pll_clk = {
98	.name = "pll_clk",
99	.id = -1,
100	.ops = &pll_clk_ops,
101	.flags = CLK_ENABLE_ON_INIT,
102	};
103
104	struct clk *main_clks[] = {
105	&r_clk,
106	&extal_clk,
107	&dll_clk,
108	&pll_clk,
109	};
110
111	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
112	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
113
0a5f337e	114	static struct clk_div_mult_table div4_div_mult_table = {
4ed37394 MD	115	.divisors = divisors,
	116	.nr_divisors = ARRAY_SIZE(divisors),
	117	.multipliers = multipliers,
	118	.nr_multipliers = ARRAY_SIZE(multipliers),
	119	};
	120
0a5f337e MD	121	static struct clk_div4_table div4_table = {
	122	.div_mult_table = &div4_div_mult_table,
	123	};
	124
4ed37394 MD	125	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
	126	DIV4_SIUA, DIV4_SIUB, DIV4_NR };
	127
	128	#define DIV4(_str, _reg, _bit, _mask, _flags) \
	129	SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
	130
	131	struct clk div4_clks[DIV4_NR] = {
	132	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	133	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	134	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	135	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	136	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	137	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	138	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	139	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
	140	};
	141
098ec49b MD	142	enum { DIV6_V, DIV6_NR };
	143
	144	struct clk div6_clks[DIV6_NR] = {
9e1985e1	145	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
4ed37394 MD	146	};
	147
	148	#define MSTP(_str, _parent, _reg, _bit, _flags) \
	149	SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
	150
	151	static struct clk mstp_clks[] = {
	152	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
	153	MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	154	MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	155	MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	156	MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	157	MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	158	MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
	159	MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
	160	MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
	161	MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
	162	MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
	163	MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
2169bc1b PM	164	MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
2169bc1b PM	165	MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
4ed37394 MD	166	MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
	167	MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
	168	MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
c7ed1ab3 PM	169	SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
	170	SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
	171	SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
4ed37394 MD	172	MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
	173	MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
	174
	175	MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
	176
	177	MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
	178	MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
	179	MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
	180	MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
	181	MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
	182	MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
	183	MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
	184	MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
	185	MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
	186	MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	187	MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
	188	MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
	189	MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
	190	MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	191	MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	192	MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
	193	};
	194
098ec49b MD	195	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	196
	197	static struct clk_lookup lookups[] = {
	198	/* DIV6 clocks */
	199	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
	200	};
	201
4ed37394 MD	202	int __init arch_clk_init(void)
	203	{
	204	int k, ret = 0;
	205
	206	/* autodetect extal or dll configuration */
	207	if (__raw_readl(PLLCR) & 0x1000)
	208	pll_clk.parent = &dll_clk;
	209	else
	210	pll_clk.parent = &extal_clk;
	211
	212	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	213	ret = clk_register(main_clks[k]);
	214
098ec49b MD	215	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
098ec49b MD	216
4ed37394 MD	217	if (!ret)
	218	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	219
	220	if (!ret)
098ec49b	221	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
4ed37394 MD	222
	223	if (!ret)
	224	ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
	225
	226	return ret;
	227	}