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287c1297 KM |
1 | /* |
2 | * linux/arch/sh/boards/se/7724/setup.c | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * | |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/mtd/physmap.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/smc91x.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/input.h> | |
fc1d003d | 22 | #include <linux/input/sh_keysc.h> |
9731f4a2 | 23 | #include <linux/usb/r8a66597.h> |
287c1297 KM |
24 | #include <video/sh_mobile_lcdc.h> |
25 | #include <media/sh_mobile_ceu.h> | |
3e9ad52b | 26 | #include <sound/sh_fsi.h> |
287c1297 KM |
27 | #include <asm/io.h> |
28 | #include <asm/heartbeat.h> | |
a80cad95 KM |
29 | #include <asm/sh_eth.h> |
30 | #include <asm/clock.h> | |
3b9f2952 | 31 | #include <asm/suspend.h> |
287c1297 KM |
32 | #include <cpu/sh7724.h> |
33 | #include <mach-se/mach/se7724.h> | |
34 | ||
35 | /* | |
36 | * SWx 1234 5678 | |
37 | * ------------------------------------ | |
38 | * SW31 : 1001 1100 : default | |
39 | * SW32 : 0111 1111 : use on board flash | |
40 | * | |
41 | * SW41 : abxx xxxx -> a = 0 : Analog monitor | |
42 | * 1 : Digital monitor | |
43 | * b = 0 : VGA | |
4f324311 KM |
44 | * 1 : 720p |
45 | */ | |
46 | ||
47 | /* | |
48 | * about 720p | |
49 | * | |
50 | * When you use 1280 x 720 lcdc output, | |
51 | * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, | |
52 | * and change SW41 to use 720p | |
287c1297 KM |
53 | */ |
54 | ||
55 | /* Heartbeat */ | |
a09d2831 PM |
56 | static struct resource heartbeat_resource = { |
57 | .start = PA_LED, | |
58 | .end = PA_LED, | |
59 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, | |
287c1297 KM |
60 | }; |
61 | ||
62 | static struct platform_device heartbeat_device = { | |
63 | .name = "heartbeat", | |
64 | .id = -1, | |
a09d2831 PM |
65 | .num_resources = 1, |
66 | .resource = &heartbeat_resource, | |
287c1297 KM |
67 | }; |
68 | ||
69 | /* LAN91C111 */ | |
70 | static struct smc91x_platdata smc91x_info = { | |
71 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | |
72 | }; | |
73 | ||
74 | static struct resource smc91x_eth_resources[] = { | |
75 | [0] = { | |
76 | .name = "SMC91C111" , | |
77 | .start = 0x1a300300, | |
78 | .end = 0x1a30030f, | |
79 | .flags = IORESOURCE_MEM, | |
80 | }, | |
81 | [1] = { | |
82 | .start = IRQ0_SMC, | |
83 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
84 | }, | |
85 | }; | |
86 | ||
87 | static struct platform_device smc91x_eth_device = { | |
88 | .name = "smc91x", | |
89 | .num_resources = ARRAY_SIZE(smc91x_eth_resources), | |
90 | .resource = smc91x_eth_resources, | |
91 | .dev = { | |
92 | .platform_data = &smc91x_info, | |
93 | }, | |
94 | }; | |
95 | ||
96 | /* MTD */ | |
97 | static struct mtd_partition nor_flash_partitions[] = { | |
98 | { | |
99 | .name = "uboot", | |
100 | .offset = 0, | |
101 | .size = (1 * 1024 * 1024), | |
102 | .mask_flags = MTD_WRITEABLE, /* Read-only */ | |
103 | }, { | |
104 | .name = "kernel", | |
105 | .offset = MTDPART_OFS_APPEND, | |
106 | .size = (2 * 1024 * 1024), | |
107 | }, { | |
108 | .name = "free-area", | |
109 | .offset = MTDPART_OFS_APPEND, | |
110 | .size = MTDPART_SIZ_FULL, | |
111 | }, | |
112 | }; | |
113 | ||
114 | static struct physmap_flash_data nor_flash_data = { | |
115 | .width = 2, | |
116 | .parts = nor_flash_partitions, | |
117 | .nr_parts = ARRAY_SIZE(nor_flash_partitions), | |
118 | }; | |
119 | ||
120 | static struct resource nor_flash_resources[] = { | |
121 | [0] = { | |
122 | .name = "NOR Flash", | |
123 | .start = 0x00000000, | |
124 | .end = 0x01ffffff, | |
125 | .flags = IORESOURCE_MEM, | |
126 | } | |
127 | }; | |
128 | ||
129 | static struct platform_device nor_flash_device = { | |
130 | .name = "physmap-flash", | |
131 | .resource = nor_flash_resources, | |
132 | .num_resources = ARRAY_SIZE(nor_flash_resources), | |
133 | .dev = { | |
134 | .platform_data = &nor_flash_data, | |
135 | }, | |
136 | }; | |
137 | ||
138 | /* LCDC */ | |
139 | static struct sh_mobile_lcdc_info lcdc_info = { | |
140 | .clock_source = LCDC_CLK_EXTERNAL, | |
141 | .ch[0] = { | |
142 | .chan = LCDC_CHAN_MAINLCD, | |
143 | .bpp = 16, | |
144 | .clock_divider = 1, | |
145 | .lcd_cfg = { | |
146 | .name = "LB070WV1", | |
147 | .sync = 0, /* hsync and vsync are active low */ | |
148 | }, | |
149 | .lcd_size_cfg = { /* 7.0 inch */ | |
150 | .width = 152, | |
151 | .height = 91, | |
152 | }, | |
153 | .board_cfg = { | |
154 | }, | |
155 | } | |
156 | }; | |
157 | ||
158 | static struct resource lcdc_resources[] = { | |
159 | [0] = { | |
160 | .name = "LCDC", | |
161 | .start = 0xfe940000, | |
a6f15ade | 162 | .end = 0xfe942fff, |
287c1297 KM |
163 | .flags = IORESOURCE_MEM, |
164 | }, | |
165 | [1] = { | |
166 | .start = 106, | |
167 | .flags = IORESOURCE_IRQ, | |
168 | }, | |
169 | }; | |
170 | ||
171 | static struct platform_device lcdc_device = { | |
172 | .name = "sh_mobile_lcdc_fb", | |
173 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
174 | .resource = lcdc_resources, | |
175 | .dev = { | |
176 | .platform_data = &lcdc_info, | |
177 | }, | |
df47cd09 MD |
178 | .archdata = { |
179 | .hwblk_id = HWBLK_LCDC, | |
180 | }, | |
287c1297 KM |
181 | }; |
182 | ||
183 | /* CEU0 */ | |
184 | static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { | |
185 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
186 | }; | |
187 | ||
188 | static struct resource ceu0_resources[] = { | |
189 | [0] = { | |
190 | .name = "CEU0", | |
191 | .start = 0xfe910000, | |
192 | .end = 0xfe91009f, | |
193 | .flags = IORESOURCE_MEM, | |
194 | }, | |
195 | [1] = { | |
196 | .start = 52, | |
197 | .flags = IORESOURCE_IRQ, | |
198 | }, | |
199 | [2] = { | |
200 | /* place holder for contiguous memory */ | |
201 | }, | |
202 | }; | |
203 | ||
204 | static struct platform_device ceu0_device = { | |
205 | .name = "sh_mobile_ceu", | |
206 | .id = 0, /* "ceu0" clock */ | |
207 | .num_resources = ARRAY_SIZE(ceu0_resources), | |
208 | .resource = ceu0_resources, | |
209 | .dev = { | |
210 | .platform_data = &sh_mobile_ceu0_info, | |
211 | }, | |
df47cd09 MD |
212 | .archdata = { |
213 | .hwblk_id = HWBLK_CEU0, | |
214 | }, | |
287c1297 KM |
215 | }; |
216 | ||
217 | /* CEU1 */ | |
218 | static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { | |
219 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
220 | }; | |
221 | ||
222 | static struct resource ceu1_resources[] = { | |
223 | [0] = { | |
224 | .name = "CEU1", | |
225 | .start = 0xfe914000, | |
226 | .end = 0xfe91409f, | |
227 | .flags = IORESOURCE_MEM, | |
228 | }, | |
229 | [1] = { | |
230 | .start = 63, | |
231 | .flags = IORESOURCE_IRQ, | |
232 | }, | |
233 | [2] = { | |
234 | /* place holder for contiguous memory */ | |
235 | }, | |
236 | }; | |
237 | ||
238 | static struct platform_device ceu1_device = { | |
239 | .name = "sh_mobile_ceu", | |
240 | .id = 1, /* "ceu1" clock */ | |
241 | .num_resources = ARRAY_SIZE(ceu1_resources), | |
242 | .resource = ceu1_resources, | |
243 | .dev = { | |
244 | .platform_data = &sh_mobile_ceu1_info, | |
245 | }, | |
df47cd09 MD |
246 | .archdata = { |
247 | .hwblk_id = HWBLK_CEU1, | |
248 | }, | |
287c1297 KM |
249 | }; |
250 | ||
3e9ad52b KM |
251 | /* FSI */ |
252 | /* | |
253 | * FSI-A use external clock which came from ak464x. | |
254 | * So, we should change parent of fsi | |
255 | */ | |
256 | #define FCLKACR 0xa4150008 | |
257 | static void fsimck_init(struct clk *clk) | |
258 | { | |
9d56dd3b | 259 | u32 status = __raw_readl(clk->enable_reg); |
3e9ad52b KM |
260 | |
261 | /* use external clock */ | |
262 | status &= ~0x000000ff; | |
263 | status |= 0x00000080; | |
9d56dd3b | 264 | __raw_writel(status, clk->enable_reg); |
3e9ad52b KM |
265 | } |
266 | ||
267 | static struct clk_ops fsimck_clk_ops = { | |
268 | .init = fsimck_init, | |
269 | }; | |
270 | ||
271 | static struct clk fsimcka_clk = { | |
272 | .name = "fsimcka_clk", | |
273 | .id = -1, | |
274 | .ops = &fsimck_clk_ops, | |
275 | .enable_reg = (void __iomem *)FCLKACR, | |
276 | .rate = 0, /* unknown */ | |
277 | }; | |
278 | ||
279 | struct sh_fsi_platform_info fsi_info = { | |
280 | .porta_flags = SH_FSI_BRS_INV | | |
281 | SH_FSI_OUT_SLAVE_MODE | | |
282 | SH_FSI_IN_SLAVE_MODE | | |
283 | SH_FSI_OFMT(PCM) | | |
284 | SH_FSI_IFMT(PCM), | |
285 | }; | |
286 | ||
287 | static struct resource fsi_resources[] = { | |
288 | [0] = { | |
289 | .name = "FSI", | |
290 | .start = 0xFE3C0000, | |
291 | .end = 0xFE3C021d, | |
292 | .flags = IORESOURCE_MEM, | |
293 | }, | |
294 | [1] = { | |
295 | .start = 108, | |
296 | .flags = IORESOURCE_IRQ, | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct platform_device fsi_device = { | |
301 | .name = "sh_fsi", | |
302 | .id = 0, | |
303 | .num_resources = ARRAY_SIZE(fsi_resources), | |
304 | .resource = fsi_resources, | |
305 | .dev = { | |
306 | .platform_data = &fsi_info, | |
307 | }, | |
d53bd80c KM |
308 | .archdata = { |
309 | .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ | |
310 | }, | |
3e9ad52b KM |
311 | }; |
312 | ||
9747e78b | 313 | /* KEYSC in SoC (Needs SW33-2 set to ON) */ |
287c1297 KM |
314 | static struct sh_keysc_info keysc_info = { |
315 | .mode = SH_KEYSC_MODE_1, | |
29463c28 | 316 | .scan_timing = 3, |
287c1297 KM |
317 | .delay = 50, |
318 | .keycodes = { | |
319 | KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, | |
320 | KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, | |
321 | KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, | |
322 | KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, | |
323 | KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, | |
324 | KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, | |
325 | }, | |
326 | }; | |
327 | ||
328 | static struct resource keysc_resources[] = { | |
329 | [0] = { | |
9747e78b MD |
330 | .name = "KEYSC", |
331 | .start = 0x044b0000, | |
332 | .end = 0x044b000f, | |
287c1297 KM |
333 | .flags = IORESOURCE_MEM, |
334 | }, | |
335 | [1] = { | |
9747e78b | 336 | .start = 79, |
287c1297 KM |
337 | .flags = IORESOURCE_IRQ, |
338 | }, | |
339 | }; | |
340 | ||
341 | static struct platform_device keysc_device = { | |
342 | .name = "sh_keysc", | |
343 | .id = 0, /* "keysc0" clock */ | |
344 | .num_resources = ARRAY_SIZE(keysc_resources), | |
345 | .resource = keysc_resources, | |
346 | .dev = { | |
347 | .platform_data = &keysc_info, | |
348 | }, | |
df47cd09 MD |
349 | .archdata = { |
350 | .hwblk_id = HWBLK_KEYSC, | |
351 | }, | |
287c1297 KM |
352 | }; |
353 | ||
a80cad95 KM |
354 | /* SH Eth */ |
355 | static struct resource sh_eth_resources[] = { | |
356 | [0] = { | |
357 | .start = SH_ETH_ADDR, | |
358 | .end = SH_ETH_ADDR + 0x1FC, | |
359 | .flags = IORESOURCE_MEM, | |
360 | }, | |
361 | [1] = { | |
362 | .start = 91, | |
363 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
364 | }, | |
365 | }; | |
366 | ||
367 | struct sh_eth_plat_data sh_eth_plat = { | |
368 | .phy = 0x1f, /* SMSC LAN8187 */ | |
369 | .edmac_endian = EDMAC_LITTLE_ENDIAN, | |
370 | }; | |
371 | ||
372 | static struct platform_device sh_eth_device = { | |
373 | .name = "sh-eth", | |
374 | .id = 0, | |
375 | .dev = { | |
376 | .platform_data = &sh_eth_plat, | |
377 | }, | |
378 | .num_resources = ARRAY_SIZE(sh_eth_resources), | |
379 | .resource = sh_eth_resources, | |
df47cd09 MD |
380 | .archdata = { |
381 | .hwblk_id = HWBLK_ETHER, | |
382 | }, | |
a80cad95 KM |
383 | }; |
384 | ||
9731f4a2 | 385 | static struct r8a66597_platdata sh7724_usb0_host_data = { |
719a72b7 | 386 | .on_chip = 1, |
9731f4a2 MD |
387 | }; |
388 | ||
389 | static struct resource sh7724_usb0_host_resources[] = { | |
390 | [0] = { | |
391 | .start = 0xa4d80000, | |
1bc265d0 | 392 | .end = 0xa4d80124 - 1, |
9731f4a2 MD |
393 | .flags = IORESOURCE_MEM, |
394 | }, | |
395 | [1] = { | |
396 | .start = 65, | |
397 | .end = 65, | |
398 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
399 | }, | |
400 | }; | |
401 | ||
402 | static struct platform_device sh7724_usb0_host_device = { | |
403 | .name = "r8a66597_hcd", | |
404 | .id = 0, | |
405 | .dev = { | |
406 | .dma_mask = NULL, /* not use dma */ | |
407 | .coherent_dma_mask = 0xffffffff, | |
408 | .platform_data = &sh7724_usb0_host_data, | |
409 | }, | |
410 | .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), | |
411 | .resource = sh7724_usb0_host_resources, | |
df47cd09 MD |
412 | .archdata = { |
413 | .hwblk_id = HWBLK_USB0, | |
414 | }, | |
9731f4a2 MD |
415 | }; |
416 | ||
f8f8c079 MD |
417 | static struct r8a66597_platdata sh7724_usb1_gadget_data = { |
418 | .on_chip = 1, | |
419 | }; | |
420 | ||
421 | static struct resource sh7724_usb1_gadget_resources[] = { | |
422 | [0] = { | |
423 | .start = 0xa4d90000, | |
424 | .end = 0xa4d90123, | |
425 | .flags = IORESOURCE_MEM, | |
426 | }, | |
427 | [1] = { | |
428 | .start = 66, | |
429 | .end = 66, | |
430 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
431 | }, | |
432 | }; | |
433 | ||
434 | static struct platform_device sh7724_usb1_gadget_device = { | |
435 | .name = "r8a66597_udc", | |
436 | .id = 1, /* USB1 */ | |
437 | .dev = { | |
438 | .dma_mask = NULL, /* not use dma */ | |
439 | .coherent_dma_mask = 0xffffffff, | |
440 | .platform_data = &sh7724_usb1_gadget_data, | |
441 | }, | |
442 | .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), | |
443 | .resource = sh7724_usb1_gadget_resources, | |
444 | }; | |
445 | ||
0f79af60 MD |
446 | static struct resource sdhi0_cn7_resources[] = { |
447 | [0] = { | |
448 | .name = "SDHI0", | |
449 | .start = 0x04ce0000, | |
450 | .end = 0x04ce01ff, | |
451 | .flags = IORESOURCE_MEM, | |
452 | }, | |
453 | [1] = { | |
3844eadc | 454 | .start = 100, |
0f79af60 MD |
455 | .flags = IORESOURCE_IRQ, |
456 | }, | |
457 | }; | |
458 | ||
459 | static struct platform_device sdhi0_cn7_device = { | |
460 | .name = "sh_mobile_sdhi", | |
5b380ec1 | 461 | .id = 0, |
0f79af60 MD |
462 | .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), |
463 | .resource = sdhi0_cn7_resources, | |
464 | .archdata = { | |
465 | .hwblk_id = HWBLK_SDHI0, | |
466 | }, | |
467 | }; | |
468 | ||
5b380ec1 MD |
469 | static struct resource sdhi1_cn8_resources[] = { |
470 | [0] = { | |
471 | .name = "SDHI1", | |
472 | .start = 0x04cf0000, | |
473 | .end = 0x04cf01ff, | |
474 | .flags = IORESOURCE_MEM, | |
475 | }, | |
476 | [1] = { | |
3844eadc | 477 | .start = 23, |
5b380ec1 MD |
478 | .flags = IORESOURCE_IRQ, |
479 | }, | |
480 | }; | |
481 | ||
482 | static struct platform_device sdhi1_cn8_device = { | |
483 | .name = "sh_mobile_sdhi", | |
484 | .id = 1, | |
485 | .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), | |
486 | .resource = sdhi1_cn8_resources, | |
487 | .archdata = { | |
488 | .hwblk_id = HWBLK_SDHI1, | |
489 | }, | |
490 | }; | |
491 | ||
bbb892aa KM |
492 | /* IrDA */ |
493 | static struct resource irda_resources[] = { | |
494 | [0] = { | |
495 | .name = "IrDA", | |
496 | .start = 0xA45D0000, | |
497 | .end = 0xA45D0049, | |
498 | .flags = IORESOURCE_MEM, | |
499 | }, | |
500 | [1] = { | |
501 | .start = 20, | |
502 | .flags = IORESOURCE_IRQ, | |
503 | }, | |
504 | }; | |
505 | ||
506 | static struct platform_device irda_device = { | |
507 | .name = "sh_sir", | |
508 | .num_resources = ARRAY_SIZE(irda_resources), | |
509 | .resource = irda_resources, | |
510 | }; | |
511 | ||
287c1297 KM |
512 | static struct platform_device *ms7724se_devices[] __initdata = { |
513 | &heartbeat_device, | |
514 | &smc91x_eth_device, | |
515 | &lcdc_device, | |
516 | &nor_flash_device, | |
517 | &ceu0_device, | |
518 | &ceu1_device, | |
519 | &keysc_device, | |
a80cad95 | 520 | &sh_eth_device, |
9731f4a2 | 521 | &sh7724_usb0_host_device, |
f8f8c079 | 522 | &sh7724_usb1_gadget_device, |
3e9ad52b | 523 | &fsi_device, |
0f79af60 | 524 | &sdhi0_cn7_device, |
5b380ec1 | 525 | &sdhi1_cn8_device, |
bbb892aa | 526 | &irda_device, |
287c1297 KM |
527 | }; |
528 | ||
9f815a17 KM |
529 | /* I2C device */ |
530 | static struct i2c_board_info i2c0_devices[] = { | |
531 | { | |
532 | I2C_BOARD_INFO("ak4642", 0x12), | |
533 | }, | |
534 | }; | |
535 | ||
a80cad95 KM |
536 | #define EEPROM_OP 0xBA206000 |
537 | #define EEPROM_ADR 0xBA206004 | |
538 | #define EEPROM_DATA 0xBA20600C | |
539 | #define EEPROM_STAT 0xBA206010 | |
540 | #define EEPROM_STRT 0xBA206014 | |
541 | static int __init sh_eth_is_eeprom_ready(void) | |
542 | { | |
543 | int t = 10000; | |
544 | ||
545 | while (t--) { | |
9d56dd3b | 546 | if (!__raw_readw(EEPROM_STAT)) |
a80cad95 | 547 | return 1; |
c718aff2 | 548 | udelay(1); |
a80cad95 KM |
549 | } |
550 | ||
551 | printk(KERN_ERR "ms7724se can not access to eeprom\n"); | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static void __init sh_eth_init(void) | |
556 | { | |
557 | int i; | |
8013cc9a | 558 | u16 mac; |
a80cad95 KM |
559 | |
560 | /* check EEPROM status */ | |
561 | if (!sh_eth_is_eeprom_ready()) | |
562 | return; | |
563 | ||
564 | /* read MAC addr from EEPROM */ | |
565 | for (i = 0 ; i < 3 ; i++) { | |
9d56dd3b PM |
566 | __raw_writew(0x0, EEPROM_OP); /* read */ |
567 | __raw_writew(i*2, EEPROM_ADR); | |
568 | __raw_writew(0x1, EEPROM_STRT); | |
a80cad95 KM |
569 | if (!sh_eth_is_eeprom_ready()) |
570 | return; | |
571 | ||
9d56dd3b | 572 | mac = __raw_readw(EEPROM_DATA); |
8013cc9a MD |
573 | sh_eth_plat.mac_addr[i << 1] = mac & 0xff; |
574 | sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; | |
a80cad95 | 575 | } |
a80cad95 KM |
576 | } |
577 | ||
287c1297 KM |
578 | #define SW4140 0xBA201000 |
579 | #define FPGA_OUT 0xBA200400 | |
580 | #define PORT_HIZA 0xA4050158 | |
9731f4a2 | 581 | #define PORT_MSELCRB 0xA4050182 |
287c1297 KM |
582 | |
583 | #define SW41_A 0x0100 | |
584 | #define SW41_B 0x0200 | |
585 | #define SW41_C 0x0400 | |
586 | #define SW41_D 0x0800 | |
587 | #define SW41_E 0x1000 | |
588 | #define SW41_F 0x2000 | |
589 | #define SW41_G 0x4000 | |
590 | #define SW41_H 0x8000 | |
9731f4a2 | 591 | |
3b9f2952 MD |
592 | extern char ms7724se_sdram_enter_start; |
593 | extern char ms7724se_sdram_enter_end; | |
594 | extern char ms7724se_sdram_leave_start; | |
595 | extern char ms7724se_sdram_leave_end; | |
596 | ||
9f815a17 KM |
597 | |
598 | static int __init arch_setup(void) | |
599 | { | |
600 | /* enable I2C device */ | |
601 | i2c_register_board_info(0, i2c0_devices, | |
602 | ARRAY_SIZE(i2c0_devices)); | |
603 | return 0; | |
604 | } | |
605 | arch_initcall(arch_setup); | |
606 | ||
287c1297 KM |
607 | static int __init devices_setup(void) |
608 | { | |
9d56dd3b | 609 | u16 sw = __raw_readw(SW4140); /* select camera, monitor */ |
16afc9fb | 610 | struct clk *clk; |
287c1297 | 611 | |
3b9f2952 | 612 | /* register board specific self-refresh code */ |
b67cf284 MD |
613 | sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | |
614 | SUSP_SH_RSTANDBY, | |
3b9f2952 MD |
615 | &ms7724se_sdram_enter_start, |
616 | &ms7724se_sdram_enter_end, | |
617 | &ms7724se_sdram_leave_start, | |
618 | &ms7724se_sdram_leave_end); | |
287c1297 | 619 | /* Reset Release */ |
9d56dd3b | 620 | __raw_writew(__raw_readw(FPGA_OUT) & |
287c1297 KM |
621 | ~((1 << 1) | /* LAN */ |
622 | (1 << 6) | /* VIDEO DAC */ | |
3e9ad52b | 623 | (1 << 7) | /* AK4643 */ |
bbb892aa | 624 | (1 << 8) | /* IrDA */ |
a80cad95 KM |
625 | (1 << 12) | /* USB0 */ |
626 | (1 << 14)), /* RMII */ | |
287c1297 KM |
627 | FPGA_OUT); |
628 | ||
9731f4a2 | 629 | /* turn on USB clocks, use external clock */ |
9d56dd3b | 630 | __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); |
9731f4a2 | 631 | |
7766e16b MD |
632 | #ifdef CONFIG_PM |
633 | /* Let LED9 show STATUS2 */ | |
634 | gpio_request(GPIO_FN_STATUS2, NULL); | |
635 | ||
636 | /* Lit LED10 show STATUS0 */ | |
637 | gpio_request(GPIO_FN_STATUS0, NULL); | |
638 | ||
639 | /* Lit LED11 show PDSTATUS */ | |
640 | gpio_request(GPIO_FN_PDSTATUS, NULL); | |
641 | #else | |
642 | /* Lit LED9 */ | |
643 | gpio_request(GPIO_PTJ6, NULL); | |
644 | gpio_direction_output(GPIO_PTJ6, 1); | |
645 | gpio_export(GPIO_PTJ6, 0); | |
646 | ||
647 | /* Lit LED10 */ | |
648 | gpio_request(GPIO_PTJ5, NULL); | |
649 | gpio_direction_output(GPIO_PTJ5, 1); | |
650 | gpio_export(GPIO_PTJ5, 0); | |
651 | ||
652 | /* Lit LED11 */ | |
653 | gpio_request(GPIO_PTJ7, NULL); | |
654 | gpio_direction_output(GPIO_PTJ7, 1); | |
655 | gpio_export(GPIO_PTJ7, 0); | |
656 | #endif | |
657 | ||
9731f4a2 | 658 | /* enable USB0 port */ |
9d56dd3b | 659 | __raw_writew(0x0600, 0xa40501d4); |
9731f4a2 | 660 | |
f8f8c079 | 661 | /* enable USB1 port */ |
9d56dd3b | 662 | __raw_writew(0x0600, 0xa4050192); |
f8f8c079 | 663 | |
287c1297 KM |
664 | /* enable IRQ 0,1,2 */ |
665 | gpio_request(GPIO_FN_INTC_IRQ0, NULL); | |
666 | gpio_request(GPIO_FN_INTC_IRQ1, NULL); | |
667 | gpio_request(GPIO_FN_INTC_IRQ2, NULL); | |
668 | ||
669 | /* enable SCIFA3 */ | |
670 | gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); | |
671 | gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); | |
672 | gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); | |
673 | gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); | |
674 | gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); | |
675 | ||
676 | /* enable LCDC */ | |
677 | gpio_request(GPIO_FN_LCDD23, NULL); | |
678 | gpio_request(GPIO_FN_LCDD22, NULL); | |
679 | gpio_request(GPIO_FN_LCDD21, NULL); | |
680 | gpio_request(GPIO_FN_LCDD20, NULL); | |
681 | gpio_request(GPIO_FN_LCDD19, NULL); | |
682 | gpio_request(GPIO_FN_LCDD18, NULL); | |
683 | gpio_request(GPIO_FN_LCDD17, NULL); | |
684 | gpio_request(GPIO_FN_LCDD16, NULL); | |
685 | gpio_request(GPIO_FN_LCDD15, NULL); | |
686 | gpio_request(GPIO_FN_LCDD14, NULL); | |
687 | gpio_request(GPIO_FN_LCDD13, NULL); | |
688 | gpio_request(GPIO_FN_LCDD12, NULL); | |
689 | gpio_request(GPIO_FN_LCDD11, NULL); | |
690 | gpio_request(GPIO_FN_LCDD10, NULL); | |
691 | gpio_request(GPIO_FN_LCDD9, NULL); | |
692 | gpio_request(GPIO_FN_LCDD8, NULL); | |
693 | gpio_request(GPIO_FN_LCDD7, NULL); | |
694 | gpio_request(GPIO_FN_LCDD6, NULL); | |
695 | gpio_request(GPIO_FN_LCDD5, NULL); | |
696 | gpio_request(GPIO_FN_LCDD4, NULL); | |
697 | gpio_request(GPIO_FN_LCDD3, NULL); | |
698 | gpio_request(GPIO_FN_LCDD2, NULL); | |
699 | gpio_request(GPIO_FN_LCDD1, NULL); | |
700 | gpio_request(GPIO_FN_LCDD0, NULL); | |
701 | gpio_request(GPIO_FN_LCDDISP, NULL); | |
702 | gpio_request(GPIO_FN_LCDHSYN, NULL); | |
703 | gpio_request(GPIO_FN_LCDDCK, NULL); | |
704 | gpio_request(GPIO_FN_LCDVSYN, NULL); | |
705 | gpio_request(GPIO_FN_LCDDON, NULL); | |
706 | gpio_request(GPIO_FN_LCDVEPWC, NULL); | |
707 | gpio_request(GPIO_FN_LCDVCPWC, NULL); | |
708 | gpio_request(GPIO_FN_LCDRD, NULL); | |
709 | gpio_request(GPIO_FN_LCDLCLK, NULL); | |
9d56dd3b | 710 | __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); |
287c1297 KM |
711 | |
712 | /* enable CEU0 */ | |
713 | gpio_request(GPIO_FN_VIO0_D15, NULL); | |
714 | gpio_request(GPIO_FN_VIO0_D14, NULL); | |
715 | gpio_request(GPIO_FN_VIO0_D13, NULL); | |
716 | gpio_request(GPIO_FN_VIO0_D12, NULL); | |
717 | gpio_request(GPIO_FN_VIO0_D11, NULL); | |
718 | gpio_request(GPIO_FN_VIO0_D10, NULL); | |
719 | gpio_request(GPIO_FN_VIO0_D9, NULL); | |
720 | gpio_request(GPIO_FN_VIO0_D8, NULL); | |
721 | gpio_request(GPIO_FN_VIO0_D7, NULL); | |
722 | gpio_request(GPIO_FN_VIO0_D6, NULL); | |
723 | gpio_request(GPIO_FN_VIO0_D5, NULL); | |
724 | gpio_request(GPIO_FN_VIO0_D4, NULL); | |
725 | gpio_request(GPIO_FN_VIO0_D3, NULL); | |
726 | gpio_request(GPIO_FN_VIO0_D2, NULL); | |
727 | gpio_request(GPIO_FN_VIO0_D1, NULL); | |
728 | gpio_request(GPIO_FN_VIO0_D0, NULL); | |
729 | gpio_request(GPIO_FN_VIO0_VD, NULL); | |
730 | gpio_request(GPIO_FN_VIO0_CLK, NULL); | |
731 | gpio_request(GPIO_FN_VIO0_FLD, NULL); | |
732 | gpio_request(GPIO_FN_VIO0_HD, NULL); | |
84f7597c | 733 | platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); |
287c1297 KM |
734 | |
735 | /* enable CEU1 */ | |
736 | gpio_request(GPIO_FN_VIO1_D7, NULL); | |
737 | gpio_request(GPIO_FN_VIO1_D6, NULL); | |
738 | gpio_request(GPIO_FN_VIO1_D5, NULL); | |
739 | gpio_request(GPIO_FN_VIO1_D4, NULL); | |
740 | gpio_request(GPIO_FN_VIO1_D3, NULL); | |
741 | gpio_request(GPIO_FN_VIO1_D2, NULL); | |
742 | gpio_request(GPIO_FN_VIO1_D1, NULL); | |
743 | gpio_request(GPIO_FN_VIO1_D0, NULL); | |
744 | gpio_request(GPIO_FN_VIO1_FLD, NULL); | |
745 | gpio_request(GPIO_FN_VIO1_HD, NULL); | |
746 | gpio_request(GPIO_FN_VIO1_VD, NULL); | |
747 | gpio_request(GPIO_FN_VIO1_CLK, NULL); | |
84f7597c | 748 | platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); |
287c1297 KM |
749 | |
750 | /* KEYSC */ | |
751 | gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); | |
752 | gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); | |
753 | gpio_request(GPIO_FN_KEYIN4, NULL); | |
754 | gpio_request(GPIO_FN_KEYIN3, NULL); | |
755 | gpio_request(GPIO_FN_KEYIN2, NULL); | |
756 | gpio_request(GPIO_FN_KEYIN1, NULL); | |
757 | gpio_request(GPIO_FN_KEYIN0, NULL); | |
758 | gpio_request(GPIO_FN_KEYOUT3, NULL); | |
759 | gpio_request(GPIO_FN_KEYOUT2, NULL); | |
760 | gpio_request(GPIO_FN_KEYOUT1, NULL); | |
761 | gpio_request(GPIO_FN_KEYOUT0, NULL); | |
762 | ||
3e9ad52b KM |
763 | /* enable FSI */ |
764 | gpio_request(GPIO_FN_FSIMCKB, NULL); | |
765 | gpio_request(GPIO_FN_FSIMCKA, NULL); | |
766 | gpio_request(GPIO_FN_FSIOASD, NULL); | |
767 | gpio_request(GPIO_FN_FSIIABCK, NULL); | |
768 | gpio_request(GPIO_FN_FSIIALRCK, NULL); | |
769 | gpio_request(GPIO_FN_FSIOABCK, NULL); | |
770 | gpio_request(GPIO_FN_FSIOALRCK, NULL); | |
771 | gpio_request(GPIO_FN_CLKAUDIOAO, NULL); | |
772 | gpio_request(GPIO_FN_FSIIBSD, NULL); | |
773 | gpio_request(GPIO_FN_FSIOBSD, NULL); | |
774 | gpio_request(GPIO_FN_FSIIBBCK, NULL); | |
775 | gpio_request(GPIO_FN_FSIIBLRCK, NULL); | |
776 | gpio_request(GPIO_FN_FSIOBBCK, NULL); | |
777 | gpio_request(GPIO_FN_FSIOBLRCK, NULL); | |
778 | gpio_request(GPIO_FN_CLKAUDIOBO, NULL); | |
779 | gpio_request(GPIO_FN_FSIIASD, NULL); | |
780 | ||
16afc9fb KM |
781 | /* set SPU2 clock to 83.4 MHz */ |
782 | clk = clk_get(NULL, "spu_clk"); | |
783 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); | |
784 | clk_put(clk); | |
785 | ||
3e9ad52b | 786 | /* change parent of FSI A */ |
16afc9fb | 787 | clk = clk_get(NULL, "fsia_clk"); |
3e9ad52b | 788 | clk_register(&fsimcka_clk); |
16afc9fb KM |
789 | clk_set_parent(clk, &fsimcka_clk); |
790 | clk_set_rate(clk, 11000); | |
3e9ad52b | 791 | clk_set_rate(&fsimcka_clk, 11000); |
16afc9fb | 792 | clk_put(clk); |
3e9ad52b | 793 | |
0f79af60 MD |
794 | /* SDHI0 connected to cn7 */ |
795 | gpio_request(GPIO_FN_SDHI0CD, NULL); | |
796 | gpio_request(GPIO_FN_SDHI0WP, NULL); | |
797 | gpio_request(GPIO_FN_SDHI0D3, NULL); | |
798 | gpio_request(GPIO_FN_SDHI0D2, NULL); | |
799 | gpio_request(GPIO_FN_SDHI0D1, NULL); | |
800 | gpio_request(GPIO_FN_SDHI0D0, NULL); | |
801 | gpio_request(GPIO_FN_SDHI0CMD, NULL); | |
802 | gpio_request(GPIO_FN_SDHI0CLK, NULL); | |
803 | ||
5b380ec1 MD |
804 | /* SDHI1 connected to cn8 */ |
805 | gpio_request(GPIO_FN_SDHI1CD, NULL); | |
806 | gpio_request(GPIO_FN_SDHI1WP, NULL); | |
807 | gpio_request(GPIO_FN_SDHI1D3, NULL); | |
808 | gpio_request(GPIO_FN_SDHI1D2, NULL); | |
809 | gpio_request(GPIO_FN_SDHI1D1, NULL); | |
810 | gpio_request(GPIO_FN_SDHI1D0, NULL); | |
811 | gpio_request(GPIO_FN_SDHI1CMD, NULL); | |
812 | gpio_request(GPIO_FN_SDHI1CLK, NULL); | |
813 | ||
bbb892aa KM |
814 | /* enable IrDA */ |
815 | gpio_request(GPIO_FN_IRDA_OUT, NULL); | |
816 | gpio_request(GPIO_FN_IRDA_IN, NULL); | |
817 | ||
a80cad95 KM |
818 | /* |
819 | * enable SH-Eth | |
820 | * | |
821 | * please remove J33 pin from your board !! | |
822 | * | |
823 | * ms7724 board should not use GPIO_FN_LNKSTA pin | |
824 | * So, This time PTX5 is set to input pin | |
825 | */ | |
826 | gpio_request(GPIO_FN_RMII_RXD0, NULL); | |
827 | gpio_request(GPIO_FN_RMII_RXD1, NULL); | |
828 | gpio_request(GPIO_FN_RMII_TXD0, NULL); | |
829 | gpio_request(GPIO_FN_RMII_TXD1, NULL); | |
830 | gpio_request(GPIO_FN_RMII_REF_CLK, NULL); | |
831 | gpio_request(GPIO_FN_RMII_TX_EN, NULL); | |
832 | gpio_request(GPIO_FN_RMII_RX_ER, NULL); | |
833 | gpio_request(GPIO_FN_RMII_CRS_DV, NULL); | |
834 | gpio_request(GPIO_FN_MDIO, NULL); | |
835 | gpio_request(GPIO_FN_MDC, NULL); | |
836 | gpio_request(GPIO_PTX5, NULL); | |
837 | gpio_direction_input(GPIO_PTX5); | |
838 | sh_eth_init(); | |
839 | ||
287c1297 | 840 | if (sw & SW41_B) { |
4f324311 KM |
841 | /* 720p */ |
842 | lcdc_info.ch[0].lcd_cfg.xres = 1280; | |
843 | lcdc_info.ch[0].lcd_cfg.yres = 720; | |
844 | lcdc_info.ch[0].lcd_cfg.left_margin = 220; | |
845 | lcdc_info.ch[0].lcd_cfg.right_margin = 110; | |
846 | lcdc_info.ch[0].lcd_cfg.hsync_len = 40; | |
847 | lcdc_info.ch[0].lcd_cfg.upper_margin = 20; | |
848 | lcdc_info.ch[0].lcd_cfg.lower_margin = 5; | |
849 | lcdc_info.ch[0].lcd_cfg.vsync_len = 5; | |
287c1297 KM |
850 | } else { |
851 | /* VGA */ | |
852 | lcdc_info.ch[0].lcd_cfg.xres = 640; | |
853 | lcdc_info.ch[0].lcd_cfg.yres = 480; | |
854 | lcdc_info.ch[0].lcd_cfg.left_margin = 105; | |
855 | lcdc_info.ch[0].lcd_cfg.right_margin = 50; | |
856 | lcdc_info.ch[0].lcd_cfg.hsync_len = 96; | |
857 | lcdc_info.ch[0].lcd_cfg.upper_margin = 33; | |
858 | lcdc_info.ch[0].lcd_cfg.lower_margin = 10; | |
859 | lcdc_info.ch[0].lcd_cfg.vsync_len = 2; | |
860 | } | |
861 | ||
862 | if (sw & SW41_A) { | |
863 | /* Digital monitor */ | |
864 | lcdc_info.ch[0].interface_type = RGB18; | |
865 | lcdc_info.ch[0].flags = 0; | |
866 | } else { | |
867 | /* Analog monitor */ | |
868 | lcdc_info.ch[0].interface_type = RGB24; | |
869 | lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; | |
870 | } | |
871 | ||
872 | return platform_add_devices(ms7724se_devices, | |
a80cad95 | 873 | ARRAY_SIZE(ms7724se_devices)); |
287c1297 KM |
874 | } |
875 | device_initcall(devices_setup); | |
876 | ||
877 | static struct sh_machine_vector mv_ms7724se __initmv = { | |
878 | .mv_name = "ms7724se", | |
879 | .mv_init_irq = init_se7724_IRQ, | |
880 | .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, | |
881 | }; |