[net-next-2.6.git] / arch / sh / boards / mach-se / 7343 / irq.c

/*
 * linux/arch/sh/boards/se/7343/irq.c
 *
 * Copyright (C) 2008  Yoshihiro Shimoda
 *
 * Based on linux/arch/sh/boards/se/7722/irq.c
 * Copyright (C) 2007  Nobuhiro Iwamatsu
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach-se/mach/se7343.h>

unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };

static void disable_se7343_irq(struct irq_data *data)
{
	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
	__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
}

static void enable_se7343_irq(struct irq_data *data)
{
	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
	__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
}

static struct irq_chip se7343_irq_chip __read_mostly = {
	.name		= "SE7343-FPGA",
	.irq_mask	= disable_se7343_irq,
	.irq_unmask	= enable_se7343_irq,
};

static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	unsigned short intv = __raw_readw(PA_CPLD_ST);
	unsigned int ext_irq = 0;

	intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;

	for (; intv; intv >>= 1, ext_irq++) {
		if (!(intv & 1))
			continue;

		generic_handle_irq(se7343_fpga_irq[ext_irq]);
	}
}

/*
 * Initialize IRQ setting
 */
void __init init_7343se_IRQ(void)
{
	int i, irq;

	__raw_writew(0, PA_CPLD_IMSK);	/* disable all irqs */
	__raw_writew(0x2000, 0xb03fffec);	/* mrshpc irq enable */

	for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
		irq = create_irq();
		if (irq < 0)
			return;
		se7343_fpga_irq[i] = irq;

		set_irq_chip_and_handler_name(se7343_fpga_irq[i],
					      &se7343_irq_chip,
					      handle_level_irq, "level");

		set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
	}

	set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
	set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
	set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
	set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
	set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
}
Commit	Line	Data
bc8fb5d0	1	/*
cafd63b0	2	* linux/arch/sh/boards/se/7343/irq.c
bc8fb5d0	3	*
cafd63b0 YS	4	* Copyright (C) 2008 Yoshihiro Shimoda
	5	*
	6	* Based on linux/arch/sh/boards/se/7722/irq.c
	7	* Copyright (C) 2007 Nobuhiro Iwamatsu
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
bc8fb5d0	12	*/
bc8fb5d0	13	#include <linux/init.h>
bc8fb5d0	14	#include <linux/irq.h>
cafd63b0	15	#include <linux/interrupt.h>
939a24a6 PM	16	#include <linux/io.h>
939a24a6 PM	17	#include <mach-se/mach/se7343.h>
bc8fb5d0	18
53e6d8e0 PM	19	unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
53e6d8e0 PM	20
15ff2c67	21	static void disable_se7343_irq(struct irq_data *data)
bc8fb5d0	22	{
15ff2c67	23	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
9d56dd3b	24	__raw_writew(__raw_readw(PA_CPLD_IMSK) \| 1 << bit, PA_CPLD_IMSK);
bc8fb5d0 PM	25	}
bc8fb5d0 PM	26
15ff2c67	27	static void enable_se7343_irq(struct irq_data *data)
bc8fb5d0	28	{
15ff2c67	29	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
9d56dd3b	30	__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
bc8fb5d0 PM	31	}
bc8fb5d0 PM	32
cafd63b0	33	static struct irq_chip se7343_irq_chip __read_mostly = {
15ff2c67 PM	34	.name = "SE7343-FPGA",
	35	.irq_mask = disable_se7343_irq,
	36	.irq_unmask = enable_se7343_irq,
bc8fb5d0 PM	37	};
bc8fb5d0 PM	38
cafd63b0	39	static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
bc8fb5d0	40	{
9d56dd3b	41	unsigned short intv = __raw_readw(PA_CPLD_ST);
53e6d8e0	42	unsigned int ext_irq = 0;
cafd63b0 YS	43
	44	intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
	45
53e6d8e0 PM	46	for (; intv; intv >>= 1, ext_irq++) {
	47	if (!(intv & 1))
	48	continue;
	49
	50	generic_handle_irq(se7343_fpga_irq[ext_irq]);
bc8fb5d0	51	}
bc8fb5d0 PM	52	}
bc8fb5d0 PM	53
bc8fb5d0 PM	54	/*
	55	* Initialize IRQ setting
	56	*/
cafd63b0	57	void __init init_7343se_IRQ(void)
bc8fb5d0	58	{
53e6d8e0	59	int i, irq;
cafd63b0	60
9d56dd3b PM	61	__raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
9d56dd3b PM	62	__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
cafd63b0	63
53e6d8e0 PM	64	for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
	65	irq = create_irq();
	66	if (irq < 0)
	67	return;
	68	se7343_fpga_irq[i] = irq;
	69
	70	set_irq_chip_and_handler_name(se7343_fpga_irq[i],
cafd63b0 YS	71	&se7343_irq_chip,
	72	handle_level_irq, "level");
	73
53e6d8e0 PM	74	set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
	75	}
	76
cafd63b0 YS	77	set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
	78	set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
	79	set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
	80	set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
	81	set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
	82	set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
	83	set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
	84	set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
bc8fb5d0	85	}