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Commit | Line | Data |
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dbd70fb4 | 1 | /* |
dbd70fb4 HC |
2 | * Copyright IBM Corp. 2007 |
3 | * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> | |
4 | */ | |
5 | ||
395d31d4 MS |
6 | #define KMSG_COMPONENT "cpu" |
7 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
8 | ||
dbd70fb4 HC |
9 | #include <linux/kernel.h> |
10 | #include <linux/mm.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/smp.h> | |
f414f5f1 | 18 | #include <linux/cpuset.h> |
dbd70fb4 HC |
19 | #include <asm/delay.h> |
20 | #include <asm/s390_ext.h> | |
dbd70fb4 | 21 | |
c10fde0d HC |
22 | #define PTF_HORIZONTAL (0UL) |
23 | #define PTF_VERTICAL (1UL) | |
24 | #define PTF_CHECK (2UL) | |
dbd70fb4 | 25 | |
4cb14bc8 HC |
26 | struct mask_info { |
27 | struct mask_info *next; | |
10d38589 | 28 | unsigned char id; |
dbd70fb4 HC |
29 | cpumask_t mask; |
30 | }; | |
31 | ||
c9af3fa9 | 32 | static int topology_enabled = 1; |
dbd70fb4 | 33 | static void topology_work_fn(struct work_struct *work); |
c30f91b6 | 34 | static struct sysinfo_15_1_x *tl_info; |
dbd70fb4 HC |
35 | static struct timer_list topology_timer; |
36 | static void set_topology_timer(void); | |
37 | static DECLARE_WORK(topology_work, topology_work_fn); | |
74af2831 HC |
38 | /* topology_lock protects the core linked list */ |
39 | static DEFINE_SPINLOCK(topology_lock); | |
dbd70fb4 | 40 | |
4cb14bc8 | 41 | static struct mask_info core_info; |
d00aa4e7 | 42 | cpumask_t cpu_core_map[NR_CPUS]; |
10d38589 | 43 | unsigned char cpu_core_id[NR_CPUS]; |
d00aa4e7 | 44 | |
4cb14bc8 HC |
45 | #ifdef CONFIG_SCHED_BOOK |
46 | static struct mask_info book_info; | |
47 | cpumask_t cpu_book_map[NR_CPUS]; | |
48 | unsigned char cpu_book_id[NR_CPUS]; | |
49 | #endif | |
50 | ||
51 | static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu) | |
dbd70fb4 | 52 | { |
dbd70fb4 HC |
53 | cpumask_t mask; |
54 | ||
55 | cpus_clear(mask); | |
0b52783d HC |
56 | if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) { |
57 | cpumask_copy(&mask, cpumask_of(cpu)); | |
58 | return mask; | |
59 | } | |
4cb14bc8 HC |
60 | while (info) { |
61 | if (cpu_isset(cpu, info->mask)) { | |
62 | mask = info->mask; | |
dbd70fb4 HC |
63 | break; |
64 | } | |
4cb14bc8 | 65 | info = info->next; |
dbd70fb4 | 66 | } |
dbd70fb4 HC |
67 | if (cpus_empty(mask)) |
68 | mask = cpumask_of_cpu(cpu); | |
69 | return mask; | |
70 | } | |
71 | ||
c30f91b6 HC |
72 | static void add_cpus_to_mask(struct topology_cpu *tl_cpu, |
73 | struct mask_info *book, struct mask_info *core) | |
dbd70fb4 HC |
74 | { |
75 | unsigned int cpu; | |
76 | ||
c30f91b6 HC |
77 | for (cpu = find_first_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS); |
78 | cpu < TOPOLOGY_CPU_BITS; | |
79 | cpu = find_next_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS, cpu + 1)) | |
dbd70fb4 HC |
80 | { |
81 | unsigned int rcpu, lcpu; | |
82 | ||
c30f91b6 | 83 | rcpu = TOPOLOGY_CPU_BITS - 1 - cpu + tl_cpu->origin; |
dbd70fb4 | 84 | for_each_present_cpu(lcpu) { |
4cb14bc8 HC |
85 | if (cpu_logical_map(lcpu) != rcpu) |
86 | continue; | |
87 | #ifdef CONFIG_SCHED_BOOK | |
88 | cpu_set(lcpu, book->mask); | |
89 | cpu_book_id[lcpu] = book->id; | |
90 | #endif | |
91 | cpu_set(lcpu, core->mask); | |
92 | cpu_core_id[lcpu] = core->id; | |
93 | smp_cpu_polarization[lcpu] = tl_cpu->pp; | |
dbd70fb4 HC |
94 | } |
95 | } | |
96 | } | |
97 | ||
4cb14bc8 | 98 | static void clear_masks(void) |
dbd70fb4 | 99 | { |
4cb14bc8 | 100 | struct mask_info *info; |
dbd70fb4 | 101 | |
4cb14bc8 HC |
102 | info = &core_info; |
103 | while (info) { | |
104 | cpus_clear(info->mask); | |
105 | info = info->next; | |
106 | } | |
107 | #ifdef CONFIG_SCHED_BOOK | |
108 | info = &book_info; | |
109 | while (info) { | |
110 | cpus_clear(info->mask); | |
111 | info = info->next; | |
dbd70fb4 | 112 | } |
4cb14bc8 | 113 | #endif |
dbd70fb4 HC |
114 | } |
115 | ||
c30f91b6 | 116 | static union topology_entry *next_tle(union topology_entry *tle) |
dbd70fb4 | 117 | { |
c30f91b6 HC |
118 | if (!tle->nl) |
119 | return (union topology_entry *)((struct topology_cpu *)tle + 1); | |
120 | return (union topology_entry *)((struct topology_container *)tle + 1); | |
dbd70fb4 HC |
121 | } |
122 | ||
c30f91b6 | 123 | static void tl_to_cores(struct sysinfo_15_1_x *info) |
dbd70fb4 | 124 | { |
4cb14bc8 HC |
125 | #ifdef CONFIG_SCHED_BOOK |
126 | struct mask_info *book = &book_info; | |
127 | #else | |
128 | struct mask_info *book = NULL; | |
129 | #endif | |
130 | struct mask_info *core = &core_info; | |
c30f91b6 | 131 | union topology_entry *tle, *end; |
4cb14bc8 | 132 | |
dbd70fb4 | 133 | |
74af2831 | 134 | spin_lock_irq(&topology_lock); |
4cb14bc8 | 135 | clear_masks(); |
c10fde0d | 136 | tle = info->tle; |
c30f91b6 | 137 | end = (union topology_entry *)((unsigned long)info + info->length); |
dbd70fb4 HC |
138 | while (tle < end) { |
139 | switch (tle->nl) { | |
4cb14bc8 | 140 | #ifdef CONFIG_SCHED_BOOK |
dbd70fb4 | 141 | case 2: |
4cb14bc8 HC |
142 | book = book->next; |
143 | book->id = tle->container.id; | |
dbd70fb4 | 144 | break; |
4cb14bc8 | 145 | #endif |
dbd70fb4 HC |
146 | case 1: |
147 | core = core->next; | |
10d38589 | 148 | core->id = tle->container.id; |
dbd70fb4 HC |
149 | break; |
150 | case 0: | |
4cb14bc8 | 151 | add_cpus_to_mask(&tle->cpu, book, core); |
dbd70fb4 HC |
152 | break; |
153 | default: | |
4cb14bc8 | 154 | clear_masks(); |
d7015c12 | 155 | goto out; |
dbd70fb4 HC |
156 | } |
157 | tle = next_tle(tle); | |
158 | } | |
d7015c12 | 159 | out: |
74af2831 | 160 | spin_unlock_irq(&topology_lock); |
dbd70fb4 HC |
161 | } |
162 | ||
c10fde0d HC |
163 | static void topology_update_polarization_simple(void) |
164 | { | |
165 | int cpu; | |
166 | ||
167 | mutex_lock(&smp_cpu_state_mutex); | |
5439050f | 168 | for_each_possible_cpu(cpu) |
c10fde0d HC |
169 | smp_cpu_polarization[cpu] = POLARIZATION_HRZ; |
170 | mutex_unlock(&smp_cpu_state_mutex); | |
171 | } | |
172 | ||
173 | static int ptf(unsigned long fc) | |
dbd70fb4 HC |
174 | { |
175 | int rc; | |
176 | ||
177 | asm volatile( | |
178 | " .insn rre,0xb9a20000,%1,%1\n" | |
179 | " ipm %0\n" | |
180 | " srl %0,28\n" | |
181 | : "=d" (rc) | |
c10fde0d HC |
182 | : "d" (fc) : "cc"); |
183 | return rc; | |
184 | } | |
185 | ||
186 | int topology_set_cpu_management(int fc) | |
187 | { | |
188 | int cpu; | |
189 | int rc; | |
190 | ||
9186d7a9 | 191 | if (!MACHINE_HAS_TOPOLOGY) |
c10fde0d HC |
192 | return -EOPNOTSUPP; |
193 | if (fc) | |
194 | rc = ptf(PTF_VERTICAL); | |
195 | else | |
196 | rc = ptf(PTF_HORIZONTAL); | |
197 | if (rc) | |
198 | return -EBUSY; | |
5439050f | 199 | for_each_possible_cpu(cpu) |
c10fde0d | 200 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
dbd70fb4 HC |
201 | return rc; |
202 | } | |
203 | ||
d00aa4e7 HC |
204 | static void update_cpu_core_map(void) |
205 | { | |
4cb14bc8 | 206 | unsigned long flags; |
d00aa4e7 HC |
207 | int cpu; |
208 | ||
4cb14bc8 HC |
209 | spin_lock_irqsave(&topology_lock, flags); |
210 | for_each_possible_cpu(cpu) { | |
211 | cpu_core_map[cpu] = cpu_group_map(&core_info, cpu); | |
212 | #ifdef CONFIG_SCHED_BOOK | |
213 | cpu_book_map[cpu] = cpu_group_map(&book_info, cpu); | |
214 | #endif | |
215 | } | |
216 | spin_unlock_irqrestore(&topology_lock, flags); | |
217 | } | |
218 | ||
96f4a70d | 219 | void store_topology(struct sysinfo_15_1_x *info) |
4cb14bc8 HC |
220 | { |
221 | #ifdef CONFIG_SCHED_BOOK | |
222 | int rc; | |
223 | ||
224 | rc = stsi(info, 15, 1, 3); | |
225 | if (rc != -ENOSYS) | |
226 | return; | |
227 | #endif | |
228 | stsi(info, 15, 1, 2); | |
d00aa4e7 HC |
229 | } |
230 | ||
ee79d1bd | 231 | int arch_update_cpu_topology(void) |
dbd70fb4 | 232 | { |
c30f91b6 | 233 | struct sysinfo_15_1_x *info = tl_info; |
dbd70fb4 HC |
234 | struct sys_device *sysdev; |
235 | int cpu; | |
236 | ||
9186d7a9 | 237 | if (!MACHINE_HAS_TOPOLOGY) { |
d00aa4e7 | 238 | update_cpu_core_map(); |
c10fde0d | 239 | topology_update_polarization_simple(); |
ee79d1bd | 240 | return 0; |
c10fde0d | 241 | } |
4cb14bc8 | 242 | store_topology(info); |
dbd70fb4 | 243 | tl_to_cores(info); |
d00aa4e7 | 244 | update_cpu_core_map(); |
dbd70fb4 HC |
245 | for_each_online_cpu(cpu) { |
246 | sysdev = get_cpu_sysdev(cpu); | |
247 | kobject_uevent(&sysdev->kobj, KOBJ_CHANGE); | |
248 | } | |
ee79d1bd | 249 | return 1; |
dbd70fb4 HC |
250 | } |
251 | ||
fd781fa2 HC |
252 | static void topology_work_fn(struct work_struct *work) |
253 | { | |
f414f5f1 | 254 | rebuild_sched_domains(); |
dbd70fb4 HC |
255 | } |
256 | ||
c10fde0d HC |
257 | void topology_schedule_update(void) |
258 | { | |
259 | schedule_work(&topology_work); | |
260 | } | |
261 | ||
dbd70fb4 HC |
262 | static void topology_timer_fn(unsigned long ignored) |
263 | { | |
c10fde0d HC |
264 | if (ptf(PTF_CHECK)) |
265 | topology_schedule_update(); | |
dbd70fb4 HC |
266 | set_topology_timer(); |
267 | } | |
268 | ||
269 | static void set_topology_timer(void) | |
270 | { | |
271 | topology_timer.function = topology_timer_fn; | |
272 | topology_timer.data = 0; | |
273 | topology_timer.expires = jiffies + 60 * HZ; | |
274 | add_timer(&topology_timer); | |
275 | } | |
276 | ||
2b1a61f0 | 277 | static int __init early_parse_topology(char *p) |
dbd70fb4 | 278 | { |
c9af3fa9 | 279 | if (strncmp(p, "off", 3)) |
2b1a61f0 | 280 | return 0; |
c9af3fa9 | 281 | topology_enabled = 0; |
2b1a61f0 | 282 | return 0; |
dbd70fb4 | 283 | } |
2b1a61f0 | 284 | early_param("topology", early_parse_topology); |
dbd70fb4 HC |
285 | |
286 | static int __init init_topology_update(void) | |
287 | { | |
288 | int rc; | |
289 | ||
d00aa4e7 | 290 | rc = 0; |
9186d7a9 | 291 | if (!MACHINE_HAS_TOPOLOGY) { |
c10fde0d | 292 | topology_update_polarization_simple(); |
d00aa4e7 | 293 | goto out; |
c10fde0d HC |
294 | } |
295 | init_timer_deferrable(&topology_timer); | |
349f1b67 | 296 | set_topology_timer(); |
d00aa4e7 HC |
297 | out: |
298 | update_cpu_core_map(); | |
299 | return rc; | |
dbd70fb4 HC |
300 | } |
301 | __initcall(init_topology_update); | |
302 | ||
c30f91b6 HC |
303 | static void alloc_masks(struct sysinfo_15_1_x *info, struct mask_info *mask, |
304 | int offset) | |
4cb14bc8 HC |
305 | { |
306 | int i, nr_masks; | |
307 | ||
c30f91b6 | 308 | nr_masks = info->mag[TOPOLOGY_NR_MAG - offset]; |
4cb14bc8 | 309 | for (i = 0; i < info->mnest - offset; i++) |
c30f91b6 | 310 | nr_masks *= info->mag[TOPOLOGY_NR_MAG - offset - 1 - i]; |
4cb14bc8 HC |
311 | nr_masks = max(nr_masks, 1); |
312 | for (i = 0; i < nr_masks; i++) { | |
313 | mask->next = alloc_bootmem(sizeof(struct mask_info)); | |
314 | mask = mask->next; | |
315 | } | |
316 | } | |
317 | ||
dbd70fb4 HC |
318 | void __init s390_init_cpu_topology(void) |
319 | { | |
c30f91b6 | 320 | struct sysinfo_15_1_x *info; |
dbd70fb4 HC |
321 | int i; |
322 | ||
9186d7a9 | 323 | if (!MACHINE_HAS_TOPOLOGY) |
dbd70fb4 | 324 | return; |
dbd70fb4 | 325 | tl_info = alloc_bootmem_pages(PAGE_SIZE); |
dbd70fb4 | 326 | info = tl_info; |
4cb14bc8 | 327 | store_topology(info); |
395d31d4 | 328 | pr_info("The CPU configuration topology of the machine is:"); |
c30f91b6 | 329 | for (i = 0; i < TOPOLOGY_NR_MAG; i++) |
dbd70fb4 HC |
330 | printk(" %d", info->mag[i]); |
331 | printk(" / %d\n", info->mnest); | |
4cb14bc8 HC |
332 | alloc_masks(info, &core_info, 2); |
333 | #ifdef CONFIG_SCHED_BOOK | |
334 | alloc_masks(info, &book_info, 3); | |
335 | #endif | |
dbd70fb4 | 336 | } |