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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/smp.c | |
3 | * | |
155af2f9 | 4 | * Copyright IBM Corp. 1999, 2009 |
1da177e4 | 5 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), |
39ce010d HC |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) |
7 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
13 | * We work with logical cpu numbering everywhere we can. The only | |
14 | * functions using the real cpu address (got from STAP) are the sigp | |
15 | * functions. For all other functions we use the identity mapping. | |
16 | * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is | |
17 | * used e.g. to find the idle task belonging to a logical cpu. Every array | |
18 | * in the kernel is sorted by the logical cpu number and not by the physical | |
19 | * one which is causing all the confusion with __cpu_logical_map and | |
20 | * cpu_number_map in other architectures. | |
21 | */ | |
22 | ||
395d31d4 MS |
23 | #define KMSG_COMPONENT "cpu" |
24 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
25 | ||
1da177e4 LT |
26 | #include <linux/module.h> |
27 | #include <linux/init.h> | |
1da177e4 | 28 | #include <linux/mm.h> |
4e950f6f | 29 | #include <linux/err.h> |
1da177e4 LT |
30 | #include <linux/spinlock.h> |
31 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
32 | #include <linux/delay.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/interrupt.h> | |
3324e60a | 35 | #include <linux/irqflags.h> |
1da177e4 | 36 | #include <linux/cpu.h> |
2b67fc46 | 37 | #include <linux/timex.h> |
411ed322 | 38 | #include <linux/bootmem.h> |
46b05d26 | 39 | #include <asm/ipl.h> |
2b67fc46 | 40 | #include <asm/setup.h> |
1da177e4 LT |
41 | #include <asm/sigp.h> |
42 | #include <asm/pgalloc.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/s390_ext.h> | |
45 | #include <asm/cpcmd.h> | |
46 | #include <asm/tlbflush.h> | |
2b67fc46 | 47 | #include <asm/timer.h> |
411ed322 | 48 | #include <asm/lowcore.h> |
08d07968 | 49 | #include <asm/sclp.h> |
76d4e00a | 50 | #include <asm/cputime.h> |
c742b31c | 51 | #include <asm/vdso.h> |
4bb5e07b | 52 | #include <asm/cpu.h> |
a806170e | 53 | #include "entry.h" |
1da177e4 | 54 | |
1da177e4 LT |
55 | static struct task_struct *current_set[NR_CPUS]; |
56 | ||
08d07968 HC |
57 | static u8 smp_cpu_type; |
58 | static int smp_use_sigp_detection; | |
59 | ||
60 | enum s390_cpu_state { | |
61 | CPU_STATE_STANDBY, | |
62 | CPU_STATE_CONFIGURED, | |
63 | }; | |
64 | ||
dbd70fb4 | 65 | DEFINE_MUTEX(smp_cpu_state_mutex); |
c10fde0d | 66 | int smp_cpu_polarization[NR_CPUS]; |
08d07968 | 67 | static int smp_cpu_state[NR_CPUS]; |
c10fde0d | 68 | static int cpu_management; |
08d07968 HC |
69 | |
70 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
08d07968 | 71 | |
1da177e4 | 72 | static void smp_ext_bitcall(int, ec_bit_sig); |
1da177e4 | 73 | |
5c0b912e HC |
74 | static int cpu_stopped(int cpu) |
75 | { | |
76 | __u32 status; | |
77 | ||
78 | switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) { | |
5c0b912e HC |
79 | case sigp_status_stored: |
80 | /* Check for stopped and check stop state */ | |
81 | if (status & 0x50) | |
82 | return 1; | |
83 | break; | |
84 | default: | |
85 | break; | |
86 | } | |
87 | return 0; | |
88 | } | |
89 | ||
677d7623 | 90 | void smp_send_stop(void) |
1da177e4 | 91 | { |
39ce010d | 92 | int cpu, rc; |
1da177e4 | 93 | |
677d7623 HC |
94 | /* Disable all interrupts/machine checks */ |
95 | __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK); | |
3324e60a | 96 | trace_hardirqs_off(); |
1da177e4 | 97 | |
677d7623 | 98 | /* stop all processors */ |
1da177e4 LT |
99 | for_each_online_cpu(cpu) { |
100 | if (cpu == smp_processor_id()) | |
101 | continue; | |
102 | do { | |
677d7623 | 103 | rc = signal_processor(cpu, sigp_stop); |
39ce010d | 104 | } while (rc == sigp_busy); |
1da177e4 | 105 | |
5c0b912e | 106 | while (!cpu_stopped(cpu)) |
c6b5b847 HC |
107 | cpu_relax(); |
108 | } | |
109 | } | |
110 | ||
1da177e4 LT |
111 | /* |
112 | * This is the main routine where commands issued by other | |
113 | * cpus are handled. | |
114 | */ | |
115 | ||
2b67fc46 | 116 | static void do_ext_call_interrupt(__u16 code) |
1da177e4 | 117 | { |
39ce010d | 118 | unsigned long bits; |
1da177e4 | 119 | |
39ce010d HC |
120 | /* |
121 | * handle bit signal external calls | |
122 | * | |
123 | * For the ec_schedule signal we have to do nothing. All the work | |
124 | * is done automatically when we return from the interrupt. | |
125 | */ | |
1da177e4 LT |
126 | bits = xchg(&S390_lowcore.ext_call_fast, 0); |
127 | ||
39ce010d | 128 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
129 | generic_smp_call_function_interrupt(); |
130 | ||
131 | if (test_bit(ec_call_function_single, &bits)) | |
132 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
133 | } |
134 | ||
135 | /* | |
136 | * Send an external call sigp to another cpu and return without waiting | |
137 | * for its completion. | |
138 | */ | |
139 | static void smp_ext_bitcall(int cpu, ec_bit_sig sig) | |
140 | { | |
39ce010d HC |
141 | /* |
142 | * Set signaling bit in lowcore of target cpu and kick it | |
143 | */ | |
1da177e4 | 144 | set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); |
39ce010d | 145 | while (signal_processor(cpu, sigp_emergency_signal) == sigp_busy) |
1da177e4 LT |
146 | udelay(10); |
147 | } | |
148 | ||
630cd046 | 149 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
150 | { |
151 | int cpu; | |
152 | ||
630cd046 | 153 | for_each_cpu(cpu, mask) |
ca9fc75a HC |
154 | smp_ext_bitcall(cpu, ec_call_function); |
155 | } | |
156 | ||
157 | void arch_send_call_function_single_ipi(int cpu) | |
158 | { | |
159 | smp_ext_bitcall(cpu, ec_call_function_single); | |
160 | } | |
161 | ||
347a8dc3 | 162 | #ifndef CONFIG_64BIT |
1da177e4 LT |
163 | /* |
164 | * this function sends a 'purge tlb' signal to another CPU. | |
165 | */ | |
a806170e | 166 | static void smp_ptlb_callback(void *info) |
1da177e4 | 167 | { |
ba8a9229 | 168 | __tlb_flush_local(); |
1da177e4 LT |
169 | } |
170 | ||
171 | void smp_ptlb_all(void) | |
172 | { | |
15c8b6c1 | 173 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
174 | } |
175 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 176 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
177 | |
178 | /* | |
179 | * this function sends a 'reschedule' IPI to another CPU. | |
180 | * it goes straight through and wastes no time serializing | |
181 | * anything. Worst case is that we lose a reschedule ... | |
182 | */ | |
183 | void smp_send_reschedule(int cpu) | |
184 | { | |
39ce010d | 185 | smp_ext_bitcall(cpu, ec_schedule); |
1da177e4 LT |
186 | } |
187 | ||
188 | /* | |
189 | * parameter area for the set/clear control bit callbacks | |
190 | */ | |
94c12cc7 | 191 | struct ec_creg_mask_parms { |
1da177e4 LT |
192 | unsigned long orvals[16]; |
193 | unsigned long andvals[16]; | |
94c12cc7 | 194 | }; |
1da177e4 LT |
195 | |
196 | /* | |
197 | * callback for setting/clearing control bits | |
198 | */ | |
39ce010d HC |
199 | static void smp_ctl_bit_callback(void *info) |
200 | { | |
94c12cc7 | 201 | struct ec_creg_mask_parms *pp = info; |
1da177e4 LT |
202 | unsigned long cregs[16]; |
203 | int i; | |
39ce010d | 204 | |
94c12cc7 MS |
205 | __ctl_store(cregs, 0, 15); |
206 | for (i = 0; i <= 15; i++) | |
1da177e4 | 207 | cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i]; |
94c12cc7 | 208 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* | |
212 | * Set a bit in a control register of all cpus | |
213 | */ | |
94c12cc7 MS |
214 | void smp_ctl_set_bit(int cr, int bit) |
215 | { | |
216 | struct ec_creg_mask_parms parms; | |
1da177e4 | 217 | |
94c12cc7 MS |
218 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
219 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 220 | parms.orvals[cr] = 1 << bit; |
15c8b6c1 | 221 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 222 | } |
39ce010d | 223 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
224 | |
225 | /* | |
226 | * Clear a bit in a control register of all cpus | |
227 | */ | |
94c12cc7 MS |
228 | void smp_ctl_clear_bit(int cr, int bit) |
229 | { | |
230 | struct ec_creg_mask_parms parms; | |
1da177e4 | 231 | |
94c12cc7 MS |
232 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
233 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 234 | parms.andvals[cr] = ~(1L << bit); |
15c8b6c1 | 235 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 236 | } |
39ce010d | 237 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 238 | |
08d07968 HC |
239 | /* |
240 | * In early ipl state a temp. logically cpu number is needed, so the sigp | |
241 | * functions can be used to sense other cpus. Since NR_CPUS is >= 2 on | |
242 | * CONFIG_SMP and the ipl cpu is logical cpu 0, it must be 1. | |
243 | */ | |
244 | #define CPU_INIT_NO 1 | |
245 | ||
59f2e69d | 246 | #ifdef CONFIG_ZFCPDUMP |
411ed322 MH |
247 | |
248 | /* | |
249 | * zfcpdump_prefix_array holds prefix registers for the following scenario: | |
250 | * 64 bit zfcpdump kernel and 31 bit kernel which is to be dumped. We have to | |
251 | * save its prefix registers, since they get lost, when switching from 31 bit | |
252 | * to 64 bit. | |
253 | */ | |
254 | unsigned int zfcpdump_prefix_array[NR_CPUS + 1] \ | |
255 | __attribute__((__section__(".data"))); | |
256 | ||
285f6722 | 257 | static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) |
411ed322 | 258 | { |
411ed322 MH |
259 | if (ipl_info.type != IPL_TYPE_FCP_DUMP) |
260 | return; | |
285f6722 | 261 | if (cpu >= NR_CPUS) { |
395d31d4 MS |
262 | pr_warning("CPU %i exceeds the maximum %i and is excluded from " |
263 | "the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 264 | return; |
411ed322 | 265 | } |
48483b32 | 266 | zfcpdump_save_areas[cpu] = kmalloc(sizeof(union save_area), GFP_KERNEL); |
08d07968 HC |
267 | __cpu_logical_map[CPU_INIT_NO] = (__u16) phy_cpu; |
268 | while (signal_processor(CPU_INIT_NO, sigp_stop_and_store_status) == | |
269 | sigp_busy) | |
285f6722 HC |
270 | cpu_relax(); |
271 | memcpy(zfcpdump_save_areas[cpu], | |
272 | (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE, | |
273 | SAVE_AREA_SIZE); | |
274 | #ifdef CONFIG_64BIT | |
275 | /* copy original prefix register */ | |
276 | zfcpdump_save_areas[cpu]->s390x.pref_reg = zfcpdump_prefix_array[cpu]; | |
277 | #endif | |
411ed322 MH |
278 | } |
279 | ||
280 | union save_area *zfcpdump_save_areas[NR_CPUS + 1]; | |
281 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
282 | ||
283 | #else | |
285f6722 HC |
284 | |
285 | static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { } | |
286 | ||
59f2e69d | 287 | #endif /* CONFIG_ZFCPDUMP */ |
411ed322 | 288 | |
08d07968 HC |
289 | static int cpu_known(int cpu_id) |
290 | { | |
291 | int cpu; | |
292 | ||
293 | for_each_present_cpu(cpu) { | |
294 | if (__cpu_logical_map[cpu] == cpu_id) | |
295 | return 1; | |
296 | } | |
297 | return 0; | |
298 | } | |
299 | ||
300 | static int smp_rescan_cpus_sigp(cpumask_t avail) | |
301 | { | |
302 | int cpu_id, logical_cpu; | |
303 | ||
93632d1b RR |
304 | logical_cpu = cpumask_first(&avail); |
305 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 306 | return 0; |
4bb5e07b | 307 | for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) { |
08d07968 HC |
308 | if (cpu_known(cpu_id)) |
309 | continue; | |
310 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 311 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
312 | if (!cpu_stopped(logical_cpu)) |
313 | continue; | |
314 | cpu_set(logical_cpu, cpu_present_map); | |
315 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
316 | logical_cpu = cpumask_next(logical_cpu, &avail); |
317 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
318 | break; |
319 | } | |
320 | return 0; | |
321 | } | |
322 | ||
48483b32 | 323 | static int smp_rescan_cpus_sclp(cpumask_t avail) |
08d07968 HC |
324 | { |
325 | struct sclp_cpu_info *info; | |
326 | int cpu_id, logical_cpu, cpu; | |
327 | int rc; | |
328 | ||
93632d1b RR |
329 | logical_cpu = cpumask_first(&avail); |
330 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 331 | return 0; |
48483b32 | 332 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
08d07968 HC |
333 | if (!info) |
334 | return -ENOMEM; | |
335 | rc = sclp_get_cpu_info(info); | |
336 | if (rc) | |
337 | goto out; | |
338 | for (cpu = 0; cpu < info->combined; cpu++) { | |
339 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
340 | continue; | |
341 | cpu_id = info->cpu[cpu].address; | |
342 | if (cpu_known(cpu_id)) | |
343 | continue; | |
344 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 345 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
346 | cpu_set(logical_cpu, cpu_present_map); |
347 | if (cpu >= info->configured) | |
348 | smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY; | |
349 | else | |
350 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
351 | logical_cpu = cpumask_next(logical_cpu, &avail); |
352 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
353 | break; |
354 | } | |
355 | out: | |
48483b32 | 356 | kfree(info); |
08d07968 HC |
357 | return rc; |
358 | } | |
359 | ||
1e489518 | 360 | static int __smp_rescan_cpus(void) |
08d07968 HC |
361 | { |
362 | cpumask_t avail; | |
363 | ||
48483b32 | 364 | cpus_xor(avail, cpu_possible_map, cpu_present_map); |
08d07968 HC |
365 | if (smp_use_sigp_detection) |
366 | return smp_rescan_cpus_sigp(avail); | |
367 | else | |
368 | return smp_rescan_cpus_sclp(avail); | |
1da177e4 LT |
369 | } |
370 | ||
48483b32 HC |
371 | static void __init smp_detect_cpus(void) |
372 | { | |
373 | unsigned int cpu, c_cpus, s_cpus; | |
374 | struct sclp_cpu_info *info; | |
375 | u16 boot_cpu_addr, cpu_addr; | |
376 | ||
377 | c_cpus = 1; | |
378 | s_cpus = 0; | |
7b468488 | 379 | boot_cpu_addr = __cpu_logical_map[0]; |
48483b32 HC |
380 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
381 | if (!info) | |
382 | panic("smp_detect_cpus failed to allocate memory\n"); | |
383 | /* Use sigp detection algorithm if sclp doesn't work. */ | |
384 | if (sclp_get_cpu_info(info)) { | |
385 | smp_use_sigp_detection = 1; | |
4bb5e07b | 386 | for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) { |
48483b32 HC |
387 | if (cpu == boot_cpu_addr) |
388 | continue; | |
389 | __cpu_logical_map[CPU_INIT_NO] = cpu; | |
390 | if (!cpu_stopped(CPU_INIT_NO)) | |
391 | continue; | |
392 | smp_get_save_area(c_cpus, cpu); | |
393 | c_cpus++; | |
394 | } | |
395 | goto out; | |
396 | } | |
397 | ||
398 | if (info->has_cpu_type) { | |
399 | for (cpu = 0; cpu < info->combined; cpu++) { | |
400 | if (info->cpu[cpu].address == boot_cpu_addr) { | |
401 | smp_cpu_type = info->cpu[cpu].type; | |
402 | break; | |
403 | } | |
404 | } | |
405 | } | |
406 | ||
407 | for (cpu = 0; cpu < info->combined; cpu++) { | |
408 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
409 | continue; | |
410 | cpu_addr = info->cpu[cpu].address; | |
411 | if (cpu_addr == boot_cpu_addr) | |
412 | continue; | |
413 | __cpu_logical_map[CPU_INIT_NO] = cpu_addr; | |
414 | if (!cpu_stopped(CPU_INIT_NO)) { | |
415 | s_cpus++; | |
416 | continue; | |
417 | } | |
418 | smp_get_save_area(c_cpus, cpu_addr); | |
419 | c_cpus++; | |
420 | } | |
421 | out: | |
422 | kfree(info); | |
395d31d4 | 423 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 424 | get_online_cpus(); |
1e489518 | 425 | __smp_rescan_cpus(); |
9d40d2e3 | 426 | put_online_cpus(); |
48483b32 HC |
427 | } |
428 | ||
1da177e4 | 429 | /* |
39ce010d | 430 | * Activate a secondary processor. |
1da177e4 | 431 | */ |
ea1f4eec | 432 | int __cpuinit start_secondary(void *cpuvoid) |
1da177e4 | 433 | { |
39ce010d HC |
434 | /* Setup the cpu */ |
435 | cpu_init(); | |
5bfb5d69 | 436 | preempt_disable(); |
d54853ef | 437 | /* Enable TOD clock interrupts on the secondary cpu. */ |
39ce010d | 438 | init_cpu_timer(); |
d54853ef | 439 | /* Enable cpu timer interrupts on the secondary cpu. */ |
39ce010d | 440 | init_cpu_vtimer(); |
1da177e4 | 441 | /* Enable pfault pseudo page faults on this cpu. */ |
29b08d2b HC |
442 | pfault_init(); |
443 | ||
e545a614 MS |
444 | /* call cpu notifiers */ |
445 | notify_cpu_starting(smp_processor_id()); | |
1da177e4 | 446 | /* Mark this cpu as online */ |
ca9fc75a | 447 | ipi_call_lock(); |
1da177e4 | 448 | cpu_set(smp_processor_id(), cpu_online_map); |
ca9fc75a | 449 | ipi_call_unlock(); |
1da177e4 LT |
450 | /* Switch on interrupts */ |
451 | local_irq_enable(); | |
39ce010d | 452 | /* Print info about this processor */ |
7b468488 | 453 | print_cpu_info(); |
39ce010d HC |
454 | /* cpu_idle will call schedule for us */ |
455 | cpu_idle(); | |
456 | return 0; | |
1da177e4 LT |
457 | } |
458 | ||
459 | static void __init smp_create_idle(unsigned int cpu) | |
460 | { | |
461 | struct task_struct *p; | |
462 | ||
463 | /* | |
464 | * don't care about the psw and regs settings since we'll never | |
465 | * reschedule the forked task. | |
466 | */ | |
467 | p = fork_idle(cpu); | |
468 | if (IS_ERR(p)) | |
469 | panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); | |
470 | current_set[cpu] = p; | |
471 | } | |
472 | ||
1cb6bb4b HC |
473 | static int __cpuinit smp_alloc_lowcore(int cpu) |
474 | { | |
475 | unsigned long async_stack, panic_stack; | |
476 | struct _lowcore *lowcore; | |
1cb6bb4b | 477 | |
3fd26a77 | 478 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
1cb6bb4b HC |
479 | if (!lowcore) |
480 | return -ENOMEM; | |
481 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
1cb6bb4b | 482 | panic_stack = __get_free_page(GFP_KERNEL); |
591bb4f6 HC |
483 | if (!panic_stack || !async_stack) |
484 | goto out; | |
98c7b388 HC |
485 | memcpy(lowcore, &S390_lowcore, 512); |
486 | memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512); | |
1cb6bb4b HC |
487 | lowcore->async_stack = async_stack + ASYNC_SIZE; |
488 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
489 | ||
490 | #ifndef CONFIG_64BIT | |
491 | if (MACHINE_HAS_IEEE) { | |
492 | unsigned long save_area; | |
493 | ||
494 | save_area = get_zeroed_page(GFP_KERNEL); | |
495 | if (!save_area) | |
33b1d09e | 496 | goto out; |
1cb6bb4b HC |
497 | lowcore->extended_save_area_addr = (u32) save_area; |
498 | } | |
c742b31c MS |
499 | #else |
500 | if (vdso_alloc_per_cpu(cpu, lowcore)) | |
501 | goto out; | |
1cb6bb4b HC |
502 | #endif |
503 | lowcore_ptr[cpu] = lowcore; | |
504 | return 0; | |
505 | ||
591bb4f6 | 506 | out: |
33b1d09e | 507 | free_page(panic_stack); |
1cb6bb4b | 508 | free_pages(async_stack, ASYNC_ORDER); |
3fd26a77 | 509 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
510 | return -ENOMEM; |
511 | } | |
512 | ||
1cb6bb4b HC |
513 | static void smp_free_lowcore(int cpu) |
514 | { | |
515 | struct _lowcore *lowcore; | |
1cb6bb4b | 516 | |
1cb6bb4b HC |
517 | lowcore = lowcore_ptr[cpu]; |
518 | #ifndef CONFIG_64BIT | |
519 | if (MACHINE_HAS_IEEE) | |
520 | free_page((unsigned long) lowcore->extended_save_area_addr); | |
c742b31c MS |
521 | #else |
522 | vdso_free_per_cpu(cpu, lowcore); | |
1cb6bb4b HC |
523 | #endif |
524 | free_page(lowcore->panic_stack - PAGE_SIZE); | |
525 | free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER); | |
3fd26a77 | 526 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
527 | lowcore_ptr[cpu] = NULL; |
528 | } | |
1cb6bb4b | 529 | |
1da177e4 | 530 | /* Upping and downing of CPUs */ |
1cb6bb4b | 531 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
532 | { |
533 | struct task_struct *idle; | |
39ce010d | 534 | struct _lowcore *cpu_lowcore; |
1da177e4 | 535 | struct stack_frame *sf; |
39ce010d | 536 | sigp_ccode ccode; |
d0d3cdf4 | 537 | u32 lowcore; |
1da177e4 | 538 | |
08d07968 HC |
539 | if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) |
540 | return -EIO; | |
1cb6bb4b HC |
541 | if (smp_alloc_lowcore(cpu)) |
542 | return -ENOMEM; | |
d0d3cdf4 HC |
543 | do { |
544 | ccode = signal_processor(cpu, sigp_initial_cpu_reset); | |
545 | if (ccode == sigp_busy) | |
546 | udelay(10); | |
547 | if (ccode == sigp_not_operational) | |
548 | goto err_out; | |
549 | } while (ccode == sigp_busy); | |
550 | ||
551 | lowcore = (u32)(unsigned long)lowcore_ptr[cpu]; | |
552 | while (signal_processor_p(lowcore, cpu, sigp_set_prefix) == sigp_busy) | |
553 | udelay(10); | |
1da177e4 LT |
554 | |
555 | idle = current_set[cpu]; | |
39ce010d | 556 | cpu_lowcore = lowcore_ptr[cpu]; |
1da177e4 | 557 | cpu_lowcore->kernel_stack = (unsigned long) |
39ce010d | 558 | task_stack_page(idle) + THREAD_SIZE; |
1cb6bb4b | 559 | cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle); |
1da177e4 LT |
560 | sf = (struct stack_frame *) (cpu_lowcore->kernel_stack |
561 | - sizeof(struct pt_regs) | |
562 | - sizeof(struct stack_frame)); | |
563 | memset(sf, 0, sizeof(struct stack_frame)); | |
564 | sf->gprs[9] = (unsigned long) sf; | |
565 | cpu_lowcore->save_area[15] = (unsigned long) sf; | |
24d3e210 | 566 | __ctl_store(cpu_lowcore->cregs_save_area, 0, 15); |
94c12cc7 MS |
567 | asm volatile( |
568 | " stam 0,15,0(%0)" | |
569 | : : "a" (&cpu_lowcore->access_regs_save_area) : "memory"); | |
1da177e4 | 570 | cpu_lowcore->percpu_offset = __per_cpu_offset[cpu]; |
39ce010d | 571 | cpu_lowcore->current_task = (unsigned long) idle; |
7b468488 | 572 | cpu_lowcore->cpu_nr = cpu; |
591bb4f6 | 573 | cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce; |
25097bf1 | 574 | cpu_lowcore->machine_flags = S390_lowcore.machine_flags; |
dfd9f7ab | 575 | cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func; |
1da177e4 | 576 | eieio(); |
699ff13f | 577 | |
39ce010d | 578 | while (signal_processor(cpu, sigp_restart) == sigp_busy) |
699ff13f | 579 | udelay(10); |
1da177e4 LT |
580 | |
581 | while (!cpu_online(cpu)) | |
582 | cpu_relax(); | |
583 | return 0; | |
d0d3cdf4 HC |
584 | |
585 | err_out: | |
586 | smp_free_lowcore(cpu); | |
587 | return -EIO; | |
1da177e4 LT |
588 | } |
589 | ||
48483b32 | 590 | static int __init setup_possible_cpus(char *s) |
255acee7 | 591 | { |
48483b32 | 592 | int pcpus, cpu; |
255acee7 | 593 | |
48483b32 | 594 | pcpus = simple_strtoul(s, NULL, 0); |
88e01285 HC |
595 | init_cpu_possible(cpumask_of(0)); |
596 | for (cpu = 1; cpu < pcpus && cpu < nr_cpu_ids; cpu++) | |
def6cfb7 | 597 | set_cpu_possible(cpu, true); |
37a33026 HC |
598 | return 0; |
599 | } | |
600 | early_param("possible_cpus", setup_possible_cpus); | |
601 | ||
48483b32 HC |
602 | #ifdef CONFIG_HOTPLUG_CPU |
603 | ||
39ce010d | 604 | int __cpu_disable(void) |
1da177e4 | 605 | { |
94c12cc7 | 606 | struct ec_creg_mask_parms cr_parms; |
f3705136 | 607 | int cpu = smp_processor_id(); |
1da177e4 | 608 | |
f3705136 | 609 | cpu_clear(cpu, cpu_online_map); |
1da177e4 | 610 | |
1da177e4 | 611 | /* Disable pfault pseudo page faults on this cpu. */ |
29b08d2b | 612 | pfault_fini(); |
1da177e4 | 613 | |
94c12cc7 MS |
614 | memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals)); |
615 | memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals)); | |
1da177e4 | 616 | |
94c12cc7 | 617 | /* disable all external interrupts */ |
1da177e4 | 618 | cr_parms.orvals[0] = 0; |
39ce010d HC |
619 | cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 12 | |
620 | 1 << 11 | 1 << 10 | 1 << 6 | 1 << 4); | |
1da177e4 | 621 | /* disable all I/O interrupts */ |
1da177e4 | 622 | cr_parms.orvals[6] = 0; |
39ce010d HC |
623 | cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | |
624 | 1 << 27 | 1 << 26 | 1 << 25 | 1 << 24); | |
1da177e4 | 625 | /* disable most machine checks */ |
1da177e4 | 626 | cr_parms.orvals[14] = 0; |
39ce010d HC |
627 | cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 | |
628 | 1 << 25 | 1 << 24); | |
94c12cc7 | 629 | |
1da177e4 LT |
630 | smp_ctl_bit_callback(&cr_parms); |
631 | ||
1da177e4 LT |
632 | return 0; |
633 | } | |
634 | ||
39ce010d | 635 | void __cpu_die(unsigned int cpu) |
1da177e4 LT |
636 | { |
637 | /* Wait until target cpu is down */ | |
5c0b912e | 638 | while (!cpu_stopped(cpu)) |
1da177e4 | 639 | cpu_relax(); |
4f8048ee HC |
640 | while (signal_processor_p(0, cpu, sigp_set_prefix) == sigp_busy) |
641 | udelay(10); | |
1cb6bb4b | 642 | smp_free_lowcore(cpu); |
395d31d4 | 643 | pr_info("Processor %d stopped\n", cpu); |
1da177e4 LT |
644 | } |
645 | ||
39ce010d | 646 | void cpu_die(void) |
1da177e4 LT |
647 | { |
648 | idle_task_exit(); | |
f8501ba7 HC |
649 | while (signal_processor(smp_processor_id(), sigp_stop) == sigp_busy) |
650 | cpu_relax(); | |
39ce010d | 651 | for (;;); |
1da177e4 LT |
652 | } |
653 | ||
255acee7 HC |
654 | #endif /* CONFIG_HOTPLUG_CPU */ |
655 | ||
1da177e4 LT |
656 | void __init smp_prepare_cpus(unsigned int max_cpus) |
657 | { | |
591bb4f6 HC |
658 | #ifndef CONFIG_64BIT |
659 | unsigned long save_area = 0; | |
660 | #endif | |
661 | unsigned long async_stack, panic_stack; | |
662 | struct _lowcore *lowcore; | |
1da177e4 | 663 | unsigned int cpu; |
39ce010d | 664 | |
48483b32 HC |
665 | smp_detect_cpus(); |
666 | ||
39ce010d HC |
667 | /* request the 0x1201 emergency signal external interrupt */ |
668 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
669 | panic("Couldn't request external interrupt 0x1201"); | |
7b468488 | 670 | print_cpu_info(); |
1da177e4 | 671 | |
591bb4f6 | 672 | /* Reallocate current lowcore, but keep its contents. */ |
3fd26a77 | 673 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
591bb4f6 HC |
674 | panic_stack = __get_free_page(GFP_KERNEL); |
675 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
c742b31c | 676 | BUG_ON(!lowcore || !panic_stack || !async_stack); |
347a8dc3 | 677 | #ifndef CONFIG_64BIT |
77fa2245 | 678 | if (MACHINE_HAS_IEEE) |
591bb4f6 | 679 | save_area = get_zeroed_page(GFP_KERNEL); |
77fa2245 | 680 | #endif |
591bb4f6 HC |
681 | local_irq_disable(); |
682 | local_mcck_disable(); | |
683 | lowcore_ptr[smp_processor_id()] = lowcore; | |
684 | *lowcore = S390_lowcore; | |
685 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
686 | lowcore->async_stack = async_stack + ASYNC_SIZE; | |
687 | #ifndef CONFIG_64BIT | |
688 | if (MACHINE_HAS_IEEE) | |
689 | lowcore->extended_save_area_addr = (u32) save_area; | |
690 | #endif | |
691 | set_prefix((u32)(unsigned long) lowcore); | |
692 | local_mcck_enable(); | |
693 | local_irq_enable(); | |
3a6ba460 HC |
694 | #ifdef CONFIG_64BIT |
695 | if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore)) | |
696 | BUG(); | |
697 | #endif | |
97db7fbf | 698 | for_each_possible_cpu(cpu) |
1da177e4 LT |
699 | if (cpu != smp_processor_id()) |
700 | smp_create_idle(cpu); | |
701 | } | |
702 | ||
ea1f4eec | 703 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
704 | { |
705 | BUG_ON(smp_processor_id() != 0); | |
706 | ||
48483b32 HC |
707 | current_thread_info()->cpu = 0; |
708 | cpu_set(0, cpu_present_map); | |
1da177e4 | 709 | cpu_set(0, cpu_online_map); |
1da177e4 LT |
710 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
711 | current_set[0] = current; | |
08d07968 | 712 | smp_cpu_state[0] = CPU_STATE_CONFIGURED; |
c10fde0d | 713 | smp_cpu_polarization[0] = POLARIZATION_UNKNWN; |
1da177e4 LT |
714 | } |
715 | ||
ea1f4eec | 716 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 717 | { |
1da177e4 LT |
718 | } |
719 | ||
02beaccc HC |
720 | void __init smp_setup_processor_id(void) |
721 | { | |
722 | S390_lowcore.cpu_nr = 0; | |
723 | __cpu_logical_map[0] = stap(); | |
724 | } | |
725 | ||
1da177e4 LT |
726 | /* |
727 | * the frequency of the profiling timer can be changed | |
728 | * by writing a multiplier value into /proc/profile. | |
729 | * | |
730 | * usually you want to run this on all CPUs ;) | |
731 | */ | |
732 | int setup_profiling_timer(unsigned int multiplier) | |
733 | { | |
39ce010d | 734 | return 0; |
1da177e4 LT |
735 | } |
736 | ||
08d07968 | 737 | #ifdef CONFIG_HOTPLUG_CPU |
4a0b2b4d AK |
738 | static ssize_t cpu_configure_show(struct sys_device *dev, |
739 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
740 | { |
741 | ssize_t count; | |
742 | ||
743 | mutex_lock(&smp_cpu_state_mutex); | |
744 | count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]); | |
745 | mutex_unlock(&smp_cpu_state_mutex); | |
746 | return count; | |
747 | } | |
748 | ||
4a0b2b4d AK |
749 | static ssize_t cpu_configure_store(struct sys_device *dev, |
750 | struct sysdev_attribute *attr, | |
751 | const char *buf, size_t count) | |
08d07968 HC |
752 | { |
753 | int cpu = dev->id; | |
754 | int val, rc; | |
755 | char delim; | |
756 | ||
757 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
758 | return -EINVAL; | |
759 | if (val != 0 && val != 1) | |
760 | return -EINVAL; | |
761 | ||
9d40d2e3 | 762 | get_online_cpus(); |
0b18d318 | 763 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 HC |
764 | rc = -EBUSY; |
765 | if (cpu_online(cpu)) | |
766 | goto out; | |
767 | rc = 0; | |
768 | switch (val) { | |
769 | case 0: | |
770 | if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) { | |
771 | rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]); | |
c10fde0d | 772 | if (!rc) { |
08d07968 | 773 | smp_cpu_state[cpu] = CPU_STATE_STANDBY; |
c10fde0d HC |
774 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
775 | } | |
08d07968 HC |
776 | } |
777 | break; | |
778 | case 1: | |
779 | if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) { | |
780 | rc = sclp_cpu_configure(__cpu_logical_map[cpu]); | |
c10fde0d | 781 | if (!rc) { |
08d07968 | 782 | smp_cpu_state[cpu] = CPU_STATE_CONFIGURED; |
c10fde0d HC |
783 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
784 | } | |
08d07968 HC |
785 | } |
786 | break; | |
787 | default: | |
788 | break; | |
789 | } | |
790 | out: | |
08d07968 | 791 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 792 | put_online_cpus(); |
08d07968 HC |
793 | return rc ? rc : count; |
794 | } | |
795 | static SYSDEV_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); | |
796 | #endif /* CONFIG_HOTPLUG_CPU */ | |
797 | ||
4a0b2b4d AK |
798 | static ssize_t cpu_polarization_show(struct sys_device *dev, |
799 | struct sysdev_attribute *attr, char *buf) | |
c10fde0d HC |
800 | { |
801 | int cpu = dev->id; | |
802 | ssize_t count; | |
803 | ||
804 | mutex_lock(&smp_cpu_state_mutex); | |
805 | switch (smp_cpu_polarization[cpu]) { | |
806 | case POLARIZATION_HRZ: | |
807 | count = sprintf(buf, "horizontal\n"); | |
808 | break; | |
809 | case POLARIZATION_VL: | |
810 | count = sprintf(buf, "vertical:low\n"); | |
811 | break; | |
812 | case POLARIZATION_VM: | |
813 | count = sprintf(buf, "vertical:medium\n"); | |
814 | break; | |
815 | case POLARIZATION_VH: | |
816 | count = sprintf(buf, "vertical:high\n"); | |
817 | break; | |
818 | default: | |
819 | count = sprintf(buf, "unknown\n"); | |
820 | break; | |
821 | } | |
822 | mutex_unlock(&smp_cpu_state_mutex); | |
823 | return count; | |
824 | } | |
825 | static SYSDEV_ATTR(polarization, 0444, cpu_polarization_show, NULL); | |
826 | ||
4a0b2b4d AK |
827 | static ssize_t show_cpu_address(struct sys_device *dev, |
828 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
829 | { |
830 | return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]); | |
831 | } | |
832 | static SYSDEV_ATTR(address, 0444, show_cpu_address, NULL); | |
833 | ||
834 | ||
835 | static struct attribute *cpu_common_attrs[] = { | |
836 | #ifdef CONFIG_HOTPLUG_CPU | |
837 | &attr_configure.attr, | |
838 | #endif | |
839 | &attr_address.attr, | |
c10fde0d | 840 | &attr_polarization.attr, |
08d07968 HC |
841 | NULL, |
842 | }; | |
843 | ||
844 | static struct attribute_group cpu_common_attr_group = { | |
845 | .attrs = cpu_common_attrs, | |
846 | }; | |
1da177e4 | 847 | |
4a0b2b4d AK |
848 | static ssize_t show_capability(struct sys_device *dev, |
849 | struct sysdev_attribute *attr, char *buf) | |
2fc2d1e9 HC |
850 | { |
851 | unsigned int capability; | |
852 | int rc; | |
853 | ||
854 | rc = get_cpu_capability(&capability); | |
855 | if (rc) | |
856 | return rc; | |
857 | return sprintf(buf, "%u\n", capability); | |
858 | } | |
859 | static SYSDEV_ATTR(capability, 0444, show_capability, NULL); | |
860 | ||
4a0b2b4d AK |
861 | static ssize_t show_idle_count(struct sys_device *dev, |
862 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
863 | { |
864 | struct s390_idle_data *idle; | |
865 | unsigned long long idle_count; | |
e98bbaaf | 866 | unsigned int sequence; |
fae8b22d HC |
867 | |
868 | idle = &per_cpu(s390_idle, dev->id); | |
e98bbaaf MS |
869 | repeat: |
870 | sequence = idle->sequence; | |
871 | smp_rmb(); | |
872 | if (sequence & 1) | |
873 | goto repeat; | |
fae8b22d | 874 | idle_count = idle->idle_count; |
6f430924 MS |
875 | if (idle->idle_enter) |
876 | idle_count++; | |
e98bbaaf MS |
877 | smp_rmb(); |
878 | if (idle->sequence != sequence) | |
879 | goto repeat; | |
fae8b22d HC |
880 | return sprintf(buf, "%llu\n", idle_count); |
881 | } | |
882 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); | |
883 | ||
4a0b2b4d AK |
884 | static ssize_t show_idle_time(struct sys_device *dev, |
885 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
886 | { |
887 | struct s390_idle_data *idle; | |
6f430924 | 888 | unsigned long long now, idle_time, idle_enter; |
e98bbaaf | 889 | unsigned int sequence; |
fae8b22d HC |
890 | |
891 | idle = &per_cpu(s390_idle, dev->id); | |
6f430924 | 892 | now = get_clock(); |
e98bbaaf MS |
893 | repeat: |
894 | sequence = idle->sequence; | |
895 | smp_rmb(); | |
896 | if (sequence & 1) | |
897 | goto repeat; | |
6f430924 MS |
898 | idle_time = idle->idle_time; |
899 | idle_enter = idle->idle_enter; | |
900 | if (idle_enter != 0ULL && idle_enter < now) | |
901 | idle_time += now - idle_enter; | |
e98bbaaf MS |
902 | smp_rmb(); |
903 | if (idle->sequence != sequence) | |
904 | goto repeat; | |
6f430924 | 905 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 906 | } |
69d39d66 | 907 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 908 | |
08d07968 | 909 | static struct attribute *cpu_online_attrs[] = { |
fae8b22d HC |
910 | &attr_capability.attr, |
911 | &attr_idle_count.attr, | |
69d39d66 | 912 | &attr_idle_time_us.attr, |
fae8b22d HC |
913 | NULL, |
914 | }; | |
915 | ||
08d07968 HC |
916 | static struct attribute_group cpu_online_attr_group = { |
917 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
918 | }; |
919 | ||
2fc2d1e9 HC |
920 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
921 | unsigned long action, void *hcpu) | |
922 | { | |
923 | unsigned int cpu = (unsigned int)(long)hcpu; | |
924 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
925 | struct sys_device *s = &c->sysdev; | |
fae8b22d | 926 | struct s390_idle_data *idle; |
2fc2d1e9 HC |
927 | |
928 | switch (action) { | |
929 | case CPU_ONLINE: | |
8bb78442 | 930 | case CPU_ONLINE_FROZEN: |
fae8b22d | 931 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 932 | memset(idle, 0, sizeof(struct s390_idle_data)); |
08d07968 | 933 | if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) |
2fc2d1e9 HC |
934 | return NOTIFY_BAD; |
935 | break; | |
936 | case CPU_DEAD: | |
8bb78442 | 937 | case CPU_DEAD_FROZEN: |
08d07968 | 938 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
939 | break; |
940 | } | |
941 | return NOTIFY_OK; | |
942 | } | |
943 | ||
944 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 945 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
946 | }; |
947 | ||
2bc89b5e | 948 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 HC |
949 | { |
950 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
951 | struct sys_device *s = &c->sysdev; | |
952 | int rc; | |
953 | ||
954 | c->hotpluggable = 1; | |
955 | rc = register_cpu(c, cpu); | |
956 | if (rc) | |
957 | goto out; | |
958 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
959 | if (rc) | |
960 | goto out_cpu; | |
961 | if (!cpu_online(cpu)) | |
962 | goto out; | |
963 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
964 | if (!rc) | |
965 | return 0; | |
966 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); | |
967 | out_cpu: | |
968 | #ifdef CONFIG_HOTPLUG_CPU | |
969 | unregister_cpu(c); | |
970 | #endif | |
971 | out: | |
972 | return rc; | |
973 | } | |
974 | ||
975 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 976 | |
67060d9c | 977 | int __ref smp_rescan_cpus(void) |
08d07968 HC |
978 | { |
979 | cpumask_t newcpus; | |
980 | int cpu; | |
981 | int rc; | |
982 | ||
9d40d2e3 | 983 | get_online_cpus(); |
0b18d318 | 984 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 985 | newcpus = cpu_present_map; |
1e489518 | 986 | rc = __smp_rescan_cpus(); |
08d07968 HC |
987 | if (rc) |
988 | goto out; | |
989 | cpus_andnot(newcpus, cpu_present_map, newcpus); | |
990 | for_each_cpu_mask(cpu, newcpus) { | |
991 | rc = smp_add_present_cpu(cpu); | |
992 | if (rc) | |
993 | cpu_clear(cpu, cpu_present_map); | |
994 | } | |
995 | rc = 0; | |
996 | out: | |
08d07968 | 997 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 998 | put_online_cpus(); |
c10fde0d HC |
999 | if (!cpus_empty(newcpus)) |
1000 | topology_schedule_update(); | |
1e489518 HC |
1001 | return rc; |
1002 | } | |
1003 | ||
da5aae70 | 1004 | static ssize_t __ref rescan_store(struct sysdev_class *class, const char *buf, |
1e489518 HC |
1005 | size_t count) |
1006 | { | |
1007 | int rc; | |
1008 | ||
1009 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1010 | return rc ? rc : count; |
1011 | } | |
da5aae70 | 1012 | static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1013 | #endif /* CONFIG_HOTPLUG_CPU */ |
1014 | ||
da5aae70 | 1015 | static ssize_t dispatching_show(struct sysdev_class *class, char *buf) |
c10fde0d HC |
1016 | { |
1017 | ssize_t count; | |
1018 | ||
1019 | mutex_lock(&smp_cpu_state_mutex); | |
1020 | count = sprintf(buf, "%d\n", cpu_management); | |
1021 | mutex_unlock(&smp_cpu_state_mutex); | |
1022 | return count; | |
1023 | } | |
1024 | ||
da5aae70 HC |
1025 | static ssize_t dispatching_store(struct sysdev_class *dev, const char *buf, |
1026 | size_t count) | |
c10fde0d HC |
1027 | { |
1028 | int val, rc; | |
1029 | char delim; | |
1030 | ||
1031 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
1032 | return -EINVAL; | |
1033 | if (val != 0 && val != 1) | |
1034 | return -EINVAL; | |
1035 | rc = 0; | |
c10fde0d | 1036 | get_online_cpus(); |
0b18d318 | 1037 | mutex_lock(&smp_cpu_state_mutex); |
c10fde0d HC |
1038 | if (cpu_management == val) |
1039 | goto out; | |
1040 | rc = topology_set_cpu_management(val); | |
1041 | if (!rc) | |
1042 | cpu_management = val; | |
1043 | out: | |
c10fde0d | 1044 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1045 | put_online_cpus(); |
c10fde0d HC |
1046 | return rc ? rc : count; |
1047 | } | |
da5aae70 HC |
1048 | static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show, |
1049 | dispatching_store); | |
c10fde0d | 1050 | |
1da177e4 LT |
1051 | static int __init topology_init(void) |
1052 | { | |
1053 | int cpu; | |
fae8b22d | 1054 | int rc; |
2fc2d1e9 HC |
1055 | |
1056 | register_cpu_notifier(&smp_cpu_nb); | |
1da177e4 | 1057 | |
08d07968 | 1058 | #ifdef CONFIG_HOTPLUG_CPU |
da5aae70 | 1059 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan); |
08d07968 HC |
1060 | if (rc) |
1061 | return rc; | |
1062 | #endif | |
da5aae70 | 1063 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching); |
c10fde0d HC |
1064 | if (rc) |
1065 | return rc; | |
08d07968 HC |
1066 | for_each_present_cpu(cpu) { |
1067 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1068 | if (rc) |
1069 | return rc; | |
1da177e4 LT |
1070 | } |
1071 | return 0; | |
1072 | } | |
1da177e4 | 1073 | subsys_initcall(topology_init); |